drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include "amdgpu_amdkfd.h"
  24 #include "amd_shared.h"
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_gfx.h"
  28 #include <linux/module.h>
  29
  30 const struct kgd2kfd_calls *kgd2kfd;
  31 bool (*kgd2kfd_init_p)(unsigned int, const struct kgd2kfd_calls**);
  32
  33 static const unsigned int compute_vmid_bitmap = 0xFF00;
  34
  35 int amdgpu_amdkfd_init(void)
  36 {
  37         int ret;
  38
  39 #if defined(CONFIG_HSA_AMD_MODULE)
  40         int (*kgd2kfd_init_p)(unsigned int, const struct kgd2kfd_calls**);
  41
  42         kgd2kfd_init_p = symbol_request(kgd2kfd_init);
  43
  44         if (kgd2kfd_init_p == NULL)
  45                 return -ENOENT;
  46
  47         ret = kgd2kfd_init_p(KFD_INTERFACE_VERSION, &kgd2kfd);
  48         if (ret) {
  49                 symbol_put(kgd2kfd_init);
  50                 kgd2kfd = NULL;
  51         }
  52
  53 #elif defined(CONFIG_HSA_AMD)
  54         ret = kgd2kfd_init(KFD_INTERFACE_VERSION, &kgd2kfd);
  55         if (ret)
  56                 kgd2kfd = NULL;
  57
  58 #else
  59         ret = -ENOENT;
  60 #endif
  61         amdgpu_amdkfd_gpuvm_init_mem_limits();
  62
  63         return ret;
  64 }
  65
  66 void amdgpu_amdkfd_fini(void)
  67 {
  68         if (kgd2kfd) {
  69                 kgd2kfd->exit();
  70                 symbol_put(kgd2kfd_init);
  71         }
  72 }
  73
  74 void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev)
  75 {
  76         const struct kfd2kgd_calls *kfd2kgd;
  77
  78         if (!kgd2kfd)
  79                 return;
  80
  81         switch (adev->asic_type) {
  82 #ifdef CONFIG_DRM_AMDGPU_CIK
  83         case CHIP_KAVERI:
  84         case CHIP_HAWAII:
  85                 kfd2kgd = amdgpu_amdkfd_gfx_7_get_functions();
  86                 break;
  87 #endif
  88         case CHIP_CARRIZO:
  89         case CHIP_TONGA:
  90         case CHIP_FIJI:
  91         case CHIP_POLARIS10:
  92         case CHIP_POLARIS11:
  93                 kfd2kgd = amdgpu_amdkfd_gfx_8_0_get_functions();
  94                 break;
  95         case CHIP_VEGA10:
  96         case CHIP_RAVEN:
  97                 kfd2kgd = amdgpu_amdkfd_gfx_9_0_get_functions();
  98                 break;
  99         default:
 100                 dev_dbg(adev->dev, "kfd not supported on this ASIC\n");
 101                 return;
 102         }
 103
 104         adev->kfd = kgd2kfd->probe((struct kgd_dev *)adev,
 105                                    adev->pdev, kfd2kgd);
 106 }
 107
 108 /**
 109  * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
 110  *                                setup amdkfd
 111  *
 112  * @adev: amdgpu_device pointer
 113  * @aperture_base: output returning doorbell aperture base physical address
 114  * @aperture_size: output returning doorbell aperture size in bytes
 115  * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
 116  *
 117  * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
 118  * takes doorbells required for its own rings and reports the setup to amdkfd.
 119  * amdgpu reserved doorbells are at the start of the doorbell aperture.
 120  */
 121 static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
 122                                          phys_addr_t *aperture_base,
 123                                          size_t *aperture_size,
 124                                          size_t *start_offset)
 125 {
 126         /*
 127          * The first num_doorbells are used by amdgpu.
 128          * amdkfd takes whatever's left in the aperture.
 129          */
 130         if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
 131                 *aperture_base = adev->doorbell.base;
 132                 *aperture_size = adev->doorbell.size;
 133                 *start_offset = adev->doorbell.num_doorbells * sizeof(u32);
 134         } else {
 135                 *aperture_base = 0;
 136                 *aperture_size = 0;
 137                 *start_offset = 0;
 138         }
 139 }
 140
 141 void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
 142 {
 143         int i;
 144         int last_valid_bit;
 145         if (adev->kfd) {
 146                 struct kgd2kfd_shared_resources gpu_resources = {
 147                         .compute_vmid_bitmap = compute_vmid_bitmap,
 148                         .num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec,
 149                         .num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe,
 150                         .gpuvm_size = min(adev->vm_manager.max_pfn
 151                                           << AMDGPU_GPU_PAGE_SHIFT,
 152                                           AMDGPU_VA_HOLE_START),
 153                         .drm_render_minor = adev->ddev->render->index
 154                 };
 155
 156                 /* this is going to have a few of the MSBs set that we need to
 157                  * clear */
 158                 bitmap_complement(gpu_resources.queue_bitmap,
 159                                   adev->gfx.mec.queue_bitmap,
 160                                   KGD_MAX_QUEUES);
 161
 162                 /* remove the KIQ bit as well */
 163                 if (adev->gfx.kiq.ring.ready)
 164                         clear_bit(amdgpu_gfx_queue_to_bit(adev,
 165                                                           adev->gfx.kiq.ring.me - 1,
 166                                                           adev->gfx.kiq.ring.pipe,
 167                                                           adev->gfx.kiq.ring.queue),
 168                                   gpu_resources.queue_bitmap);
 169
 170                 /* According to linux/bitmap.h we shouldn't use bitmap_clear if
 171                  * nbits is not compile time constant */
 172                 last_valid_bit = 1 /* only first MEC can have compute queues */
 173                                 * adev->gfx.mec.num_pipe_per_mec
 174                                 * adev->gfx.mec.num_queue_per_pipe;
 175                 for (i = last_valid_bit; i < KGD_MAX_QUEUES; ++i)
 176                         clear_bit(i, gpu_resources.queue_bitmap);
 177
 178                 amdgpu_doorbell_get_kfd_info(adev,
 179                                 &gpu_resources.doorbell_physical_address,
 180                                 &gpu_resources.doorbell_aperture_size,
 181                                 &gpu_resources.doorbell_start_offset);
 182                 if (adev->asic_type >= CHIP_VEGA10) {
 183                         /* On SOC15 the BIF is involved in routing
 184                          * doorbells using the low 12 bits of the
 185                          * address. Communicate the assignments to
 186                          * KFD. KFD uses two doorbell pages per
 187                          * process in case of 64-bit doorbells so we
 188                          * can use each doorbell assignment twice.
 189                          */
 190                         gpu_resources.sdma_doorbell[0][0] =
 191                                 AMDGPU_DOORBELL64_sDMA_ENGINE0;
 192                         gpu_resources.sdma_doorbell[0][1] =
 193                                 AMDGPU_DOORBELL64_sDMA_ENGINE0 + 0x200;
 194                         gpu_resources.sdma_doorbell[1][0] =
 195                                 AMDGPU_DOORBELL64_sDMA_ENGINE1;
 196                         gpu_resources.sdma_doorbell[1][1] =
 197                                 AMDGPU_DOORBELL64_sDMA_ENGINE1 + 0x200;
 198                         /* Doorbells 0x0f0-0ff and 0x2f0-2ff are reserved for
 199                          * SDMA, IH and VCN. So don't use them for the CP.
 200                          */
 201                         gpu_resources.reserved_doorbell_mask = 0x1f0;
 202                         gpu_resources.reserved_doorbell_val  = 0x0f0;
 203                 }
 204
 205                 kgd2kfd->device_init(adev->kfd, &gpu_resources);
 206         }
 207 }
 208
 209 void amdgpu_amdkfd_device_fini(struct amdgpu_device *adev)
 210 {
 211         if (adev->kfd) {
 212                 kgd2kfd->device_exit(adev->kfd);
 213                 adev->kfd = NULL;
 214         }
 215 }
 216
 217 void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,
 218                 const void *ih_ring_entry)
 219 {
 220         if (adev->kfd)
 221                 kgd2kfd->interrupt(adev->kfd, ih_ring_entry);
 222 }
 223
 224 void amdgpu_amdkfd_suspend(struct amdgpu_device *adev)
 225 {
 226         if (adev->kfd)
 227                 kgd2kfd->suspend(adev->kfd);
 228 }
 229
 230 int amdgpu_amdkfd_resume(struct amdgpu_device *adev)
 231 {
 232         int r = 0;
 233
 234         if (adev->kfd)
 235                 r = kgd2kfd->resume(adev->kfd);
 236
 237         return r;
 238 }
 239
 240 int alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
 241                         void **mem_obj, uint64_t *gpu_addr,
 242                         void **cpu_ptr)
 243 {
 244         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 245         struct amdgpu_bo *bo = NULL;
 246         struct amdgpu_bo_param bp;
 247         int r;
 248         uint64_t gpu_addr_tmp = 0;
 249         void *cpu_ptr_tmp = NULL;
 250
 251         memset(&bp, 0, sizeof(bp));
 252         bp.size = size;
 253         bp.byte_align = PAGE_SIZE;
 254         bp.domain = AMDGPU_GEM_DOMAIN_GTT;
 255         bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 256         bp.type = ttm_bo_type_kernel;
 257         bp.resv = NULL;
 258         r = amdgpu_bo_create(adev, &bp, &bo);
 259         if (r) {
 260                 dev_err(adev->dev,
 261                         "failed to allocate BO for amdkfd (%d)\n", r);
 262                 return r;
 263         }
 264
 265         /* map the buffer */
 266         r = amdgpu_bo_reserve(bo, true);
 267         if (r) {
 268                 dev_err(adev->dev, "(%d) failed to reserve bo for amdkfd\n", r);
 269                 goto allocate_mem_reserve_bo_failed;
 270         }
 271
 272         r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT,
 273                                 &gpu_addr_tmp);
 274         if (r) {
 275                 dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r);
 276                 goto allocate_mem_pin_bo_failed;
 277         }
 278
 279         r = amdgpu_bo_kmap(bo, &cpu_ptr_tmp);
 280         if (r) {
 281                 dev_err(adev->dev,
 282                         "(%d) failed to map bo to kernel for amdkfd\n", r);
 283                 goto allocate_mem_kmap_bo_failed;
 284         }
 285
 286         *mem_obj = bo;
 287         *gpu_addr = gpu_addr_tmp;
 288         *cpu_ptr = cpu_ptr_tmp;
 289
 290         amdgpu_bo_unreserve(bo);
 291
 292         return 0;
 293
 294 allocate_mem_kmap_bo_failed:
 295         amdgpu_bo_unpin(bo);
 296 allocate_mem_pin_bo_failed:
 297         amdgpu_bo_unreserve(bo);
 298 allocate_mem_reserve_bo_failed:
 299         amdgpu_bo_unref(&bo);
 300
 301         return r;
 302 }
 303
 304 void free_gtt_mem(struct kgd_dev *kgd, void *mem_obj)
 305 {
 306         struct amdgpu_bo *bo = (struct amdgpu_bo *) mem_obj;
 307
 308         amdgpu_bo_reserve(bo, true);
 309         amdgpu_bo_kunmap(bo);
 310         amdgpu_bo_unpin(bo);
 311         amdgpu_bo_unreserve(bo);
 312         amdgpu_bo_unref(&(bo));
 313 }
 314
 315 void get_local_mem_info(struct kgd_dev *kgd,
 316                         struct kfd_local_mem_info *mem_info)
 317 {
 318         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 319         uint64_t address_mask = adev->dev->dma_mask ? ~*adev->dev->dma_mask :
 320                                              ~((1ULL << 32) - 1);
 321         resource_size_t aper_limit = adev->gmc.aper_base + adev->gmc.aper_size;
 322
 323         memset(mem_info, 0, sizeof(*mem_info));
 324         if (!(adev->gmc.aper_base & address_mask || aper_limit & address_mask)) {
 325                 mem_info->local_mem_size_public = adev->gmc.visible_vram_size;
 326                 mem_info->local_mem_size_private = adev->gmc.real_vram_size -
 327                                 adev->gmc.visible_vram_size;
 328         } else {
 329                 mem_info->local_mem_size_public = 0;
 330                 mem_info->local_mem_size_private = adev->gmc.real_vram_size;
 331         }
 332         mem_info->vram_width = adev->gmc.vram_width;
 333
 334         pr_debug("Address base: %pap limit %pap public 0x%llx private 0x%llx\n",
 335                         &adev->gmc.aper_base, &aper_limit,
 336                         mem_info->local_mem_size_public,
 337                         mem_info->local_mem_size_private);
 338
 339         if (amdgpu_emu_mode == 1) {
 340                 mem_info->mem_clk_max = 100;
 341                 return;
 342         }
 343
 344         if (amdgpu_sriov_vf(adev))
 345                 mem_info->mem_clk_max = adev->clock.default_mclk / 100;
 346         else
 347                 mem_info->mem_clk_max = amdgpu_dpm_get_mclk(adev, false) / 100;
 348 }
 349
 350 uint64_t get_gpu_clock_counter(struct kgd_dev *kgd)
 351 {
 352         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 353
 354         if (adev->gfx.funcs->get_gpu_clock_counter)
 355                 return adev->gfx.funcs->get_gpu_clock_counter(adev);
 356         return 0;
 357 }
 358
 359 uint32_t get_max_engine_clock_in_mhz(struct kgd_dev *kgd)
 360 {
 361         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 362
 363         /* the sclk is in quantas of 10kHz */
 364         if (amdgpu_emu_mode == 1)
 365                 return 100;
 366
 367         if (amdgpu_sriov_vf(adev))
 368                 return adev->clock.default_sclk / 100;
 369
 370         return amdgpu_dpm_get_sclk(adev, false) / 100;
 371 }
 372
 373 void get_cu_info(struct kgd_dev *kgd, struct kfd_cu_info *cu_info)
 374 {
 375         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 376         struct amdgpu_cu_info acu_info = adev->gfx.cu_info;
 377
 378         memset(cu_info, 0, sizeof(*cu_info));
 379         if (sizeof(cu_info->cu_bitmap) != sizeof(acu_info.bitmap))
 380                 return;
 381
 382         cu_info->cu_active_number = acu_info.number;
 383         cu_info->cu_ao_mask = acu_info.ao_cu_mask;
 384         memcpy(&cu_info->cu_bitmap[0], &acu_info.bitmap[0],
 385                sizeof(acu_info.bitmap));
 386         cu_info->num_shader_engines = adev->gfx.config.max_shader_engines;
 387         cu_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
 388         cu_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
 389         cu_info->simd_per_cu = acu_info.simd_per_cu;
 390         cu_info->max_waves_per_simd = acu_info.max_waves_per_simd;
 391         cu_info->wave_front_size = acu_info.wave_front_size;
 392         cu_info->max_scratch_slots_per_cu = acu_info.max_scratch_slots_per_cu;
 393         cu_info->lds_size = acu_info.lds_size;
 394 }
 395
 396 uint64_t amdgpu_amdkfd_get_vram_usage(struct kgd_dev *kgd)
 397 {
 398         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 399
 400         return amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 401 }
 402
 403 int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum kgd_engine_type engine,
 404                                 uint32_t vmid, uint64_t gpu_addr,
 405                                 uint32_t *ib_cmd, uint32_t ib_len)
 406 {
 407         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 408         struct amdgpu_job *job;
 409         struct amdgpu_ib *ib;
 410         struct amdgpu_ring *ring;
 411         struct dma_fence *f = NULL;
 412         int ret;
 413
 414         switch (engine) {
 415         case KGD_ENGINE_MEC1:
 416                 ring = &adev->gfx.compute_ring[0];
 417                 break;
 418         case KGD_ENGINE_SDMA1:
 419                 ring = &adev->sdma.instance[0].ring;
 420                 break;
 421         case KGD_ENGINE_SDMA2:
 422                 ring = &adev->sdma.instance[1].ring;
 423                 break;
 424         default:
 425                 pr_err("Invalid engine in IB submission: %d\n", engine);
 426                 ret = -EINVAL;
 427                 goto err;
 428         }
 429
 430         ret = amdgpu_job_alloc(adev, 1, &job, NULL);
 431         if (ret)
 432                 goto err;
 433
 434         ib = &job->ibs[0];
 435         memset(ib, 0, sizeof(struct amdgpu_ib));
 436
 437         ib->gpu_addr = gpu_addr;
 438         ib->ptr = ib_cmd;
 439         ib->length_dw = ib_len;
 440         /* This works for NO_HWS. TODO: need to handle without knowing VMID */
 441         job->vmid = vmid;
 442
 443         ret = amdgpu_ib_schedule(ring, 1, ib, job, &f);
 444         if (ret) {
 445                 DRM_ERROR("amdgpu: failed to schedule IB.\n");
 446                 goto err_ib_sched;
 447         }
 448
 449         ret = dma_fence_wait(f, false);
 450
 451 err_ib_sched:
 452         dma_fence_put(f);
 453         amdgpu_job_free(job);
 454 err:
 455         return ret;
 456 }
 457
 458 bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid)
 459 {
 460         if (adev->kfd) {
 461                 if ((1 << vmid) & compute_vmid_bitmap)
 462                         return true;
 463         }
 464
 465         return false;
 466 }