drivers/edac/altera_edac.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  *  Copyright (C) 2017-2018, Intel Corporation. All rights reserved
   4  *  Copyright Altera Corporation (C) 2014-2016. All rights reserved.
   5  *  Copyright 2011-2012 Calxeda, Inc.
   6  */
   7
   8 #include <asm/cacheflush.h>
   9 #include <linux/ctype.h>
  10 #include <linux/delay.h>
  11 #include <linux/edac.h>
  12 #include <linux/genalloc.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/irqchip/chained_irq.h>
  15 #include <linux/kernel.h>
  16 #include <linux/mfd/syscon.h>
  17 #include <linux/notifier.h>
  18 #include <linux/of_address.h>
  19 #include <linux/of_irq.h>
  20 #include <linux/of_platform.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/regmap.h>
  23 #include <linux/types.h>
  24 #include <linux/uaccess.h>
  25
  26 #include "altera_edac.h"
  27 #include "edac_module.h"
  28
  29 #define EDAC_MOD_STR            "altera_edac"
  30 #define EDAC_DEVICE             "Altera"
  31
  32 static const struct altr_sdram_prv_data c5_data = {
  33         .ecc_ctrl_offset    = CV_CTLCFG_OFST,
  34         .ecc_ctl_en_mask    = CV_CTLCFG_ECC_AUTO_EN,
  35         .ecc_stat_offset    = CV_DRAMSTS_OFST,
  36         .ecc_stat_ce_mask   = CV_DRAMSTS_SBEERR,
  37         .ecc_stat_ue_mask   = CV_DRAMSTS_DBEERR,
  38         .ecc_saddr_offset   = CV_ERRADDR_OFST,
  39         .ecc_daddr_offset   = CV_ERRADDR_OFST,
  40         .ecc_cecnt_offset   = CV_SBECOUNT_OFST,
  41         .ecc_uecnt_offset   = CV_DBECOUNT_OFST,
  42         .ecc_irq_en_offset  = CV_DRAMINTR_OFST,
  43         .ecc_irq_en_mask    = CV_DRAMINTR_INTREN,
  44         .ecc_irq_clr_offset = CV_DRAMINTR_OFST,
  45         .ecc_irq_clr_mask   = (CV_DRAMINTR_INTRCLR | CV_DRAMINTR_INTREN),
  46         .ecc_cnt_rst_offset = CV_DRAMINTR_OFST,
  47         .ecc_cnt_rst_mask   = CV_DRAMINTR_INTRCLR,
  48         .ce_ue_trgr_offset  = CV_CTLCFG_OFST,
  49         .ce_set_mask        = CV_CTLCFG_GEN_SB_ERR,
  50         .ue_set_mask        = CV_CTLCFG_GEN_DB_ERR,
  51 };
  52
  53 static const struct altr_sdram_prv_data a10_data = {
  54         .ecc_ctrl_offset    = A10_ECCCTRL1_OFST,
  55         .ecc_ctl_en_mask    = A10_ECCCTRL1_ECC_EN,
  56         .ecc_stat_offset    = A10_INTSTAT_OFST,
  57         .ecc_stat_ce_mask   = A10_INTSTAT_SBEERR,
  58         .ecc_stat_ue_mask   = A10_INTSTAT_DBEERR,
  59         .ecc_saddr_offset   = A10_SERRADDR_OFST,
  60         .ecc_daddr_offset   = A10_DERRADDR_OFST,
  61         .ecc_irq_en_offset  = A10_ERRINTEN_OFST,
  62         .ecc_irq_en_mask    = A10_ECC_IRQ_EN_MASK,
  63         .ecc_irq_clr_offset = A10_INTSTAT_OFST,
  64         .ecc_irq_clr_mask   = (A10_INTSTAT_SBEERR | A10_INTSTAT_DBEERR),
  65         .ecc_cnt_rst_offset = A10_ECCCTRL1_OFST,
  66         .ecc_cnt_rst_mask   = A10_ECC_CNT_RESET_MASK,
  67         .ce_ue_trgr_offset  = A10_DIAGINTTEST_OFST,
  68         .ce_set_mask        = A10_DIAGINT_TSERRA_MASK,
  69         .ue_set_mask        = A10_DIAGINT_TDERRA_MASK,
  70 };
  71
  72 /*********************** EDAC Memory Controller Functions ****************/
  73
  74 /* The SDRAM controller uses the EDAC Memory Controller framework.       */
  75
  76 static irqreturn_t altr_sdram_mc_err_handler(int irq, void *dev_id)
  77 {
  78         struct mem_ctl_info *mci = dev_id;
  79         struct altr_sdram_mc_data *drvdata = mci->pvt_info;
  80         const struct altr_sdram_prv_data *priv = drvdata->data;
  81         u32 status, err_count = 1, err_addr;
  82
  83         regmap_read(drvdata->mc_vbase, priv->ecc_stat_offset, &status);
  84
  85         if (status & priv->ecc_stat_ue_mask) {
  86                 regmap_read(drvdata->mc_vbase, priv->ecc_daddr_offset,
  87                             &err_addr);
  88                 if (priv->ecc_uecnt_offset)
  89                         regmap_read(drvdata->mc_vbase, priv->ecc_uecnt_offset,
  90                                     &err_count);
  91                 panic("\nEDAC: [%d Uncorrectable errors @ 0x%08X]\n",
  92                       err_count, err_addr);
  93         }
  94         if (status & priv->ecc_stat_ce_mask) {
  95                 regmap_read(drvdata->mc_vbase, priv->ecc_saddr_offset,
  96                             &err_addr);
  97                 if (priv->ecc_uecnt_offset)
  98                         regmap_read(drvdata->mc_vbase,  priv->ecc_cecnt_offset,
  99                                     &err_count);
 100                 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, err_count,
 101                                      err_addr >> PAGE_SHIFT,
 102                                      err_addr & ~PAGE_MASK, 0,
 103                                      0, 0, -1, mci->ctl_name, "");
 104                 /* Clear IRQ to resume */
 105                 regmap_write(drvdata->mc_vbase, priv->ecc_irq_clr_offset,
 106                              priv->ecc_irq_clr_mask);
 107
 108                 return IRQ_HANDLED;
 109         }
 110         return IRQ_NONE;
 111 }
 112
 113 static ssize_t altr_sdr_mc_err_inject_write(struct file *file,
 114                                             const char __user *data,
 115                                             size_t count, loff_t *ppos)
 116 {
 117         struct mem_ctl_info *mci = file->private_data;
 118         struct altr_sdram_mc_data *drvdata = mci->pvt_info;
 119         const struct altr_sdram_prv_data *priv = drvdata->data;
 120         u32 *ptemp;
 121         dma_addr_t dma_handle;
 122         u32 reg, read_reg;
 123
 124         ptemp = dma_alloc_coherent(mci->pdev, 16, &dma_handle, GFP_KERNEL);
 125         if (!ptemp) {
 126                 dma_free_coherent(mci->pdev, 16, ptemp, dma_handle);
 127                 edac_printk(KERN_ERR, EDAC_MC,
 128                             "Inject: Buffer Allocation error\n");
 129                 return -ENOMEM;
 130         }
 131
 132         regmap_read(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
 133                     &read_reg);
 134         read_reg &= ~(priv->ce_set_mask | priv->ue_set_mask);
 135
 136         /* Error are injected by writing a word while the SBE or DBE
 137          * bit in the CTLCFG register is set. Reading the word will
 138          * trigger the SBE or DBE error and the corresponding IRQ.
 139          */
 140         if (count == 3) {
 141                 edac_printk(KERN_ALERT, EDAC_MC,
 142                             "Inject Double bit error\n");
 143                 local_irq_disable();
 144                 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
 145                              (read_reg | priv->ue_set_mask));
 146                 local_irq_enable();
 147         } else {
 148                 edac_printk(KERN_ALERT, EDAC_MC,
 149                             "Inject Single bit error\n");
 150                 local_irq_disable();
 151                 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
 152                              (read_reg | priv->ce_set_mask));
 153                 local_irq_enable();
 154         }
 155
 156         ptemp[0] = 0x5A5A5A5A;
 157         ptemp[1] = 0xA5A5A5A5;
 158
 159         /* Clear the error injection bits */
 160         regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, read_reg);
 161         /* Ensure it has been written out */
 162         wmb();
 163
 164         /*
 165          * To trigger the error, we need to read the data back
 166          * (the data was written with errors above).
 167          * The READ_ONCE macros and printk are used to prevent the
 168          * the compiler optimizing these reads out.
 169          */
 170         reg = READ_ONCE(ptemp[0]);
 171         read_reg = READ_ONCE(ptemp[1]);
 172         /* Force Read */
 173         rmb();
 174
 175         edac_printk(KERN_ALERT, EDAC_MC, "Read Data [0x%X, 0x%X]\n",
 176                     reg, read_reg);
 177
 178         dma_free_coherent(mci->pdev, 16, ptemp, dma_handle);
 179
 180         return count;
 181 }
 182
 183 static const struct file_operations altr_sdr_mc_debug_inject_fops = {
 184         .open = simple_open,
 185         .write = altr_sdr_mc_err_inject_write,
 186         .llseek = generic_file_llseek,
 187 };
 188
 189 static void altr_sdr_mc_create_debugfs_nodes(struct mem_ctl_info *mci)
 190 {
 191         if (!IS_ENABLED(CONFIG_EDAC_DEBUG))
 192                 return;
 193
 194         if (!mci->debugfs)
 195                 return;
 196
 197         edac_debugfs_create_file("altr_trigger", S_IWUSR, mci->debugfs, mci,
 198                                  &altr_sdr_mc_debug_inject_fops);
 199 }
 200
 201 /* Get total memory size from Open Firmware DTB */
 202 static unsigned long get_total_mem(void)
 203 {
 204         struct device_node *np = NULL;
 205         struct resource res;
 206         int ret;
 207         unsigned long total_mem = 0;
 208
 209         for_each_node_by_type(np, "memory") {
 210                 ret = of_address_to_resource(np, 0, &res);
 211                 if (ret)
 212                         continue;
 213
 214                 total_mem += resource_size(&res);
 215         }
 216         edac_dbg(0, "total_mem 0x%lx\n", total_mem);
 217         return total_mem;
 218 }
 219
 220 static const struct of_device_id altr_sdram_ctrl_of_match[] = {
 221         { .compatible = "altr,sdram-edac", .data = &c5_data},
 222         { .compatible = "altr,sdram-edac-a10", .data = &a10_data},
 223         { .compatible = "altr,sdram-edac-s10", .data = &a10_data},
 224         {},
 225 };
 226 MODULE_DEVICE_TABLE(of, altr_sdram_ctrl_of_match);
 227
 228 static int a10_init(struct regmap *mc_vbase)
 229 {
 230         if (regmap_update_bits(mc_vbase, A10_INTMODE_OFST,
 231                                A10_INTMODE_SB_INT, A10_INTMODE_SB_INT)) {
 232                 edac_printk(KERN_ERR, EDAC_MC,
 233                             "Error setting SB IRQ mode\n");
 234                 return -ENODEV;
 235         }
 236
 237         if (regmap_write(mc_vbase, A10_SERRCNTREG_OFST, 1)) {
 238                 edac_printk(KERN_ERR, EDAC_MC,
 239                             "Error setting trigger count\n");
 240                 return -ENODEV;
 241         }
 242
 243         return 0;
 244 }
 245
 246 static int a10_unmask_irq(struct platform_device *pdev, u32 mask)
 247 {
 248         void __iomem  *sm_base;
 249         int  ret = 0;
 250
 251         if (!request_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32),
 252                                 dev_name(&pdev->dev))) {
 253                 edac_printk(KERN_ERR, EDAC_MC,
 254                             "Unable to request mem region\n");
 255                 return -EBUSY;
 256         }
 257
 258         sm_base = ioremap(A10_SYMAN_INTMASK_CLR, sizeof(u32));
 259         if (!sm_base) {
 260                 edac_printk(KERN_ERR, EDAC_MC,
 261                             "Unable to ioremap device\n");
 262
 263                 ret = -ENOMEM;
 264                 goto release;
 265         }
 266
 267         iowrite32(mask, sm_base);
 268
 269         iounmap(sm_base);
 270
 271 release:
 272         release_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32));
 273
 274         return ret;
 275 }
 276
 277 static int socfpga_is_a10(void);
 278 static int altr_sdram_probe(struct platform_device *pdev)
 279 {
 280         const struct of_device_id *id;
 281         struct edac_mc_layer layers[2];
 282         struct mem_ctl_info *mci;
 283         struct altr_sdram_mc_data *drvdata;
 284         const struct altr_sdram_prv_data *priv;
 285         struct regmap *mc_vbase;
 286         struct dimm_info *dimm;
 287         u32 read_reg;
 288         int irq, irq2, res = 0;
 289         unsigned long mem_size, irqflags = 0;
 290
 291         id = of_match_device(altr_sdram_ctrl_of_match, &pdev->dev);
 292         if (!id)
 293                 return -ENODEV;
 294
 295         /* Grab the register range from the sdr controller in device tree */
 296         mc_vbase = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
 297                                                    "altr,sdr-syscon");
 298         if (IS_ERR(mc_vbase)) {
 299                 edac_printk(KERN_ERR, EDAC_MC,
 300                             "regmap for altr,sdr-syscon lookup failed.\n");
 301                 return -ENODEV;
 302         }
 303
 304         /* Check specific dependencies for the module */
 305         priv = of_match_node(altr_sdram_ctrl_of_match,
 306                              pdev->dev.of_node)->data;
 307
 308         /* Validate the SDRAM controller has ECC enabled */
 309         if (regmap_read(mc_vbase, priv->ecc_ctrl_offset, &read_reg) ||
 310             ((read_reg & priv->ecc_ctl_en_mask) != priv->ecc_ctl_en_mask)) {
 311                 edac_printk(KERN_ERR, EDAC_MC,
 312                             "No ECC/ECC disabled [0x%08X]\n", read_reg);
 313                 return -ENODEV;
 314         }
 315
 316         /* Grab memory size from device tree. */
 317         mem_size = get_total_mem();
 318         if (!mem_size) {
 319                 edac_printk(KERN_ERR, EDAC_MC, "Unable to calculate memory size\n");
 320                 return -ENODEV;
 321         }
 322
 323         /* Ensure the SDRAM Interrupt is disabled */
 324         if (regmap_update_bits(mc_vbase, priv->ecc_irq_en_offset,
 325                                priv->ecc_irq_en_mask, 0)) {
 326                 edac_printk(KERN_ERR, EDAC_MC,
 327                             "Error disabling SDRAM ECC IRQ\n");
 328                 return -ENODEV;
 329         }
 330
 331         /* Toggle to clear the SDRAM Error count */
 332         if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset,
 333                                priv->ecc_cnt_rst_mask,
 334                                priv->ecc_cnt_rst_mask)) {
 335                 edac_printk(KERN_ERR, EDAC_MC,
 336                             "Error clearing SDRAM ECC count\n");
 337                 return -ENODEV;
 338         }
 339
 340         if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset,
 341                                priv->ecc_cnt_rst_mask, 0)) {
 342                 edac_printk(KERN_ERR, EDAC_MC,
 343                             "Error clearing SDRAM ECC count\n");
 344                 return -ENODEV;
 345         }
 346
 347         irq = platform_get_irq(pdev, 0);
 348         if (irq < 0) {
 349                 edac_printk(KERN_ERR, EDAC_MC,
 350                             "No irq %d in DT\n", irq);
 351                 return -ENODEV;
 352         }
 353
 354         /* Arria10 has a 2nd IRQ */
 355         irq2 = platform_get_irq(pdev, 1);
 356
 357         layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
 358         layers[0].size = 1;
 359         layers[0].is_virt_csrow = true;
 360         layers[1].type = EDAC_MC_LAYER_CHANNEL;
 361         layers[1].size = 1;
 362         layers[1].is_virt_csrow = false;
 363         mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
 364                             sizeof(struct altr_sdram_mc_data));
 365         if (!mci)
 366                 return -ENOMEM;
 367
 368         mci->pdev = &pdev->dev;
 369         drvdata = mci->pvt_info;
 370         drvdata->mc_vbase = mc_vbase;
 371         drvdata->data = priv;
 372         platform_set_drvdata(pdev, mci);
 373
 374         if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) {
 375                 edac_printk(KERN_ERR, EDAC_MC,
 376                             "Unable to get managed device resource\n");
 377                 res = -ENOMEM;
 378                 goto free;
 379         }
 380
 381         mci->mtype_cap = MEM_FLAG_DDR3;
 382         mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
 383         mci->edac_cap = EDAC_FLAG_SECDED;
 384         mci->mod_name = EDAC_MOD_STR;
 385         mci->ctl_name = dev_name(&pdev->dev);
 386         mci->scrub_mode = SCRUB_SW_SRC;
 387         mci->dev_name = dev_name(&pdev->dev);
 388
 389         dimm = *mci->dimms;
 390         dimm->nr_pages = ((mem_size - 1) >> PAGE_SHIFT) + 1;
 391         dimm->grain = 8;
 392         dimm->dtype = DEV_X8;
 393         dimm->mtype = MEM_DDR3;
 394         dimm->edac_mode = EDAC_SECDED;
 395
 396         res = edac_mc_add_mc(mci);
 397         if (res < 0)
 398                 goto err;
 399
 400         /* Only the Arria10 has separate IRQs */
 401         if (socfpga_is_a10()) {
 402                 /* Arria10 specific initialization */
 403                 res = a10_init(mc_vbase);
 404                 if (res < 0)
 405                         goto err2;
 406
 407                 res = devm_request_irq(&pdev->dev, irq2,
 408                                        altr_sdram_mc_err_handler,
 409                                        IRQF_SHARED, dev_name(&pdev->dev), mci);
 410                 if (res < 0) {
 411                         edac_mc_printk(mci, KERN_ERR,
 412                                        "Unable to request irq %d\n", irq2);
 413                         res = -ENODEV;
 414                         goto err2;
 415                 }
 416
 417                 res = a10_unmask_irq(pdev, A10_DDR0_IRQ_MASK);
 418                 if (res < 0)
 419                         goto err2;
 420
 421                 irqflags = IRQF_SHARED;
 422         }
 423
 424         res = devm_request_irq(&pdev->dev, irq, altr_sdram_mc_err_handler,
 425                                irqflags, dev_name(&pdev->dev), mci);
 426         if (res < 0) {
 427                 edac_mc_printk(mci, KERN_ERR,
 428                                "Unable to request irq %d\n", irq);
 429                 res = -ENODEV;
 430                 goto err2;
 431         }
 432
 433         /* Infrastructure ready - enable the IRQ */
 434         if (regmap_update_bits(drvdata->mc_vbase, priv->ecc_irq_en_offset,
 435                                priv->ecc_irq_en_mask, priv->ecc_irq_en_mask)) {
 436                 edac_mc_printk(mci, KERN_ERR,
 437                                "Error enabling SDRAM ECC IRQ\n");
 438                 res = -ENODEV;
 439                 goto err2;
 440         }
 441
 442         altr_sdr_mc_create_debugfs_nodes(mci);
 443
 444         devres_close_group(&pdev->dev, NULL);
 445
 446         return 0;
 447
 448 err2:
 449         edac_mc_del_mc(&pdev->dev);
 450 err:
 451         devres_release_group(&pdev->dev, NULL);
 452 free:
 453         edac_mc_free(mci);
 454         edac_printk(KERN_ERR, EDAC_MC,
 455                     "EDAC Probe Failed; Error %d\n", res);
 456
 457         return res;
 458 }
 459
 460 static int altr_sdram_remove(struct platform_device *pdev)
 461 {
 462         struct mem_ctl_info *mci = platform_get_drvdata(pdev);
 463
 464         edac_mc_del_mc(&pdev->dev);
 465         edac_mc_free(mci);
 466         platform_set_drvdata(pdev, NULL);
 467
 468         return 0;
 469 }
 470
 471 /**************** Stratix 10 EDAC Memory Controller Functions ************/
 472
 473 /**
 474  * s10_protected_reg_write
 475  * Write to a protected SMC register.
 476  * @context: Not used.
 477  * @reg: Address of register
 478  * @value: Value to write
 479  * Return: INTEL_SIP_SMC_STATUS_OK (0) on success
 480  *         INTEL_SIP_SMC_REG_ERROR on error
 481  *         INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION if not supported
 482  */
 483 static int s10_protected_reg_write(void *context, unsigned int reg,
 484                                    unsigned int val)
 485 {
 486         struct arm_smccc_res result;
 487         unsigned long offset = (unsigned long)context;
 488
 489         arm_smccc_smc(INTEL_SIP_SMC_REG_WRITE, offset + reg, val, 0, 0,
 490                       0, 0, 0, &result);
 491
 492         return (int)result.a0;
 493 }
 494
 495 /**
 496  * s10_protected_reg_read
 497  * Read the status of a protected SMC register
 498  * @context: Not used.
 499  * @reg: Address of register
 500  * @value: Value read.
 501  * Return: INTEL_SIP_SMC_STATUS_OK (0) on success
 502  *         INTEL_SIP_SMC_REG_ERROR on error
 503  *         INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION if not supported
 504  */
 505 static int s10_protected_reg_read(void *context, unsigned int reg,
 506                                   unsigned int *val)
 507 {
 508         struct arm_smccc_res result;
 509         unsigned long offset = (unsigned long)context;
 510
 511         arm_smccc_smc(INTEL_SIP_SMC_REG_READ, offset + reg, 0, 0, 0,
 512                       0, 0, 0, &result);
 513
 514         *val = (unsigned int)result.a1;
 515
 516         return (int)result.a0;
 517 }
 518
 519 static const struct regmap_config s10_sdram_regmap_cfg = {
 520         .name = "s10_ddr",
 521         .reg_bits = 32,
 522         .reg_stride = 4,
 523         .val_bits = 32,
 524         .max_register = 0xffd12228,
 525         .reg_read = s10_protected_reg_read,
 526         .reg_write = s10_protected_reg_write,
 527         .use_single_read = true,
 528         .use_single_write = true,
 529 };
 530
 531 /************** </Stratix10 EDAC Memory Controller Functions> ***********/
 532
 533 /*
 534  * If you want to suspend, need to disable EDAC by removing it
 535  * from the device tree or defconfig.
 536  */
 537 #ifdef CONFIG_PM
 538 static int altr_sdram_prepare(struct device *dev)
 539 {
 540         pr_err("Suspend not allowed when EDAC is enabled.\n");
 541
 542         return -EPERM;
 543 }
 544
 545 static const struct dev_pm_ops altr_sdram_pm_ops = {
 546         .prepare = altr_sdram_prepare,
 547 };
 548 #endif
 549
 550 static struct platform_driver altr_sdram_edac_driver = {
 551         .probe = altr_sdram_probe,
 552         .remove = altr_sdram_remove,
 553         .driver = {
 554                 .name = "altr_sdram_edac",
 555 #ifdef CONFIG_PM
 556                 .pm = &altr_sdram_pm_ops,
 557 #endif
 558                 .of_match_table = altr_sdram_ctrl_of_match,
 559         },
 560 };
 561
 562 module_platform_driver(altr_sdram_edac_driver);
 563
 564 /************************* EDAC Parent Probe *************************/
 565
 566 static const struct of_device_id altr_edac_device_of_match[];
 567
 568 static const struct of_device_id altr_edac_of_match[] = {
 569         { .compatible = "altr,socfpga-ecc-manager" },
 570         {},
 571 };
 572 MODULE_DEVICE_TABLE(of, altr_edac_of_match);
 573
 574 static int altr_edac_probe(struct platform_device *pdev)
 575 {
 576         of_platform_populate(pdev->dev.of_node, altr_edac_device_of_match,
 577                              NULL, &pdev->dev);
 578         return 0;
 579 }
 580
 581 static struct platform_driver altr_edac_driver = {
 582         .probe =  altr_edac_probe,
 583         .driver = {
 584                 .name = "socfpga_ecc_manager",
 585                 .of_match_table = altr_edac_of_match,
 586         },
 587 };
 588 module_platform_driver(altr_edac_driver);
 589
 590 /************************* EDAC Device Functions *************************/
 591
 592 /*
 593  * EDAC Device Functions (shared between various IPs).
 594  * The discrete memories use the EDAC Device framework. The probe
 595  * and error handling functions are very similar between memories
 596  * so they are shared. The memory allocation and freeing for EDAC
 597  * trigger testing are different for each memory.
 598  */
 599
 600 static const struct edac_device_prv_data ocramecc_data;
 601 static const struct edac_device_prv_data l2ecc_data;
 602 static const struct edac_device_prv_data a10_ocramecc_data;
 603 static const struct edac_device_prv_data a10_l2ecc_data;
 604
 605 static irqreturn_t altr_edac_device_handler(int irq, void *dev_id)
 606 {
 607         irqreturn_t ret_value = IRQ_NONE;
 608         struct edac_device_ctl_info *dci = dev_id;
 609         struct altr_edac_device_dev *drvdata = dci->pvt_info;
 610         const struct edac_device_prv_data *priv = drvdata->data;
 611
 612         if (irq == drvdata->sb_irq) {
 613                 if (priv->ce_clear_mask)
 614                         writel(priv->ce_clear_mask, drvdata->base);
 615                 edac_device_handle_ce(dci, 0, 0, drvdata->edac_dev_name);
 616                 ret_value = IRQ_HANDLED;
 617         } else if (irq == drvdata->db_irq) {
 618                 if (priv->ue_clear_mask)
 619                         writel(priv->ue_clear_mask, drvdata->base);
 620                 edac_device_handle_ue(dci, 0, 0, drvdata->edac_dev_name);
 621                 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
 622                 ret_value = IRQ_HANDLED;
 623         } else {
 624                 WARN_ON(1);
 625         }
 626
 627         return ret_value;
 628 }
 629
 630 static ssize_t altr_edac_device_trig(struct file *file,
 631                                      const char __user *user_buf,
 632                                      size_t count, loff_t *ppos)
 633
 634 {
 635         u32 *ptemp, i, error_mask;
 636         int result = 0;
 637         u8 trig_type;
 638         unsigned long flags;
 639         struct edac_device_ctl_info *edac_dci = file->private_data;
 640         struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
 641         const struct edac_device_prv_data *priv = drvdata->data;
 642         void *generic_ptr = edac_dci->dev;
 643
 644         if (!user_buf || get_user(trig_type, user_buf))
 645                 return -EFAULT;
 646
 647         if (!priv->alloc_mem)
 648                 return -ENOMEM;
 649
 650         /*
 651          * Note that generic_ptr is initialized to the device * but in
 652          * some alloc_functions, this is overridden and returns data.
 653          */
 654         ptemp = priv->alloc_mem(priv->trig_alloc_sz, &generic_ptr);
 655         if (!ptemp) {
 656                 edac_printk(KERN_ERR, EDAC_DEVICE,
 657                             "Inject: Buffer Allocation error\n");
 658                 return -ENOMEM;
 659         }
 660
 661         if (trig_type == ALTR_UE_TRIGGER_CHAR)
 662                 error_mask = priv->ue_set_mask;
 663         else
 664                 error_mask = priv->ce_set_mask;
 665
 666         edac_printk(KERN_ALERT, EDAC_DEVICE,
 667                     "Trigger Error Mask (0x%X)\n", error_mask);
 668
 669         local_irq_save(flags);
 670         /* write ECC corrupted data out. */
 671         for (i = 0; i < (priv->trig_alloc_sz / sizeof(*ptemp)); i++) {
 672                 /* Read data so we're in the correct state */
 673                 rmb();
 674                 if (READ_ONCE(ptemp[i]))
 675                         result = -1;
 676                 /* Toggle Error bit (it is latched), leave ECC enabled */
 677                 writel(error_mask, (drvdata->base + priv->set_err_ofst));
 678                 writel(priv->ecc_enable_mask, (drvdata->base +
 679                                                priv->set_err_ofst));
 680                 ptemp[i] = i;
 681         }
 682         /* Ensure it has been written out */
 683         wmb();
 684         local_irq_restore(flags);
 685
 686         if (result)
 687                 edac_printk(KERN_ERR, EDAC_DEVICE, "Mem Not Cleared\n");
 688
 689         /* Read out written data. ECC error caused here */
 690         for (i = 0; i < ALTR_TRIGGER_READ_WRD_CNT; i++)
 691                 if (READ_ONCE(ptemp[i]) != i)
 692                         edac_printk(KERN_ERR, EDAC_DEVICE,
 693                                     "Read doesn't match written data\n");
 694
 695         if (priv->free_mem)
 696                 priv->free_mem(ptemp, priv->trig_alloc_sz, generic_ptr);
 697
 698         return count;
 699 }
 700
 701 static const struct file_operations altr_edac_device_inject_fops = {
 702         .open = simple_open,
 703         .write = altr_edac_device_trig,
 704         .llseek = generic_file_llseek,
 705 };
 706
 707 static ssize_t altr_edac_a10_device_trig(struct file *file,
 708                                          const char __user *user_buf,
 709                                          size_t count, loff_t *ppos);
 710
 711 static const struct file_operations altr_edac_a10_device_inject_fops = {
 712         .open = simple_open,
 713         .write = altr_edac_a10_device_trig,
 714         .llseek = generic_file_llseek,
 715 };
 716
 717 static ssize_t altr_edac_a10_device_trig2(struct file *file,
 718                                           const char __user *user_buf,
 719                                           size_t count, loff_t *ppos);
 720
 721 static const struct file_operations altr_edac_a10_device_inject2_fops = {
 722         .open = simple_open,
 723         .write = altr_edac_a10_device_trig2,
 724         .llseek = generic_file_llseek,
 725 };
 726
 727 static void altr_create_edacdev_dbgfs(struct edac_device_ctl_info *edac_dci,
 728                                       const struct edac_device_prv_data *priv)
 729 {
 730         struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
 731
 732         if (!IS_ENABLED(CONFIG_EDAC_DEBUG))
 733                 return;
 734
 735         drvdata->debugfs_dir = edac_debugfs_create_dir(drvdata->edac_dev_name);
 736         if (!drvdata->debugfs_dir)
 737                 return;
 738
 739         if (!edac_debugfs_create_file("altr_trigger", S_IWUSR,
 740                                       drvdata->debugfs_dir, edac_dci,
 741                                       priv->inject_fops))
 742                 debugfs_remove_recursive(drvdata->debugfs_dir);
 743 }
 744
 745 static const struct of_device_id altr_edac_device_of_match[] = {
 746 #ifdef CONFIG_EDAC_ALTERA_L2C
 747         { .compatible = "altr,socfpga-l2-ecc", .data = &l2ecc_data },
 748 #endif
 749 #ifdef CONFIG_EDAC_ALTERA_OCRAM
 750         { .compatible = "altr,socfpga-ocram-ecc", .data = &ocramecc_data },
 751 #endif
 752         {},
 753 };
 754 MODULE_DEVICE_TABLE(of, altr_edac_device_of_match);
 755
 756 /*
 757  * altr_edac_device_probe()
 758  *      This is a generic EDAC device driver that will support
 759  *      various Altera memory devices such as the L2 cache ECC and
 760  *      OCRAM ECC as well as the memories for other peripherals.
 761  *      Module specific initialization is done by passing the
 762  *      function index in the device tree.
 763  */
 764 static int altr_edac_device_probe(struct platform_device *pdev)
 765 {
 766         struct edac_device_ctl_info *dci;
 767         struct altr_edac_device_dev *drvdata;
 768         struct resource *r;
 769         int res = 0;
 770         struct device_node *np = pdev->dev.of_node;
 771         char *ecc_name = (char *)np->name;
 772         static int dev_instance;
 773
 774         if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) {
 775                 edac_printk(KERN_ERR, EDAC_DEVICE,
 776                             "Unable to open devm\n");
 777                 return -ENOMEM;
 778         }
 779
 780         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 781         if (!r) {
 782                 edac_printk(KERN_ERR, EDAC_DEVICE,
 783                             "Unable to get mem resource\n");
 784                 res = -ENODEV;
 785                 goto fail;
 786         }
 787
 788         if (!devm_request_mem_region(&pdev->dev, r->start, resource_size(r),
 789                                      dev_name(&pdev->dev))) {
 790                 edac_printk(KERN_ERR, EDAC_DEVICE,
 791                             "%s:Error requesting mem region\n", ecc_name);
 792                 res = -EBUSY;
 793                 goto fail;
 794         }
 795
 796         dci = edac_device_alloc_ctl_info(sizeof(*drvdata), ecc_name,
 797                                          1, ecc_name, 1, 0, NULL, 0,
 798                                          dev_instance++);
 799
 800         if (!dci) {
 801                 edac_printk(KERN_ERR, EDAC_DEVICE,
 802                             "%s: Unable to allocate EDAC device\n", ecc_name);
 803                 res = -ENOMEM;
 804                 goto fail;
 805         }
 806
 807         drvdata = dci->pvt_info;
 808         dci->dev = &pdev->dev;
 809         platform_set_drvdata(pdev, dci);
 810         drvdata->edac_dev_name = ecc_name;
 811
 812         drvdata->base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
 813         if (!drvdata->base) {
 814                 res = -ENOMEM;
 815                 goto fail1;
 816         }
 817
 818         /* Get driver specific data for this EDAC device */
 819         drvdata->data = of_match_node(altr_edac_device_of_match, np)->data;
 820
 821         /* Check specific dependencies for the module */
 822         if (drvdata->data->setup) {
 823                 res = drvdata->data->setup(drvdata);
 824                 if (res)
 825                         goto fail1;
 826         }
 827
 828         drvdata->sb_irq = platform_get_irq(pdev, 0);
 829         res = devm_request_irq(&pdev->dev, drvdata->sb_irq,
 830                                altr_edac_device_handler,
 831                                0, dev_name(&pdev->dev), dci);
 832         if (res)
 833                 goto fail1;
 834
 835         drvdata->db_irq = platform_get_irq(pdev, 1);
 836         res = devm_request_irq(&pdev->dev, drvdata->db_irq,
 837                                altr_edac_device_handler,
 838                                0, dev_name(&pdev->dev), dci);
 839         if (res)
 840                 goto fail1;
 841
 842         dci->mod_name = "Altera ECC Manager";
 843         dci->dev_name = drvdata->edac_dev_name;
 844
 845         res = edac_device_add_device(dci);
 846         if (res)
 847                 goto fail1;
 848
 849         altr_create_edacdev_dbgfs(dci, drvdata->data);
 850
 851         devres_close_group(&pdev->dev, NULL);
 852
 853         return 0;
 854
 855 fail1:
 856         edac_device_free_ctl_info(dci);
 857 fail:
 858         devres_release_group(&pdev->dev, NULL);
 859         edac_printk(KERN_ERR, EDAC_DEVICE,
 860                     "%s:Error setting up EDAC device: %d\n", ecc_name, res);
 861
 862         return res;
 863 }
 864
 865 static int altr_edac_device_remove(struct platform_device *pdev)
 866 {
 867         struct edac_device_ctl_info *dci = platform_get_drvdata(pdev);
 868         struct altr_edac_device_dev *drvdata = dci->pvt_info;
 869
 870         debugfs_remove_recursive(drvdata->debugfs_dir);
 871         edac_device_del_device(&pdev->dev);
 872         edac_device_free_ctl_info(dci);
 873
 874         return 0;
 875 }
 876
 877 static struct platform_driver altr_edac_device_driver = {
 878         .probe =  altr_edac_device_probe,
 879         .remove = altr_edac_device_remove,
 880         .driver = {
 881                 .name = "altr_edac_device",
 882                 .of_match_table = altr_edac_device_of_match,
 883         },
 884 };
 885 module_platform_driver(altr_edac_device_driver);
 886
 887 /******************* Arria10 Device ECC Shared Functions *****************/
 888
 889 /*
 890  *  Test for memory's ECC dependencies upon entry because platform specific
 891  *  startup should have initialized the memory and enabled the ECC.
 892  *  Can't turn on ECC here because accessing un-initialized memory will
 893  *  cause CE/UE errors possibly causing an ABORT.
 894  */
 895 static int __maybe_unused
 896 altr_check_ecc_deps(struct altr_edac_device_dev *device)
 897 {
 898         void __iomem  *base = device->base;
 899         const struct edac_device_prv_data *prv = device->data;
 900
 901         if (readl(base + prv->ecc_en_ofst) & prv->ecc_enable_mask)
 902                 return 0;
 903
 904         edac_printk(KERN_ERR, EDAC_DEVICE,
 905                     "%s: No ECC present or ECC disabled.\n",
 906                     device->edac_dev_name);
 907         return -ENODEV;
 908 }
 909
 910 static irqreturn_t __maybe_unused altr_edac_a10_ecc_irq(int irq, void *dev_id)
 911 {
 912         struct altr_edac_device_dev *dci = dev_id;
 913         void __iomem  *base = dci->base;
 914
 915         if (irq == dci->sb_irq) {
 916                 writel(ALTR_A10_ECC_SERRPENA,
 917                        base + ALTR_A10_ECC_INTSTAT_OFST);
 918                 edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name);
 919
 920                 return IRQ_HANDLED;
 921         } else if (irq == dci->db_irq) {
 922                 writel(ALTR_A10_ECC_DERRPENA,
 923                        base + ALTR_A10_ECC_INTSTAT_OFST);
 924                 edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name);
 925                 if (dci->data->panic)
 926                         panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
 927
 928                 return IRQ_HANDLED;
 929         }
 930
 931         WARN_ON(1);
 932
 933         return IRQ_NONE;
 934 }
 935
 936 /******************* Arria10 Memory Buffer Functions *********************/
 937
 938 static inline int a10_get_irq_mask(struct device_node *np)
 939 {
 940         int irq;
 941         const u32 *handle = of_get_property(np, "interrupts", NULL);
 942
 943         if (!handle)
 944                 return -ENODEV;
 945         irq = be32_to_cpup(handle);
 946         return irq;
 947 }
 948
 949 static inline void ecc_set_bits(u32 bit_mask, void __iomem *ioaddr)
 950 {
 951         u32 value = readl(ioaddr);
 952
 953         value |= bit_mask;
 954         writel(value, ioaddr);
 955 }
 956
 957 static inline void ecc_clear_bits(u32 bit_mask, void __iomem *ioaddr)
 958 {
 959         u32 value = readl(ioaddr);
 960
 961         value &= ~bit_mask;
 962         writel(value, ioaddr);
 963 }
 964
 965 static inline int ecc_test_bits(u32 bit_mask, void __iomem *ioaddr)
 966 {
 967         u32 value = readl(ioaddr);
 968
 969         return (value & bit_mask) ? 1 : 0;
 970 }
 971
 972 /*
 973  * This function uses the memory initialization block in the Arria10 ECC
 974  * controller to initialize/clear the entire memory data and ECC data.
 975  */
 976 static int __maybe_unused altr_init_memory_port(void __iomem *ioaddr, int port)
 977 {
 978         int limit = ALTR_A10_ECC_INIT_WATCHDOG_10US;
 979         u32 init_mask, stat_mask, clear_mask;
 980         int ret = 0;
 981
 982         if (port) {
 983                 init_mask = ALTR_A10_ECC_INITB;
 984                 stat_mask = ALTR_A10_ECC_INITCOMPLETEB;
 985                 clear_mask = ALTR_A10_ECC_ERRPENB_MASK;
 986         } else {
 987                 init_mask = ALTR_A10_ECC_INITA;
 988                 stat_mask = ALTR_A10_ECC_INITCOMPLETEA;
 989                 clear_mask = ALTR_A10_ECC_ERRPENA_MASK;
 990         }
 991
 992         ecc_set_bits(init_mask, (ioaddr + ALTR_A10_ECC_CTRL_OFST));
 993         while (limit--) {
 994                 if (ecc_test_bits(stat_mask,
 995                                   (ioaddr + ALTR_A10_ECC_INITSTAT_OFST)))
 996                         break;
 997                 udelay(1);
 998         }
 999         if (limit < 0)
1000                 ret = -EBUSY;
1001
1002         /* Clear any pending ECC interrupts */
1003         writel(clear_mask, (ioaddr + ALTR_A10_ECC_INTSTAT_OFST));
1004
1005         return ret;
1006 }
1007
1008 static int socfpga_is_a10(void)
1009 {
1010         return of_machine_is_compatible("altr,socfpga-arria10");
1011 }
1012
1013 static int socfpga_is_s10(void)
1014 {
1015         return of_machine_is_compatible("altr,socfpga-stratix10");
1016 }
1017
1018 static __init int __maybe_unused
1019 altr_init_a10_ecc_block(struct device_node *np, u32 irq_mask,
1020                         u32 ecc_ctrl_en_mask, bool dual_port)
1021 {
1022         int ret = 0;
1023         void __iomem *ecc_block_base;
1024         struct regmap *ecc_mgr_map;
1025         char *ecc_name;
1026         struct device_node *np_eccmgr;
1027
1028         ecc_name = (char *)np->name;
1029
1030         /* Get the ECC Manager - parent of the device EDACs */
1031         np_eccmgr = of_get_parent(np);
1032
1033         if (socfpga_is_a10()) {
1034                 ecc_mgr_map = syscon_regmap_lookup_by_phandle(np_eccmgr,
1035                                                               "altr,sysmgr-syscon");
1036         } else {
1037                 struct device_node *sysmgr_np;
1038                 struct resource res;
1039                 uintptr_t base;
1040
1041                 sysmgr_np = of_parse_phandle(np_eccmgr,
1042                                              "altr,sysmgr-syscon", 0);
1043                 if (!sysmgr_np) {
1044                         edac_printk(KERN_ERR, EDAC_DEVICE,
1045                                     "Unable to find altr,sysmgr-syscon\n");
1046                         return -ENODEV;
1047                 }
1048
1049                 if (of_address_to_resource(sysmgr_np, 0, &res))
1050                         return -ENOMEM;
1051
1052                 /* Need physical address for SMCC call */
1053                 base = res.start;
1054
1055                 ecc_mgr_map = regmap_init(NULL, NULL, (void *)base,
1056                                           &s10_sdram_regmap_cfg);
1057         }
1058         of_node_put(np_eccmgr);
1059         if (IS_ERR(ecc_mgr_map)) {
1060                 edac_printk(KERN_ERR, EDAC_DEVICE,
1061                             "Unable to get syscon altr,sysmgr-syscon\n");
1062                 return -ENODEV;
1063         }
1064
1065         /* Map the ECC Block */
1066         ecc_block_base = of_iomap(np, 0);
1067         if (!ecc_block_base) {
1068                 edac_printk(KERN_ERR, EDAC_DEVICE,
1069                             "Unable to map %s ECC block\n", ecc_name);
1070                 return -ENODEV;
1071         }
1072
1073         /* Disable ECC */
1074         regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST, irq_mask);
1075         writel(ALTR_A10_ECC_SERRINTEN,
1076                (ecc_block_base + ALTR_A10_ECC_ERRINTENR_OFST));
1077         ecc_clear_bits(ecc_ctrl_en_mask,
1078                        (ecc_block_base + ALTR_A10_ECC_CTRL_OFST));
1079         /* Ensure all writes complete */
1080         wmb();
1081         /* Use HW initialization block to initialize memory for ECC */
1082         ret = altr_init_memory_port(ecc_block_base, 0);
1083         if (ret) {
1084                 edac_printk(KERN_ERR, EDAC_DEVICE,
1085                             "ECC: cannot init %s PORTA memory\n", ecc_name);
1086                 goto out;
1087         }
1088
1089         if (dual_port) {
1090                 ret = altr_init_memory_port(ecc_block_base, 1);
1091                 if (ret) {
1092                         edac_printk(KERN_ERR, EDAC_DEVICE,
1093                                     "ECC: cannot init %s PORTB memory\n",
1094                                     ecc_name);
1095                         goto out;
1096                 }
1097         }
1098
1099         /* Interrupt mode set to every SBERR */
1100         regmap_write(ecc_mgr_map, ALTR_A10_ECC_INTMODE_OFST,
1101                      ALTR_A10_ECC_INTMODE);
1102         /* Enable ECC */
1103         ecc_set_bits(ecc_ctrl_en_mask, (ecc_block_base +
1104                                         ALTR_A10_ECC_CTRL_OFST));
1105         writel(ALTR_A10_ECC_SERRINTEN,
1106                (ecc_block_base + ALTR_A10_ECC_ERRINTENS_OFST));
1107         regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_CLR_OFST, irq_mask);
1108         /* Ensure all writes complete */
1109         wmb();
1110 out:
1111         iounmap(ecc_block_base);
1112         return ret;
1113 }
1114
1115 static int validate_parent_available(struct device_node *np);
1116 static const struct of_device_id altr_edac_a10_device_of_match[];
1117 static int __init __maybe_unused altr_init_a10_ecc_device_type(char *compat)
1118 {
1119         int irq;
1120         struct device_node *child, *np;
1121
1122         if (!socfpga_is_a10() && !socfpga_is_s10())
1123                 return -ENODEV;
1124
1125         np = of_find_compatible_node(NULL, NULL,
1126                                      "altr,socfpga-a10-ecc-manager");
1127         if (!np) {
1128                 edac_printk(KERN_ERR, EDAC_DEVICE, "ECC Manager not found\n");
1129                 return -ENODEV;
1130         }
1131
1132         for_each_child_of_node(np, child) {
1133                 const struct of_device_id *pdev_id;
1134                 const struct edac_device_prv_data *prv;
1135
1136                 if (!of_device_is_available(child))
1137                         continue;
1138                 if (!of_device_is_compatible(child, compat))
1139                         continue;
1140
1141                 if (validate_parent_available(child))
1142                         continue;
1143
1144                 irq = a10_get_irq_mask(child);
1145                 if (irq < 0)
1146                         continue;
1147
1148                 /* Get matching node and check for valid result */
1149                 pdev_id = of_match_node(altr_edac_a10_device_of_match, child);
1150                 if (IS_ERR_OR_NULL(pdev_id))
1151                         continue;
1152
1153                 /* Validate private data pointer before dereferencing */
1154                 prv = pdev_id->data;
1155                 if (!prv)
1156                         continue;
1157
1158                 altr_init_a10_ecc_block(child, BIT(irq),
1159                                         prv->ecc_enable_mask, 0);
1160         }
1161
1162         of_node_put(np);
1163         return 0;
1164 }
1165
1166 /*********************** OCRAM EDAC Device Functions *********************/
1167
1168 #ifdef CONFIG_EDAC_ALTERA_OCRAM
1169
1170 static void *ocram_alloc_mem(size_t size, void **other)
1171 {
1172         struct device_node *np;
1173         struct gen_pool *gp;
1174         void *sram_addr;
1175
1176         np = of_find_compatible_node(NULL, NULL, "altr,socfpga-ocram-ecc");
1177         if (!np)
1178                 return NULL;
1179
1180         gp = of_gen_pool_get(np, "iram", 0);
1181         of_node_put(np);
1182         if (!gp)
1183                 return NULL;
1184
1185         sram_addr = (void *)gen_pool_alloc(gp, size);
1186         if (!sram_addr)
1187                 return NULL;
1188
1189         memset(sram_addr, 0, size);
1190         /* Ensure data is written out */
1191         wmb();
1192
1193         /* Remember this handle for freeing  later */
1194         *other = gp;
1195
1196         return sram_addr;
1197 }
1198
1199 static void ocram_free_mem(void *p, size_t size, void *other)
1200 {
1201         gen_pool_free((struct gen_pool *)other, (unsigned long)p, size);
1202 }
1203
1204 static const struct edac_device_prv_data ocramecc_data = {
1205         .setup = altr_check_ecc_deps,
1206         .ce_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_SERR),
1207         .ue_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_DERR),
1208         .alloc_mem = ocram_alloc_mem,
1209         .free_mem = ocram_free_mem,
1210         .ecc_enable_mask = ALTR_OCR_ECC_EN,
1211         .ecc_en_ofst = ALTR_OCR_ECC_REG_OFFSET,
1212         .ce_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJS),
1213         .ue_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJD),
1214         .set_err_ofst = ALTR_OCR_ECC_REG_OFFSET,
1215         .trig_alloc_sz = ALTR_TRIG_OCRAM_BYTE_SIZE,
1216         .inject_fops = &altr_edac_device_inject_fops,
1217 };
1218
1219 static const struct edac_device_prv_data a10_ocramecc_data = {
1220         .setup = altr_check_ecc_deps,
1221         .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1222         .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1223         .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_OCRAM,
1224         .ecc_enable_mask = ALTR_A10_OCRAM_ECC_EN_CTL,
1225         .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1226         .ce_set_mask = ALTR_A10_ECC_TSERRA,
1227         .ue_set_mask = ALTR_A10_ECC_TDERRA,
1228         .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1229         .ecc_irq_handler = altr_edac_a10_ecc_irq,
1230         .inject_fops = &altr_edac_a10_device_inject_fops,
1231         /*
1232          * OCRAM panic on uncorrectable error because sleep/resume
1233          * functions and FPGA contents are stored in OCRAM. Prefer
1234          * a kernel panic over executing/loading corrupted data.
1235          */
1236         .panic = true,
1237 };
1238
1239 #endif  /* CONFIG_EDAC_ALTERA_OCRAM */
1240
1241 /********************* L2 Cache EDAC Device Functions ********************/
1242
1243 #ifdef CONFIG_EDAC_ALTERA_L2C
1244
1245 static void *l2_alloc_mem(size_t size, void **other)
1246 {
1247         struct device *dev = *other;
1248         void *ptemp = devm_kzalloc(dev, size, GFP_KERNEL);
1249
1250         if (!ptemp)
1251                 return NULL;
1252
1253         /* Make sure everything is written out */
1254         wmb();
1255
1256         /*
1257          * Clean all cache levels up to LoC (includes L2)
1258          * This ensures the corrupted data is written into
1259          * L2 cache for readback test (which causes ECC error).
1260          */
1261         flush_cache_all();
1262
1263         return ptemp;
1264 }
1265
1266 static void l2_free_mem(void *p, size_t size, void *other)
1267 {
1268         struct device *dev = other;
1269
1270         if (dev && p)
1271                 devm_kfree(dev, p);
1272 }
1273
1274 /*
1275  * altr_l2_check_deps()
1276  *      Test for L2 cache ECC dependencies upon entry because
1277  *      platform specific startup should have initialized the L2
1278  *      memory and enabled the ECC.
1279  *      Bail if ECC is not enabled.
1280  *      Note that L2 Cache Enable is forced at build time.
1281  */
1282 static int altr_l2_check_deps(struct altr_edac_device_dev *device)
1283 {
1284         void __iomem *base = device->base;
1285         const struct edac_device_prv_data *prv = device->data;
1286
1287         if ((readl(base) & prv->ecc_enable_mask) ==
1288              prv->ecc_enable_mask)
1289                 return 0;
1290
1291         edac_printk(KERN_ERR, EDAC_DEVICE,
1292                     "L2: No ECC present, or ECC disabled\n");
1293         return -ENODEV;
1294 }
1295
1296 static irqreturn_t altr_edac_a10_l2_irq(int irq, void *dev_id)
1297 {
1298         struct altr_edac_device_dev *dci = dev_id;
1299
1300         if (irq == dci->sb_irq) {
1301                 regmap_write(dci->edac->ecc_mgr_map,
1302                              A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST,
1303                              A10_SYSGMR_MPU_CLEAR_L2_ECC_SB);
1304                 edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name);
1305
1306                 return IRQ_HANDLED;
1307         } else if (irq == dci->db_irq) {
1308                 regmap_write(dci->edac->ecc_mgr_map,
1309                              A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST,
1310                              A10_SYSGMR_MPU_CLEAR_L2_ECC_MB);
1311                 edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name);
1312                 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
1313
1314                 return IRQ_HANDLED;
1315         }
1316
1317         WARN_ON(1);
1318
1319         return IRQ_NONE;
1320 }
1321
1322 static const struct edac_device_prv_data l2ecc_data = {
1323         .setup = altr_l2_check_deps,
1324         .ce_clear_mask = 0,
1325         .ue_clear_mask = 0,
1326         .alloc_mem = l2_alloc_mem,
1327         .free_mem = l2_free_mem,
1328         .ecc_enable_mask = ALTR_L2_ECC_EN,
1329         .ce_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJS),
1330         .ue_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJD),
1331         .set_err_ofst = ALTR_L2_ECC_REG_OFFSET,
1332         .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE,
1333         .inject_fops = &altr_edac_device_inject_fops,
1334 };
1335
1336 static const struct edac_device_prv_data a10_l2ecc_data = {
1337         .setup = altr_l2_check_deps,
1338         .ce_clear_mask = ALTR_A10_L2_ECC_SERR_CLR,
1339         .ue_clear_mask = ALTR_A10_L2_ECC_MERR_CLR,
1340         .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_L2,
1341         .alloc_mem = l2_alloc_mem,
1342         .free_mem = l2_free_mem,
1343         .ecc_enable_mask = ALTR_A10_L2_ECC_EN_CTL,
1344         .ce_set_mask = ALTR_A10_L2_ECC_CE_INJ_MASK,
1345         .ue_set_mask = ALTR_A10_L2_ECC_UE_INJ_MASK,
1346         .set_err_ofst = ALTR_A10_L2_ECC_INJ_OFST,
1347         .ecc_irq_handler = altr_edac_a10_l2_irq,
1348         .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE,
1349         .inject_fops = &altr_edac_device_inject_fops,
1350 };
1351
1352 #endif  /* CONFIG_EDAC_ALTERA_L2C */
1353
1354 /********************* Ethernet Device Functions ********************/
1355
1356 #ifdef CONFIG_EDAC_ALTERA_ETHERNET
1357
1358 static const struct edac_device_prv_data a10_enetecc_data = {
1359         .setup = altr_check_ecc_deps,
1360         .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1361         .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1362         .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1363         .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1364         .ce_set_mask = ALTR_A10_ECC_TSERRA,
1365         .ue_set_mask = ALTR_A10_ECC_TDERRA,
1366         .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1367         .ecc_irq_handler = altr_edac_a10_ecc_irq,
1368         .inject_fops = &altr_edac_a10_device_inject2_fops,
1369 };
1370
1371 static int __init socfpga_init_ethernet_ecc(void)
1372 {
1373         return altr_init_a10_ecc_device_type("altr,socfpga-eth-mac-ecc");
1374 }
1375
1376 early_initcall(socfpga_init_ethernet_ecc);
1377
1378 #endif  /* CONFIG_EDAC_ALTERA_ETHERNET */
1379
1380 /********************** NAND Device Functions **********************/
1381
1382 #ifdef CONFIG_EDAC_ALTERA_NAND
1383
1384 static const struct edac_device_prv_data a10_nandecc_data = {
1385         .setup = altr_check_ecc_deps,
1386         .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1387         .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1388         .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1389         .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1390         .ce_set_mask = ALTR_A10_ECC_TSERRA,
1391         .ue_set_mask = ALTR_A10_ECC_TDERRA,
1392         .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1393         .ecc_irq_handler = altr_edac_a10_ecc_irq,
1394         .inject_fops = &altr_edac_a10_device_inject_fops,
1395 };
1396
1397 static int __init socfpga_init_nand_ecc(void)
1398 {
1399         return altr_init_a10_ecc_device_type("altr,socfpga-nand-ecc");
1400 }
1401
1402 early_initcall(socfpga_init_nand_ecc);
1403
1404 #endif  /* CONFIG_EDAC_ALTERA_NAND */
1405
1406 /********************** DMA Device Functions **********************/
1407
1408 #ifdef CONFIG_EDAC_ALTERA_DMA
1409
1410 static const struct edac_device_prv_data a10_dmaecc_data = {
1411         .setup = altr_check_ecc_deps,
1412         .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1413         .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1414         .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1415         .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1416         .ce_set_mask = ALTR_A10_ECC_TSERRA,
1417         .ue_set_mask = ALTR_A10_ECC_TDERRA,
1418         .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1419         .ecc_irq_handler = altr_edac_a10_ecc_irq,
1420         .inject_fops = &altr_edac_a10_device_inject_fops,
1421 };
1422
1423 static int __init socfpga_init_dma_ecc(void)
1424 {
1425         return altr_init_a10_ecc_device_type("altr,socfpga-dma-ecc");
1426 }
1427
1428 early_initcall(socfpga_init_dma_ecc);
1429
1430 #endif  /* CONFIG_EDAC_ALTERA_DMA */
1431
1432 /********************** USB Device Functions **********************/
1433
1434 #ifdef CONFIG_EDAC_ALTERA_USB
1435
1436 static const struct edac_device_prv_data a10_usbecc_data = {
1437         .setup = altr_check_ecc_deps,
1438         .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1439         .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1440         .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1441         .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1442         .ce_set_mask = ALTR_A10_ECC_TSERRA,
1443         .ue_set_mask = ALTR_A10_ECC_TDERRA,
1444         .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1445         .ecc_irq_handler = altr_edac_a10_ecc_irq,
1446         .inject_fops = &altr_edac_a10_device_inject2_fops,
1447 };
1448
1449 static int __init socfpga_init_usb_ecc(void)
1450 {
1451         return altr_init_a10_ecc_device_type("altr,socfpga-usb-ecc");
1452 }
1453
1454 early_initcall(socfpga_init_usb_ecc);
1455
1456 #endif  /* CONFIG_EDAC_ALTERA_USB */
1457
1458 /********************** QSPI Device Functions **********************/
1459
1460 #ifdef CONFIG_EDAC_ALTERA_QSPI
1461
1462 static const struct edac_device_prv_data a10_qspiecc_data = {
1463         .setup = altr_check_ecc_deps,
1464         .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1465         .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1466         .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1467         .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1468         .ce_set_mask = ALTR_A10_ECC_TSERRA,
1469         .ue_set_mask = ALTR_A10_ECC_TDERRA,
1470         .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1471         .ecc_irq_handler = altr_edac_a10_ecc_irq,
1472         .inject_fops = &altr_edac_a10_device_inject_fops,
1473 };
1474
1475 static int __init socfpga_init_qspi_ecc(void)
1476 {
1477         return altr_init_a10_ecc_device_type("altr,socfpga-qspi-ecc");
1478 }
1479
1480 early_initcall(socfpga_init_qspi_ecc);
1481
1482 #endif  /* CONFIG_EDAC_ALTERA_QSPI */
1483
1484 /********************* SDMMC Device Functions **********************/
1485
1486 #ifdef CONFIG_EDAC_ALTERA_SDMMC
1487
1488 static const struct edac_device_prv_data a10_sdmmceccb_data;
1489 static int altr_portb_setup(struct altr_edac_device_dev *device)
1490 {
1491         struct edac_device_ctl_info *dci;
1492         struct altr_edac_device_dev *altdev;
1493         char *ecc_name = "sdmmcb-ecc";
1494         int edac_idx, rc;
1495         struct device_node *np;
1496         const struct edac_device_prv_data *prv = &a10_sdmmceccb_data;
1497
1498         rc = altr_check_ecc_deps(device);
1499         if (rc)
1500                 return rc;
1501
1502         np = of_find_compatible_node(NULL, NULL, "altr,socfpga-sdmmc-ecc");
1503         if (!np) {
1504                 edac_printk(KERN_WARNING, EDAC_DEVICE, "SDMMC node not found\n");
1505                 return -ENODEV;
1506         }
1507
1508         /* Create the PortB EDAC device */
1509         edac_idx = edac_device_alloc_index();
1510         dci = edac_device_alloc_ctl_info(sizeof(*altdev), ecc_name, 1,
1511                                          ecc_name, 1, 0, NULL, 0, edac_idx);
1512         if (!dci) {
1513                 edac_printk(KERN_ERR, EDAC_DEVICE,
1514                             "%s: Unable to allocate PortB EDAC device\n",
1515                             ecc_name);
1516                 return -ENOMEM;
1517         }
1518
1519         /* Initialize the PortB EDAC device structure from PortA structure */
1520         altdev = dci->pvt_info;
1521         *altdev = *device;
1522
1523         if (!devres_open_group(&altdev->ddev, altr_portb_setup, GFP_KERNEL))
1524                 return -ENOMEM;
1525
1526         /* Update PortB specific values */
1527         altdev->edac_dev_name = ecc_name;
1528         altdev->edac_idx = edac_idx;
1529         altdev->edac_dev = dci;
1530         altdev->data = prv;
1531         dci->dev = &altdev->ddev;
1532         dci->ctl_name = "Altera ECC Manager";
1533         dci->mod_name = ecc_name;
1534         dci->dev_name = ecc_name;
1535
1536         /* Update the IRQs for PortB */
1537         altdev->sb_irq = irq_of_parse_and_map(np, 2);
1538         if (!altdev->sb_irq) {
1539                 edac_printk(KERN_ERR, EDAC_DEVICE, "Error PortB SBIRQ alloc\n");
1540                 rc = -ENODEV;
1541                 goto err_release_group_1;
1542         }
1543         rc = devm_request_irq(&altdev->ddev, altdev->sb_irq,
1544                               prv->ecc_irq_handler,
1545                               IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
1546                               ecc_name, altdev);
1547         if (rc) {
1548                 edac_printk(KERN_ERR, EDAC_DEVICE, "PortB SBERR IRQ error\n");
1549                 goto err_release_group_1;
1550         }
1551
1552         altdev->db_irq = irq_of_parse_and_map(np, 3);
1553         if (!altdev->db_irq) {
1554                 edac_printk(KERN_ERR, EDAC_DEVICE, "Error PortB DBIRQ alloc\n");
1555                 rc = -ENODEV;
1556                 goto err_release_group_1;
1557         }
1558         rc = devm_request_irq(&altdev->ddev, altdev->db_irq,
1559                               prv->ecc_irq_handler,
1560                               IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
1561                               ecc_name, altdev);
1562         if (rc) {
1563                 edac_printk(KERN_ERR, EDAC_DEVICE, "PortB DBERR IRQ error\n");
1564                 goto err_release_group_1;
1565         }
1566
1567         rc = edac_device_add_device(dci);
1568         if (rc) {
1569                 edac_printk(KERN_ERR, EDAC_DEVICE,
1570                             "edac_device_add_device portB failed\n");
1571                 rc = -ENOMEM;
1572                 goto err_release_group_1;
1573         }
1574         altr_create_edacdev_dbgfs(dci, prv);
1575
1576         list_add(&altdev->next, &altdev->edac->a10_ecc_devices);
1577
1578         devres_remove_group(&altdev->ddev, altr_portb_setup);
1579
1580         return 0;
1581
1582 err_release_group_1:
1583         edac_device_free_ctl_info(dci);
1584         devres_release_group(&altdev->ddev, altr_portb_setup);
1585         edac_printk(KERN_ERR, EDAC_DEVICE,
1586                     "%s:Error setting up EDAC device: %d\n", ecc_name, rc);
1587         return rc;
1588 }
1589
1590 static irqreturn_t altr_edac_a10_ecc_irq_portb(int irq, void *dev_id)
1591 {
1592         struct altr_edac_device_dev *ad = dev_id;
1593         void __iomem  *base = ad->base;
1594         const struct edac_device_prv_data *priv = ad->data;
1595
1596         if (irq == ad->sb_irq) {
1597                 writel(priv->ce_clear_mask,
1598                        base + ALTR_A10_ECC_INTSTAT_OFST);
1599                 edac_device_handle_ce(ad->edac_dev, 0, 0, ad->edac_dev_name);
1600                 return IRQ_HANDLED;
1601         } else if (irq == ad->db_irq) {
1602                 writel(priv->ue_clear_mask,
1603                        base + ALTR_A10_ECC_INTSTAT_OFST);
1604                 edac_device_handle_ue(ad->edac_dev, 0, 0, ad->edac_dev_name);
1605                 return IRQ_HANDLED;
1606         }
1607
1608         WARN_ONCE(1, "Unhandled IRQ%d on Port B.", irq);
1609
1610         return IRQ_NONE;
1611 }
1612
1613 static const struct edac_device_prv_data a10_sdmmcecca_data = {
1614         .setup = altr_portb_setup,
1615         .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1616         .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1617         .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1618         .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1619         .ce_set_mask = ALTR_A10_ECC_SERRPENA,
1620         .ue_set_mask = ALTR_A10_ECC_DERRPENA,
1621         .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1622         .ecc_irq_handler = altr_edac_a10_ecc_irq,
1623         .inject_fops = &altr_edac_a10_device_inject_fops,
1624 };
1625
1626 static const struct edac_device_prv_data a10_sdmmceccb_data = {
1627         .setup = altr_portb_setup,
1628         .ce_clear_mask = ALTR_A10_ECC_SERRPENB,
1629         .ue_clear_mask = ALTR_A10_ECC_DERRPENB,
1630         .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1631         .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1632         .ce_set_mask = ALTR_A10_ECC_TSERRB,
1633         .ue_set_mask = ALTR_A10_ECC_TDERRB,
1634         .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1635         .ecc_irq_handler = altr_edac_a10_ecc_irq_portb,
1636         .inject_fops = &altr_edac_a10_device_inject_fops,
1637 };
1638
1639 static int __init socfpga_init_sdmmc_ecc(void)
1640 {
1641         int rc = -ENODEV;
1642         struct device_node *child;
1643
1644         if (!socfpga_is_a10() && !socfpga_is_s10())
1645                 return -ENODEV;
1646
1647         child = of_find_compatible_node(NULL, NULL, "altr,socfpga-sdmmc-ecc");
1648         if (!child) {
1649                 edac_printk(KERN_WARNING, EDAC_DEVICE, "SDMMC node not found\n");
1650                 return -ENODEV;
1651         }
1652
1653         if (!of_device_is_available(child))
1654                 goto exit;
1655
1656         if (validate_parent_available(child))
1657                 goto exit;
1658
1659         rc = altr_init_a10_ecc_block(child, ALTR_A10_SDMMC_IRQ_MASK,
1660                                      a10_sdmmcecca_data.ecc_enable_mask, 1);
1661 exit:
1662         of_node_put(child);
1663         return rc;
1664 }
1665
1666 early_initcall(socfpga_init_sdmmc_ecc);
1667
1668 #endif  /* CONFIG_EDAC_ALTERA_SDMMC */
1669
1670 /********************* Arria10 EDAC Device Functions *************************/
1671 static const struct of_device_id altr_edac_a10_device_of_match[] = {
1672 #ifdef CONFIG_EDAC_ALTERA_L2C
1673         { .compatible = "altr,socfpga-a10-l2-ecc", .data = &a10_l2ecc_data },
1674 #endif
1675 #ifdef CONFIG_EDAC_ALTERA_OCRAM
1676         { .compatible = "altr,socfpga-a10-ocram-ecc",
1677           .data = &a10_ocramecc_data },
1678 #endif
1679 #ifdef CONFIG_EDAC_ALTERA_ETHERNET
1680         { .compatible = "altr,socfpga-eth-mac-ecc",
1681           .data = &a10_enetecc_data },
1682 #endif
1683 #ifdef CONFIG_EDAC_ALTERA_NAND
1684         { .compatible = "altr,socfpga-nand-ecc", .data = &a10_nandecc_data },
1685 #endif
1686 #ifdef CONFIG_EDAC_ALTERA_DMA
1687         { .compatible = "altr,socfpga-dma-ecc", .data = &a10_dmaecc_data },
1688 #endif
1689 #ifdef CONFIG_EDAC_ALTERA_USB
1690         { .compatible = "altr,socfpga-usb-ecc", .data = &a10_usbecc_data },
1691 #endif
1692 #ifdef CONFIG_EDAC_ALTERA_QSPI
1693         { .compatible = "altr,socfpga-qspi-ecc", .data = &a10_qspiecc_data },
1694 #endif
1695 #ifdef CONFIG_EDAC_ALTERA_SDMMC
1696         { .compatible = "altr,socfpga-sdmmc-ecc", .data = &a10_sdmmcecca_data },
1697 #endif
1698         {},
1699 };
1700 MODULE_DEVICE_TABLE(of, altr_edac_a10_device_of_match);
1701
1702 /*
1703  * The Arria10 EDAC Device Functions differ from the Cyclone5/Arria5
1704  * because 2 IRQs are shared among the all ECC peripherals. The ECC
1705  * manager manages the IRQs and the children.
1706  * Based on xgene_edac.c peripheral code.
1707  */
1708
1709 static ssize_t altr_edac_a10_device_trig(struct file *file,
1710                                          const char __user *user_buf,
1711                                          size_t count, loff_t *ppos)
1712 {
1713         struct edac_device_ctl_info *edac_dci = file->private_data;
1714         struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
1715         const struct edac_device_prv_data *priv = drvdata->data;
1716         void __iomem *set_addr = (drvdata->base + priv->set_err_ofst);
1717         unsigned long flags;
1718         u8 trig_type;
1719
1720         if (!user_buf || get_user(trig_type, user_buf))
1721                 return -EFAULT;
1722
1723         local_irq_save(flags);
1724         if (trig_type == ALTR_UE_TRIGGER_CHAR)
1725                 writel(priv->ue_set_mask, set_addr);
1726         else
1727                 writel(priv->ce_set_mask, set_addr);
1728
1729         /* Ensure the interrupt test bits are set */
1730         wmb();
1731         local_irq_restore(flags);
1732
1733         return count;
1734 }
1735
1736 /*
1737  * The Stratix10 EDAC Error Injection Functions differ from Arria10
1738  * slightly. A few Arria10 peripherals can use this injection function.
1739  * Inject the error into the memory and then readback to trigger the IRQ.
1740  */
1741 static ssize_t altr_edac_a10_device_trig2(struct file *file,
1742                                           const char __user *user_buf,
1743                                           size_t count, loff_t *ppos)
1744 {
1745         struct edac_device_ctl_info *edac_dci = file->private_data;
1746         struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
1747         const struct edac_device_prv_data *priv = drvdata->data;
1748         void __iomem *set_addr = (drvdata->base + priv->set_err_ofst);
1749         unsigned long flags;
1750         u8 trig_type;
1751
1752         if (!user_buf || get_user(trig_type, user_buf))
1753                 return -EFAULT;
1754
1755         local_irq_save(flags);
1756         if (trig_type == ALTR_UE_TRIGGER_CHAR) {
1757                 writel(priv->ue_set_mask, set_addr);
1758         } else {
1759                 /* Setup write of 0 to first 4 bytes */
1760                 writel(0x0, drvdata->base + ECC_BLK_WDATA0_OFST);
1761                 writel(0x0, drvdata->base + ECC_BLK_WDATA1_OFST);
1762                 writel(0x0, drvdata->base + ECC_BLK_WDATA2_OFST);
1763                 writel(0x0, drvdata->base + ECC_BLK_WDATA3_OFST);
1764                 /* Setup write of 4 bytes */
1765                 writel(ECC_WORD_WRITE, drvdata->base + ECC_BLK_DBYTECTRL_OFST);
1766                 /* Setup Address to 0 */
1767                 writel(0x0, drvdata->base + ECC_BLK_ADDRESS_OFST);
1768                 /* Setup accctrl to write & data override */
1769                 writel(ECC_WRITE_DOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST);
1770                 /* Kick it. */
1771                 writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST);
1772                 /* Setup accctrl to read & ecc override */
1773                 writel(ECC_READ_EOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST);
1774                 /* Kick it. */
1775                 writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST);
1776                 /* Setup write for single bit change */
1777                 writel(0x1, drvdata->base + ECC_BLK_WDATA0_OFST);
1778                 writel(0x0, drvdata->base + ECC_BLK_WDATA1_OFST);
1779                 writel(0x0, drvdata->base + ECC_BLK_WDATA2_OFST);
1780                 writel(0x0, drvdata->base + ECC_BLK_WDATA3_OFST);
1781                 /* Copy Read ECC to Write ECC */
1782                 writel(readl(drvdata->base + ECC_BLK_RECC0_OFST),
1783                        drvdata->base + ECC_BLK_WECC0_OFST);
1784                 writel(readl(drvdata->base + ECC_BLK_RECC1_OFST),
1785                        drvdata->base + ECC_BLK_WECC1_OFST);
1786                 /* Setup accctrl to write & ecc override & data override */
1787                 writel(ECC_WRITE_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST);
1788                 /* Kick it. */
1789                 writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST);
1790                 /* Setup accctrl to read & ecc overwrite & data overwrite */
1791                 writel(ECC_READ_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST);
1792                 /* Kick it. */
1793                 writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST);
1794         }
1795
1796         /* Ensure the interrupt test bits are set */
1797         wmb();
1798         local_irq_restore(flags);
1799
1800         return count;
1801 }
1802
1803 static void altr_edac_a10_irq_handler(struct irq_desc *desc)
1804 {
1805         int dberr, bit, sm_offset, irq_status;
1806         struct altr_arria10_edac *edac = irq_desc_get_handler_data(desc);
1807         struct irq_chip *chip = irq_desc_get_chip(desc);
1808         int irq = irq_desc_get_irq(desc);
1809
1810         dberr = (irq == edac->db_irq) ? 1 : 0;
1811         sm_offset = dberr ? A10_SYSMGR_ECC_INTSTAT_DERR_OFST :
1812                             A10_SYSMGR_ECC_INTSTAT_SERR_OFST;
1813
1814         chained_irq_enter(chip, desc);
1815
1816         regmap_read(edac->ecc_mgr_map, sm_offset, &irq_status);
1817
1818         for_each_set_bit(bit, (unsigned long *)&irq_status, 32) {
1819                 irq = irq_linear_revmap(edac->domain, dberr * 32 + bit);
1820                 if (irq)
1821                         generic_handle_irq(irq);
1822         }
1823
1824         chained_irq_exit(chip, desc);
1825 }
1826
1827 static int validate_parent_available(struct device_node *np)
1828 {
1829         struct device_node *parent;
1830         int ret = 0;
1831
1832         /* Ensure parent device is enabled if parent node exists */
1833         parent = of_parse_phandle(np, "altr,ecc-parent", 0);
1834         if (parent && !of_device_is_available(parent))
1835                 ret = -ENODEV;
1836
1837         of_node_put(parent);
1838         return ret;
1839 }
1840
1841 static int altr_edac_a10_device_add(struct altr_arria10_edac *edac,
1842                                     struct device_node *np)
1843 {
1844         struct edac_device_ctl_info *dci;
1845         struct altr_edac_device_dev *altdev;
1846         char *ecc_name = (char *)np->name;
1847         struct resource res;
1848         int edac_idx;
1849         int rc = 0;
1850         const struct edac_device_prv_data *prv;
1851         /* Get matching node and check for valid result */
1852         const struct of_device_id *pdev_id =
1853                 of_match_node(altr_edac_a10_device_of_match, np);
1854         if (IS_ERR_OR_NULL(pdev_id))
1855                 return -ENODEV;
1856
1857         /* Get driver specific data for this EDAC device */
1858         prv = pdev_id->data;
1859         if (IS_ERR_OR_NULL(prv))
1860                 return -ENODEV;
1861
1862         if (validate_parent_available(np))
1863                 return -ENODEV;
1864
1865         if (!devres_open_group(edac->dev, altr_edac_a10_device_add, GFP_KERNEL))
1866                 return -ENOMEM;
1867
1868         rc = of_address_to_resource(np, 0, &res);
1869         if (rc < 0) {
1870                 edac_printk(KERN_ERR, EDAC_DEVICE,
1871                             "%s: no resource address\n", ecc_name);
1872                 goto err_release_group;
1873         }
1874
1875         edac_idx = edac_device_alloc_index();
1876         dci = edac_device_alloc_ctl_info(sizeof(*altdev), ecc_name,
1877                                          1, ecc_name, 1, 0, NULL, 0,
1878                                          edac_idx);
1879
1880         if (!dci) {
1881                 edac_printk(KERN_ERR, EDAC_DEVICE,
1882                             "%s: Unable to allocate EDAC device\n", ecc_name);
1883                 rc = -ENOMEM;
1884                 goto err_release_group;
1885         }
1886
1887         altdev = dci->pvt_info;
1888         dci->dev = edac->dev;
1889         altdev->edac_dev_name = ecc_name;
1890         altdev->edac_idx = edac_idx;
1891         altdev->edac = edac;
1892         altdev->edac_dev = dci;
1893         altdev->data = prv;
1894         altdev->ddev = *edac->dev;
1895         dci->dev = &altdev->ddev;
1896         dci->ctl_name = "Altera ECC Manager";
1897         dci->mod_name = ecc_name;
1898         dci->dev_name = ecc_name;
1899
1900         altdev->base = devm_ioremap_resource(edac->dev, &res);
1901         if (IS_ERR(altdev->base)) {
1902                 rc = PTR_ERR(altdev->base);
1903                 goto err_release_group1;
1904         }
1905
1906         /* Check specific dependencies for the module */
1907         if (altdev->data->setup) {
1908                 rc = altdev->data->setup(altdev);
1909                 if (rc)
1910                         goto err_release_group1;
1911         }
1912
1913         altdev->sb_irq = irq_of_parse_and_map(np, 0);
1914         if (!altdev->sb_irq) {
1915                 edac_printk(KERN_ERR, EDAC_DEVICE, "Error allocating SBIRQ\n");
1916                 rc = -ENODEV;
1917                 goto err_release_group1;
1918         }
1919         rc = devm_request_irq(edac->dev, altdev->sb_irq, prv->ecc_irq_handler,
1920                               IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
1921                               ecc_name, altdev);
1922         if (rc) {
1923                 edac_printk(KERN_ERR, EDAC_DEVICE, "No SBERR IRQ resource\n");
1924                 goto err_release_group1;
1925         }
1926
1927         altdev->db_irq = irq_of_parse_and_map(np, 1);
1928         if (!altdev->db_irq) {
1929                 edac_printk(KERN_ERR, EDAC_DEVICE, "Error allocating DBIRQ\n");
1930                 rc = -ENODEV;
1931                 goto err_release_group1;
1932         }
1933         rc = devm_request_irq(edac->dev, altdev->db_irq, prv->ecc_irq_handler,
1934                               IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
1935                               ecc_name, altdev);
1936         if (rc) {
1937                 edac_printk(KERN_ERR, EDAC_DEVICE, "No DBERR IRQ resource\n");
1938                 goto err_release_group1;
1939         }
1940
1941         rc = edac_device_add_device(dci);
1942         if (rc) {
1943                 dev_err(edac->dev, "edac_device_add_device failed\n");
1944                 rc = -ENOMEM;
1945                 goto err_release_group1;
1946         }
1947
1948         altr_create_edacdev_dbgfs(dci, prv);
1949
1950         list_add(&altdev->next, &edac->a10_ecc_devices);
1951
1952         devres_remove_group(edac->dev, altr_edac_a10_device_add);
1953
1954         return 0;
1955
1956 err_release_group1:
1957         edac_device_free_ctl_info(dci);
1958 err_release_group:
1959         devres_release_group(edac->dev, NULL);
1960         edac_printk(KERN_ERR, EDAC_DEVICE,
1961                     "%s:Error setting up EDAC device: %d\n", ecc_name, rc);
1962
1963         return rc;
1964 }
1965
1966 static void a10_eccmgr_irq_mask(struct irq_data *d)
1967 {
1968         struct altr_arria10_edac *edac = irq_data_get_irq_chip_data(d);
1969
1970         regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST,
1971                      BIT(d->hwirq));
1972 }
1973
1974 static void a10_eccmgr_irq_unmask(struct irq_data *d)
1975 {
1976         struct altr_arria10_edac *edac = irq_data_get_irq_chip_data(d);
1977
1978         regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_CLR_OFST,
1979                      BIT(d->hwirq));
1980 }
1981
1982 static int a10_eccmgr_irqdomain_map(struct irq_domain *d, unsigned int irq,
1983                                     irq_hw_number_t hwirq)
1984 {
1985         struct altr_arria10_edac *edac = d->host_data;
1986
1987         irq_set_chip_and_handler(irq, &edac->irq_chip, handle_simple_irq);
1988         irq_set_chip_data(irq, edac);
1989         irq_set_noprobe(irq);
1990
1991         return 0;
1992 }
1993
1994 static const struct irq_domain_ops a10_eccmgr_ic_ops = {
1995         .map = a10_eccmgr_irqdomain_map,
1996         .xlate = irq_domain_xlate_twocell,
1997 };
1998
1999 /************** Stratix 10 EDAC Double Bit Error Handler ************/
2000 #define to_a10edac(p, m) container_of(p, struct altr_arria10_edac, m)
2001
2002 /*
2003  * The double bit error is handled through SError which is fatal. This is
2004  * called as a panic notifier to printout ECC error info as part of the panic.
2005  */
2006 static int s10_edac_dberr_handler(struct notifier_block *this,
2007                                   unsigned long event, void *ptr)
2008 {
2009         struct altr_arria10_edac *edac = to_a10edac(this, panic_notifier);
2010         int err_addr, dberror;
2011
2012         regmap_read(edac->ecc_mgr_map, S10_SYSMGR_ECC_INTSTAT_DERR_OFST,
2013                     &dberror);
2014         regmap_write(edac->ecc_mgr_map, S10_SYSMGR_UE_VAL_OFST, dberror);
2015         if (dberror & S10_DDR0_IRQ_MASK) {
2016                 regmap_read(edac->ecc_mgr_map, A10_DERRADDR_OFST, &err_addr);
2017                 regmap_write(edac->ecc_mgr_map, S10_SYSMGR_UE_ADDR_OFST,
2018                              err_addr);
2019                 edac_printk(KERN_ERR, EDAC_MC,
2020                             "EDAC: [Uncorrectable errors @ 0x%08X]\n\n",
2021                             err_addr);
2022         }
2023
2024         return NOTIFY_DONE;
2025 }
2026
2027 /****************** Arria 10 EDAC Probe Function *********************/
2028 static int altr_edac_a10_probe(struct platform_device *pdev)
2029 {
2030         struct altr_arria10_edac *edac;
2031         struct device_node *child;
2032
2033         edac = devm_kzalloc(&pdev->dev, sizeof(*edac), GFP_KERNEL);
2034         if (!edac)
2035                 return -ENOMEM;
2036
2037         edac->dev = &pdev->dev;
2038         platform_set_drvdata(pdev, edac);
2039         INIT_LIST_HEAD(&edac->a10_ecc_devices);
2040
2041         if (socfpga_is_a10()) {
2042                 edac->ecc_mgr_map =
2043                         syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
2044                                                         "altr,sysmgr-syscon");
2045         } else {
2046                 struct device_node *sysmgr_np;
2047                 struct resource res;
2048                 uintptr_t base;
2049
2050                 sysmgr_np = of_parse_phandle(pdev->dev.of_node,
2051                                              "altr,sysmgr-syscon", 0);
2052                 if (!sysmgr_np) {
2053                         edac_printk(KERN_ERR, EDAC_DEVICE,
2054                                     "Unable to find altr,sysmgr-syscon\n");
2055                         return -ENODEV;
2056                 }
2057
2058                 if (of_address_to_resource(sysmgr_np, 0, &res))
2059                         return -ENOMEM;
2060
2061                 /* Need physical address for SMCC call */
2062                 base = res.start;
2063
2064                 edac->ecc_mgr_map = devm_regmap_init(&pdev->dev, NULL,
2065                                                      (void *)base,
2066                                                      &s10_sdram_regmap_cfg);
2067         }
2068
2069         if (IS_ERR(edac->ecc_mgr_map)) {
2070                 edac_printk(KERN_ERR, EDAC_DEVICE,
2071                             "Unable to get syscon altr,sysmgr-syscon\n");
2072                 return PTR_ERR(edac->ecc_mgr_map);
2073         }
2074
2075         edac->irq_chip.name = pdev->dev.of_node->name;
2076         edac->irq_chip.irq_mask = a10_eccmgr_irq_mask;
2077         edac->irq_chip.irq_unmask = a10_eccmgr_irq_unmask;
2078         edac->domain = irq_domain_add_linear(pdev->dev.of_node, 64,
2079                                              &a10_eccmgr_ic_ops, edac);
2080         if (!edac->domain) {
2081                 dev_err(&pdev->dev, "Error adding IRQ domain\n");
2082                 return -ENOMEM;
2083         }
2084
2085         edac->sb_irq = platform_get_irq(pdev, 0);
2086         if (edac->sb_irq < 0) {
2087                 dev_err(&pdev->dev, "No SBERR IRQ resource\n");
2088                 return edac->sb_irq;
2089         }
2090
2091         irq_set_chained_handler_and_data(edac->sb_irq,
2092                                          altr_edac_a10_irq_handler,
2093                                          edac);
2094
2095         if (socfpga_is_a10()) {
2096                 edac->db_irq = platform_get_irq(pdev, 1);
2097                 if (edac->db_irq < 0) {
2098                         dev_err(&pdev->dev, "No DBERR IRQ resource\n");
2099                         return edac->db_irq;
2100                 }
2101                 irq_set_chained_handler_and_data(edac->db_irq,
2102                                                  altr_edac_a10_irq_handler,
2103                                                  edac);
2104         } else {
2105                 int dberror, err_addr;
2106
2107                 edac->panic_notifier.notifier_call = s10_edac_dberr_handler;
2108                 atomic_notifier_chain_register(&panic_notifier_list,
2109                                                &edac->panic_notifier);
2110
2111                 /* Printout a message if uncorrectable error previously. */
2112                 regmap_read(edac->ecc_mgr_map, S10_SYSMGR_UE_VAL_OFST,
2113                             &dberror);
2114                 if (dberror) {
2115                         regmap_read(edac->ecc_mgr_map, S10_SYSMGR_UE_ADDR_OFST,
2116                                     &err_addr);
2117                         edac_printk(KERN_ERR, EDAC_DEVICE,
2118                                     "Previous Boot UE detected[0x%X] @ 0x%X\n",
2119                                     dberror, err_addr);
2120                         /* Reset the sticky registers */
2121                         regmap_write(edac->ecc_mgr_map,
2122                                      S10_SYSMGR_UE_VAL_OFST, 0);
2123                         regmap_write(edac->ecc_mgr_map,
2124                                      S10_SYSMGR_UE_ADDR_OFST, 0);
2125                 }
2126         }
2127
2128         for_each_child_of_node(pdev->dev.of_node, child) {
2129                 if (!of_device_is_available(child))
2130                         continue;
2131
2132                 if (of_device_is_compatible(child, "altr,socfpga-a10-l2-ecc") ||
2133                     of_device_is_compatible(child, "altr,socfpga-a10-ocram-ecc") ||
2134                     of_device_is_compatible(child, "altr,socfpga-eth-mac-ecc") ||
2135                     of_device_is_compatible(child, "altr,socfpga-nand-ecc") ||
2136                     of_device_is_compatible(child, "altr,socfpga-dma-ecc") ||
2137                     of_device_is_compatible(child, "altr,socfpga-usb-ecc") ||
2138                     of_device_is_compatible(child, "altr,socfpga-qspi-ecc") ||
2139                     of_device_is_compatible(child, "altr,socfpga-sdmmc-ecc"))
2140
2141                         altr_edac_a10_device_add(edac, child);
2142
2143                 else if ((of_device_is_compatible(child, "altr,sdram-edac-a10")) ||
2144                          (of_device_is_compatible(child, "altr,sdram-edac-s10")))
2145                         of_platform_populate(pdev->dev.of_node,
2146                                              altr_sdram_ctrl_of_match,
2147                                              NULL, &pdev->dev);
2148         }
2149
2150         return 0;
2151 }
2152
2153 static const struct of_device_id altr_edac_a10_of_match[] = {
2154         { .compatible = "altr,socfpga-a10-ecc-manager" },
2155         { .compatible = "altr,socfpga-s10-ecc-manager" },
2156         {},
2157 };
2158 MODULE_DEVICE_TABLE(of, altr_edac_a10_of_match);
2159
2160 static struct platform_driver altr_edac_a10_driver = {
2161         .probe =  altr_edac_a10_probe,
2162         .driver = {
2163                 .name = "socfpga_a10_ecc_manager",
2164                 .of_match_table = altr_edac_a10_of_match,
2165         },
2166 };
2167 module_platform_driver(altr_edac_a10_driver);
2168
2169 MODULE_LICENSE("GPL v2");
2170 MODULE_AUTHOR("Thor Thayer");
2171 MODULE_DESCRIPTION("EDAC Driver for Altera Memories");