3 # Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com
4 # Licensed and distributed under the GPL
11 bool "EDAC (Error Detection And Correction) reporting"
13 depends on X86 || PPC || TILE || ARM || EDAC_SUPPORT
15 EDAC is designed to report errors in the core system.
16 These are low-level errors that are reported in the CPU or
17 supporting chipset or other subsystems:
18 memory errors, cache errors, PCI errors, thermal throttling, etc..
19 If unsure, select 'Y'.
21 If this code is reporting problems on your system, please
22 see the EDAC project web pages for more information at:
24 <http://bluesmoke.sourceforge.net/>
28 <http://buttersideup.com/edacwiki>
30 There is also a mailing list for the EDAC project, which can
31 be found via the sourceforge page.
35 config EDAC_LEGACY_SYSFS
36 bool "EDAC legacy sysfs"
39 Enable the compatibility sysfs nodes.
40 Use 'Y' if your edac utilities aren't ported to work with the newer
46 This turns on debugging information for the entire EDAC subsystem.
47 You do so by inserting edac_module with "edac_debug_level=x." Valid
48 levels are 0-4 (from low to high) and by default it is set to 2.
49 Usually you should select 'N' here.
51 config EDAC_DECODE_MCE
52 tristate "Decode MCEs in human-readable form (only on AMD for now)"
53 depends on CPU_SUP_AMD && X86_MCE_AMD
56 Enable this option if you want to decode Machine Check Exceptions
57 occurring on your machine in human-readable form.
59 You should definitely say Y here in case you want to decode MCEs
60 which occur really early upon boot, before the module infrastructure
64 tristate "Simple MCE injection interface over /sysfs"
65 depends on EDAC_DECODE_MCE
68 This is a simple interface to inject MCEs over /sysfs and test
69 the MCE decoding code in EDAC.
71 This is currently AMD-only.
74 tristate "Main Memory EDAC (Error Detection And Correction) reporting"
77 Some systems are able to detect and correct errors in main
78 memory. EDAC can report statistics on memory error
79 detection and correction (EDAC - or commonly referred to ECC
80 errors). EDAC will also try to decode where these errors
81 occurred so that a particular failing memory module can be
82 replaced. If unsure, select 'Y'.
85 bool "Output ACPI APEI/GHES BIOS detected errors via EDAC"
86 depends on ACPI_APEI_GHES && (EDAC_MM_EDAC=y)
89 Not all machines support hardware-driven error report. Some of those
90 provide a BIOS-driven error report mechanism via ACPI, using the
91 APEI/GHES driver. By enabling this option, the error reports provided
92 by GHES are sent to userspace via the EDAC API.
94 When this option is enabled, it will disable the hardware-driven
95 mechanisms, if a GHES BIOS is detected, entering into the
96 "Firmware First" mode.
98 It should be noticed that keeping both GHES and a hardware-driven
99 error mechanism won't work well, as BIOS will race with OS, while
100 reading the error registers. So, if you want to not use "Firmware
101 first" GHES error mechanism, you should disable GHES either at
102 compilation time or by passing "ghes.disable=1" Kernel parameter
108 tristate "AMD64 (Opteron, Athlon64) K8, F10h"
109 depends on EDAC_MM_EDAC && AMD_NB && X86_64 && EDAC_DECODE_MCE
111 Support for error detection and correction of DRAM ECC errors on
112 the AMD64 families of memory controllers (K8 and F10h)
114 config EDAC_AMD64_ERROR_INJECTION
115 bool "Sysfs HW Error injection facilities"
116 depends on EDAC_AMD64
118 Recent Opterons (Family 10h and later) provide for Memory Error
119 Injection into the ECC detection circuits. The amd64_edac module
120 allows the operator/user to inject Uncorrectable and Correctable
123 When enabled, in each of the respective memory controller directories
124 (/sys/devices/system/edac/mc/mcX), there are 3 input files:
126 - inject_section (0..3, 16-byte section of 64-byte cacheline),
127 - inject_word (0..8, 16-bit word of 16-byte section),
128 - inject_ecc_vector (hex ecc vector: select bits of inject word)
130 In addition, there are two control files, inject_read and inject_write,
131 which trigger the DRAM ECC Read and Write respectively.
134 tristate "AMD 76x (760, 762, 768)"
135 depends on EDAC_MM_EDAC && PCI && X86_32
137 Support for error detection and correction on the AMD 76x
138 series of chipsets used with the Athlon processor.
141 tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
142 depends on EDAC_MM_EDAC && PCI && X86_32
144 Support for error detection and correction on the Intel
145 E7205, E7500, E7501 and E7505 server chipsets.
148 tristate "Intel e752x (e7520, e7525, e7320) and 3100"
149 depends on EDAC_MM_EDAC && PCI && X86
151 Support for error detection and correction on the Intel
152 E7520, E7525, E7320 server chipsets.
154 config EDAC_I82443BXGX
155 tristate "Intel 82443BX/GX (440BX/GX)"
156 depends on EDAC_MM_EDAC && PCI && X86_32
159 Support for error detection and correction on the Intel
160 82443BX/GX memory controllers (440BX/GX chipsets).
163 tristate "Intel 82875p (D82875P, E7210)"
164 depends on EDAC_MM_EDAC && PCI && X86_32
166 Support for error detection and correction on the Intel
167 DP82785P and E7210 server chipsets.
170 tristate "Intel 82975x (D82975x)"
171 depends on EDAC_MM_EDAC && PCI && X86
173 Support for error detection and correction on the Intel
174 DP82975x server chipsets.
177 tristate "Intel 3000/3010"
178 depends on EDAC_MM_EDAC && PCI && X86
180 Support for error detection and correction on the Intel
181 3000 and 3010 server chipsets.
184 tristate "Intel 3200"
185 depends on EDAC_MM_EDAC && PCI && X86
187 Support for error detection and correction on the Intel
188 3200 and 3210 server chipsets.
192 depends on EDAC_MM_EDAC && PCI && X86
194 Support for error detection and correction on the Intel
198 tristate "Intel 5400 (Seaburg) chipsets"
199 depends on EDAC_MM_EDAC && PCI && X86
201 Support for error detection and correction the Intel
202 i5400 MCH chipset (Seaburg).
205 tristate "Intel i7 Core (Nehalem) processors"
206 depends on EDAC_MM_EDAC && PCI && X86 && X86_MCE_INTEL
208 Support for error detection and correction the Intel
209 i7 Core (Nehalem) Integrated Memory Controller that exists on
210 newer processors like i7 Core, i7 Core Extreme, Xeon 35xx
211 and Xeon 55xx processors.
214 tristate "Intel 82860"
215 depends on EDAC_MM_EDAC && PCI && X86_32
217 Support for error detection and correction on the Intel
221 tristate "Radisys 82600 embedded chipset"
222 depends on EDAC_MM_EDAC && PCI && X86_32
224 Support for error detection and correction on the Radisys
225 82600 embedded chipset.
228 tristate "Intel Greencreek/Blackford chipset"
229 depends on EDAC_MM_EDAC && X86 && PCI
231 Support for error detection and correction the Intel
232 Greekcreek/Blackford chipsets.
235 tristate "Intel San Clemente MCH"
236 depends on EDAC_MM_EDAC && X86 && PCI
238 Support for error detection and correction the Intel
242 tristate "Intel Clarksboro MCH"
243 depends on EDAC_MM_EDAC && X86 && PCI
245 Support for error detection and correction the Intel
246 Clarksboro MCH (Intel 7300 chipset).
249 tristate "Intel Sandy-Bridge Integrated MC"
250 depends on EDAC_MM_EDAC && PCI && X86_64 && X86_MCE_INTEL
251 depends on PCI_MMCONFIG
253 Support for error detection and correction the Intel
254 Sandy Bridge Integrated Memory Controller.
257 tristate "Freescale MPC83xx / MPC85xx"
258 depends on EDAC_MM_EDAC && FSL_SOC && (PPC_83xx || PPC_85xx)
260 Support for error detection and correction on the Freescale
261 MPC8349, MPC8560, MPC8540, MPC8548
264 tristate "Marvell MV64x60"
265 depends on EDAC_MM_EDAC && MV64X60
267 Support for error detection and correction on the Marvell
268 MV64360 and MV64460 chipsets.
271 tristate "PA Semi PWRficient"
272 depends on EDAC_MM_EDAC && PCI
273 depends on PPC_PASEMI
275 Support for error detection and correction on PA Semi
279 tristate "Cell Broadband Engine memory controller"
280 depends on EDAC_MM_EDAC && PPC_CELL_COMMON
282 Support for error detection and correction on the
283 Cell Broadband Engine internal memory controller
284 on platform without a hypervisor
287 tristate "PPC4xx IBM DDR2 Memory Controller"
288 depends on EDAC_MM_EDAC && 4xx
290 This enables support for EDAC on the ECC memory used
291 with the IBM DDR2 memory controller found in various
292 PowerPC 4xx embedded processors such as the 405EX[r],
293 440SP, 440SPe, 460EX, 460GT and 460SX.
296 tristate "AMD8131 HyperTransport PCI-X Tunnel"
297 depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
299 Support for error detection and correction on the
300 AMD8131 HyperTransport PCI-X Tunnel chip.
301 Note, add more Kconfig dependency if it's adopted
302 on some machine other than Maple.
305 tristate "AMD8111 HyperTransport I/O Hub"
306 depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
308 Support for error detection and correction on the
309 AMD8111 HyperTransport I/O Hub chip.
310 Note, add more Kconfig dependency if it's adopted
311 on some machine other than Maple.
314 tristate "IBM CPC925 Memory Controller (PPC970FX)"
315 depends on EDAC_MM_EDAC && PPC64
317 Support for error detection and correction on the
318 IBM CPC925 Bridge and Memory Controller, which is
319 a companion chip to the PowerPC 970 family of
323 tristate "Tilera Memory Controller"
324 depends on EDAC_MM_EDAC && TILE
327 Support for error detection and correction on the
328 Tilera memory controller.
330 config EDAC_HIGHBANK_MC
331 tristate "Highbank Memory Controller"
332 depends on EDAC_MM_EDAC && ARCH_HIGHBANK
334 Support for error detection and correction on the
335 Calxeda Highbank memory controller.
337 config EDAC_HIGHBANK_L2
338 tristate "Highbank L2 Cache"
339 depends on EDAC_MM_EDAC && ARCH_HIGHBANK
341 Support for error detection and correction on the
342 Calxeda Highbank memory controller.
344 config EDAC_OCTEON_PC
345 tristate "Cavium Octeon Primary Caches"
346 depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON
348 Support for error detection and correction on the primary caches of
349 the cnMIPS cores of Cavium Octeon family SOCs.
351 config EDAC_OCTEON_L2C
352 tristate "Cavium Octeon Secondary Caches (L2C)"
353 depends on EDAC_MM_EDAC && CAVIUM_OCTEON_SOC
355 Support for error detection and correction on the
356 Cavium Octeon family of SOCs.
358 config EDAC_OCTEON_LMC
359 tristate "Cavium Octeon DRAM Memory Controller (LMC)"
360 depends on EDAC_MM_EDAC && CAVIUM_OCTEON_SOC
362 Support for error detection and correction on the
363 Cavium Octeon family of SOCs.
365 config EDAC_OCTEON_PCI
366 tristate "Cavium Octeon PCI Controller"
367 depends on EDAC_MM_EDAC && PCI && CAVIUM_OCTEON_SOC
369 Support for error detection and correction on the
370 Cavium Octeon family of SOCs.