drivers/clk/qcom/gcc-msm8996.c

   1 /*
   2  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/bitops.h>
  16 #include <linux/err.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/of_device.h>
  21 #include <linux/clk-provider.h>
  22 #include <linux/regmap.h>
  23 #include <linux/reset-controller.h>
  24
  25 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
  26
  27 #include "common.h"
  28 #include "clk-regmap.h"
  29 #include "clk-alpha-pll.h"
  30 #include "clk-rcg.h"
  31 #include "clk-branch.h"
  32 #include "reset.h"
  33 #include "gdsc.h"
  34
  35 enum {
  36         P_XO,
  37         P_GPLL0,
  38         P_GPLL2,
  39         P_GPLL3,
  40         P_GPLL1,
  41         P_GPLL2_EARLY,
  42         P_GPLL0_EARLY_DIV,
  43         P_SLEEP_CLK,
  44         P_GPLL4,
  45         P_AUD_REF_CLK,
  46         P_GPLL1_EARLY_DIV
  47 };
  48
  49 static const struct parent_map gcc_sleep_clk_map[] = {
  50         { P_SLEEP_CLK, 5 }
  51 };
  52
  53 static const char * const gcc_sleep_clk[] = {
  54         "sleep_clk"
  55 };
  56
  57 static const struct parent_map gcc_xo_gpll0_map[] = {
  58         { P_XO, 0 },
  59         { P_GPLL0, 1 }
  60 };
  61
  62 static const char * const gcc_xo_gpll0[] = {
  63         "xo",
  64         "gpll0"
  65 };
  66
  67 static const struct parent_map gcc_xo_sleep_clk_map[] = {
  68         { P_XO, 0 },
  69         { P_SLEEP_CLK, 5 }
  70 };
  71
  72 static const char * const gcc_xo_sleep_clk[] = {
  73         "xo",
  74         "sleep_clk"
  75 };
  76
  77 static const struct parent_map gcc_xo_gpll0_gpll0_early_div_map[] = {
  78         { P_XO, 0 },
  79         { P_GPLL0, 1 },
  80         { P_GPLL0_EARLY_DIV, 6 }
  81 };
  82
  83 static const char * const gcc_xo_gpll0_gpll0_early_div[] = {
  84         "xo",
  85         "gpll0",
  86         "gpll0_early_div"
  87 };
  88
  89 static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
  90         { P_XO, 0 },
  91         { P_GPLL0, 1 },
  92         { P_GPLL4, 5 }
  93 };
  94
  95 static const char * const gcc_xo_gpll0_gpll4[] = {
  96         "xo",
  97         "gpll0",
  98         "gpll4"
  99 };
 100
 101 static const struct parent_map gcc_xo_gpll0_aud_ref_clk_map[] = {
 102         { P_XO, 0 },
 103         { P_GPLL0, 1 },
 104         { P_AUD_REF_CLK, 2 }
 105 };
 106
 107 static const char * const gcc_xo_gpll0_aud_ref_clk[] = {
 108         "xo",
 109         "gpll0",
 110         "aud_ref_clk"
 111 };
 112
 113 static const struct parent_map gcc_xo_gpll0_sleep_clk_gpll0_early_div_map[] = {
 114         { P_XO, 0 },
 115         { P_GPLL0, 1 },
 116         { P_SLEEP_CLK, 5 },
 117         { P_GPLL0_EARLY_DIV, 6 }
 118 };
 119
 120 static const char * const gcc_xo_gpll0_sleep_clk_gpll0_early_div[] = {
 121         "xo",
 122         "gpll0",
 123         "sleep_clk",
 124         "gpll0_early_div"
 125 };
 126
 127 static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_early_div_map[] = {
 128         { P_XO, 0 },
 129         { P_GPLL0, 1 },
 130         { P_GPLL4, 5 },
 131         { P_GPLL0_EARLY_DIV, 6 }
 132 };
 133
 134 static const char * const gcc_xo_gpll0_gpll4_gpll0_early_div[] = {
 135         "xo",
 136         "gpll0",
 137         "gpll4",
 138         "gpll0_early_div"
 139 };
 140
 141 static const struct parent_map gcc_xo_gpll0_gpll2_gpll3_gpll0_early_div_map[] = {
 142         { P_XO, 0 },
 143         { P_GPLL0, 1 },
 144         { P_GPLL2, 2 },
 145         { P_GPLL3, 3 },
 146         { P_GPLL0_EARLY_DIV, 6 }
 147 };
 148
 149 static const char * const gcc_xo_gpll0_gpll2_gpll3_gpll0_early_div[] = {
 150         "xo",
 151         "gpll0",
 152         "gpll2",
 153         "gpll3",
 154         "gpll0_early_div"
 155 };
 156
 157 static const struct parent_map gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div_map[] = {
 158         { P_XO, 0 },
 159         { P_GPLL0, 1 },
 160         { P_GPLL1_EARLY_DIV, 3 },
 161         { P_GPLL1, 4 },
 162         { P_GPLL4, 5 },
 163         { P_GPLL0_EARLY_DIV, 6 }
 164 };
 165
 166 static const char * const gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div[] = {
 167         "xo",
 168         "gpll0",
 169         "gpll1_early_div",
 170         "gpll1",
 171         "gpll4",
 172         "gpll0_early_div"
 173 };
 174
 175 static const struct parent_map gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div_map[] = {
 176         { P_XO, 0 },
 177         { P_GPLL0, 1 },
 178         { P_GPLL2, 2 },
 179         { P_GPLL3, 3 },
 180         { P_GPLL1, 4 },
 181         { P_GPLL2_EARLY, 5 },
 182         { P_GPLL0_EARLY_DIV, 6 }
 183 };
 184
 185 static const char * const gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div[] = {
 186         "xo",
 187         "gpll0",
 188         "gpll2",
 189         "gpll3",
 190         "gpll1",
 191         "gpll2_early",
 192         "gpll0_early_div"
 193 };
 194
 195 static const struct parent_map gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll4_gpll0_early_div_map[] = {
 196         { P_XO, 0 },
 197         { P_GPLL0, 1 },
 198         { P_GPLL2, 2 },
 199         { P_GPLL3, 3 },
 200         { P_GPLL1, 4 },
 201         { P_GPLL4, 5 },
 202         { P_GPLL0_EARLY_DIV, 6 }
 203 };
 204
 205 static const char * const gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll4_gpll0_early_div[] = {
 206         "xo",
 207         "gpll0",
 208         "gpll2",
 209         "gpll3",
 210         "gpll1",
 211         "gpll4",
 212         "gpll0_early_div"
 213 };
 214
 215 static struct clk_fixed_factor xo = {
 216         .mult = 1,
 217         .div = 1,
 218         .hw.init = &(struct clk_init_data){
 219                 .name = "xo",
 220                 .parent_names = (const char *[]){ "xo_board" },
 221                 .num_parents = 1,
 222                 .ops = &clk_fixed_factor_ops,
 223         },
 224 };
 225
 226 static struct clk_alpha_pll gpll0_early = {
 227         .offset = 0x00000,
 228         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 229         .clkr = {
 230                 .enable_reg = 0x52000,
 231                 .enable_mask = BIT(0),
 232                 .hw.init = &(struct clk_init_data){
 233                         .name = "gpll0_early",
 234                         .parent_names = (const char *[]){ "xo" },
 235                         .num_parents = 1,
 236                         .ops = &clk_alpha_pll_ops,
 237                 },
 238         },
 239 };
 240
 241 static struct clk_fixed_factor gpll0_early_div = {
 242         .mult = 1,
 243         .div = 2,
 244         .hw.init = &(struct clk_init_data){
 245                 .name = "gpll0_early_div",
 246                 .parent_names = (const char *[]){ "gpll0_early" },
 247                 .num_parents = 1,
 248                 .ops = &clk_fixed_factor_ops,
 249         },
 250 };
 251
 252 static struct clk_alpha_pll_postdiv gpll0 = {
 253         .offset = 0x00000,
 254         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 255         .clkr.hw.init = &(struct clk_init_data){
 256                 .name = "gpll0",
 257                 .parent_names = (const char *[]){ "gpll0_early" },
 258                 .num_parents = 1,
 259                 .ops = &clk_alpha_pll_postdiv_ops,
 260         },
 261 };
 262
 263 static struct clk_alpha_pll gpll4_early = {
 264         .offset = 0x77000,
 265         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 266         .clkr = {
 267                 .enable_reg = 0x52000,
 268                 .enable_mask = BIT(4),
 269                 .hw.init = &(struct clk_init_data){
 270                         .name = "gpll4_early",
 271                         .parent_names = (const char *[]){ "xo" },
 272                         .num_parents = 1,
 273                         .ops = &clk_alpha_pll_ops,
 274                 },
 275         },
 276 };
 277
 278 static struct clk_alpha_pll_postdiv gpll4 = {
 279         .offset = 0x77000,
 280         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 281         .clkr.hw.init = &(struct clk_init_data){
 282                 .name = "gpll4",
 283                 .parent_names = (const char *[]){ "gpll4_early" },
 284                 .num_parents = 1,
 285                 .ops = &clk_alpha_pll_postdiv_ops,
 286         },
 287 };
 288
 289 static const struct freq_tbl ftbl_system_noc_clk_src[] = {
 290         F(19200000, P_XO, 1, 0, 0),
 291         F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
 292         F(100000000, P_GPLL0, 6, 0, 0),
 293         F(150000000, P_GPLL0, 4, 0, 0),
 294         F(200000000, P_GPLL0, 3, 0, 0),
 295         F(240000000, P_GPLL0, 2.5, 0, 0),
 296         { }
 297 };
 298
 299 static struct clk_rcg2 system_noc_clk_src = {
 300         .cmd_rcgr = 0x0401c,
 301         .hid_width = 5,
 302         .parent_map = gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div_map,
 303         .freq_tbl = ftbl_system_noc_clk_src,
 304         .clkr.hw.init = &(struct clk_init_data){
 305                 .name = "system_noc_clk_src",
 306                 .parent_names = gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div,
 307                 .num_parents = 7,
 308                 .ops = &clk_rcg2_ops,
 309         },
 310 };
 311
 312 static const struct freq_tbl ftbl_config_noc_clk_src[] = {
 313         F(19200000, P_XO, 1, 0, 0),
 314         F(37500000, P_GPLL0, 16, 0, 0),
 315         F(75000000, P_GPLL0, 8, 0, 0),
 316         { }
 317 };
 318
 319 static struct clk_rcg2 config_noc_clk_src = {
 320         .cmd_rcgr = 0x0500c,
 321         .hid_width = 5,
 322         .parent_map = gcc_xo_gpll0_map,
 323         .freq_tbl = ftbl_config_noc_clk_src,
 324         .clkr.hw.init = &(struct clk_init_data){
 325                 .name = "config_noc_clk_src",
 326                 .parent_names = gcc_xo_gpll0,
 327                 .num_parents = 2,
 328                 .ops = &clk_rcg2_ops,
 329         },
 330 };
 331
 332 static const struct freq_tbl ftbl_periph_noc_clk_src[] = {
 333         F(19200000, P_XO, 1, 0, 0),
 334         F(37500000, P_GPLL0, 16, 0, 0),
 335         F(50000000, P_GPLL0, 12, 0, 0),
 336         F(75000000, P_GPLL0, 8, 0, 0),
 337         F(100000000, P_GPLL0, 6, 0, 0),
 338         { }
 339 };
 340
 341 static struct clk_rcg2 periph_noc_clk_src = {
 342         .cmd_rcgr = 0x06014,
 343         .hid_width = 5,
 344         .parent_map = gcc_xo_gpll0_map,
 345         .freq_tbl = ftbl_periph_noc_clk_src,
 346         .clkr.hw.init = &(struct clk_init_data){
 347                 .name = "periph_noc_clk_src",
 348                 .parent_names = gcc_xo_gpll0,
 349                 .num_parents = 2,
 350                 .ops = &clk_rcg2_ops,
 351         },
 352 };
 353
 354 static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
 355         F(19200000, P_XO, 1, 0, 0),
 356         F(120000000, P_GPLL0, 5, 0, 0),
 357         F(150000000, P_GPLL0, 4, 0, 0),
 358         { }
 359 };
 360
 361 static struct clk_rcg2 usb30_master_clk_src = {
 362         .cmd_rcgr = 0x0f014,
 363         .mnd_width = 8,
 364         .hid_width = 5,
 365         .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
 366         .freq_tbl = ftbl_usb30_master_clk_src,
 367         .clkr.hw.init = &(struct clk_init_data){
 368                 .name = "usb30_master_clk_src",
 369                 .parent_names = gcc_xo_gpll0_gpll0_early_div,
 370                 .num_parents = 3,
 371                 .ops = &clk_rcg2_ops,
 372         },
 373 };
 374
 375 static const struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {
 376         F(19200000, P_XO, 1, 0, 0),
 377         { }
 378 };
 379
 380 static struct clk_rcg2 usb30_mock_utmi_clk_src = {
 381         .cmd_rcgr = 0x0f028,
 382         .hid_width = 5,
 383         .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
 384         .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
 385         .clkr.hw.init = &(struct clk_init_data){
 386                 .name = "usb30_mock_utmi_clk_src",
 387                 .parent_names = gcc_xo_gpll0_gpll0_early_div,
 388                 .num_parents = 3,
 389                 .ops = &clk_rcg2_ops,
 390         },
 391 };
 392
 393 static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
 394         F(1200000, P_XO, 16, 0, 0),
 395         { }
 396 };
 397
 398 static struct clk_rcg2 usb3_phy_aux_clk_src = {
 399         .cmd_rcgr = 0x5000c,
 400         .hid_width = 5,
 401         .parent_map = gcc_xo_sleep_clk_map,
 402         .freq_tbl = ftbl_usb3_phy_aux_clk_src,
 403         .clkr.hw.init = &(struct clk_init_data){
 404                 .name = "usb3_phy_aux_clk_src",
 405                 .parent_names = gcc_xo_sleep_clk,
 406                 .num_parents = 2,
 407                 .ops = &clk_rcg2_ops,
 408         },
 409 };
 410
 411 static const struct freq_tbl ftbl_usb20_master_clk_src[] = {
 412         F(120000000, P_GPLL0, 5, 0, 0),
 413         { }
 414 };
 415
 416 static struct clk_rcg2 usb20_master_clk_src = {
 417         .cmd_rcgr = 0x12010,
 418         .mnd_width = 8,
 419         .hid_width = 5,
 420         .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
 421         .freq_tbl = ftbl_usb20_master_clk_src,
 422         .clkr.hw.init = &(struct clk_init_data){
 423                 .name = "usb20_master_clk_src",
 424                 .parent_names = gcc_xo_gpll0_gpll0_early_div,
 425                 .num_parents = 3,
 426                 .ops = &clk_rcg2_ops,
 427         },
 428 };
 429
 430 static struct clk_rcg2 usb20_mock_utmi_clk_src = {
 431         .cmd_rcgr = 0x12024,
 432         .hid_width = 5,
 433         .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
 434         .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
 435         .clkr.hw.init = &(struct clk_init_data){
 436                 .name = "usb20_mock_utmi_clk_src",
 437                 .parent_names = gcc_xo_gpll0_gpll0_early_div,
 438                 .num_parents = 3,
 439                 .ops = &clk_rcg2_ops,
 440         },
 441 };
 442
 443 static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
 444         F(144000, P_XO, 16, 3, 25),
 445         F(400000, P_XO, 12, 1, 4),
 446         F(20000000, P_GPLL0, 15, 1, 2),
 447         F(25000000, P_GPLL0, 12, 1, 2),
 448         F(50000000, P_GPLL0, 12, 0, 0),
 449         F(96000000, P_GPLL4, 4, 0, 0),
 450         F(192000000, P_GPLL4, 2, 0, 0),
 451         F(384000000, P_GPLL4, 1, 0, 0),
 452         { }
 453 };
 454
 455 static struct clk_rcg2 sdcc1_apps_clk_src = {
 456         .cmd_rcgr = 0x13010,
 457         .mnd_width = 8,
 458         .hid_width = 5,
 459         .parent_map = gcc_xo_gpll0_gpll4_gpll0_early_div_map,
 460         .freq_tbl = ftbl_sdcc1_apps_clk_src,
 461         .clkr.hw.init = &(struct clk_init_data){
 462                 .name = "sdcc1_apps_clk_src",
 463                 .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
 464                 .num_parents = 4,
 465                 .ops = &clk_rcg2_floor_ops,
 466         },
 467 };
 468
 469 static struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = {
 470         F(19200000, P_XO, 1, 0, 0),
 471         F(150000000, P_GPLL0, 4, 0, 0),
 472         F(300000000, P_GPLL0, 2, 0, 0),
 473         { }
 474 };
 475
 476 static struct clk_rcg2 sdcc1_ice_core_clk_src = {
 477         .cmd_rcgr = 0x13024,
 478         .hid_width = 5,
 479         .parent_map = gcc_xo_gpll0_gpll4_gpll0_early_div_map,
 480         .freq_tbl = ftbl_sdcc1_ice_core_clk_src,
 481         .clkr.hw.init = &(struct clk_init_data){
 482                 .name = "sdcc1_ice_core_clk_src",
 483                 .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
 484                 .num_parents = 4,
 485                 .ops = &clk_rcg2_ops,
 486         },
 487 };
 488
 489 static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
 490         F(144000, P_XO, 16, 3, 25),
 491         F(400000, P_XO, 12, 1, 4),
 492         F(20000000, P_GPLL0, 15, 1, 2),
 493         F(25000000, P_GPLL0, 12, 1, 2),
 494         F(50000000, P_GPLL0, 12, 0, 0),
 495         F(100000000, P_GPLL0, 6, 0, 0),
 496         F(200000000, P_GPLL0, 3, 0, 0),
 497         { }
 498 };
 499
 500 static struct clk_rcg2 sdcc2_apps_clk_src = {
 501         .cmd_rcgr = 0x14010,
 502         .mnd_width = 8,
 503         .hid_width = 5,
 504         .parent_map = gcc_xo_gpll0_gpll4_map,
 505         .freq_tbl = ftbl_sdcc2_apps_clk_src,
 506         .clkr.hw.init = &(struct clk_init_data){
 507                 .name = "sdcc2_apps_clk_src",
 508                 .parent_names = gcc_xo_gpll0_gpll4,
 509                 .num_parents = 3,
 510                 .ops = &clk_rcg2_floor_ops,
 511         },
 512 };
 513
 514 static struct clk_rcg2 sdcc3_apps_clk_src = {
 515         .cmd_rcgr = 0x15010,
 516         .mnd_width = 8,
 517         .hid_width = 5,
 518         .parent_map = gcc_xo_gpll0_gpll4_map,
 519         .freq_tbl = ftbl_sdcc2_apps_clk_src,
 520         .clkr.hw.init = &(struct clk_init_data){
 521                 .name = "sdcc3_apps_clk_src",
 522                 .parent_names = gcc_xo_gpll0_gpll4,
 523                 .num_parents = 3,
 524                 .ops = &clk_rcg2_floor_ops,
 525         },
 526 };
 527
 528 static const struct freq_tbl ftbl_sdcc4_apps_clk_src[] = {
 529         F(144000, P_XO, 16, 3, 25),
 530         F(400000, P_XO, 12, 1, 4),
 531         F(20000000, P_GPLL0, 15, 1, 2),
 532         F(25000000, P_GPLL0, 12, 1, 2),
 533         F(50000000, P_GPLL0, 12, 0, 0),
 534         F(100000000, P_GPLL0, 6, 0, 0),
 535         { }
 536 };
 537
 538 static struct clk_rcg2 sdcc4_apps_clk_src = {
 539         .cmd_rcgr = 0x16010,
 540         .mnd_width = 8,
 541         .hid_width = 5,
 542         .parent_map = gcc_xo_gpll0_map,
 543         .freq_tbl = ftbl_sdcc4_apps_clk_src,
 544         .clkr.hw.init = &(struct clk_init_data){
 545                 .name = "sdcc4_apps_clk_src",
 546                 .parent_names = gcc_xo_gpll0,
 547                 .num_parents = 2,
 548                 .ops = &clk_rcg2_floor_ops,
 549         },
 550 };
 551
 552 static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
 553         F(960000, P_XO, 10, 1, 2),
 554         F(4800000, P_XO, 4, 0, 0),
 555         F(9600000, P_XO, 2, 0, 0),
 556         F(15000000, P_GPLL0, 10, 1, 4),
 557         F(19200000, P_XO, 1, 0, 0),
 558         F(25000000, P_GPLL0, 12, 1, 2),
 559         F(50000000, P_GPLL0, 12, 0, 0),
 560         { }
 561 };
 562
 563 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
 564         .cmd_rcgr = 0x1900c,
 565         .mnd_width = 8,
 566         .hid_width = 5,
 567         .parent_map = gcc_xo_gpll0_map,
 568         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 569         .clkr.hw.init = &(struct clk_init_data){
 570                 .name = "blsp1_qup1_spi_apps_clk_src",
 571                 .parent_names = gcc_xo_gpll0,
 572                 .num_parents = 2,
 573                 .ops = &clk_rcg2_ops,
 574         },
 575 };
 576
 577 static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = {
 578         F(19200000, P_XO, 1, 0, 0),
 579         F(50000000, P_GPLL0, 12, 0, 0),
 580         { }
 581 };
 582
 583 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
 584         .cmd_rcgr = 0x19020,
 585         .hid_width = 5,
 586         .parent_map = gcc_xo_gpll0_map,
 587         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 588         .clkr.hw.init = &(struct clk_init_data){
 589                 .name = "blsp1_qup1_i2c_apps_clk_src",
 590                 .parent_names = gcc_xo_gpll0,
 591                 .num_parents = 2,
 592                 .ops = &clk_rcg2_ops,
 593         },
 594 };
 595
 596 static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] = {
 597         F(3686400, P_GPLL0, 1, 96, 15625),
 598         F(7372800, P_GPLL0, 1, 192, 15625),
 599         F(14745600, P_GPLL0, 1, 384, 15625),
 600         F(16000000, P_GPLL0, 5, 2, 15),
 601         F(19200000, P_XO, 1, 0, 0),
 602         F(24000000, P_GPLL0, 5, 1, 5),
 603         F(32000000, P_GPLL0, 1, 4, 75),
 604         F(40000000, P_GPLL0, 15, 0, 0),
 605         F(46400000, P_GPLL0, 1, 29, 375),
 606         F(48000000, P_GPLL0, 12.5, 0, 0),
 607         F(51200000, P_GPLL0, 1, 32, 375),
 608         F(56000000, P_GPLL0, 1, 7, 75),
 609         F(58982400, P_GPLL0, 1, 1536, 15625),
 610         F(60000000, P_GPLL0, 10, 0, 0),
 611         F(63157895, P_GPLL0, 9.5, 0, 0),
 612         { }
 613 };
 614
 615 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
 616         .cmd_rcgr = 0x1a00c,
 617         .mnd_width = 16,
 618         .hid_width = 5,
 619         .parent_map = gcc_xo_gpll0_map,
 620         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 621         .clkr.hw.init = &(struct clk_init_data){
 622                 .name = "blsp1_uart1_apps_clk_src",
 623                 .parent_names = gcc_xo_gpll0,
 624                 .num_parents = 2,
 625                 .ops = &clk_rcg2_ops,
 626         },
 627 };
 628
 629 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
 630         .cmd_rcgr = 0x1b00c,
 631         .mnd_width = 8,
 632         .hid_width = 5,
 633         .parent_map = gcc_xo_gpll0_map,
 634         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 635         .clkr.hw.init = &(struct clk_init_data){
 636                 .name = "blsp1_qup2_spi_apps_clk_src",
 637                 .parent_names = gcc_xo_gpll0,
 638                 .num_parents = 2,
 639                 .ops = &clk_rcg2_ops,
 640         },
 641 };
 642
 643 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
 644         .cmd_rcgr = 0x1b020,
 645         .hid_width = 5,
 646         .parent_map = gcc_xo_gpll0_map,
 647         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 648         .clkr.hw.init = &(struct clk_init_data){
 649                 .name = "blsp1_qup2_i2c_apps_clk_src",
 650                 .parent_names = gcc_xo_gpll0,
 651                 .num_parents = 2,
 652                 .ops = &clk_rcg2_ops,
 653         },
 654 };
 655
 656 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
 657         .cmd_rcgr = 0x1c00c,
 658         .mnd_width = 16,
 659         .hid_width = 5,
 660         .parent_map = gcc_xo_gpll0_map,
 661         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 662         .clkr.hw.init = &(struct clk_init_data){
 663                 .name = "blsp1_uart2_apps_clk_src",
 664                 .parent_names = gcc_xo_gpll0,
 665                 .num_parents = 2,
 666                 .ops = &clk_rcg2_ops,
 667         },
 668 };
 669
 670 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
 671         .cmd_rcgr = 0x1d00c,
 672         .mnd_width = 8,
 673         .hid_width = 5,
 674         .parent_map = gcc_xo_gpll0_map,
 675         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 676         .clkr.hw.init = &(struct clk_init_data){
 677                 .name = "blsp1_qup3_spi_apps_clk_src",
 678                 .parent_names = gcc_xo_gpll0,
 679                 .num_parents = 2,
 680                 .ops = &clk_rcg2_ops,
 681         },
 682 };
 683
 684 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
 685         .cmd_rcgr = 0x1d020,
 686         .hid_width = 5,
 687         .parent_map = gcc_xo_gpll0_map,
 688         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 689         .clkr.hw.init = &(struct clk_init_data){
 690                 .name = "blsp1_qup3_i2c_apps_clk_src",
 691                 .parent_names = gcc_xo_gpll0,
 692                 .num_parents = 2,
 693                 .ops = &clk_rcg2_ops,
 694         },
 695 };
 696
 697 static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
 698         .cmd_rcgr = 0x1e00c,
 699         .mnd_width = 16,
 700         .hid_width = 5,
 701         .parent_map = gcc_xo_gpll0_map,
 702         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 703         .clkr.hw.init = &(struct clk_init_data){
 704                 .name = "blsp1_uart3_apps_clk_src",
 705                 .parent_names = gcc_xo_gpll0,
 706                 .num_parents = 2,
 707                 .ops = &clk_rcg2_ops,
 708         },
 709 };
 710
 711 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
 712         .cmd_rcgr = 0x1f00c,
 713         .mnd_width = 8,
 714         .hid_width = 5,
 715         .parent_map = gcc_xo_gpll0_map,
 716         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 717         .clkr.hw.init = &(struct clk_init_data){
 718                 .name = "blsp1_qup4_spi_apps_clk_src",
 719                 .parent_names = gcc_xo_gpll0,
 720                 .num_parents = 2,
 721                 .ops = &clk_rcg2_ops,
 722         },
 723 };
 724
 725 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
 726         .cmd_rcgr = 0x1f020,
 727         .hid_width = 5,
 728         .parent_map = gcc_xo_gpll0_map,
 729         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 730         .clkr.hw.init = &(struct clk_init_data){
 731                 .name = "blsp1_qup4_i2c_apps_clk_src",
 732                 .parent_names = gcc_xo_gpll0,
 733                 .num_parents = 2,
 734                 .ops = &clk_rcg2_ops,
 735         },
 736 };
 737
 738 static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
 739         .cmd_rcgr = 0x2000c,
 740         .mnd_width = 16,
 741         .hid_width = 5,
 742         .parent_map = gcc_xo_gpll0_map,
 743         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 744         .clkr.hw.init = &(struct clk_init_data){
 745                 .name = "blsp1_uart4_apps_clk_src",
 746                 .parent_names = gcc_xo_gpll0,
 747                 .num_parents = 2,
 748                 .ops = &clk_rcg2_ops,
 749         },
 750 };
 751
 752 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
 753         .cmd_rcgr = 0x2100c,
 754         .mnd_width = 8,
 755         .hid_width = 5,
 756         .parent_map = gcc_xo_gpll0_map,
 757         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 758         .clkr.hw.init = &(struct clk_init_data){
 759                 .name = "blsp1_qup5_spi_apps_clk_src",
 760                 .parent_names = gcc_xo_gpll0,
 761                 .num_parents = 2,
 762                 .ops = &clk_rcg2_ops,
 763         },
 764 };
 765
 766 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
 767         .cmd_rcgr = 0x21020,
 768         .hid_width = 5,
 769         .parent_map = gcc_xo_gpll0_map,
 770         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 771         .clkr.hw.init = &(struct clk_init_data){
 772                 .name = "blsp1_qup5_i2c_apps_clk_src",
 773                 .parent_names = gcc_xo_gpll0,
 774                 .num_parents = 2,
 775                 .ops = &clk_rcg2_ops,
 776         },
 777 };
 778
 779 static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
 780         .cmd_rcgr = 0x2200c,
 781         .mnd_width = 16,
 782         .hid_width = 5,
 783         .parent_map = gcc_xo_gpll0_map,
 784         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 785         .clkr.hw.init = &(struct clk_init_data){
 786                 .name = "blsp1_uart5_apps_clk_src",
 787                 .parent_names = gcc_xo_gpll0,
 788                 .num_parents = 2,
 789                 .ops = &clk_rcg2_ops,
 790         },
 791 };
 792
 793 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
 794         .cmd_rcgr = 0x2300c,
 795         .mnd_width = 8,
 796         .hid_width = 5,
 797         .parent_map = gcc_xo_gpll0_map,
 798         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 799         .clkr.hw.init = &(struct clk_init_data){
 800                 .name = "blsp1_qup6_spi_apps_clk_src",
 801                 .parent_names = gcc_xo_gpll0,
 802                 .num_parents = 2,
 803                 .ops = &clk_rcg2_ops,
 804         },
 805 };
 806
 807 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
 808         .cmd_rcgr = 0x23020,
 809         .hid_width = 5,
 810         .parent_map = gcc_xo_gpll0_map,
 811         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 812         .clkr.hw.init = &(struct clk_init_data){
 813                 .name = "blsp1_qup6_i2c_apps_clk_src",
 814                 .parent_names = gcc_xo_gpll0,
 815                 .num_parents = 2,
 816                 .ops = &clk_rcg2_ops,
 817         },
 818 };
 819
 820 static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
 821         .cmd_rcgr = 0x2400c,
 822         .mnd_width = 16,
 823         .hid_width = 5,
 824         .parent_map = gcc_xo_gpll0_map,
 825         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 826         .clkr.hw.init = &(struct clk_init_data){
 827                 .name = "blsp1_uart6_apps_clk_src",
 828                 .parent_names = gcc_xo_gpll0,
 829                 .num_parents = 2,
 830                 .ops = &clk_rcg2_ops,
 831         },
 832 };
 833
 834 static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
 835         .cmd_rcgr = 0x2600c,
 836         .mnd_width = 8,
 837         .hid_width = 5,
 838         .parent_map = gcc_xo_gpll0_map,
 839         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 840         .clkr.hw.init = &(struct clk_init_data){
 841                 .name = "blsp2_qup1_spi_apps_clk_src",
 842                 .parent_names = gcc_xo_gpll0,
 843                 .num_parents = 2,
 844                 .ops = &clk_rcg2_ops,
 845         },
 846 };
 847
 848 static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
 849         .cmd_rcgr = 0x26020,
 850         .hid_width = 5,
 851         .parent_map = gcc_xo_gpll0_map,
 852         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 853         .clkr.hw.init = &(struct clk_init_data){
 854                 .name = "blsp2_qup1_i2c_apps_clk_src",
 855                 .parent_names = gcc_xo_gpll0,
 856                 .num_parents = 2,
 857                 .ops = &clk_rcg2_ops,
 858         },
 859 };
 860
 861 static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
 862         .cmd_rcgr = 0x2700c,
 863         .mnd_width = 16,
 864         .hid_width = 5,
 865         .parent_map = gcc_xo_gpll0_map,
 866         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 867         .clkr.hw.init = &(struct clk_init_data){
 868                 .name = "blsp2_uart1_apps_clk_src",
 869                 .parent_names = gcc_xo_gpll0,
 870                 .num_parents = 2,
 871                 .ops = &clk_rcg2_ops,
 872         },
 873 };
 874
 875 static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
 876         .cmd_rcgr = 0x2800c,
 877         .mnd_width = 8,
 878         .hid_width = 5,
 879         .parent_map = gcc_xo_gpll0_map,
 880         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 881         .clkr.hw.init = &(struct clk_init_data){
 882                 .name = "blsp2_qup2_spi_apps_clk_src",
 883                 .parent_names = gcc_xo_gpll0,
 884                 .num_parents = 2,
 885                 .ops = &clk_rcg2_ops,
 886         },
 887 };
 888
 889 static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
 890         .cmd_rcgr = 0x28020,
 891         .hid_width = 5,
 892         .parent_map = gcc_xo_gpll0_map,
 893         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 894         .clkr.hw.init = &(struct clk_init_data){
 895                 .name = "blsp2_qup2_i2c_apps_clk_src",
 896                 .parent_names = gcc_xo_gpll0,
 897                 .num_parents = 2,
 898                 .ops = &clk_rcg2_ops,
 899         },
 900 };
 901
 902 static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
 903         .cmd_rcgr = 0x2900c,
 904         .mnd_width = 16,
 905         .hid_width = 5,
 906         .parent_map = gcc_xo_gpll0_map,
 907         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 908         .clkr.hw.init = &(struct clk_init_data){
 909                 .name = "blsp2_uart2_apps_clk_src",
 910                 .parent_names = gcc_xo_gpll0,
 911                 .num_parents = 2,
 912                 .ops = &clk_rcg2_ops,
 913         },
 914 };
 915
 916 static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
 917         .cmd_rcgr = 0x2a00c,
 918         .mnd_width = 8,
 919         .hid_width = 5,
 920         .parent_map = gcc_xo_gpll0_map,
 921         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 922         .clkr.hw.init = &(struct clk_init_data){
 923                 .name = "blsp2_qup3_spi_apps_clk_src",
 924                 .parent_names = gcc_xo_gpll0,
 925                 .num_parents = 2,
 926                 .ops = &clk_rcg2_ops,
 927         },
 928 };
 929
 930 static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
 931         .cmd_rcgr = 0x2a020,
 932         .hid_width = 5,
 933         .parent_map = gcc_xo_gpll0_map,
 934         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 935         .clkr.hw.init = &(struct clk_init_data){
 936                 .name = "blsp2_qup3_i2c_apps_clk_src",
 937                 .parent_names = gcc_xo_gpll0,
 938                 .num_parents = 2,
 939                 .ops = &clk_rcg2_ops,
 940         },
 941 };
 942
 943 static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
 944         .cmd_rcgr = 0x2b00c,
 945         .mnd_width = 16,
 946         .hid_width = 5,
 947         .parent_map = gcc_xo_gpll0_map,
 948         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 949         .clkr.hw.init = &(struct clk_init_data){
 950                 .name = "blsp2_uart3_apps_clk_src",
 951                 .parent_names = gcc_xo_gpll0,
 952                 .num_parents = 2,
 953                 .ops = &clk_rcg2_ops,
 954         },
 955 };
 956
 957 static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
 958         .cmd_rcgr = 0x2c00c,
 959         .mnd_width = 8,
 960         .hid_width = 5,
 961         .parent_map = gcc_xo_gpll0_map,
 962         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 963         .clkr.hw.init = &(struct clk_init_data){
 964                 .name = "blsp2_qup4_spi_apps_clk_src",
 965                 .parent_names = gcc_xo_gpll0,
 966                 .num_parents = 2,
 967                 .ops = &clk_rcg2_ops,
 968         },
 969 };
 970
 971 static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
 972         .cmd_rcgr = 0x2c020,
 973         .hid_width = 5,
 974         .parent_map = gcc_xo_gpll0_map,
 975         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 976         .clkr.hw.init = &(struct clk_init_data){
 977                 .name = "blsp2_qup4_i2c_apps_clk_src",
 978                 .parent_names = gcc_xo_gpll0,
 979                 .num_parents = 2,
 980                 .ops = &clk_rcg2_ops,
 981         },
 982 };
 983
 984 static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
 985         .cmd_rcgr = 0x2d00c,
 986         .mnd_width = 16,
 987         .hid_width = 5,
 988         .parent_map = gcc_xo_gpll0_map,
 989         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 990         .clkr.hw.init = &(struct clk_init_data){
 991                 .name = "blsp2_uart4_apps_clk_src",
 992                 .parent_names = gcc_xo_gpll0,
 993                 .num_parents = 2,
 994                 .ops = &clk_rcg2_ops,
 995         },
 996 };
 997
 998 static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
 999         .cmd_rcgr = 0x2e00c,
1000         .mnd_width = 8,
1001         .hid_width = 5,
1002         .parent_map = gcc_xo_gpll0_map,
1003         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
1004         .clkr.hw.init = &(struct clk_init_data){
1005                 .name = "blsp2_qup5_spi_apps_clk_src",
1006                 .parent_names = gcc_xo_gpll0,
1007                 .num_parents = 2,
1008                 .ops = &clk_rcg2_ops,
1009         },
1010 };
1011
1012 static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
1013         .cmd_rcgr = 0x2e020,
1014         .hid_width = 5,
1015         .parent_map = gcc_xo_gpll0_map,
1016         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
1017         .clkr.hw.init = &(struct clk_init_data){
1018                 .name = "blsp2_qup5_i2c_apps_clk_src",
1019                 .parent_names = gcc_xo_gpll0,
1020                 .num_parents = 2,
1021                 .ops = &clk_rcg2_ops,
1022         },
1023 };
1024
1025 static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
1026         .cmd_rcgr = 0x2f00c,
1027         .mnd_width = 16,
1028         .hid_width = 5,
1029         .parent_map = gcc_xo_gpll0_map,
1030         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
1031         .clkr.hw.init = &(struct clk_init_data){
1032                 .name = "blsp2_uart5_apps_clk_src",
1033                 .parent_names = gcc_xo_gpll0,
1034                 .num_parents = 2,
1035                 .ops = &clk_rcg2_ops,
1036         },
1037 };
1038
1039 static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
1040         .cmd_rcgr = 0x3000c,
1041         .mnd_width = 8,
1042         .hid_width = 5,
1043         .parent_map = gcc_xo_gpll0_map,
1044         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
1045         .clkr.hw.init = &(struct clk_init_data){
1046                 .name = "blsp2_qup6_spi_apps_clk_src",
1047                 .parent_names = gcc_xo_gpll0,
1048                 .num_parents = 2,
1049                 .ops = &clk_rcg2_ops,
1050         },
1051 };
1052
1053 static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
1054         .cmd_rcgr = 0x30020,
1055         .hid_width = 5,
1056         .parent_map = gcc_xo_gpll0_map,
1057         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
1058         .clkr.hw.init = &(struct clk_init_data){
1059                 .name = "blsp2_qup6_i2c_apps_clk_src",
1060                 .parent_names = gcc_xo_gpll0,
1061                 .num_parents = 2,
1062                 .ops = &clk_rcg2_ops,
1063         },
1064 };
1065
1066 static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
1067         .cmd_rcgr = 0x3100c,
1068         .mnd_width = 16,
1069         .hid_width = 5,
1070         .parent_map = gcc_xo_gpll0_map,
1071         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
1072         .clkr.hw.init = &(struct clk_init_data){
1073                 .name = "blsp2_uart6_apps_clk_src",
1074                 .parent_names = gcc_xo_gpll0,
1075                 .num_parents = 2,
1076                 .ops = &clk_rcg2_ops,
1077         },
1078 };
1079
1080 static const struct freq_tbl ftbl_pdm2_clk_src[] = {
1081         F(60000000, P_GPLL0, 10, 0, 0),
1082         { }
1083 };
1084
1085 static struct clk_rcg2 pdm2_clk_src = {
1086         .cmd_rcgr = 0x33010,
1087         .hid_width = 5,
1088         .parent_map = gcc_xo_gpll0_map,
1089         .freq_tbl = ftbl_pdm2_clk_src,
1090         .clkr.hw.init = &(struct clk_init_data){
1091                 .name = "pdm2_clk_src",
1092                 .parent_names = gcc_xo_gpll0,
1093                 .num_parents = 2,
1094                 .ops = &clk_rcg2_ops,
1095         },
1096 };
1097
1098 static const struct freq_tbl ftbl_tsif_ref_clk_src[] = {
1099         F(105495, P_XO, 1, 1, 182),
1100         { }
1101 };
1102
1103 static struct clk_rcg2 tsif_ref_clk_src = {
1104         .cmd_rcgr = 0x36010,
1105         .mnd_width = 8,
1106         .hid_width = 5,
1107         .parent_map = gcc_xo_gpll0_aud_ref_clk_map,
1108         .freq_tbl = ftbl_tsif_ref_clk_src,
1109         .clkr.hw.init = &(struct clk_init_data){
1110                 .name = "tsif_ref_clk_src",
1111                 .parent_names = gcc_xo_gpll0_aud_ref_clk,
1112                 .num_parents = 3,
1113                 .ops = &clk_rcg2_ops,
1114         },
1115 };
1116
1117 static struct clk_rcg2 gcc_sleep_clk_src = {
1118         .cmd_rcgr = 0x43014,
1119         .hid_width = 5,
1120         .parent_map = gcc_sleep_clk_map,
1121         .clkr.hw.init = &(struct clk_init_data){
1122                 .name = "gcc_sleep_clk_src",
1123                 .parent_names = gcc_sleep_clk,
1124                 .num_parents = 1,
1125                 .ops = &clk_rcg2_ops,
1126         },
1127 };
1128
1129 static struct clk_rcg2 hmss_rbcpr_clk_src = {
1130         .cmd_rcgr = 0x48040,
1131         .hid_width = 5,
1132         .parent_map = gcc_xo_gpll0_map,
1133         .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
1134         .clkr.hw.init = &(struct clk_init_data){
1135                 .name = "hmss_rbcpr_clk_src",
1136                 .parent_names = gcc_xo_gpll0,
1137                 .num_parents = 2,
1138                 .ops = &clk_rcg2_ops,
1139         },
1140 };
1141
1142 static struct clk_rcg2 hmss_gpll0_clk_src = {
1143         .cmd_rcgr = 0x48058,
1144         .hid_width = 5,
1145         .parent_map = gcc_xo_gpll0_map,
1146         .clkr.hw.init = &(struct clk_init_data){
1147                 .name = "hmss_gpll0_clk_src",
1148                 .parent_names = gcc_xo_gpll0,
1149                 .num_parents = 2,
1150                 .ops = &clk_rcg2_ops,
1151         },
1152 };
1153
1154 static const struct freq_tbl ftbl_gp1_clk_src[] = {
1155         F(19200000, P_XO, 1, 0, 0),
1156         F(100000000, P_GPLL0, 6, 0, 0),
1157         F(200000000, P_GPLL0, 3, 0, 0),
1158         { }
1159 };
1160
1161 static struct clk_rcg2 gp1_clk_src = {
1162         .cmd_rcgr = 0x64004,
1163         .mnd_width = 8,
1164         .hid_width = 5,
1165         .parent_map = gcc_xo_gpll0_sleep_clk_gpll0_early_div_map,
1166         .freq_tbl = ftbl_gp1_clk_src,
1167         .clkr.hw.init = &(struct clk_init_data){
1168                 .name = "gp1_clk_src",
1169                 .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
1170                 .num_parents = 4,
1171                 .ops = &clk_rcg2_ops,
1172         },
1173 };
1174
1175 static struct clk_rcg2 gp2_clk_src = {
1176         .cmd_rcgr = 0x65004,
1177         .mnd_width = 8,
1178         .hid_width = 5,
1179         .parent_map = gcc_xo_gpll0_sleep_clk_gpll0_early_div_map,
1180         .freq_tbl = ftbl_gp1_clk_src,
1181         .clkr.hw.init = &(struct clk_init_data){
1182                 .name = "gp2_clk_src",
1183                 .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
1184                 .num_parents = 4,
1185                 .ops = &clk_rcg2_ops,
1186         },
1187 };
1188
1189 static struct clk_rcg2 gp3_clk_src = {
1190         .cmd_rcgr = 0x66004,
1191         .mnd_width = 8,
1192         .hid_width = 5,
1193         .parent_map = gcc_xo_gpll0_sleep_clk_gpll0_early_div_map,
1194         .freq_tbl = ftbl_gp1_clk_src,
1195         .clkr.hw.init = &(struct clk_init_data){
1196                 .name = "gp3_clk_src",
1197                 .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
1198                 .num_parents = 4,
1199                 .ops = &clk_rcg2_ops,
1200         },
1201 };
1202
1203 static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {
1204         F(1010526, P_XO, 1, 1, 19),
1205         { }
1206 };
1207
1208 static struct clk_rcg2 pcie_aux_clk_src = {
1209         .cmd_rcgr = 0x6c000,
1210         .mnd_width = 16,
1211         .hid_width = 5,
1212         .parent_map = gcc_xo_sleep_clk_map,
1213         .freq_tbl = ftbl_pcie_aux_clk_src,
1214         .clkr.hw.init = &(struct clk_init_data){
1215                 .name = "pcie_aux_clk_src",
1216                 .parent_names = gcc_xo_sleep_clk,
1217                 .num_parents = 2,
1218                 .ops = &clk_rcg2_ops,
1219         },
1220 };
1221
1222 static const struct freq_tbl ftbl_ufs_axi_clk_src[] = {
1223         F(100000000, P_GPLL0, 6, 0, 0),
1224         F(200000000, P_GPLL0, 3, 0, 0),
1225         F(240000000, P_GPLL0, 2.5, 0, 0),
1226         { }
1227 };
1228
1229 static struct clk_rcg2 ufs_axi_clk_src = {
1230         .cmd_rcgr = 0x75024,
1231         .mnd_width = 8,
1232         .hid_width = 5,
1233         .parent_map = gcc_xo_gpll0_map,
1234         .freq_tbl = ftbl_ufs_axi_clk_src,
1235         .clkr.hw.init = &(struct clk_init_data){
1236                 .name = "ufs_axi_clk_src",
1237                 .parent_names = gcc_xo_gpll0,
1238                 .num_parents = 2,
1239                 .ops = &clk_rcg2_ops,
1240         },
1241 };
1242
1243 static const struct freq_tbl ftbl_ufs_ice_core_clk_src[] = {
1244         F(19200000, P_XO, 1, 0, 0),
1245         F(150000000, P_GPLL0, 4, 0, 0),
1246         F(300000000, P_GPLL0, 2, 0, 0),
1247         { }
1248 };
1249
1250 static struct clk_rcg2 ufs_ice_core_clk_src = {
1251         .cmd_rcgr = 0x76014,
1252         .hid_width = 5,
1253         .parent_map = gcc_xo_gpll0_map,
1254         .freq_tbl = ftbl_ufs_ice_core_clk_src,
1255         .clkr.hw.init = &(struct clk_init_data){
1256                 .name = "ufs_ice_core_clk_src",
1257                 .parent_names = gcc_xo_gpll0,
1258                 .num_parents = 2,
1259                 .ops = &clk_rcg2_ops,
1260         },
1261 };
1262
1263 static const struct freq_tbl ftbl_qspi_ser_clk_src[] = {
1264         F(75000000, P_GPLL0, 8, 0, 0),
1265         F(150000000, P_GPLL0, 4, 0, 0),
1266         F(256000000, P_GPLL4, 1.5, 0, 0),
1267         F(300000000, P_GPLL0, 2, 0, 0),
1268         { }
1269 };
1270
1271 static struct clk_rcg2 qspi_ser_clk_src = {
1272         .cmd_rcgr = 0x8b00c,
1273         .hid_width = 5,
1274         .parent_map = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div_map,
1275         .freq_tbl = ftbl_qspi_ser_clk_src,
1276         .clkr.hw.init = &(struct clk_init_data){
1277                 .name = "qspi_ser_clk_src",
1278                 .parent_names = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div,
1279                 .num_parents = 6,
1280                 .ops = &clk_rcg2_ops,
1281         },
1282 };
1283
1284 static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
1285         .halt_reg = 0x0f03c,
1286         .clkr = {
1287                 .enable_reg = 0x0f03c,
1288                 .enable_mask = BIT(0),
1289                 .hw.init = &(struct clk_init_data){
1290                         .name = "gcc_sys_noc_usb3_axi_clk",
1291                         .parent_names = (const char *[]){ "usb30_master_clk_src" },
1292                         .num_parents = 1,
1293                         .flags = CLK_SET_RATE_PARENT,
1294                         .ops = &clk_branch2_ops,
1295                 },
1296         },
1297 };
1298
1299 static struct clk_branch gcc_sys_noc_ufs_axi_clk = {
1300         .halt_reg = 0x75038,
1301         .clkr = {
1302                 .enable_reg = 0x75038,
1303                 .enable_mask = BIT(0),
1304                 .hw.init = &(struct clk_init_data){
1305                         .name = "gcc_sys_noc_ufs_axi_clk",
1306                         .parent_names = (const char *[]){ "ufs_axi_clk_src" },
1307                         .num_parents = 1,
1308                         .flags = CLK_SET_RATE_PARENT,
1309                         .ops = &clk_branch2_ops,
1310                 },
1311         },
1312 };
1313
1314 static struct clk_branch gcc_periph_noc_usb20_ahb_clk = {
1315         .halt_reg = 0x6010,
1316         .clkr = {
1317                 .enable_reg = 0x6010,
1318                 .enable_mask = BIT(0),
1319                 .hw.init = &(struct clk_init_data){
1320                         .name = "gcc_periph_noc_usb20_ahb_clk",
1321                         .parent_names = (const char *[]){ "usb20_master_clk_src" },
1322                         .num_parents = 1,
1323                         .flags = CLK_SET_RATE_PARENT,
1324                         .ops = &clk_branch2_ops,
1325                 },
1326         },
1327 };
1328
1329 static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
1330         .halt_reg = 0x9008,
1331         .clkr = {
1332                 .enable_reg = 0x9008,
1333                 .enable_mask = BIT(0),
1334                 .hw.init = &(struct clk_init_data){
1335                         .name = "gcc_mmss_noc_cfg_ahb_clk",
1336                         .parent_names = (const char *[]){ "config_noc_clk_src" },
1337                         .num_parents = 1,
1338                         .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1339                         .ops = &clk_branch2_ops,
1340                 },
1341         },
1342 };
1343
1344 static struct clk_branch gcc_mmss_bimc_gfx_clk = {
1345         .halt_reg = 0x9010,
1346         .clkr = {
1347                 .enable_reg = 0x9010,
1348                 .enable_mask = BIT(0),
1349                 .hw.init = &(struct clk_init_data){
1350                         .name = "gcc_mmss_bimc_gfx_clk",
1351                         .flags = CLK_SET_RATE_PARENT,
1352                         .ops = &clk_branch2_ops,
1353                 },
1354         },
1355 };
1356
1357 static struct clk_branch gcc_usb30_master_clk = {
1358         .halt_reg = 0x0f008,
1359         .clkr = {
1360                 .enable_reg = 0x0f008,
1361                 .enable_mask = BIT(0),
1362                 .hw.init = &(struct clk_init_data){
1363                         .name = "gcc_usb30_master_clk",
1364                         .parent_names = (const char *[]){ "usb30_master_clk_src" },
1365                         .num_parents = 1,
1366                         .flags = CLK_SET_RATE_PARENT,
1367                         .ops = &clk_branch2_ops,
1368                 },
1369         },
1370 };
1371
1372 static struct clk_branch gcc_usb30_sleep_clk = {
1373         .halt_reg = 0x0f00c,
1374         .clkr = {
1375                 .enable_reg = 0x0f00c,
1376                 .enable_mask = BIT(0),
1377                 .hw.init = &(struct clk_init_data){
1378                         .name = "gcc_usb30_sleep_clk",
1379                         .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
1380                         .num_parents = 1,
1381                         .flags = CLK_SET_RATE_PARENT,
1382                         .ops = &clk_branch2_ops,
1383                 },
1384         },
1385 };
1386
1387 static struct clk_branch gcc_usb30_mock_utmi_clk = {
1388         .halt_reg = 0x0f010,
1389         .clkr = {
1390                 .enable_reg = 0x0f010,
1391                 .enable_mask = BIT(0),
1392                 .hw.init = &(struct clk_init_data){
1393                         .name = "gcc_usb30_mock_utmi_clk",
1394                         .parent_names = (const char *[]){ "usb30_mock_utmi_clk_src" },
1395                         .num_parents = 1,
1396                         .flags = CLK_SET_RATE_PARENT,
1397                         .ops = &clk_branch2_ops,
1398                 },
1399         },
1400 };
1401
1402 static struct clk_branch gcc_usb3_phy_aux_clk = {
1403         .halt_reg = 0x50000,
1404         .clkr = {
1405                 .enable_reg = 0x50000,
1406                 .enable_mask = BIT(0),
1407                 .hw.init = &(struct clk_init_data){
1408                         .name = "gcc_usb3_phy_aux_clk",
1409                         .parent_names = (const char *[]){ "usb3_phy_aux_clk_src" },
1410                         .num_parents = 1,
1411                         .flags = CLK_SET_RATE_PARENT,
1412                         .ops = &clk_branch2_ops,
1413                 },
1414         },
1415 };
1416
1417 static struct clk_branch gcc_usb3_phy_pipe_clk = {
1418         .halt_reg = 0x50004,
1419         .halt_check = BRANCH_HALT_SKIP,
1420         .clkr = {
1421                 .enable_reg = 0x50004,
1422                 .enable_mask = BIT(0),
1423                 .hw.init = &(struct clk_init_data){
1424                         .name = "gcc_usb3_phy_pipe_clk",
1425                         .parent_names = (const char *[]){ "usb3_phy_pipe_clk_src" },
1426                         .num_parents = 1,
1427                         .flags = CLK_SET_RATE_PARENT,
1428                         .ops = &clk_branch2_ops,
1429                 },
1430         },
1431 };
1432
1433 static struct clk_branch gcc_usb20_master_clk = {
1434         .halt_reg = 0x12004,
1435         .clkr = {
1436                 .enable_reg = 0x12004,
1437                 .enable_mask = BIT(0),
1438                 .hw.init = &(struct clk_init_data){
1439                         .name = "gcc_usb20_master_clk",
1440                         .parent_names = (const char *[]){ "usb20_master_clk_src" },
1441                         .num_parents = 1,
1442                         .flags = CLK_SET_RATE_PARENT,
1443                         .ops = &clk_branch2_ops,
1444                 },
1445         },
1446 };
1447
1448 static struct clk_branch gcc_usb20_sleep_clk = {
1449         .halt_reg = 0x12008,
1450         .clkr = {
1451                 .enable_reg = 0x12008,
1452                 .enable_mask = BIT(0),
1453                 .hw.init = &(struct clk_init_data){
1454                         .name = "gcc_usb20_sleep_clk",
1455                         .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
1456                         .num_parents = 1,
1457                         .flags = CLK_SET_RATE_PARENT,
1458                         .ops = &clk_branch2_ops,
1459                 },
1460         },
1461 };
1462
1463 static struct clk_branch gcc_usb20_mock_utmi_clk = {
1464         .halt_reg = 0x1200c,
1465         .clkr = {
1466                 .enable_reg = 0x1200c,
1467                 .enable_mask = BIT(0),
1468                 .hw.init = &(struct clk_init_data){
1469                         .name = "gcc_usb20_mock_utmi_clk",
1470                         .parent_names = (const char *[]){ "usb20_mock_utmi_clk_src" },
1471                         .num_parents = 1,
1472                         .flags = CLK_SET_RATE_PARENT,
1473                         .ops = &clk_branch2_ops,
1474                 },
1475         },
1476 };
1477
1478 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
1479         .halt_reg = 0x6a004,
1480         .clkr = {
1481                 .enable_reg = 0x6a004,
1482                 .enable_mask = BIT(0),
1483                 .hw.init = &(struct clk_init_data){
1484                         .name = "gcc_usb_phy_cfg_ahb2phy_clk",
1485                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
1486                         .num_parents = 1,
1487                         .flags = CLK_SET_RATE_PARENT,
1488                         .ops = &clk_branch2_ops,
1489                 },
1490         },
1491 };
1492
1493 static struct clk_branch gcc_sdcc1_apps_clk = {
1494         .halt_reg = 0x13004,
1495         .clkr = {
1496                 .enable_reg = 0x13004,
1497                 .enable_mask = BIT(0),
1498                 .hw.init = &(struct clk_init_data){
1499                         .name = "gcc_sdcc1_apps_clk",
1500                         .parent_names = (const char *[]){ "sdcc1_apps_clk_src" },
1501                         .num_parents = 1,
1502                         .flags = CLK_SET_RATE_PARENT,
1503                         .ops = &clk_branch2_ops,
1504                 },
1505         },
1506 };
1507
1508 static struct clk_branch gcc_sdcc1_ahb_clk = {
1509         .halt_reg = 0x13008,
1510         .clkr = {
1511                 .enable_reg = 0x13008,
1512                 .enable_mask = BIT(0),
1513                 .hw.init = &(struct clk_init_data){
1514                         .name = "gcc_sdcc1_ahb_clk",
1515                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
1516                         .num_parents = 1,
1517                         .flags = CLK_SET_RATE_PARENT,
1518                         .ops = &clk_branch2_ops,
1519                 },
1520         },
1521 };
1522
1523 static struct clk_branch gcc_sdcc1_ice_core_clk = {
1524         .halt_reg = 0x13038,
1525         .clkr = {
1526                 .enable_reg = 0x13038,
1527                 .enable_mask = BIT(0),
1528                 .hw.init = &(struct clk_init_data){
1529                         .name = "gcc_sdcc1_ice_core_clk",
1530                         .parent_names = (const char *[]){ "sdcc1_ice_core_clk_src" },
1531                         .num_parents = 1,
1532                         .flags = CLK_SET_RATE_PARENT,
1533                         .ops = &clk_branch2_ops,
1534                 },
1535         },
1536 };
1537
1538 static struct clk_branch gcc_sdcc2_apps_clk = {
1539         .halt_reg = 0x14004,
1540         .clkr = {
1541                 .enable_reg = 0x14004,
1542                 .enable_mask = BIT(0),
1543                 .hw.init = &(struct clk_init_data){
1544                         .name = "gcc_sdcc2_apps_clk",
1545                         .parent_names = (const char *[]){ "sdcc2_apps_clk_src" },
1546                         .num_parents = 1,
1547                         .flags = CLK_SET_RATE_PARENT,
1548                         .ops = &clk_branch2_ops,
1549                 },
1550         },
1551 };
1552
1553 static struct clk_branch gcc_sdcc2_ahb_clk = {
1554         .halt_reg = 0x14008,
1555         .clkr = {
1556                 .enable_reg = 0x14008,
1557                 .enable_mask = BIT(0),
1558                 .hw.init = &(struct clk_init_data){
1559                         .name = "gcc_sdcc2_ahb_clk",
1560                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
1561                         .num_parents = 1,
1562                         .flags = CLK_SET_RATE_PARENT,
1563                         .ops = &clk_branch2_ops,
1564                 },
1565         },
1566 };
1567
1568 static struct clk_branch gcc_sdcc3_apps_clk = {
1569         .halt_reg = 0x15004,
1570         .clkr = {
1571                 .enable_reg = 0x15004,
1572                 .enable_mask = BIT(0),
1573                 .hw.init = &(struct clk_init_data){
1574                         .name = "gcc_sdcc3_apps_clk",
1575                         .parent_names = (const char *[]){ "sdcc3_apps_clk_src" },
1576                         .num_parents = 1,
1577                         .flags = CLK_SET_RATE_PARENT,
1578                         .ops = &clk_branch2_ops,
1579                 },
1580         },
1581 };
1582
1583 static struct clk_branch gcc_sdcc3_ahb_clk = {
1584         .halt_reg = 0x15008,
1585         .clkr = {
1586                 .enable_reg = 0x15008,
1587                 .enable_mask = BIT(0),
1588                 .hw.init = &(struct clk_init_data){
1589                         .name = "gcc_sdcc3_ahb_clk",
1590                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
1591                         .num_parents = 1,
1592                         .flags = CLK_SET_RATE_PARENT,
1593                         .ops = &clk_branch2_ops,
1594                 },
1595         },
1596 };
1597
1598 static struct clk_branch gcc_sdcc4_apps_clk = {
1599         .halt_reg = 0x16004,
1600         .clkr = {
1601                 .enable_reg = 0x16004,
1602                 .enable_mask = BIT(0),
1603                 .hw.init = &(struct clk_init_data){
1604                         .name = "gcc_sdcc4_apps_clk",
1605                         .parent_names = (const char *[]){ "sdcc4_apps_clk_src" },
1606                         .num_parents = 1,
1607                         .flags = CLK_SET_RATE_PARENT,
1608                         .ops = &clk_branch2_ops,
1609                 },
1610         },
1611 };
1612
1613 static struct clk_branch gcc_sdcc4_ahb_clk = {
1614         .halt_reg = 0x16008,
1615         .clkr = {
1616                 .enable_reg = 0x16008,
1617                 .enable_mask = BIT(0),
1618                 .hw.init = &(struct clk_init_data){
1619                         .name = "gcc_sdcc4_ahb_clk",
1620                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
1621                         .num_parents = 1,
1622                         .flags = CLK_SET_RATE_PARENT,
1623                         .ops = &clk_branch2_ops,
1624                 },
1625         },
1626 };
1627
1628 static struct clk_branch gcc_blsp1_ahb_clk = {
1629         .halt_reg = 0x17004,
1630         .halt_check = BRANCH_HALT_VOTED,
1631         .clkr = {
1632                 .enable_reg = 0x52004,
1633                 .enable_mask = BIT(17),
1634                 .hw.init = &(struct clk_init_data){
1635                         .name = "gcc_blsp1_ahb_clk",
1636                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
1637                         .num_parents = 1,
1638                         .flags = CLK_SET_RATE_PARENT,
1639                         .ops = &clk_branch2_ops,
1640                 },
1641         },
1642 };
1643
1644 static struct clk_branch gcc_blsp1_sleep_clk = {
1645         .halt_reg = 0x17008,
1646         .halt_check = BRANCH_HALT_VOTED,
1647         .clkr = {
1648                 .enable_reg = 0x52004,
1649                 .enable_mask = BIT(16),
1650                 .hw.init = &(struct clk_init_data){
1651                         .name = "gcc_blsp1_sleep_clk",
1652                         .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
1653                         .num_parents = 1,
1654                         .flags = CLK_SET_RATE_PARENT,
1655                         .ops = &clk_branch2_ops,
1656                 },
1657         },
1658 };
1659
1660 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1661         .halt_reg = 0x19004,
1662         .clkr = {
1663                 .enable_reg = 0x19004,
1664                 .enable_mask = BIT(0),
1665                 .hw.init = &(struct clk_init_data){
1666                         .name = "gcc_blsp1_qup1_spi_apps_clk",
1667                         .parent_names = (const char *[]){ "blsp1_qup1_spi_apps_clk_src" },
1668                         .num_parents = 1,
1669                         .flags = CLK_SET_RATE_PARENT,
1670                         .ops = &clk_branch2_ops,
1671                 },
1672         },
1673 };
1674
1675 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1676         .halt_reg = 0x19008,
1677         .clkr = {
1678                 .enable_reg = 0x19008,
1679                 .enable_mask = BIT(0),
1680                 .hw.init = &(struct clk_init_data){
1681                         .name = "gcc_blsp1_qup1_i2c_apps_clk",
1682                         .parent_names = (const char *[]){ "blsp1_qup1_i2c_apps_clk_src" },
1683                         .num_parents = 1,
1684                         .flags = CLK_SET_RATE_PARENT,
1685                         .ops = &clk_branch2_ops,
1686                 },
1687         },
1688 };
1689
1690 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1691         .halt_reg = 0x1a004,
1692         .clkr = {
1693                 .enable_reg = 0x1a004,
1694                 .enable_mask = BIT(0),
1695                 .hw.init = &(struct clk_init_data){
1696                         .name = "gcc_blsp1_uart1_apps_clk",
1697                         .parent_names = (const char *[]){ "blsp1_uart1_apps_clk_src" },
1698                         .num_parents = 1,
1699                         .flags = CLK_SET_RATE_PARENT,
1700                         .ops = &clk_branch2_ops,
1701                 },
1702         },
1703 };
1704
1705 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1706         .halt_reg = 0x1b004,
1707         .clkr = {
1708                 .enable_reg = 0x1b004,
1709                 .enable_mask = BIT(0),
1710                 .hw.init = &(struct clk_init_data){
1711                         .name = "gcc_blsp1_qup2_spi_apps_clk",
1712                         .parent_names = (const char *[]){ "blsp1_qup2_spi_apps_clk_src" },
1713                         .num_parents = 1,
1714                         .flags = CLK_SET_RATE_PARENT,
1715                         .ops = &clk_branch2_ops,
1716                 },
1717         },
1718 };
1719
1720 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1721         .halt_reg = 0x1b008,
1722         .clkr = {
1723                 .enable_reg = 0x1b008,
1724                 .enable_mask = BIT(0),
1725                 .hw.init = &(struct clk_init_data){
1726                         .name = "gcc_blsp1_qup2_i2c_apps_clk",
1727                         .parent_names = (const char *[]){ "blsp1_qup2_i2c_apps_clk_src" },
1728                         .num_parents = 1,
1729                         .flags = CLK_SET_RATE_PARENT,
1730                         .ops = &clk_branch2_ops,
1731                 },
1732         },
1733 };
1734
1735 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1736         .halt_reg = 0x1c004,
1737         .clkr = {
1738                 .enable_reg = 0x1c004,
1739                 .enable_mask = BIT(0),
1740                 .hw.init = &(struct clk_init_data){
1741                         .name = "gcc_blsp1_uart2_apps_clk",
1742                         .parent_names = (const char *[]){ "blsp1_uart2_apps_clk_src" },
1743                         .num_parents = 1,
1744                         .flags = CLK_SET_RATE_PARENT,
1745                         .ops = &clk_branch2_ops,
1746                 },
1747         },
1748 };
1749
1750 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1751         .halt_reg = 0x1d004,
1752         .clkr = {
1753                 .enable_reg = 0x1d004,
1754                 .enable_mask = BIT(0),
1755                 .hw.init = &(struct clk_init_data){
1756                         .name = "gcc_blsp1_qup3_spi_apps_clk",
1757                         .parent_names = (const char *[]){ "blsp1_qup3_spi_apps_clk_src" },
1758                         .num_parents = 1,
1759                         .flags = CLK_SET_RATE_PARENT,
1760                         .ops = &clk_branch2_ops,
1761                 },
1762         },
1763 };
1764
1765 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1766         .halt_reg = 0x1d008,
1767         .clkr = {
1768                 .enable_reg = 0x1d008,
1769                 .enable_mask = BIT(0),
1770                 .hw.init = &(struct clk_init_data){
1771                         .name = "gcc_blsp1_qup3_i2c_apps_clk",
1772                         .parent_names = (const char *[]){ "blsp1_qup3_i2c_apps_clk_src" },
1773                         .num_parents = 1,
1774                         .flags = CLK_SET_RATE_PARENT,
1775                         .ops = &clk_branch2_ops,
1776                 },
1777         },
1778 };
1779
1780 static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1781         .halt_reg = 0x1e004,
1782         .clkr = {
1783                 .enable_reg = 0x1e004,
1784                 .enable_mask = BIT(0),
1785                 .hw.init = &(struct clk_init_data){
1786                         .name = "gcc_blsp1_uart3_apps_clk",
1787                         .parent_names = (const char *[]){ "blsp1_uart3_apps_clk_src" },
1788                         .num_parents = 1,
1789                         .flags = CLK_SET_RATE_PARENT,
1790                         .ops = &clk_branch2_ops,
1791                 },
1792         },
1793 };
1794
1795 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1796         .halt_reg = 0x1f004,
1797         .clkr = {
1798                 .enable_reg = 0x1f004,
1799                 .enable_mask = BIT(0),
1800                 .hw.init = &(struct clk_init_data){
1801                         .name = "gcc_blsp1_qup4_spi_apps_clk",
1802                         .parent_names = (const char *[]){ "blsp1_qup4_spi_apps_clk_src" },
1803                         .num_parents = 1,
1804                         .flags = CLK_SET_RATE_PARENT,
1805                         .ops = &clk_branch2_ops,
1806                 },
1807         },
1808 };
1809
1810 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1811         .halt_reg = 0x1f008,
1812         .clkr = {
1813                 .enable_reg = 0x1f008,
1814                 .enable_mask = BIT(0),
1815                 .hw.init = &(struct clk_init_data){
1816                         .name = "gcc_blsp1_qup4_i2c_apps_clk",
1817                         .parent_names = (const char *[]){ "blsp1_qup4_i2c_apps_clk_src" },
1818                         .num_parents = 1,
1819                         .flags = CLK_SET_RATE_PARENT,
1820                         .ops = &clk_branch2_ops,
1821                 },
1822         },
1823 };
1824
1825 static struct clk_branch gcc_blsp1_uart4_apps_clk = {
1826         .halt_reg = 0x20004,
1827         .clkr = {
1828                 .enable_reg = 0x20004,
1829                 .enable_mask = BIT(0),
1830                 .hw.init = &(struct clk_init_data){
1831                         .name = "gcc_blsp1_uart4_apps_clk",
1832                         .parent_names = (const char *[]){ "blsp1_uart4_apps_clk_src" },
1833                         .num_parents = 1,
1834                         .flags = CLK_SET_RATE_PARENT,
1835                         .ops = &clk_branch2_ops,
1836                 },
1837         },
1838 };
1839
1840 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
1841         .halt_reg = 0x21004,
1842         .clkr = {
1843                 .enable_reg = 0x21004,
1844                 .enable_mask = BIT(0),
1845                 .hw.init = &(struct clk_init_data){
1846                         .name = "gcc_blsp1_qup5_spi_apps_clk",
1847                         .parent_names = (const char *[]){ "blsp1_qup5_spi_apps_clk_src" },
1848                         .num_parents = 1,
1849                         .flags = CLK_SET_RATE_PARENT,
1850                         .ops = &clk_branch2_ops,
1851                 },
1852         },
1853 };
1854
1855 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
1856         .halt_reg = 0x21008,
1857         .clkr = {
1858                 .enable_reg = 0x21008,
1859                 .enable_mask = BIT(0),
1860                 .hw.init = &(struct clk_init_data){
1861                         .name = "gcc_blsp1_qup5_i2c_apps_clk",
1862                         .parent_names = (const char *[]){ "blsp1_qup5_i2c_apps_clk_src" },
1863                         .num_parents = 1,
1864                         .flags = CLK_SET_RATE_PARENT,
1865                         .ops = &clk_branch2_ops,
1866                 },
1867         },
1868 };
1869
1870 static struct clk_branch gcc_blsp1_uart5_apps_clk = {
1871         .halt_reg = 0x22004,
1872         .clkr = {
1873                 .enable_reg = 0x22004,
1874                 .enable_mask = BIT(0),
1875                 .hw.init = &(struct clk_init_data){
1876                         .name = "gcc_blsp1_uart5_apps_clk",
1877                         .parent_names = (const char *[]){ "blsp1_uart5_apps_clk_src" },
1878                         .num_parents = 1,
1879                         .flags = CLK_SET_RATE_PARENT,
1880                         .ops = &clk_branch2_ops,
1881                 },
1882         },
1883 };
1884
1885 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1886         .halt_reg = 0x23004,
1887         .clkr = {
1888                 .enable_reg = 0x23004,
1889                 .enable_mask = BIT(0),
1890                 .hw.init = &(struct clk_init_data){
1891                         .name = "gcc_blsp1_qup6_spi_apps_clk",
1892                         .parent_names = (const char *[]){ "blsp1_qup6_spi_apps_clk_src" },
1893                         .num_parents = 1,
1894                         .flags = CLK_SET_RATE_PARENT,
1895                         .ops = &clk_branch2_ops,
1896                 },
1897         },
1898 };
1899
1900 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
1901         .halt_reg = 0x23008,
1902         .clkr = {
1903                 .enable_reg = 0x23008,
1904                 .enable_mask = BIT(0),
1905                 .hw.init = &(struct clk_init_data){
1906                         .name = "gcc_blsp1_qup6_i2c_apps_clk",
1907                         .parent_names = (const char *[]){ "blsp1_qup6_i2c_apps_clk_src" },
1908                         .num_parents = 1,
1909                         .flags = CLK_SET_RATE_PARENT,
1910                         .ops = &clk_branch2_ops,
1911                 },
1912         },
1913 };
1914
1915 static struct clk_branch gcc_blsp1_uart6_apps_clk = {
1916         .halt_reg = 0x24004,
1917         .clkr = {
1918                 .enable_reg = 0x24004,
1919                 .enable_mask = BIT(0),
1920                 .hw.init = &(struct clk_init_data){
1921                         .name = "gcc_blsp1_uart6_apps_clk",
1922                         .parent_names = (const char *[]){ "blsp1_uart6_apps_clk_src" },
1923                         .num_parents = 1,
1924                         .flags = CLK_SET_RATE_PARENT,
1925                         .ops = &clk_branch2_ops,
1926                 },
1927         },
1928 };
1929
1930 static struct clk_branch gcc_blsp2_ahb_clk = {
1931         .halt_reg = 0x25004,
1932         .halt_check = BRANCH_HALT_VOTED,
1933         .clkr = {
1934                 .enable_reg = 0x52004,
1935                 .enable_mask = BIT(15),
1936                 .hw.init = &(struct clk_init_data){
1937                         .name = "gcc_blsp2_ahb_clk",
1938                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
1939                         .num_parents = 1,
1940                         .flags = CLK_SET_RATE_PARENT,
1941                         .ops = &clk_branch2_ops,
1942                 },
1943         },
1944 };
1945
1946 static struct clk_branch gcc_blsp2_sleep_clk = {
1947         .halt_reg = 0x25008,
1948         .halt_check = BRANCH_HALT_VOTED,
1949         .clkr = {
1950                 .enable_reg = 0x52004,
1951                 .enable_mask = BIT(14),
1952                 .hw.init = &(struct clk_init_data){
1953                         .name = "gcc_blsp2_sleep_clk",
1954                         .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
1955                         .num_parents = 1,
1956                         .flags = CLK_SET_RATE_PARENT,
1957                         .ops = &clk_branch2_ops,
1958                 },
1959         },
1960 };
1961
1962 static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
1963         .halt_reg = 0x26004,
1964         .clkr = {
1965                 .enable_reg = 0x26004,
1966                 .enable_mask = BIT(0),
1967                 .hw.init = &(struct clk_init_data){
1968                         .name = "gcc_blsp2_qup1_spi_apps_clk",
1969                         .parent_names = (const char *[]){ "blsp2_qup1_spi_apps_clk_src" },
1970                         .num_parents = 1,
1971                         .flags = CLK_SET_RATE_PARENT,
1972                         .ops = &clk_branch2_ops,
1973                 },
1974         },
1975 };
1976
1977 static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
1978         .halt_reg = 0x26008,
1979         .clkr = {
1980                 .enable_reg = 0x26008,
1981                 .enable_mask = BIT(0),
1982                 .hw.init = &(struct clk_init_data){
1983                         .name = "gcc_blsp2_qup1_i2c_apps_clk",
1984                         .parent_names = (const char *[]){ "blsp2_qup1_i2c_apps_clk_src" },
1985                         .num_parents = 1,
1986                         .flags = CLK_SET_RATE_PARENT,
1987                         .ops = &clk_branch2_ops,
1988                 },
1989         },
1990 };
1991
1992 static struct clk_branch gcc_blsp2_uart1_apps_clk = {
1993         .halt_reg = 0x27004,
1994         .clkr = {
1995                 .enable_reg = 0x27004,
1996                 .enable_mask = BIT(0),
1997                 .hw.init = &(struct clk_init_data){
1998                         .name = "gcc_blsp2_uart1_apps_clk",
1999                         .parent_names = (const char *[]){ "blsp2_uart1_apps_clk_src" },
2000                         .num_parents = 1,
2001                         .flags = CLK_SET_RATE_PARENT,
2002                         .ops = &clk_branch2_ops,
2003                 },
2004         },
2005 };
2006
2007 static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
2008         .halt_reg = 0x28004,
2009         .clkr = {
2010                 .enable_reg = 0x28004,
2011                 .enable_mask = BIT(0),
2012                 .hw.init = &(struct clk_init_data){
2013                         .name = "gcc_blsp2_qup2_spi_apps_clk",
2014                         .parent_names = (const char *[]){ "blsp2_qup2_spi_apps_clk_src" },
2015                         .num_parents = 1,
2016                         .flags = CLK_SET_RATE_PARENT,
2017                         .ops = &clk_branch2_ops,
2018                 },
2019         },
2020 };
2021
2022 static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
2023         .halt_reg = 0x28008,
2024         .clkr = {
2025                 .enable_reg = 0x28008,
2026                 .enable_mask = BIT(0),
2027                 .hw.init = &(struct clk_init_data){
2028                         .name = "gcc_blsp2_qup2_i2c_apps_clk",
2029                         .parent_names = (const char *[]){ "blsp2_qup2_i2c_apps_clk_src" },
2030                         .num_parents = 1,
2031                         .flags = CLK_SET_RATE_PARENT,
2032                         .ops = &clk_branch2_ops,
2033                 },
2034         },
2035 };
2036
2037 static struct clk_branch gcc_blsp2_uart2_apps_clk = {
2038         .halt_reg = 0x29004,
2039         .clkr = {
2040                 .enable_reg = 0x29004,
2041                 .enable_mask = BIT(0),
2042                 .hw.init = &(struct clk_init_data){
2043                         .name = "gcc_blsp2_uart2_apps_clk",
2044                         .parent_names = (const char *[]){ "blsp2_uart2_apps_clk_src" },
2045                         .num_parents = 1,
2046                         .flags = CLK_SET_RATE_PARENT,
2047                         .ops = &clk_branch2_ops,
2048                 },
2049         },
2050 };
2051
2052 static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
2053         .halt_reg = 0x2a004,
2054         .clkr = {
2055                 .enable_reg = 0x2a004,
2056                 .enable_mask = BIT(0),
2057                 .hw.init = &(struct clk_init_data){
2058                         .name = "gcc_blsp2_qup3_spi_apps_clk",
2059                         .parent_names = (const char *[]){ "blsp2_qup3_spi_apps_clk_src" },
2060                         .num_parents = 1,
2061                         .flags = CLK_SET_RATE_PARENT,
2062                         .ops = &clk_branch2_ops,
2063                 },
2064         },
2065 };
2066
2067 static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
2068         .halt_reg = 0x2a008,
2069         .clkr = {
2070                 .enable_reg = 0x2a008,
2071                 .enable_mask = BIT(0),
2072                 .hw.init = &(struct clk_init_data){
2073                         .name = "gcc_blsp2_qup3_i2c_apps_clk",
2074                         .parent_names = (const char *[]){ "blsp2_qup3_i2c_apps_clk_src" },
2075                         .num_parents = 1,
2076                         .flags = CLK_SET_RATE_PARENT,
2077                         .ops = &clk_branch2_ops,
2078                 },
2079         },
2080 };
2081
2082 static struct clk_branch gcc_blsp2_uart3_apps_clk = {
2083         .halt_reg = 0x2b004,
2084         .clkr = {
2085                 .enable_reg = 0x2b004,
2086                 .enable_mask = BIT(0),
2087                 .hw.init = &(struct clk_init_data){
2088                         .name = "gcc_blsp2_uart3_apps_clk",
2089                         .parent_names = (const char *[]){ "blsp2_uart3_apps_clk_src" },
2090                         .num_parents = 1,
2091                         .flags = CLK_SET_RATE_PARENT,
2092                         .ops = &clk_branch2_ops,
2093                 },
2094         },
2095 };
2096
2097 static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
2098         .halt_reg = 0x2c004,
2099         .clkr = {
2100                 .enable_reg = 0x2c004,
2101                 .enable_mask = BIT(0),
2102                 .hw.init = &(struct clk_init_data){
2103                         .name = "gcc_blsp2_qup4_spi_apps_clk",
2104                         .parent_names = (const char *[]){ "blsp2_qup4_spi_apps_clk_src" },
2105                         .num_parents = 1,
2106                         .flags = CLK_SET_RATE_PARENT,
2107                         .ops = &clk_branch2_ops,
2108                 },
2109         },
2110 };
2111
2112 static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
2113         .halt_reg = 0x2c008,
2114         .clkr = {
2115                 .enable_reg = 0x2c008,
2116                 .enable_mask = BIT(0),
2117                 .hw.init = &(struct clk_init_data){
2118                         .name = "gcc_blsp2_qup4_i2c_apps_clk",
2119                         .parent_names = (const char *[]){ "blsp2_qup4_i2c_apps_clk_src" },
2120                         .num_parents = 1,
2121                         .flags = CLK_SET_RATE_PARENT,
2122                         .ops = &clk_branch2_ops,
2123                 },
2124         },
2125 };
2126
2127 static struct clk_branch gcc_blsp2_uart4_apps_clk = {
2128         .halt_reg = 0x2d004,
2129         .clkr = {
2130                 .enable_reg = 0x2d004,
2131                 .enable_mask = BIT(0),
2132                 .hw.init = &(struct clk_init_data){
2133                         .name = "gcc_blsp2_uart4_apps_clk",
2134                         .parent_names = (const char *[]){ "blsp2_uart4_apps_clk_src" },
2135                         .num_parents = 1,
2136                         .flags = CLK_SET_RATE_PARENT,
2137                         .ops = &clk_branch2_ops,
2138                 },
2139         },
2140 };
2141
2142 static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
2143         .halt_reg = 0x2e004,
2144         .clkr = {
2145                 .enable_reg = 0x2e004,
2146                 .enable_mask = BIT(0),
2147                 .hw.init = &(struct clk_init_data){
2148                         .name = "gcc_blsp2_qup5_spi_apps_clk",
2149                         .parent_names = (const char *[]){ "blsp2_qup5_spi_apps_clk_src" },
2150                         .num_parents = 1,
2151                         .flags = CLK_SET_RATE_PARENT,
2152                         .ops = &clk_branch2_ops,
2153                 },
2154         },
2155 };
2156
2157 static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
2158         .halt_reg = 0x2e008,
2159         .clkr = {
2160                 .enable_reg = 0x2e008,
2161                 .enable_mask = BIT(0),
2162                 .hw.init = &(struct clk_init_data){
2163                         .name = "gcc_blsp2_qup5_i2c_apps_clk",
2164                         .parent_names = (const char *[]){ "blsp2_qup5_i2c_apps_clk_src" },
2165                         .num_parents = 1,
2166                         .flags = CLK_SET_RATE_PARENT,
2167                         .ops = &clk_branch2_ops,
2168                 },
2169         },
2170 };
2171
2172 static struct clk_branch gcc_blsp2_uart5_apps_clk = {
2173         .halt_reg = 0x2f004,
2174         .clkr = {
2175                 .enable_reg = 0x2f004,
2176                 .enable_mask = BIT(0),
2177                 .hw.init = &(struct clk_init_data){
2178                         .name = "gcc_blsp2_uart5_apps_clk",
2179                         .parent_names = (const char *[]){ "blsp2_uart5_apps_clk_src" },
2180                         .num_parents = 1,
2181                         .flags = CLK_SET_RATE_PARENT,
2182                         .ops = &clk_branch2_ops,
2183                 },
2184         },
2185 };
2186
2187 static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
2188         .halt_reg = 0x30004,
2189         .clkr = {
2190                 .enable_reg = 0x30004,
2191                 .enable_mask = BIT(0),
2192                 .hw.init = &(struct clk_init_data){
2193                         .name = "gcc_blsp2_qup6_spi_apps_clk",
2194                         .parent_names = (const char *[]){ "blsp2_qup6_spi_apps_clk_src" },
2195                         .num_parents = 1,
2196                         .flags = CLK_SET_RATE_PARENT,
2197                         .ops = &clk_branch2_ops,
2198                 },
2199         },
2200 };
2201
2202 static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
2203         .halt_reg = 0x30008,
2204         .clkr = {
2205                 .enable_reg = 0x30008,
2206                 .enable_mask = BIT(0),
2207                 .hw.init = &(struct clk_init_data){
2208                         .name = "gcc_blsp2_qup6_i2c_apps_clk",
2209                         .parent_names = (const char *[]){ "blsp2_qup6_i2c_apps_clk_src" },
2210                         .num_parents = 1,
2211                         .flags = CLK_SET_RATE_PARENT,
2212                         .ops = &clk_branch2_ops,
2213                 },
2214         },
2215 };
2216
2217 static struct clk_branch gcc_blsp2_uart6_apps_clk = {
2218         .halt_reg = 0x31004,
2219         .clkr = {
2220                 .enable_reg = 0x31004,
2221                 .enable_mask = BIT(0),
2222                 .hw.init = &(struct clk_init_data){
2223                         .name = "gcc_blsp2_uart6_apps_clk",
2224                         .parent_names = (const char *[]){ "blsp2_uart6_apps_clk_src" },
2225                         .num_parents = 1,
2226                         .flags = CLK_SET_RATE_PARENT,
2227                         .ops = &clk_branch2_ops,
2228                 },
2229         },
2230 };
2231
2232 static struct clk_branch gcc_pdm_ahb_clk = {
2233         .halt_reg = 0x33004,
2234         .clkr = {
2235                 .enable_reg = 0x33004,
2236                 .enable_mask = BIT(0),
2237                 .hw.init = &(struct clk_init_data){
2238                         .name = "gcc_pdm_ahb_clk",
2239                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
2240                         .num_parents = 1,
2241                         .flags = CLK_SET_RATE_PARENT,
2242                         .ops = &clk_branch2_ops,
2243                 },
2244         },
2245 };
2246
2247 static struct clk_branch gcc_pdm2_clk = {
2248         .halt_reg = 0x3300c,
2249         .clkr = {
2250                 .enable_reg = 0x3300c,
2251                 .enable_mask = BIT(0),
2252                 .hw.init = &(struct clk_init_data){
2253                         .name = "gcc_pdm2_clk",
2254                         .parent_names = (const char *[]){ "pdm2_clk_src" },
2255                         .num_parents = 1,
2256                         .flags = CLK_SET_RATE_PARENT,
2257                         .ops = &clk_branch2_ops,
2258                 },
2259         },
2260 };
2261
2262 static struct clk_branch gcc_prng_ahb_clk = {
2263         .halt_reg = 0x34004,
2264         .halt_check = BRANCH_HALT_VOTED,
2265         .clkr = {
2266                 .enable_reg = 0x52004,
2267                 .enable_mask = BIT(13),
2268                 .hw.init = &(struct clk_init_data){
2269                         .name = "gcc_prng_ahb_clk",
2270                         .parent_names = (const char *[]){ "config_noc_clk_src" },
2271                         .num_parents = 1,
2272                         .flags = CLK_SET_RATE_PARENT,
2273                         .ops = &clk_branch2_ops,
2274                 },
2275         },
2276 };
2277
2278 static struct clk_branch gcc_tsif_ahb_clk = {
2279         .halt_reg = 0x36004,
2280         .clkr = {
2281                 .enable_reg = 0x36004,
2282                 .enable_mask = BIT(0),
2283                 .hw.init = &(struct clk_init_data){
2284                         .name = "gcc_tsif_ahb_clk",
2285                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
2286                         .num_parents = 1,
2287                         .flags = CLK_SET_RATE_PARENT,
2288                         .ops = &clk_branch2_ops,
2289                 },
2290         },
2291 };
2292
2293 static struct clk_branch gcc_tsif_ref_clk = {
2294         .halt_reg = 0x36008,
2295         .clkr = {
2296                 .enable_reg = 0x36008,
2297                 .enable_mask = BIT(0),
2298                 .hw.init = &(struct clk_init_data){
2299                         .name = "gcc_tsif_ref_clk",
2300                         .parent_names = (const char *[]){ "tsif_ref_clk_src" },
2301                         .num_parents = 1,
2302                         .flags = CLK_SET_RATE_PARENT,
2303                         .ops = &clk_branch2_ops,
2304                 },
2305         },
2306 };
2307
2308 static struct clk_branch gcc_tsif_inactivity_timers_clk = {
2309         .halt_reg = 0x3600c,
2310         .clkr = {
2311                 .enable_reg = 0x3600c,
2312                 .enable_mask = BIT(0),
2313                 .hw.init = &(struct clk_init_data){
2314                         .name = "gcc_tsif_inactivity_timers_clk",
2315                         .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
2316                         .num_parents = 1,
2317                         .flags = CLK_SET_RATE_PARENT,
2318                         .ops = &clk_branch2_ops,
2319                 },
2320         },
2321 };
2322
2323 static struct clk_branch gcc_boot_rom_ahb_clk = {
2324         .halt_reg = 0x38004,
2325         .halt_check = BRANCH_HALT_VOTED,
2326         .clkr = {
2327                 .enable_reg = 0x52004,
2328                 .enable_mask = BIT(10),
2329                 .hw.init = &(struct clk_init_data){
2330                         .name = "gcc_boot_rom_ahb_clk",
2331                         .parent_names = (const char *[]){ "config_noc_clk_src" },
2332                         .num_parents = 1,
2333                         .flags = CLK_SET_RATE_PARENT,
2334                         .ops = &clk_branch2_ops,
2335                 },
2336         },
2337 };
2338
2339 static struct clk_branch gcc_bimc_gfx_clk = {
2340         .halt_reg = 0x46018,
2341         .clkr = {
2342                 .enable_reg = 0x46018,
2343                 .enable_mask = BIT(0),
2344                 .hw.init = &(struct clk_init_data){
2345                         .name = "gcc_bimc_gfx_clk",
2346                         .flags = CLK_SET_RATE_PARENT,
2347                         .ops = &clk_branch2_ops,
2348                 },
2349         },
2350 };
2351
2352 static struct clk_branch gcc_hmss_rbcpr_clk = {
2353         .halt_reg = 0x4800c,
2354         .clkr = {
2355                 .enable_reg = 0x4800c,
2356                 .enable_mask = BIT(0),
2357                 .hw.init = &(struct clk_init_data){
2358                         .name = "gcc_hmss_rbcpr_clk",
2359                         .parent_names = (const char *[]){ "hmss_rbcpr_clk_src" },
2360                         .num_parents = 1,
2361                         .flags = CLK_SET_RATE_PARENT,
2362                         .ops = &clk_branch2_ops,
2363                 },
2364         },
2365 };
2366
2367 static struct clk_branch gcc_gp1_clk = {
2368         .halt_reg = 0x64000,
2369         .clkr = {
2370                 .enable_reg = 0x64000,
2371                 .enable_mask = BIT(0),
2372                 .hw.init = &(struct clk_init_data){
2373                         .name = "gcc_gp1_clk",
2374                         .parent_names = (const char *[]){ "gp1_clk_src" },
2375                         .num_parents = 1,
2376                         .flags = CLK_SET_RATE_PARENT,
2377                         .ops = &clk_branch2_ops,
2378                 },
2379         },
2380 };
2381
2382 static struct clk_branch gcc_gp2_clk = {
2383         .halt_reg = 0x65000,
2384         .clkr = {
2385                 .enable_reg = 0x65000,
2386                 .enable_mask = BIT(0),
2387                 .hw.init = &(struct clk_init_data){
2388                         .name = "gcc_gp2_clk",
2389                         .parent_names = (const char *[]){ "gp2_clk_src" },
2390                         .num_parents = 1,
2391                         .flags = CLK_SET_RATE_PARENT,
2392                         .ops = &clk_branch2_ops,
2393                 },
2394         },
2395 };
2396
2397 static struct clk_branch gcc_gp3_clk = {
2398         .halt_reg = 0x66000,
2399         .clkr = {
2400                 .enable_reg = 0x66000,
2401                 .enable_mask = BIT(0),
2402                 .hw.init = &(struct clk_init_data){
2403                         .name = "gcc_gp3_clk",
2404                         .parent_names = (const char *[]){ "gp3_clk_src" },
2405                         .num_parents = 1,
2406                         .flags = CLK_SET_RATE_PARENT,
2407                         .ops = &clk_branch2_ops,
2408                 },
2409         },
2410 };
2411
2412 static struct clk_branch gcc_pcie_0_slv_axi_clk = {
2413         .halt_reg = 0x6b008,
2414         .clkr = {
2415                 .enable_reg = 0x6b008,
2416                 .enable_mask = BIT(0),
2417                 .hw.init = &(struct clk_init_data){
2418                         .name = "gcc_pcie_0_slv_axi_clk",
2419                         .parent_names = (const char *[]){ "system_noc_clk_src" },
2420                         .num_parents = 1,
2421                         .flags = CLK_SET_RATE_PARENT,
2422                         .ops = &clk_branch2_ops,
2423                 },
2424         },
2425 };
2426
2427 static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
2428         .halt_reg = 0x6b00c,
2429         .clkr = {
2430                 .enable_reg = 0x6b00c,
2431                 .enable_mask = BIT(0),
2432                 .hw.init = &(struct clk_init_data){
2433                         .name = "gcc_pcie_0_mstr_axi_clk",
2434                         .parent_names = (const char *[]){ "system_noc_clk_src" },
2435                         .num_parents = 1,
2436                         .flags = CLK_SET_RATE_PARENT,
2437                         .ops = &clk_branch2_ops,
2438                 },
2439         },
2440 };
2441
2442 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
2443         .halt_reg = 0x6b010,
2444         .clkr = {
2445                 .enable_reg = 0x6b010,
2446                 .enable_mask = BIT(0),
2447                 .hw.init = &(struct clk_init_data){
2448                         .name = "gcc_pcie_0_cfg_ahb_clk",
2449                         .parent_names = (const char *[]){ "config_noc_clk_src" },
2450                         .num_parents = 1,
2451                         .flags = CLK_SET_RATE_PARENT,
2452                         .ops = &clk_branch2_ops,
2453                 },
2454         },
2455 };
2456
2457 static struct clk_branch gcc_pcie_0_aux_clk = {
2458         .halt_reg = 0x6b014,
2459         .clkr = {
2460                 .enable_reg = 0x6b014,
2461                 .enable_mask = BIT(0),
2462                 .hw.init = &(struct clk_init_data){
2463                         .name = "gcc_pcie_0_aux_clk",
2464                         .parent_names = (const char *[]){ "pcie_aux_clk_src" },
2465                         .num_parents = 1,
2466                         .flags = CLK_SET_RATE_PARENT,
2467                         .ops = &clk_branch2_ops,
2468                 },
2469         },
2470 };
2471
2472 static struct clk_branch gcc_pcie_0_pipe_clk = {
2473         .halt_reg = 0x6b018,
2474         .halt_check = BRANCH_HALT_SKIP,
2475         .clkr = {
2476                 .enable_reg = 0x6b018,
2477                 .enable_mask = BIT(0),
2478                 .hw.init = &(struct clk_init_data){
2479                         .name = "gcc_pcie_0_pipe_clk",
2480                         .parent_names = (const char *[]){ "pcie_0_pipe_clk_src" },
2481                         .num_parents = 1,
2482                         .flags = CLK_SET_RATE_PARENT,
2483                         .ops = &clk_branch2_ops,
2484                 },
2485         },
2486 };
2487
2488 static struct clk_branch gcc_pcie_1_slv_axi_clk = {
2489         .halt_reg = 0x6d008,
2490         .clkr = {
2491                 .enable_reg = 0x6d008,
2492                 .enable_mask = BIT(0),
2493                 .hw.init = &(struct clk_init_data){
2494                         .name = "gcc_pcie_1_slv_axi_clk",
2495                         .parent_names = (const char *[]){ "system_noc_clk_src" },
2496                         .num_parents = 1,
2497                         .flags = CLK_SET_RATE_PARENT,
2498                         .ops = &clk_branch2_ops,
2499                 },
2500         },
2501 };
2502
2503 static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
2504         .halt_reg = 0x6d00c,
2505         .clkr = {
2506                 .enable_reg = 0x6d00c,
2507                 .enable_mask = BIT(0),
2508                 .hw.init = &(struct clk_init_data){
2509                         .name = "gcc_pcie_1_mstr_axi_clk",
2510                         .parent_names = (const char *[]){ "system_noc_clk_src" },
2511                         .num_parents = 1,
2512                         .flags = CLK_SET_RATE_PARENT,
2513                         .ops = &clk_branch2_ops,
2514                 },
2515         },
2516 };
2517
2518 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
2519         .halt_reg = 0x6d010,
2520         .clkr = {
2521                 .enable_reg = 0x6d010,
2522                 .enable_mask = BIT(0),
2523                 .hw.init = &(struct clk_init_data){
2524                         .name = "gcc_pcie_1_cfg_ahb_clk",
2525                         .parent_names = (const char *[]){ "config_noc_clk_src" },
2526                         .num_parents = 1,
2527                         .flags = CLK_SET_RATE_PARENT,
2528                         .ops = &clk_branch2_ops,
2529                 },
2530         },
2531 };
2532
2533 static struct clk_branch gcc_pcie_1_aux_clk = {
2534         .halt_reg = 0x6d014,
2535         .clkr = {
2536                 .enable_reg = 0x6d014,
2537                 .enable_mask = BIT(0),
2538                 .hw.init = &(struct clk_init_data){
2539                         .name = "gcc_pcie_1_aux_clk",
2540                         .parent_names = (const char *[]){ "pcie_aux_clk_src" },
2541                         .num_parents = 1,
2542                         .flags = CLK_SET_RATE_PARENT,
2543                         .ops = &clk_branch2_ops,
2544                 },
2545         },
2546 };
2547
2548 static struct clk_branch gcc_pcie_1_pipe_clk = {
2549         .halt_reg = 0x6d018,
2550         .halt_check = BRANCH_HALT_SKIP,
2551         .clkr = {
2552                 .enable_reg = 0x6d018,
2553                 .enable_mask = BIT(0),
2554                 .hw.init = &(struct clk_init_data){
2555                         .name = "gcc_pcie_1_pipe_clk",
2556                         .parent_names = (const char *[]){ "pcie_1_pipe_clk_src" },
2557                         .num_parents = 1,
2558                         .flags = CLK_SET_RATE_PARENT,
2559                         .ops = &clk_branch2_ops,
2560                 },
2561         },
2562 };
2563
2564 static struct clk_branch gcc_pcie_2_slv_axi_clk = {
2565         .halt_reg = 0x6e008,
2566         .clkr = {
2567                 .enable_reg = 0x6e008,
2568                 .enable_mask = BIT(0),
2569                 .hw.init = &(struct clk_init_data){
2570                         .name = "gcc_pcie_2_slv_axi_clk",
2571                         .parent_names = (const char *[]){ "system_noc_clk_src" },
2572                         .num_parents = 1,
2573                         .flags = CLK_SET_RATE_PARENT,
2574                         .ops = &clk_branch2_ops,
2575                 },
2576         },
2577 };
2578
2579 static struct clk_branch gcc_pcie_2_mstr_axi_clk = {
2580         .halt_reg = 0x6e00c,
2581         .clkr = {
2582                 .enable_reg = 0x6e00c,
2583                 .enable_mask = BIT(0),
2584                 .hw.init = &(struct clk_init_data){
2585                         .name = "gcc_pcie_2_mstr_axi_clk",
2586                         .parent_names = (const char *[]){ "system_noc_clk_src" },
2587                         .num_parents = 1,
2588                         .flags = CLK_SET_RATE_PARENT,
2589                         .ops = &clk_branch2_ops,
2590                 },
2591         },
2592 };
2593
2594 static struct clk_branch gcc_pcie_2_cfg_ahb_clk = {
2595         .halt_reg = 0x6e010,
2596         .clkr = {
2597                 .enable_reg = 0x6e010,
2598                 .enable_mask = BIT(0),
2599                 .hw.init = &(struct clk_init_data){
2600                         .name = "gcc_pcie_2_cfg_ahb_clk",
2601                         .parent_names = (const char *[]){ "config_noc_clk_src" },
2602                         .num_parents = 1,
2603                         .flags = CLK_SET_RATE_PARENT,
2604                         .ops = &clk_branch2_ops,
2605                 },
2606         },
2607 };
2608
2609 static struct clk_branch gcc_pcie_2_aux_clk = {
2610         .halt_reg = 0x6e014,
2611         .clkr = {
2612                 .enable_reg = 0x6e014,
2613                 .enable_mask = BIT(0),
2614                 .hw.init = &(struct clk_init_data){
2615                         .name = "gcc_pcie_2_aux_clk",
2616                         .parent_names = (const char *[]){ "pcie_aux_clk_src" },
2617                         .num_parents = 1,
2618                         .flags = CLK_SET_RATE_PARENT,
2619                         .ops = &clk_branch2_ops,
2620                 },
2621         },
2622 };
2623
2624 static struct clk_branch gcc_pcie_2_pipe_clk = {
2625         .halt_reg = 0x6e018,
2626         .halt_check = BRANCH_HALT_SKIP,
2627         .clkr = {
2628                 .enable_reg = 0x6e018,
2629                 .enable_mask = BIT(0),
2630                 .hw.init = &(struct clk_init_data){
2631                         .name = "gcc_pcie_2_pipe_clk",
2632                         .parent_names = (const char *[]){ "pcie_2_pipe_clk_src" },
2633                         .num_parents = 1,
2634                         .flags = CLK_SET_RATE_PARENT,
2635                         .ops = &clk_branch2_ops,
2636                 },
2637         },
2638 };
2639
2640 static struct clk_branch gcc_pcie_phy_cfg_ahb_clk = {
2641         .halt_reg = 0x6f004,
2642         .clkr = {
2643                 .enable_reg = 0x6f004,
2644                 .enable_mask = BIT(0),
2645                 .hw.init = &(struct clk_init_data){
2646                         .name = "gcc_pcie_phy_cfg_ahb_clk",
2647                         .parent_names = (const char *[]){ "config_noc_clk_src" },
2648                         .num_parents = 1,
2649                         .flags = CLK_SET_RATE_PARENT,
2650                         .ops = &clk_branch2_ops,
2651                 },
2652         },
2653 };
2654
2655 static struct clk_branch gcc_pcie_phy_aux_clk = {
2656         .halt_reg = 0x6f008,
2657         .clkr = {
2658                 .enable_reg = 0x6f008,
2659                 .enable_mask = BIT(0),
2660                 .hw.init = &(struct clk_init_data){
2661                         .name = "gcc_pcie_phy_aux_clk",
2662                         .parent_names = (const char *[]){ "pcie_aux_clk_src" },
2663                         .num_parents = 1,
2664                         .flags = CLK_SET_RATE_PARENT,
2665                         .ops = &clk_branch2_ops,
2666                 },
2667         },
2668 };
2669
2670 static struct clk_branch gcc_ufs_axi_clk = {
2671         .halt_reg = 0x75008,
2672         .clkr = {
2673                 .enable_reg = 0x75008,
2674                 .enable_mask = BIT(0),
2675                 .hw.init = &(struct clk_init_data){
2676                         .name = "gcc_ufs_axi_clk",
2677                         .parent_names = (const char *[]){ "ufs_axi_clk_src" },
2678                         .num_parents = 1,
2679                         .flags = CLK_SET_RATE_PARENT,
2680                         .ops = &clk_branch2_ops,
2681                 },
2682         },
2683 };
2684
2685 static struct clk_branch gcc_ufs_ahb_clk = {
2686         .halt_reg = 0x7500c,
2687         .clkr = {
2688                 .enable_reg = 0x7500c,
2689                 .enable_mask = BIT(0),
2690                 .hw.init = &(struct clk_init_data){
2691                         .name = "gcc_ufs_ahb_clk",
2692                         .parent_names = (const char *[]){ "config_noc_clk_src" },
2693                         .num_parents = 1,
2694                         .flags = CLK_SET_RATE_PARENT,
2695                         .ops = &clk_branch2_ops,
2696                 },
2697         },
2698 };
2699
2700 static struct clk_fixed_factor ufs_tx_cfg_clk_src = {
2701         .mult = 1,
2702         .div = 16,
2703         .hw.init = &(struct clk_init_data){
2704                 .name = "ufs_tx_cfg_clk_src",
2705                 .parent_names = (const char *[]){ "ufs_axi_clk_src" },
2706                 .num_parents = 1,
2707                 .flags = CLK_SET_RATE_PARENT,
2708                 .ops = &clk_fixed_factor_ops,
2709         },
2710 };
2711
2712 static struct clk_branch gcc_ufs_tx_cfg_clk = {
2713         .halt_reg = 0x75010,
2714         .clkr = {
2715                 .enable_reg = 0x75010,
2716                 .enable_mask = BIT(0),
2717                 .hw.init = &(struct clk_init_data){
2718                         .name = "gcc_ufs_tx_cfg_clk",
2719                         .parent_names = (const char *[]){ "ufs_tx_cfg_clk_src" },
2720                         .num_parents = 1,
2721                         .flags = CLK_SET_RATE_PARENT,
2722                         .ops = &clk_branch2_ops,
2723                 },
2724         },
2725 };
2726
2727 static struct clk_fixed_factor ufs_rx_cfg_clk_src = {
2728         .mult = 1,
2729         .div = 16,
2730         .hw.init = &(struct clk_init_data){
2731                 .name = "ufs_rx_cfg_clk_src",
2732                 .parent_names = (const char *[]){ "ufs_axi_clk_src" },
2733                 .num_parents = 1,
2734                 .flags = CLK_SET_RATE_PARENT,
2735                 .ops = &clk_fixed_factor_ops,
2736         },
2737 };
2738
2739 static struct clk_branch gcc_hlos1_vote_lpass_core_smmu_clk = {
2740         .halt_reg = 0x7d010,
2741         .halt_check = BRANCH_HALT_VOTED,
2742         .clkr = {
2743                 .enable_reg = 0x7d010,
2744                 .enable_mask = BIT(0),
2745                 .hw.init = &(struct clk_init_data){
2746                         .name = "hlos1_vote_lpass_core_smmu_clk",
2747                         .ops = &clk_branch2_ops,
2748                 },
2749         },
2750 };
2751
2752 static struct clk_branch gcc_hlos1_vote_lpass_adsp_smmu_clk = {
2753         .halt_reg = 0x7d014,
2754         .halt_check = BRANCH_HALT_VOTED,
2755         .clkr = {
2756                 .enable_reg = 0x7d014,
2757                 .enable_mask = BIT(0),
2758                 .hw.init = &(struct clk_init_data){
2759                         .name = "hlos1_vote_lpass_adsp_smmu_clk",
2760                         .ops = &clk_branch2_ops,
2761                 },
2762         },
2763 };
2764
2765 static struct clk_branch gcc_ufs_rx_cfg_clk = {
2766         .halt_reg = 0x75014,
2767         .clkr = {
2768                 .enable_reg = 0x75014,
2769                 .enable_mask = BIT(0),
2770                 .hw.init = &(struct clk_init_data){
2771                         .name = "gcc_ufs_rx_cfg_clk",
2772                         .parent_names = (const char *[]){ "ufs_rx_cfg_clk_src" },
2773                         .num_parents = 1,
2774                         .flags = CLK_SET_RATE_PARENT,
2775                         .ops = &clk_branch2_ops,
2776                 },
2777         },
2778 };
2779
2780 static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
2781         .halt_reg = 0x75018,
2782         .halt_check = BRANCH_HALT_SKIP,
2783         .clkr = {
2784                 .enable_reg = 0x75018,
2785                 .enable_mask = BIT(0),
2786                 .hw.init = &(struct clk_init_data){
2787                         .name = "gcc_ufs_tx_symbol_0_clk",
2788                         .parent_names = (const char *[]){ "ufs_tx_symbol_0_clk_src" },
2789                         .num_parents = 1,
2790                         .flags = CLK_SET_RATE_PARENT,
2791                         .ops = &clk_branch2_ops,
2792                 },
2793         },
2794 };
2795
2796 static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
2797         .halt_reg = 0x7501c,
2798         .halt_check = BRANCH_HALT_SKIP,
2799         .clkr = {
2800                 .enable_reg = 0x7501c,
2801                 .enable_mask = BIT(0),
2802                 .hw.init = &(struct clk_init_data){
2803                         .name = "gcc_ufs_rx_symbol_0_clk",
2804                         .parent_names = (const char *[]){ "ufs_rx_symbol_0_clk_src" },
2805                         .num_parents = 1,
2806                         .flags = CLK_SET_RATE_PARENT,
2807                         .ops = &clk_branch2_ops,
2808                 },
2809         },
2810 };
2811
2812 static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
2813         .halt_reg = 0x75020,
2814         .halt_check = BRANCH_HALT_SKIP,
2815         .clkr = {
2816                 .enable_reg = 0x75020,
2817                 .enable_mask = BIT(0),
2818                 .hw.init = &(struct clk_init_data){
2819                         .name = "gcc_ufs_rx_symbol_1_clk",
2820                         .parent_names = (const char *[]){ "ufs_rx_symbol_1_clk_src" },
2821                         .num_parents = 1,
2822                         .flags = CLK_SET_RATE_PARENT,
2823                         .ops = &clk_branch2_ops,
2824                 },
2825         },
2826 };
2827
2828 static struct clk_fixed_factor ufs_ice_core_postdiv_clk_src = {
2829         .mult = 1,
2830         .div = 2,
2831         .hw.init = &(struct clk_init_data){
2832                 .name = "ufs_ice_core_postdiv_clk_src",
2833                 .parent_names = (const char *[]){ "ufs_ice_core_clk_src" },
2834                 .num_parents = 1,
2835                 .flags = CLK_SET_RATE_PARENT,
2836                 .ops = &clk_fixed_factor_ops,
2837         },
2838 };
2839
2840 static struct clk_branch gcc_ufs_unipro_core_clk = {
2841         .halt_reg = 0x7600c,
2842         .clkr = {
2843                 .enable_reg = 0x7600c,
2844                 .enable_mask = BIT(0),
2845                 .hw.init = &(struct clk_init_data){
2846                         .name = "gcc_ufs_unipro_core_clk",
2847                         .parent_names = (const char *[]){ "ufs_ice_core_postdiv_clk_src" },
2848                         .num_parents = 1,
2849                         .flags = CLK_SET_RATE_PARENT,
2850                         .ops = &clk_branch2_ops,
2851                 },
2852         },
2853 };
2854
2855 static struct clk_branch gcc_ufs_ice_core_clk = {
2856         .halt_reg = 0x76010,
2857         .clkr = {
2858                 .enable_reg = 0x76010,
2859                 .enable_mask = BIT(0),
2860                 .hw.init = &(struct clk_init_data){
2861                         .name = "gcc_ufs_ice_core_clk",
2862                         .parent_names = (const char *[]){ "ufs_ice_core_clk_src" },
2863                         .num_parents = 1,
2864                         .flags = CLK_SET_RATE_PARENT,
2865                         .ops = &clk_branch2_ops,
2866                 },
2867         },
2868 };
2869
2870 static struct clk_branch gcc_ufs_sys_clk_core_clk = {
2871         .halt_check = BRANCH_HALT_DELAY,
2872         .clkr = {
2873                 .enable_reg = 0x76030,
2874                 .enable_mask = BIT(0),
2875                 .hw.init = &(struct clk_init_data){
2876                         .name = "gcc_ufs_sys_clk_core_clk",
2877                         .ops = &clk_branch2_ops,
2878                 },
2879         },
2880 };
2881
2882 static struct clk_branch gcc_ufs_tx_symbol_clk_core_clk = {
2883         .halt_check = BRANCH_HALT_DELAY,
2884         .clkr = {
2885                 .enable_reg = 0x76034,
2886                 .enable_mask = BIT(0),
2887                 .hw.init = &(struct clk_init_data){
2888                         .name = "gcc_ufs_tx_symbol_clk_core_clk",
2889                         .ops = &clk_branch2_ops,
2890                 },
2891         },
2892 };
2893
2894 static struct clk_branch gcc_aggre0_snoc_axi_clk = {
2895         .halt_reg = 0x81008,
2896         .clkr = {
2897                 .enable_reg = 0x81008,
2898                 .enable_mask = BIT(0),
2899                 .hw.init = &(struct clk_init_data){
2900                         .name = "gcc_aggre0_snoc_axi_clk",
2901                         .parent_names = (const char *[]){ "system_noc_clk_src" },
2902                         .num_parents = 1,
2903                         .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
2904                         .ops = &clk_branch2_ops,
2905                 },
2906         },
2907 };
2908
2909 static struct clk_branch gcc_aggre0_cnoc_ahb_clk = {
2910         .halt_reg = 0x8100c,
2911         .clkr = {
2912                 .enable_reg = 0x8100c,
2913                 .enable_mask = BIT(0),
2914                 .hw.init = &(struct clk_init_data){
2915                         .name = "gcc_aggre0_cnoc_ahb_clk",
2916                         .parent_names = (const char *[]){ "config_noc_clk_src" },
2917                         .num_parents = 1,
2918                         .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
2919                         .ops = &clk_branch2_ops,
2920                 },
2921         },
2922 };
2923
2924 static struct clk_branch gcc_smmu_aggre0_axi_clk = {
2925         .halt_reg = 0x81014,
2926         .clkr = {
2927                 .enable_reg = 0x81014,
2928                 .enable_mask = BIT(0),
2929                 .hw.init = &(struct clk_init_data){
2930                         .name = "gcc_smmu_aggre0_axi_clk",
2931                         .parent_names = (const char *[]){ "system_noc_clk_src" },
2932                         .num_parents = 1,
2933                         .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
2934                         .ops = &clk_branch2_ops,
2935                 },
2936         },
2937 };
2938
2939 static struct clk_branch gcc_smmu_aggre0_ahb_clk = {
2940         .halt_reg = 0x81018,
2941         .clkr = {
2942                 .enable_reg = 0x81018,
2943                 .enable_mask = BIT(0),
2944                 .hw.init = &(struct clk_init_data){
2945                         .name = "gcc_smmu_aggre0_ahb_clk",
2946                         .parent_names = (const char *[]){ "config_noc_clk_src" },
2947                         .num_parents = 1,
2948                         .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
2949                         .ops = &clk_branch2_ops,
2950                 },
2951         },
2952 };
2953
2954 static struct clk_branch gcc_aggre2_ufs_axi_clk = {
2955         .halt_reg = 0x83014,
2956         .clkr = {
2957                 .enable_reg = 0x83014,
2958                 .enable_mask = BIT(0),
2959                 .hw.init = &(struct clk_init_data){
2960                         .name = "gcc_aggre2_ufs_axi_clk",
2961                         .parent_names = (const char *[]){ "ufs_axi_clk_src" },
2962                         .num_parents = 1,
2963                         .flags = CLK_SET_RATE_PARENT,
2964                         .ops = &clk_branch2_ops,
2965                 },
2966         },
2967 };
2968
2969 static struct clk_branch gcc_aggre2_usb3_axi_clk = {
2970         .halt_reg = 0x83018,
2971         .clkr = {
2972                 .enable_reg = 0x83018,
2973                 .enable_mask = BIT(0),
2974                 .hw.init = &(struct clk_init_data){
2975                         .name = "gcc_aggre2_usb3_axi_clk",
2976                         .parent_names = (const char *[]){ "usb30_master_clk_src" },
2977                         .num_parents = 1,
2978                         .flags = CLK_SET_RATE_PARENT,
2979                         .ops = &clk_branch2_ops,
2980                 },
2981         },
2982 };
2983
2984 static struct clk_branch gcc_qspi_ahb_clk = {
2985         .halt_reg = 0x8b004,
2986         .clkr = {
2987                 .enable_reg = 0x8b004,
2988                 .enable_mask = BIT(0),
2989                 .hw.init = &(struct clk_init_data){
2990                         .name = "gcc_qspi_ahb_clk",
2991                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
2992                         .num_parents = 1,
2993                         .flags = CLK_SET_RATE_PARENT,
2994                         .ops = &clk_branch2_ops,
2995                 },
2996         },
2997 };
2998
2999 static struct clk_branch gcc_qspi_ser_clk = {
3000         .halt_reg = 0x8b008,
3001         .clkr = {
3002                 .enable_reg = 0x8b008,
3003                 .enable_mask = BIT(0),
3004                 .hw.init = &(struct clk_init_data){
3005                         .name = "gcc_qspi_ser_clk",
3006                         .parent_names = (const char *[]){ "qspi_ser_clk_src" },
3007                         .num_parents = 1,
3008                         .flags = CLK_SET_RATE_PARENT,
3009                         .ops = &clk_branch2_ops,
3010                 },
3011         },
3012 };
3013
3014 static struct clk_branch gcc_usb3_clkref_clk = {
3015         .halt_reg = 0x8800C,
3016         .clkr = {
3017                 .enable_reg = 0x8800C,
3018                 .enable_mask = BIT(0),
3019                 .hw.init = &(struct clk_init_data){
3020                         .name = "gcc_usb3_clkref_clk",
3021                         .parent_names = (const char *[]){ "xo" },
3022                         .num_parents = 1,
3023                         .ops = &clk_branch2_ops,
3024                 },
3025         },
3026 };
3027
3028 static struct clk_branch gcc_hdmi_clkref_clk = {
3029         .halt_reg = 0x88000,
3030         .clkr = {
3031                 .enable_reg = 0x88000,
3032                 .enable_mask = BIT(0),
3033                 .hw.init = &(struct clk_init_data){
3034                         .name = "gcc_hdmi_clkref_clk",
3035                         .parent_names = (const char *[]){ "xo" },
3036                         .num_parents = 1,
3037                         .ops = &clk_branch2_ops,
3038                 },
3039         },
3040 };
3041
3042 static struct clk_branch gcc_ufs_clkref_clk = {
3043         .halt_reg = 0x88008,
3044         .clkr = {
3045                 .enable_reg = 0x88008,
3046                 .enable_mask = BIT(0),
3047                 .hw.init = &(struct clk_init_data){
3048                         .name = "gcc_ufs_clkref_clk",
3049                         .parent_names = (const char *[]){ "xo" },
3050                         .num_parents = 1,
3051                         .ops = &clk_branch2_ops,
3052                 },
3053         },
3054 };
3055
3056 static struct clk_branch gcc_pcie_clkref_clk = {
3057         .halt_reg = 0x88010,
3058         .clkr = {
3059                 .enable_reg = 0x88010,
3060                 .enable_mask = BIT(0),
3061                 .hw.init = &(struct clk_init_data){
3062                         .name = "gcc_pcie_clkref_clk",
3063                         .parent_names = (const char *[]){ "xo" },
3064                         .num_parents = 1,
3065                         .ops = &clk_branch2_ops,
3066                 },
3067         },
3068 };
3069
3070 static struct clk_branch gcc_rx2_usb2_clkref_clk = {
3071         .halt_reg = 0x88014,
3072         .clkr = {
3073                 .enable_reg = 0x88014,
3074                 .enable_mask = BIT(0),
3075                 .hw.init = &(struct clk_init_data){
3076                         .name = "gcc_rx2_usb2_clkref_clk",
3077                         .parent_names = (const char *[]){ "xo" },
3078                         .num_parents = 1,
3079                         .ops = &clk_branch2_ops,
3080                 },
3081         },
3082 };
3083
3084 static struct clk_branch gcc_rx1_usb2_clkref_clk = {
3085         .halt_reg = 0x88018,
3086         .clkr = {
3087                 .enable_reg = 0x88018,
3088                 .enable_mask = BIT(0),
3089                 .hw.init = &(struct clk_init_data){
3090                         .name = "gcc_rx1_usb2_clkref_clk",
3091                         .parent_names = (const char *[]){ "xo" },
3092                         .num_parents = 1,
3093                         .ops = &clk_branch2_ops,
3094                 },
3095         },
3096 };
3097
3098 static struct clk_hw *gcc_msm8996_hws[] = {
3099         &xo.hw,
3100         &gpll0_early_div.hw,
3101         &ufs_tx_cfg_clk_src.hw,
3102         &ufs_rx_cfg_clk_src.hw,
3103         &ufs_ice_core_postdiv_clk_src.hw,
3104 };
3105
3106 static struct gdsc aggre0_noc_gdsc = {
3107         .gdscr = 0x81004,
3108         .gds_hw_ctrl = 0x81028,
3109         .pd = {
3110                 .name = "aggre0_noc",
3111         },
3112         .pwrsts = PWRSTS_OFF_ON,
3113         .flags = VOTABLE | ALWAYS_ON,
3114 };
3115
3116 static struct gdsc hlos1_vote_aggre0_noc_gdsc = {
3117         .gdscr = 0x7d024,
3118         .pd = {
3119                 .name = "hlos1_vote_aggre0_noc",
3120         },
3121         .pwrsts = PWRSTS_OFF_ON,
3122         .flags = VOTABLE,
3123 };
3124
3125 static struct gdsc hlos1_vote_lpass_adsp_gdsc = {
3126         .gdscr = 0x7d034,
3127         .pd = {
3128                 .name = "hlos1_vote_lpass_adsp",
3129         },
3130         .pwrsts = PWRSTS_OFF_ON,
3131         .flags = VOTABLE,
3132 };
3133
3134 static struct gdsc hlos1_vote_lpass_core_gdsc = {
3135         .gdscr = 0x7d038,
3136         .pd = {
3137                 .name = "hlos1_vote_lpass_core",
3138         },
3139         .pwrsts = PWRSTS_OFF_ON,
3140         .flags = VOTABLE,
3141 };
3142
3143 static struct gdsc usb30_gdsc = {
3144         .gdscr = 0xf004,
3145         .pd = {
3146                 .name = "usb30",
3147         },
3148         .pwrsts = PWRSTS_OFF_ON,
3149 };
3150
3151 static struct gdsc pcie0_gdsc = {
3152         .gdscr = 0x6b004,
3153         .pd = {
3154                 .name = "pcie0",
3155         },
3156         .pwrsts = PWRSTS_OFF_ON,
3157 };
3158
3159 static struct gdsc pcie1_gdsc = {
3160         .gdscr = 0x6d004,
3161         .pd = {
3162                 .name = "pcie1",
3163         },
3164         .pwrsts = PWRSTS_OFF_ON,
3165 };
3166
3167 static struct gdsc pcie2_gdsc = {
3168         .gdscr = 0x6e004,
3169         .pd = {
3170                 .name = "pcie2",
3171         },
3172         .pwrsts = PWRSTS_OFF_ON,
3173 };
3174
3175 static struct gdsc ufs_gdsc = {
3176         .gdscr = 0x75004,
3177         .pd = {
3178                 .name = "ufs",
3179         },
3180         .pwrsts = PWRSTS_OFF_ON,
3181 };
3182
3183 static struct clk_regmap *gcc_msm8996_clocks[] = {
3184         [GPLL0_EARLY] = &gpll0_early.clkr,
3185         [GPLL0] = &gpll0.clkr,
3186         [GPLL4_EARLY] = &gpll4_early.clkr,
3187         [GPLL4] = &gpll4.clkr,
3188         [SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr,
3189         [CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr,
3190         [PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr,
3191         [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
3192         [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
3193         [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
3194         [USB20_MASTER_CLK_SRC] = &usb20_master_clk_src.clkr,
3195         [USB20_MOCK_UTMI_CLK_SRC] = &usb20_mock_utmi_clk_src.clkr,
3196         [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
3197         [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
3198         [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
3199         [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
3200         [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
3201         [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
3202         [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
3203         [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
3204         [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
3205         [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
3206         [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
3207         [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
3208         [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
3209         [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
3210         [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
3211         [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
3212         [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
3213         [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
3214         [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
3215         [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
3216         [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
3217         [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
3218         [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
3219         [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
3220         [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
3221         [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
3222         [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
3223         [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
3224         [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
3225         [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
3226         [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
3227         [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
3228         [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
3229         [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
3230         [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr,
3231         [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
3232         [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
3233         [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr,
3234         [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
3235         [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
3236         [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr,
3237         [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
3238         [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
3239         [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
3240         [HMSS_RBCPR_CLK_SRC] = &hmss_rbcpr_clk_src.clkr,
3241         [HMSS_GPLL0_CLK_SRC] = &hmss_gpll0_clk_src.clkr,
3242         [GP1_CLK_SRC] = &gp1_clk_src.clkr,
3243         [GP2_CLK_SRC] = &gp2_clk_src.clkr,
3244         [GP3_CLK_SRC] = &gp3_clk_src.clkr,
3245         [PCIE_AUX_CLK_SRC] = &pcie_aux_clk_src.clkr,
3246         [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
3247         [UFS_ICE_CORE_CLK_SRC] = &ufs_ice_core_clk_src.clkr,
3248         [QSPI_SER_CLK_SRC] = &qspi_ser_clk_src.clkr,
3249         [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr,
3250         [GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr,
3251         [GCC_PERIPH_NOC_USB20_AHB_CLK] = &gcc_periph_noc_usb20_ahb_clk.clkr,
3252         [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr,
3253         [GCC_MMSS_BIMC_GFX_CLK] = &gcc_mmss_bimc_gfx_clk.clkr,
3254         [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
3255         [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
3256         [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
3257         [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
3258         [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
3259         [GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr,
3260         [GCC_USB20_SLEEP_CLK] = &gcc_usb20_sleep_clk.clkr,
3261         [GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr,
3262         [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
3263         [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
3264         [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
3265         [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
3266         [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3267         [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3268         [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
3269         [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr,
3270         [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
3271         [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
3272         [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
3273         [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
3274         [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
3275         [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
3276         [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
3277         [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
3278         [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
3279         [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
3280         [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
3281         [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
3282         [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
3283         [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
3284         [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
3285         [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
3286         [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
3287         [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
3288         [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
3289         [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
3290         [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
3291         [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
3292         [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
3293         [GCC_BLSP2_SLEEP_CLK] = &gcc_blsp2_sleep_clk.clkr,
3294         [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
3295         [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
3296         [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
3297         [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
3298         [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
3299         [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
3300         [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
3301         [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
3302         [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
3303         [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
3304         [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
3305         [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr,
3306         [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
3307         [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
3308         [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr,
3309         [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
3310         [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
3311         [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr,
3312         [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3313         [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3314         [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3315         [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
3316         [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
3317         [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
3318         [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3319         [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
3320         [GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr,
3321         [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3322         [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3323         [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3324         [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
3325         [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
3326         [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
3327         [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
3328         [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
3329         [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
3330         [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
3331         [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
3332         [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
3333         [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
3334         [GCC_PCIE_2_SLV_AXI_CLK] = &gcc_pcie_2_slv_axi_clk.clkr,
3335         [GCC_PCIE_2_MSTR_AXI_CLK] = &gcc_pcie_2_mstr_axi_clk.clkr,
3336         [GCC_PCIE_2_CFG_AHB_CLK] = &gcc_pcie_2_cfg_ahb_clk.clkr,
3337         [GCC_PCIE_2_AUX_CLK] = &gcc_pcie_2_aux_clk.clkr,
3338         [GCC_PCIE_2_PIPE_CLK] = &gcc_pcie_2_pipe_clk.clkr,
3339         [GCC_PCIE_PHY_CFG_AHB_CLK] = &gcc_pcie_phy_cfg_ahb_clk.clkr,
3340         [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
3341         [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
3342         [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
3343         [GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr,
3344         [GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr,
3345         [GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK] = &gcc_hlos1_vote_lpass_core_smmu_clk.clkr,
3346         [GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK] = &gcc_hlos1_vote_lpass_adsp_smmu_clk.clkr,
3347         [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
3348         [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
3349         [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
3350         [GCC_UFS_UNIPRO_CORE_CLK] = &gcc_ufs_unipro_core_clk.clkr,
3351         [GCC_UFS_ICE_CORE_CLK] = &gcc_ufs_ice_core_clk.clkr,
3352         [GCC_UFS_SYS_CLK_CORE_CLK] = &gcc_ufs_sys_clk_core_clk.clkr,
3353         [GCC_UFS_TX_SYMBOL_CLK_CORE_CLK] = &gcc_ufs_tx_symbol_clk_core_clk.clkr,
3354         [GCC_AGGRE0_SNOC_AXI_CLK] = &gcc_aggre0_snoc_axi_clk.clkr,
3355         [GCC_AGGRE0_CNOC_AHB_CLK] = &gcc_aggre0_cnoc_ahb_clk.clkr,
3356         [GCC_SMMU_AGGRE0_AXI_CLK] = &gcc_smmu_aggre0_axi_clk.clkr,
3357         [GCC_SMMU_AGGRE0_AHB_CLK] = &gcc_smmu_aggre0_ahb_clk.clkr,
3358         [GCC_AGGRE2_UFS_AXI_CLK] = &gcc_aggre2_ufs_axi_clk.clkr,
3359         [GCC_AGGRE2_USB3_AXI_CLK] = &gcc_aggre2_usb3_axi_clk.clkr,
3360         [GCC_QSPI_AHB_CLK] = &gcc_qspi_ahb_clk.clkr,
3361         [GCC_QSPI_SER_CLK] = &gcc_qspi_ser_clk.clkr,
3362         [GCC_USB3_CLKREF_CLK] = &gcc_usb3_clkref_clk.clkr,
3363         [GCC_HDMI_CLKREF_CLK] = &gcc_hdmi_clkref_clk.clkr,
3364         [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr,
3365         [GCC_PCIE_CLKREF_CLK] = &gcc_pcie_clkref_clk.clkr,
3366         [GCC_RX2_USB2_CLKREF_CLK] = &gcc_rx2_usb2_clkref_clk.clkr,
3367         [GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr,
3368 };
3369
3370 static struct gdsc *gcc_msm8996_gdscs[] = {
3371         [AGGRE0_NOC_GDSC] = &aggre0_noc_gdsc,
3372         [HLOS1_VOTE_AGGRE0_NOC_GDSC] = &hlos1_vote_aggre0_noc_gdsc,
3373         [HLOS1_VOTE_LPASS_ADSP_GDSC] = &hlos1_vote_lpass_adsp_gdsc,
3374         [HLOS1_VOTE_LPASS_CORE_GDSC] = &hlos1_vote_lpass_core_gdsc,
3375         [USB30_GDSC] = &usb30_gdsc,
3376         [PCIE0_GDSC] = &pcie0_gdsc,
3377         [PCIE1_GDSC] = &pcie1_gdsc,
3378         [PCIE2_GDSC] = &pcie2_gdsc,
3379         [UFS_GDSC] = &ufs_gdsc,
3380 };
3381
3382 static const struct qcom_reset_map gcc_msm8996_resets[] = {
3383         [GCC_SYSTEM_NOC_BCR] = { 0x4000 },
3384         [GCC_CONFIG_NOC_BCR] = { 0x5000 },
3385         [GCC_PERIPH_NOC_BCR] = { 0x6000 },
3386         [GCC_IMEM_BCR] = { 0x8000 },
3387         [GCC_MMSS_BCR] = { 0x9000 },
3388         [GCC_PIMEM_BCR] = { 0x0a000 },
3389         [GCC_QDSS_BCR] = { 0x0c000 },
3390         [GCC_USB_30_BCR] = { 0x0f000 },
3391         [GCC_USB_20_BCR] = { 0x12000 },
3392         [GCC_QUSB2PHY_PRIM_BCR] = { 0x12038 },
3393         [GCC_QUSB2PHY_SEC_BCR] = { 0x1203c },
3394         [GCC_USB3_PHY_BCR] = { 0x50020 },
3395         [GCC_USB3PHY_PHY_BCR] = { 0x50024 },
3396         [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3397         [GCC_SDCC1_BCR] = { 0x13000 },
3398         [GCC_SDCC2_BCR] = { 0x14000 },
3399         [GCC_SDCC3_BCR] = { 0x15000 },
3400         [GCC_SDCC4_BCR] = { 0x16000 },
3401         [GCC_BLSP1_BCR] = { 0x17000 },
3402         [GCC_BLSP1_QUP1_BCR] = { 0x19000 },
3403         [GCC_BLSP1_UART1_BCR] = { 0x1a000 },
3404         [GCC_BLSP1_QUP2_BCR] = { 0x1b000 },
3405         [GCC_BLSP1_UART2_BCR] = { 0x1c000 },
3406         [GCC_BLSP1_QUP3_BCR] = { 0x1d000 },
3407         [GCC_BLSP1_UART3_BCR] = { 0x1e000 },
3408         [GCC_BLSP1_QUP4_BCR] = { 0x1f000 },
3409         [GCC_BLSP1_UART4_BCR] = { 0x20000 },
3410         [GCC_BLSP1_QUP5_BCR] = { 0x21000 },
3411         [GCC_BLSP1_UART5_BCR] = { 0x22000 },
3412         [GCC_BLSP1_QUP6_BCR] = { 0x23000 },
3413         [GCC_BLSP1_UART6_BCR] = { 0x24000 },
3414         [GCC_BLSP2_BCR] = { 0x25000 },
3415         [GCC_BLSP2_QUP1_BCR] = { 0x26000 },
3416         [GCC_BLSP2_UART1_BCR] = { 0x27000 },
3417         [GCC_BLSP2_QUP2_BCR] = { 0x28000 },
3418         [GCC_BLSP2_UART2_BCR] = { 0x29000 },
3419         [GCC_BLSP2_QUP3_BCR] = { 0x2a000 },
3420         [GCC_BLSP2_UART3_BCR] = { 0x2b000 },
3421         [GCC_BLSP2_QUP4_BCR] = { 0x2c000 },
3422         [GCC_BLSP2_UART4_BCR] = { 0x2d000 },
3423         [GCC_BLSP2_QUP5_BCR] = { 0x2e000 },
3424         [GCC_BLSP2_UART5_BCR] = { 0x2f000 },
3425         [GCC_BLSP2_QUP6_BCR] = { 0x30000 },
3426         [GCC_BLSP2_UART6_BCR] = { 0x31000 },
3427         [GCC_PDM_BCR] = { 0x33000 },
3428         [GCC_PRNG_BCR] = { 0x34000 },
3429         [GCC_TSIF_BCR] = { 0x36000 },
3430         [GCC_TCSR_BCR] = { 0x37000 },
3431         [GCC_BOOT_ROM_BCR] = { 0x38000 },
3432         [GCC_MSG_RAM_BCR] = { 0x39000 },
3433         [GCC_TLMM_BCR] = { 0x3a000 },
3434         [GCC_MPM_BCR] = { 0x3b000 },
3435         [GCC_SEC_CTRL_BCR] = { 0x3d000 },
3436         [GCC_SPMI_BCR] = { 0x3f000 },
3437         [GCC_SPDM_BCR] = { 0x40000 },
3438         [GCC_CE1_BCR] = { 0x41000 },
3439         [GCC_BIMC_BCR] = { 0x44000 },
3440         [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x49000 },
3441         [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x49008 },
3442         [GCC_SNOC_BUS_TIMEOUT1_BCR] = { 0x49010 },
3443         [GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x49018 },
3444         [GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x49020 },
3445         [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x4a000 },
3446         [GCC_PNOC_BUS_TIMEOUT1_BCR] = { 0x4a008 },
3447         [GCC_PNOC_BUS_TIMEOUT2_BCR] = { 0x4a010 },
3448         [GCC_PNOC_BUS_TIMEOUT3_BCR] = { 0x4a018 },
3449         [GCC_PNOC_BUS_TIMEOUT4_BCR] = { 0x4a020 },
3450         [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x4b000 },
3451         [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x4b008 },
3452         [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x4b010 },
3453         [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x4b018 },
3454         [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x4b020 },
3455         [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x4b028 },
3456         [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x4b030 },
3457         [GCC_CNOC_BUS_TIMEOUT7_BCR] = { 0x4b038 },
3458         [GCC_CNOC_BUS_TIMEOUT8_BCR] = { 0x80000 },
3459         [GCC_CNOC_BUS_TIMEOUT9_BCR] = { 0x80008 },
3460         [GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x80010 },
3461         [GCC_APB2JTAG_BCR] = { 0x4c000 },
3462         [GCC_RBCPR_CX_BCR] = { 0x4e000 },
3463         [GCC_RBCPR_MX_BCR] = { 0x4f000 },
3464         [GCC_PCIE_0_BCR] = { 0x6b000 },
3465         [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3466         [GCC_PCIE_1_BCR] = { 0x6d000 },
3467         [GCC_PCIE_1_PHY_BCR] = { 0x6d038 },
3468         [GCC_PCIE_2_BCR] = { 0x6e000 },
3469         [GCC_PCIE_2_PHY_BCR] = { 0x6e038 },
3470         [GCC_PCIE_PHY_BCR] = { 0x6f000 },
3471         [GCC_PCIE_PHY_COM_BCR] = { 0x6f014 },
3472         [GCC_PCIE_PHY_COM_NOCSR_BCR] = { 0x6f00c },
3473         [GCC_DCD_BCR] = { 0x70000 },
3474         [GCC_OBT_ODT_BCR] = { 0x73000 },
3475         [GCC_UFS_BCR] = { 0x75000 },
3476         [GCC_SSC_BCR] = { 0x63000 },
3477         [GCC_VS_BCR] = { 0x7a000 },
3478         [GCC_AGGRE0_NOC_BCR] = { 0x81000 },
3479         [GCC_AGGRE1_NOC_BCR] = { 0x82000 },
3480         [GCC_AGGRE2_NOC_BCR] = { 0x83000 },
3481         [GCC_DCC_BCR] = { 0x84000 },
3482         [GCC_IPA_BCR] = { 0x89000 },
3483         [GCC_QSPI_BCR] = { 0x8b000 },
3484         [GCC_SKL_BCR] = { 0x8c000 },
3485         [GCC_MSMPU_BCR] = { 0x8d000 },
3486         [GCC_MSS_Q6_BCR] = { 0x8e000 },
3487         [GCC_QREFS_VBG_CAL_BCR] = { 0x88020 },
3488         [GCC_MSS_RESTART] = { 0x8f008 },
3489 };
3490
3491 static const struct regmap_config gcc_msm8996_regmap_config = {
3492         .reg_bits       = 32,
3493         .reg_stride     = 4,
3494         .val_bits       = 32,
3495         .max_register   = 0x8f010,
3496         .fast_io        = true,
3497 };
3498
3499 static const struct qcom_cc_desc gcc_msm8996_desc = {
3500         .config = &gcc_msm8996_regmap_config,
3501         .clks = gcc_msm8996_clocks,
3502         .num_clks = ARRAY_SIZE(gcc_msm8996_clocks),
3503         .resets = gcc_msm8996_resets,
3504         .num_resets = ARRAY_SIZE(gcc_msm8996_resets),
3505         .gdscs = gcc_msm8996_gdscs,
3506         .num_gdscs = ARRAY_SIZE(gcc_msm8996_gdscs),
3507 };
3508
3509 static const struct of_device_id gcc_msm8996_match_table[] = {
3510         { .compatible = "qcom,gcc-msm8996" },
3511         { }
3512 };
3513 MODULE_DEVICE_TABLE(of, gcc_msm8996_match_table);
3514
3515 static int gcc_msm8996_probe(struct platform_device *pdev)
3516 {
3517         struct device *dev = &pdev->dev;
3518         int i, ret;
3519         struct regmap *regmap;
3520
3521         regmap = qcom_cc_map(pdev, &gcc_msm8996_desc);
3522         if (IS_ERR(regmap))
3523                 return PTR_ERR(regmap);
3524
3525         /*
3526          * Set the HMSS_AHB_CLK_SLEEP_ENA bit to allow the hmss_ahb_clk to be
3527          * turned off by hardware during certain apps low power modes.
3528          */
3529         regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21));
3530
3531         for (i = 0; i < ARRAY_SIZE(gcc_msm8996_hws); i++) {
3532                 ret = devm_clk_hw_register(dev, gcc_msm8996_hws[i]);
3533                 if (ret)
3534                         return ret;
3535         }
3536
3537         return qcom_cc_really_probe(pdev, &gcc_msm8996_desc, regmap);
3538 }
3539
3540 static struct platform_driver gcc_msm8996_driver = {
3541         .probe          = gcc_msm8996_probe,
3542         .driver         = {
3543                 .name   = "gcc-msm8996",
3544                 .of_match_table = gcc_msm8996_match_table,
3545         },
3546 };
3547
3548 static int __init gcc_msm8996_init(void)
3549 {
3550         return platform_driver_register(&gcc_msm8996_driver);
3551 }
3552 core_initcall(gcc_msm8996_init);
3553
3554 static void __exit gcc_msm8996_exit(void)
3555 {
3556         platform_driver_unregister(&gcc_msm8996_driver);
3557 }
3558 module_exit(gcc_msm8996_exit);
3559
3560 MODULE_DESCRIPTION("QCOM GCC MSM8996 Driver");
3561 MODULE_LICENSE("GPL v2");
3562 MODULE_ALIAS("platform:gcc-msm8996");