drivers/block/nvme-core.c

   1 /*
   2  * NVM Express device driver
   3  * Copyright (c) 2011-2014, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #include <linux/nvme.h>
  16 #include <linux/bitops.h>
  17 #include <linux/blkdev.h>
  18 #include <linux/blk-mq.h>
  19 #include <linux/cpu.h>
  20 #include <linux/delay.h>
  21 #include <linux/errno.h>
  22 #include <linux/fs.h>
  23 #include <linux/genhd.h>
  24 #include <linux/hdreg.h>
  25 #include <linux/idr.h>
  26 #include <linux/init.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/io.h>
  29 #include <linux/kdev_t.h>
  30 #include <linux/kthread.h>
  31 #include <linux/kernel.h>
  32 #include <linux/mm.h>
  33 #include <linux/module.h>
  34 #include <linux/moduleparam.h>
  35 #include <linux/pci.h>
  36 #include <linux/poison.h>
  37 #include <linux/ptrace.h>
  38 #include <linux/sched.h>
  39 #include <linux/slab.h>
  40 #include <linux/t10-pi.h>
  41 #include <linux/types.h>
  42 #include <scsi/sg.h>
  43 #include <asm-generic/io-64-nonatomic-lo-hi.h>
  44
  45 #define NVME_MINORS             (1U << MINORBITS)
  46 #define NVME_Q_DEPTH            1024
  47 #define NVME_AQ_DEPTH           256
  48 #define SQ_SIZE(depth)          (depth * sizeof(struct nvme_command))
  49 #define CQ_SIZE(depth)          (depth * sizeof(struct nvme_completion))
  50 #define ADMIN_TIMEOUT           (admin_timeout * HZ)
  51 #define SHUTDOWN_TIMEOUT        (shutdown_timeout * HZ)
  52
  53 static unsigned char admin_timeout = 60;
  54 module_param(admin_timeout, byte, 0644);
  55 MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
  56
  57 unsigned char nvme_io_timeout = 30;
  58 module_param_named(io_timeout, nvme_io_timeout, byte, 0644);
  59 MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
  60
  61 static unsigned char shutdown_timeout = 5;
  62 module_param(shutdown_timeout, byte, 0644);
  63 MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
  64
  65 static int nvme_major;
  66 module_param(nvme_major, int, 0);
  67
  68 static int nvme_char_major;
  69 module_param(nvme_char_major, int, 0);
  70
  71 static int use_threaded_interrupts;
  72 module_param(use_threaded_interrupts, int, 0);
  73
  74 static DEFINE_SPINLOCK(dev_list_lock);
  75 static LIST_HEAD(dev_list);
  76 static struct task_struct *nvme_thread;
  77 static struct workqueue_struct *nvme_workq;
  78 static wait_queue_head_t nvme_kthread_wait;
  79
  80 static struct class *nvme_class;
  81
  82 static void nvme_reset_failed_dev(struct work_struct *ws);
  83 static int nvme_process_cq(struct nvme_queue *nvmeq);
  84
  85 struct async_cmd_info {
  86         struct kthread_work work;
  87         struct kthread_worker *worker;
  88         struct request *req;
  89         u32 result;
  90         int status;
  91         void *ctx;
  92 };
  93
  94 /*
  95  * An NVM Express queue.  Each device has at least two (one for admin
  96  * commands and one for I/O commands).
  97  */
  98 struct nvme_queue {
  99         struct device *q_dmadev;
 100         struct nvme_dev *dev;
 101         char irqname[24];       /* nvme4294967295-65535\0 */
 102         spinlock_t q_lock;
 103         struct nvme_command *sq_cmds;
 104         volatile struct nvme_completion *cqes;
 105         dma_addr_t sq_dma_addr;
 106         dma_addr_t cq_dma_addr;
 107         u32 __iomem *q_db;
 108         u16 q_depth;
 109         s16 cq_vector;
 110         u16 sq_head;
 111         u16 sq_tail;
 112         u16 cq_head;
 113         u16 qid;
 114         u8 cq_phase;
 115         u8 cqe_seen;
 116         struct async_cmd_info cmdinfo;
 117         struct blk_mq_hw_ctx *hctx;
 118 };
 119
 120 /*
 121  * Check we didin't inadvertently grow the command struct
 122  */
 123 static inline void _nvme_check_size(void)
 124 {
 125         BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
 126         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
 127         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
 128         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
 129         BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
 130         BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
 131         BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
 132         BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
 133         BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
 134         BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
 135         BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
 136         BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
 137 }
 138
 139 typedef void (*nvme_completion_fn)(struct nvme_queue *, void *,
 140                                                 struct nvme_completion *);
 141
 142 struct nvme_cmd_info {
 143         nvme_completion_fn fn;
 144         void *ctx;
 145         int aborted;
 146         struct nvme_queue *nvmeq;
 147         struct nvme_iod iod[0];
 148 };
 149
 150 /*
 151  * Max size of iod being embedded in the request payload
 152  */
 153 #define NVME_INT_PAGES          2
 154 #define NVME_INT_BYTES(dev)     (NVME_INT_PAGES * (dev)->page_size)
 155 #define NVME_INT_MASK           0x01
 156
 157 /*
 158  * Will slightly overestimate the number of pages needed.  This is OK
 159  * as it only leads to a small amount of wasted memory for the lifetime of
 160  * the I/O.
 161  */
 162 static int nvme_npages(unsigned size, struct nvme_dev *dev)
 163 {
 164         unsigned nprps = DIV_ROUND_UP(size + dev->page_size, dev->page_size);
 165         return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
 166 }
 167
 168 static unsigned int nvme_cmd_size(struct nvme_dev *dev)
 169 {
 170         unsigned int ret = sizeof(struct nvme_cmd_info);
 171
 172         ret += sizeof(struct nvme_iod);
 173         ret += sizeof(__le64 *) * nvme_npages(NVME_INT_BYTES(dev), dev);
 174         ret += sizeof(struct scatterlist) * NVME_INT_PAGES;
 175
 176         return ret;
 177 }
 178
 179 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 180                                 unsigned int hctx_idx)
 181 {
 182         struct nvme_dev *dev = data;
 183         struct nvme_queue *nvmeq = dev->queues[0];
 184
 185         WARN_ON(nvmeq->hctx);
 186         nvmeq->hctx = hctx;
 187         hctx->driver_data = nvmeq;
 188         return 0;
 189 }
 190
 191 static int nvme_admin_init_request(void *data, struct request *req,
 192                                 unsigned int hctx_idx, unsigned int rq_idx,
 193                                 unsigned int numa_node)
 194 {
 195         struct nvme_dev *dev = data;
 196         struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
 197         struct nvme_queue *nvmeq = dev->queues[0];
 198
 199         BUG_ON(!nvmeq);
 200         cmd->nvmeq = nvmeq;
 201         return 0;
 202 }
 203
 204 static void nvme_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
 205 {
 206         struct nvme_queue *nvmeq = hctx->driver_data;
 207
 208         nvmeq->hctx = NULL;
 209 }
 210
 211 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 212                           unsigned int hctx_idx)
 213 {
 214         struct nvme_dev *dev = data;
 215         struct nvme_queue *nvmeq = dev->queues[
 216                                         (hctx_idx % dev->queue_count) + 1];
 217
 218         if (!nvmeq->hctx)
 219                 nvmeq->hctx = hctx;
 220
 221         /* nvmeq queues are shared between namespaces. We assume here that
 222          * blk-mq map the tags so they match up with the nvme queue tags. */
 223         WARN_ON(nvmeq->hctx->tags != hctx->tags);
 224
 225         hctx->driver_data = nvmeq;
 226         return 0;
 227 }
 228
 229 static int nvme_init_request(void *data, struct request *req,
 230                                 unsigned int hctx_idx, unsigned int rq_idx,
 231                                 unsigned int numa_node)
 232 {
 233         struct nvme_dev *dev = data;
 234         struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
 235         struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
 236
 237         BUG_ON(!nvmeq);
 238         cmd->nvmeq = nvmeq;
 239         return 0;
 240 }
 241
 242 static void nvme_set_info(struct nvme_cmd_info *cmd, void *ctx,
 243                                 nvme_completion_fn handler)
 244 {
 245         cmd->fn = handler;
 246         cmd->ctx = ctx;
 247         cmd->aborted = 0;
 248         blk_mq_start_request(blk_mq_rq_from_pdu(cmd));
 249 }
 250
 251 static void *iod_get_private(struct nvme_iod *iod)
 252 {
 253         return (void *) (iod->private & ~0x1UL);
 254 }
 255
 256 /*
 257  * If bit 0 is set, the iod is embedded in the request payload.
 258  */
 259 static bool iod_should_kfree(struct nvme_iod *iod)
 260 {
 261         return (iod->private & NVME_INT_MASK) == 0;
 262 }
 263
 264 /* Special values must be less than 0x1000 */
 265 #define CMD_CTX_BASE            ((void *)POISON_POINTER_DELTA)
 266 #define CMD_CTX_CANCELLED       (0x30C + CMD_CTX_BASE)
 267 #define CMD_CTX_COMPLETED       (0x310 + CMD_CTX_BASE)
 268 #define CMD_CTX_INVALID         (0x314 + CMD_CTX_BASE)
 269
 270 static void special_completion(struct nvme_queue *nvmeq, void *ctx,
 271                                                 struct nvme_completion *cqe)
 272 {
 273         if (ctx == CMD_CTX_CANCELLED)
 274                 return;
 275         if (ctx == CMD_CTX_COMPLETED) {
 276                 dev_warn(nvmeq->q_dmadev,
 277                                 "completed id %d twice on queue %d\n",
 278                                 cqe->command_id, le16_to_cpup(&cqe->sq_id));
 279                 return;
 280         }
 281         if (ctx == CMD_CTX_INVALID) {
 282                 dev_warn(nvmeq->q_dmadev,
 283                                 "invalid id %d completed on queue %d\n",
 284                                 cqe->command_id, le16_to_cpup(&cqe->sq_id));
 285                 return;
 286         }
 287         dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx);
 288 }
 289
 290 static void *cancel_cmd_info(struct nvme_cmd_info *cmd, nvme_completion_fn *fn)
 291 {
 292         void *ctx;
 293
 294         if (fn)
 295                 *fn = cmd->fn;
 296         ctx = cmd->ctx;
 297         cmd->fn = special_completion;
 298         cmd->ctx = CMD_CTX_CANCELLED;
 299         return ctx;
 300 }
 301
 302 static void async_req_completion(struct nvme_queue *nvmeq, void *ctx,
 303                                                 struct nvme_completion *cqe)
 304 {
 305         u32 result = le32_to_cpup(&cqe->result);
 306         u16 status = le16_to_cpup(&cqe->status) >> 1;
 307
 308         if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ)
 309                 ++nvmeq->dev->event_limit;
 310         if (status == NVME_SC_SUCCESS)
 311                 dev_warn(nvmeq->q_dmadev,
 312                         "async event result %08x\n", result);
 313 }
 314
 315 static void abort_completion(struct nvme_queue *nvmeq, void *ctx,
 316                                                 struct nvme_completion *cqe)
 317 {
 318         struct request *req = ctx;
 319
 320         u16 status = le16_to_cpup(&cqe->status) >> 1;
 321         u32 result = le32_to_cpup(&cqe->result);
 322
 323         blk_mq_free_hctx_request(nvmeq->hctx, req);
 324
 325         dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result);
 326         ++nvmeq->dev->abort_limit;
 327 }
 328
 329 static void async_completion(struct nvme_queue *nvmeq, void *ctx,
 330                                                 struct nvme_completion *cqe)
 331 {
 332         struct async_cmd_info *cmdinfo = ctx;
 333         cmdinfo->result = le32_to_cpup(&cqe->result);
 334         cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
 335         queue_kthread_work(cmdinfo->worker, &cmdinfo->work);
 336         blk_mq_free_hctx_request(nvmeq->hctx, cmdinfo->req);
 337 }
 338
 339 static inline struct nvme_cmd_info *get_cmd_from_tag(struct nvme_queue *nvmeq,
 340                                   unsigned int tag)
 341 {
 342         struct blk_mq_hw_ctx *hctx = nvmeq->hctx;
 343         struct request *req = blk_mq_tag_to_rq(hctx->tags, tag);
 344
 345         return blk_mq_rq_to_pdu(req);
 346 }
 347
 348 /*
 349  * Called with local interrupts disabled and the q_lock held.  May not sleep.
 350  */
 351 static void *nvme_finish_cmd(struct nvme_queue *nvmeq, int tag,
 352                                                 nvme_completion_fn *fn)
 353 {
 354         struct nvme_cmd_info *cmd = get_cmd_from_tag(nvmeq, tag);
 355         void *ctx;
 356         if (tag >= nvmeq->q_depth) {
 357                 *fn = special_completion;
 358                 return CMD_CTX_INVALID;
 359         }
 360         if (fn)
 361                 *fn = cmd->fn;
 362         ctx = cmd->ctx;
 363         cmd->fn = special_completion;
 364         cmd->ctx = CMD_CTX_COMPLETED;
 365         return ctx;
 366 }
 367
 368 /**
 369  * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
 370  * @nvmeq: The queue to use
 371  * @cmd: The command to send
 372  *
 373  * Safe to use from interrupt context
 374  */
 375 static int __nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
 376 {
 377         u16 tail = nvmeq->sq_tail;
 378
 379         memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
 380         if (++tail == nvmeq->q_depth)
 381                 tail = 0;
 382         writel(tail, nvmeq->q_db);
 383         nvmeq->sq_tail = tail;
 384
 385         return 0;
 386 }
 387
 388 static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
 389 {
 390         unsigned long flags;
 391         int ret;
 392         spin_lock_irqsave(&nvmeq->q_lock, flags);
 393         ret = __nvme_submit_cmd(nvmeq, cmd);
 394         spin_unlock_irqrestore(&nvmeq->q_lock, flags);
 395         return ret;
 396 }
 397
 398 static __le64 **iod_list(struct nvme_iod *iod)
 399 {
 400         return ((void *)iod) + iod->offset;
 401 }
 402
 403 static inline void iod_init(struct nvme_iod *iod, unsigned nbytes,
 404                             unsigned nseg, unsigned long private)
 405 {
 406         iod->private = private;
 407         iod->offset = offsetof(struct nvme_iod, sg[nseg]);
 408         iod->npages = -1;
 409         iod->length = nbytes;
 410         iod->nents = 0;
 411 }
 412
 413 static struct nvme_iod *
 414 __nvme_alloc_iod(unsigned nseg, unsigned bytes, struct nvme_dev *dev,
 415                  unsigned long priv, gfp_t gfp)
 416 {
 417         struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
 418                                 sizeof(__le64 *) * nvme_npages(bytes, dev) +
 419                                 sizeof(struct scatterlist) * nseg, gfp);
 420
 421         if (iod)
 422                 iod_init(iod, bytes, nseg, priv);
 423
 424         return iod;
 425 }
 426
 427 static struct nvme_iod *nvme_alloc_iod(struct request *rq, struct nvme_dev *dev,
 428                                        gfp_t gfp)
 429 {
 430         unsigned size = !(rq->cmd_flags & REQ_DISCARD) ? blk_rq_bytes(rq) :
 431                                                 sizeof(struct nvme_dsm_range);
 432         struct nvme_iod *iod;
 433
 434         if (rq->nr_phys_segments <= NVME_INT_PAGES &&
 435             size <= NVME_INT_BYTES(dev)) {
 436                 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(rq);
 437
 438                 iod = cmd->iod;
 439                 iod_init(iod, size, rq->nr_phys_segments,
 440                                 (unsigned long) rq | NVME_INT_MASK);
 441                 return iod;
 442         }
 443
 444         return __nvme_alloc_iod(rq->nr_phys_segments, size, dev,
 445                                 (unsigned long) rq, gfp);
 446 }
 447
 448 void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
 449 {
 450         const int last_prp = dev->page_size / 8 - 1;
 451         int i;
 452         __le64 **list = iod_list(iod);
 453         dma_addr_t prp_dma = iod->first_dma;
 454
 455         if (iod->npages == 0)
 456                 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
 457         for (i = 0; i < iod->npages; i++) {
 458                 __le64 *prp_list = list[i];
 459                 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
 460                 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
 461                 prp_dma = next_prp_dma;
 462         }
 463
 464         if (iod_should_kfree(iod))
 465                 kfree(iod);
 466 }
 467
 468 static int nvme_error_status(u16 status)
 469 {
 470         switch (status & 0x7ff) {
 471         case NVME_SC_SUCCESS:
 472                 return 0;
 473         case NVME_SC_CAP_EXCEEDED:
 474                 return -ENOSPC;
 475         default:
 476                 return -EIO;
 477         }
 478 }
 479
 480 #ifdef CONFIG_BLK_DEV_INTEGRITY
 481 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
 482 {
 483         if (be32_to_cpu(pi->ref_tag) == v)
 484                 pi->ref_tag = cpu_to_be32(p);
 485 }
 486
 487 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
 488 {
 489         if (be32_to_cpu(pi->ref_tag) == p)
 490                 pi->ref_tag = cpu_to_be32(v);
 491 }
 492
 493 /**
 494  * nvme_dif_remap - remaps ref tags to bip seed and physical lba
 495  *
 496  * The virtual start sector is the one that was originally submitted by the
 497  * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
 498  * start sector may be different. Remap protection information to match the
 499  * physical LBA on writes, and back to the original seed on reads.
 500  *
 501  * Type 0 and 3 do not have a ref tag, so no remapping required.
 502  */
 503 static void nvme_dif_remap(struct request *req,
 504                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
 505 {
 506         struct nvme_ns *ns = req->rq_disk->private_data;
 507         struct bio_integrity_payload *bip;
 508         struct t10_pi_tuple *pi;
 509         void *p, *pmap;
 510         u32 i, nlb, ts, phys, virt;
 511
 512         if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
 513                 return;
 514
 515         bip = bio_integrity(req->bio);
 516         if (!bip)
 517                 return;
 518
 519         pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
 520         if (!pmap)
 521                 return;
 522
 523         p = pmap;
 524         virt = bip_get_seed(bip);
 525         phys = nvme_block_nr(ns, blk_rq_pos(req));
 526         nlb = (blk_rq_bytes(req) >> ns->lba_shift);
 527         ts = ns->disk->integrity->tuple_size;
 528
 529         for (i = 0; i < nlb; i++, virt++, phys++) {
 530                 pi = (struct t10_pi_tuple *)p;
 531                 dif_swap(phys, virt, pi);
 532                 p += ts;
 533         }
 534         kunmap_atomic(pmap);
 535 }
 536
 537 static int nvme_noop_verify(struct blk_integrity_iter *iter)
 538 {
 539         return 0;
 540 }
 541
 542 static int nvme_noop_generate(struct blk_integrity_iter *iter)
 543 {
 544         return 0;
 545 }
 546
 547 struct blk_integrity nvme_meta_noop = {
 548         .name                   = "NVME_META_NOOP",
 549         .generate_fn            = nvme_noop_generate,
 550         .verify_fn              = nvme_noop_verify,
 551 };
 552
 553 static void nvme_init_integrity(struct nvme_ns *ns)
 554 {
 555         struct blk_integrity integrity;
 556
 557         switch (ns->pi_type) {
 558         case NVME_NS_DPS_PI_TYPE3:
 559                 integrity = t10_pi_type3_crc;
 560                 break;
 561         case NVME_NS_DPS_PI_TYPE1:
 562         case NVME_NS_DPS_PI_TYPE2:
 563                 integrity = t10_pi_type1_crc;
 564                 break;
 565         default:
 566                 integrity = nvme_meta_noop;
 567                 break;
 568         }
 569         integrity.tuple_size = ns->ms;
 570         blk_integrity_register(ns->disk, &integrity);
 571         blk_queue_max_integrity_segments(ns->queue, 1);
 572 }
 573 #else /* CONFIG_BLK_DEV_INTEGRITY */
 574 static void nvme_dif_remap(struct request *req,
 575                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
 576 {
 577 }
 578 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
 579 {
 580 }
 581 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
 582 {
 583 }
 584 static void nvme_init_integrity(struct nvme_ns *ns)
 585 {
 586 }
 587 #endif
 588
 589 static void req_completion(struct nvme_queue *nvmeq, void *ctx,
 590                                                 struct nvme_completion *cqe)
 591 {
 592         struct nvme_iod *iod = ctx;
 593         struct request *req = iod_get_private(iod);
 594         struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
 595
 596         u16 status = le16_to_cpup(&cqe->status) >> 1;
 597
 598         if (unlikely(status)) {
 599                 if (!(status & NVME_SC_DNR || blk_noretry_request(req))
 600                     && (jiffies - req->start_time) < req->timeout) {
 601                         unsigned long flags;
 602
 603                         blk_mq_requeue_request(req);
 604                         spin_lock_irqsave(req->q->queue_lock, flags);
 605                         if (!blk_queue_stopped(req->q))
 606                                 blk_mq_kick_requeue_list(req->q);
 607                         spin_unlock_irqrestore(req->q->queue_lock, flags);
 608                         return;
 609                 }
 610                 req->errors = nvme_error_status(status);
 611         } else
 612                 req->errors = 0;
 613
 614         if (cmd_rq->aborted)
 615                 dev_warn(&nvmeq->dev->pci_dev->dev,
 616                         "completing aborted command with status:%04x\n",
 617                         status);
 618
 619         if (iod->nents) {
 620                 dma_unmap_sg(&nvmeq->dev->pci_dev->dev, iod->sg, iod->nents,
 621                         rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
 622                 if (blk_integrity_rq(req)) {
 623                         if (!rq_data_dir(req))
 624                                 nvme_dif_remap(req, nvme_dif_complete);
 625                         dma_unmap_sg(&nvmeq->dev->pci_dev->dev, iod->meta_sg, 1,
 626                                 rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
 627                 }
 628         }
 629         nvme_free_iod(nvmeq->dev, iod);
 630
 631         blk_mq_complete_request(req);
 632 }
 633
 634 /* length is in bytes.  gfp flags indicates whether we may sleep. */
 635 int nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod, int total_len,
 636                                                                 gfp_t gfp)
 637 {
 638         struct dma_pool *pool;
 639         int length = total_len;
 640         struct scatterlist *sg = iod->sg;
 641         int dma_len = sg_dma_len(sg);
 642         u64 dma_addr = sg_dma_address(sg);
 643         u32 page_size = dev->page_size;
 644         int offset = dma_addr & (page_size - 1);
 645         __le64 *prp_list;
 646         __le64 **list = iod_list(iod);
 647         dma_addr_t prp_dma;
 648         int nprps, i;
 649
 650         length -= (page_size - offset);
 651         if (length <= 0)
 652                 return total_len;
 653
 654         dma_len -= (page_size - offset);
 655         if (dma_len) {
 656                 dma_addr += (page_size - offset);
 657         } else {
 658                 sg = sg_next(sg);
 659                 dma_addr = sg_dma_address(sg);
 660                 dma_len = sg_dma_len(sg);
 661         }
 662
 663         if (length <= page_size) {
 664                 iod->first_dma = dma_addr;
 665                 return total_len;
 666         }
 667
 668         nprps = DIV_ROUND_UP(length, page_size);
 669         if (nprps <= (256 / 8)) {
 670                 pool = dev->prp_small_pool;
 671                 iod->npages = 0;
 672         } else {
 673                 pool = dev->prp_page_pool;
 674                 iod->npages = 1;
 675         }
 676
 677         prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
 678         if (!prp_list) {
 679                 iod->first_dma = dma_addr;
 680                 iod->npages = -1;
 681                 return (total_len - length) + page_size;
 682         }
 683         list[0] = prp_list;
 684         iod->first_dma = prp_dma;
 685         i = 0;
 686         for (;;) {
 687                 if (i == page_size >> 3) {
 688                         __le64 *old_prp_list = prp_list;
 689                         prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
 690                         if (!prp_list)
 691                                 return total_len - length;
 692                         list[iod->npages++] = prp_list;
 693                         prp_list[0] = old_prp_list[i - 1];
 694                         old_prp_list[i - 1] = cpu_to_le64(prp_dma);
 695                         i = 1;
 696                 }
 697                 prp_list[i++] = cpu_to_le64(dma_addr);
 698                 dma_len -= page_size;
 699                 dma_addr += page_size;
 700                 length -= page_size;
 701                 if (length <= 0)
 702                         break;
 703                 if (dma_len > 0)
 704                         continue;
 705                 BUG_ON(dma_len < 0);
 706                 sg = sg_next(sg);
 707                 dma_addr = sg_dma_address(sg);
 708                 dma_len = sg_dma_len(sg);
 709         }
 710
 711         return total_len;
 712 }
 713
 714 /*
 715  * We reuse the small pool to allocate the 16-byte range here as it is not
 716  * worth having a special pool for these or additional cases to handle freeing
 717  * the iod.
 718  */
 719 static void nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
 720                 struct request *req, struct nvme_iod *iod)
 721 {
 722         struct nvme_dsm_range *range =
 723                                 (struct nvme_dsm_range *)iod_list(iod)[0];
 724         struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
 725
 726         range->cattr = cpu_to_le32(0);
 727         range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift);
 728         range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
 729
 730         memset(cmnd, 0, sizeof(*cmnd));
 731         cmnd->dsm.opcode = nvme_cmd_dsm;
 732         cmnd->dsm.command_id = req->tag;
 733         cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
 734         cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma);
 735         cmnd->dsm.nr = 0;
 736         cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
 737
 738         if (++nvmeq->sq_tail == nvmeq->q_depth)
 739                 nvmeq->sq_tail = 0;
 740         writel(nvmeq->sq_tail, nvmeq->q_db);
 741 }
 742
 743 static void nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
 744                                                                 int cmdid)
 745 {
 746         struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
 747
 748         memset(cmnd, 0, sizeof(*cmnd));
 749         cmnd->common.opcode = nvme_cmd_flush;
 750         cmnd->common.command_id = cmdid;
 751         cmnd->common.nsid = cpu_to_le32(ns->ns_id);
 752
 753         if (++nvmeq->sq_tail == nvmeq->q_depth)
 754                 nvmeq->sq_tail = 0;
 755         writel(nvmeq->sq_tail, nvmeq->q_db);
 756 }
 757
 758 static int nvme_submit_iod(struct nvme_queue *nvmeq, struct nvme_iod *iod,
 759                                                         struct nvme_ns *ns)
 760 {
 761         struct request *req = iod_get_private(iod);
 762         struct nvme_command *cmnd;
 763         u16 control = 0;
 764         u32 dsmgmt = 0;
 765
 766         if (req->cmd_flags & REQ_FUA)
 767                 control |= NVME_RW_FUA;
 768         if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
 769                 control |= NVME_RW_LR;
 770
 771         if (req->cmd_flags & REQ_RAHEAD)
 772                 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
 773
 774         cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
 775         memset(cmnd, 0, sizeof(*cmnd));
 776
 777         cmnd->rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read);
 778         cmnd->rw.command_id = req->tag;
 779         cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
 780         cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
 781         cmnd->rw.prp2 = cpu_to_le64(iod->first_dma);
 782         cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
 783         cmnd->rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
 784
 785         if (blk_integrity_rq(req)) {
 786                 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(iod->meta_sg));
 787                 switch (ns->pi_type) {
 788                 case NVME_NS_DPS_PI_TYPE3:
 789                         control |= NVME_RW_PRINFO_PRCHK_GUARD;
 790                         break;
 791                 case NVME_NS_DPS_PI_TYPE1:
 792                 case NVME_NS_DPS_PI_TYPE2:
 793                         control |= NVME_RW_PRINFO_PRCHK_GUARD |
 794                                         NVME_RW_PRINFO_PRCHK_REF;
 795                         cmnd->rw.reftag = cpu_to_le32(
 796                                         nvme_block_nr(ns, blk_rq_pos(req)));
 797                         break;
 798                 }
 799         } else if (ns->ms)
 800                 control |= NVME_RW_PRINFO_PRACT;
 801
 802         cmnd->rw.control = cpu_to_le16(control);
 803         cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
 804
 805         if (++nvmeq->sq_tail == nvmeq->q_depth)
 806                 nvmeq->sq_tail = 0;
 807         writel(nvmeq->sq_tail, nvmeq->q_db);
 808
 809         return 0;
 810 }
 811
 812 static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
 813                          const struct blk_mq_queue_data *bd)
 814 {
 815         struct nvme_ns *ns = hctx->queue->queuedata;
 816         struct nvme_queue *nvmeq = hctx->driver_data;
 817         struct request *req = bd->rq;
 818         struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
 819         struct nvme_iod *iod;
 820         enum dma_data_direction dma_dir;
 821
 822         /*
 823          * If formated with metadata, require the block layer provide a buffer
 824          * unless this namespace is formated such that the metadata can be
 825          * stripped/generated by the controller with PRACT=1.
 826          */
 827         if (ns->ms && !blk_integrity_rq(req)) {
 828                 if (!(ns->pi_type && ns->ms == 8)) {
 829                         req->errors = -EFAULT;
 830                         blk_mq_complete_request(req);
 831                         return BLK_MQ_RQ_QUEUE_OK;
 832                 }
 833         }
 834
 835         iod = nvme_alloc_iod(req, ns->dev, GFP_ATOMIC);
 836         if (!iod)
 837                 return BLK_MQ_RQ_QUEUE_BUSY;
 838
 839         if (req->cmd_flags & REQ_DISCARD) {
 840                 void *range;
 841                 /*
 842                  * We reuse the small pool to allocate the 16-byte range here
 843                  * as it is not worth having a special pool for these or
 844                  * additional cases to handle freeing the iod.
 845                  */
 846                 range = dma_pool_alloc(nvmeq->dev->prp_small_pool,
 847                                                 GFP_ATOMIC,
 848                                                 &iod->first_dma);
 849                 if (!range)
 850                         goto retry_cmd;
 851                 iod_list(iod)[0] = (__le64 *)range;
 852                 iod->npages = 0;
 853         } else if (req->nr_phys_segments) {
 854                 dma_dir = rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
 855
 856                 sg_init_table(iod->sg, req->nr_phys_segments);
 857                 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
 858                 if (!iod->nents)
 859                         goto error_cmd;
 860
 861                 if (!dma_map_sg(nvmeq->q_dmadev, iod->sg, iod->nents, dma_dir))
 862                         goto retry_cmd;
 863
 864                 if (blk_rq_bytes(req) !=
 865                     nvme_setup_prps(nvmeq->dev, iod, blk_rq_bytes(req), GFP_ATOMIC)) {
 866                         dma_unmap_sg(&nvmeq->dev->pci_dev->dev, iod->sg,
 867                                         iod->nents, dma_dir);
 868                         goto retry_cmd;
 869                 }
 870                 if (blk_integrity_rq(req)) {
 871                         if (blk_rq_count_integrity_sg(req->q, req->bio) != 1)
 872                                 goto error_cmd;
 873
 874                         sg_init_table(iod->meta_sg, 1);
 875                         if (blk_rq_map_integrity_sg(
 876                                         req->q, req->bio, iod->meta_sg) != 1)
 877                                 goto error_cmd;
 878
 879                         if (rq_data_dir(req))
 880                                 nvme_dif_remap(req, nvme_dif_prep);
 881
 882                         if (!dma_map_sg(nvmeq->q_dmadev, iod->meta_sg, 1, dma_dir))
 883                                 goto error_cmd;
 884                 }
 885         }
 886
 887         nvme_set_info(cmd, iod, req_completion);
 888         spin_lock_irq(&nvmeq->q_lock);
 889         if (req->cmd_flags & REQ_DISCARD)
 890                 nvme_submit_discard(nvmeq, ns, req, iod);
 891         else if (req->cmd_flags & REQ_FLUSH)
 892                 nvme_submit_flush(nvmeq, ns, req->tag);
 893         else
 894                 nvme_submit_iod(nvmeq, iod, ns);
 895
 896         nvme_process_cq(nvmeq);
 897         spin_unlock_irq(&nvmeq->q_lock);
 898         return BLK_MQ_RQ_QUEUE_OK;
 899
 900  error_cmd:
 901         nvme_free_iod(nvmeq->dev, iod);
 902         return BLK_MQ_RQ_QUEUE_ERROR;
 903  retry_cmd:
 904         nvme_free_iod(nvmeq->dev, iod);
 905         return BLK_MQ_RQ_QUEUE_BUSY;
 906 }
 907
 908 static int nvme_process_cq(struct nvme_queue *nvmeq)
 909 {
 910         u16 head, phase;
 911
 912         head = nvmeq->cq_head;
 913         phase = nvmeq->cq_phase;
 914
 915         for (;;) {
 916                 void *ctx;
 917                 nvme_completion_fn fn;
 918                 struct nvme_completion cqe = nvmeq->cqes[head];
 919                 if ((le16_to_cpu(cqe.status) & 1) != phase)
 920                         break;
 921                 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
 922                 if (++head == nvmeq->q_depth) {
 923                         head = 0;
 924                         phase = !phase;
 925                 }
 926                 ctx = nvme_finish_cmd(nvmeq, cqe.command_id, &fn);
 927                 fn(nvmeq, ctx, &cqe);
 928         }
 929
 930         /* If the controller ignores the cq head doorbell and continuously
 931          * writes to the queue, it is theoretically possible to wrap around
 932          * the queue twice and mistakenly return IRQ_NONE.  Linux only
 933          * requires that 0.1% of your interrupts are handled, so this isn't
 934          * a big problem.
 935          */
 936         if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
 937                 return 0;
 938
 939         writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
 940         nvmeq->cq_head = head;
 941         nvmeq->cq_phase = phase;
 942
 943         nvmeq->cqe_seen = 1;
 944         return 1;
 945 }
 946
 947 /* Admin queue isn't initialized as a request queue. If at some point this
 948  * happens anyway, make sure to notify the user */
 949 static int nvme_admin_queue_rq(struct blk_mq_hw_ctx *hctx,
 950                                const struct blk_mq_queue_data *bd)
 951 {
 952         WARN_ON_ONCE(1);
 953         return BLK_MQ_RQ_QUEUE_ERROR;
 954 }
 955
 956 static irqreturn_t nvme_irq(int irq, void *data)
 957 {
 958         irqreturn_t result;
 959         struct nvme_queue *nvmeq = data;
 960         spin_lock(&nvmeq->q_lock);
 961         nvme_process_cq(nvmeq);
 962         result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
 963         nvmeq->cqe_seen = 0;
 964         spin_unlock(&nvmeq->q_lock);
 965         return result;
 966 }
 967
 968 static irqreturn_t nvme_irq_check(int irq, void *data)
 969 {
 970         struct nvme_queue *nvmeq = data;
 971         struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
 972         if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
 973                 return IRQ_NONE;
 974         return IRQ_WAKE_THREAD;
 975 }
 976
 977 struct sync_cmd_info {
 978         struct task_struct *task;
 979         u32 result;
 980         int status;
 981 };
 982
 983 static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
 984                                                 struct nvme_completion *cqe)
 985 {
 986         struct sync_cmd_info *cmdinfo = ctx;
 987         cmdinfo->result = le32_to_cpup(&cqe->result);
 988         cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
 989         wake_up_process(cmdinfo->task);
 990 }
 991
 992 /*
 993  * Returns 0 on success.  If the result is negative, it's a Linux error code;
 994  * if the result is positive, it's an NVM Express status code
 995  */
 996 static int nvme_submit_sync_cmd(struct request *req, struct nvme_command *cmd,
 997                                                 u32 *result, unsigned timeout)
 998 {
 999         struct sync_cmd_info cmdinfo;
1000         struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
1001         struct nvme_queue *nvmeq = cmd_rq->nvmeq;
1002
1003         cmdinfo.task = current;
1004         cmdinfo.status = -EINTR;
1005
1006         cmd->common.command_id = req->tag;
1007
1008         nvme_set_info(cmd_rq, &cmdinfo, sync_completion);
1009
1010         set_current_state(TASK_UNINTERRUPTIBLE);
1011         nvme_submit_cmd(nvmeq, cmd);
1012         schedule();
1013
1014         if (result)
1015                 *result = cmdinfo.result;
1016         return cmdinfo.status;
1017 }
1018
1019 static int nvme_submit_async_admin_req(struct nvme_dev *dev)
1020 {
1021         struct nvme_queue *nvmeq = dev->queues[0];
1022         struct nvme_command c;
1023         struct nvme_cmd_info *cmd_info;
1024         struct request *req;
1025
1026         req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC, true);
1027         if (IS_ERR(req))
1028                 return PTR_ERR(req);
1029
1030         req->cmd_flags |= REQ_NO_TIMEOUT;
1031         cmd_info = blk_mq_rq_to_pdu(req);
1032         nvme_set_info(cmd_info, NULL, async_req_completion);
1033
1034         memset(&c, 0, sizeof(c));
1035         c.common.opcode = nvme_admin_async_event;
1036         c.common.command_id = req->tag;
1037
1038         blk_mq_free_hctx_request(nvmeq->hctx, req);
1039         return __nvme_submit_cmd(nvmeq, &c);
1040 }
1041
1042 static int nvme_submit_admin_async_cmd(struct nvme_dev *dev,
1043                         struct nvme_command *cmd,
1044                         struct async_cmd_info *cmdinfo, unsigned timeout)
1045 {
1046         struct nvme_queue *nvmeq = dev->queues[0];
1047         struct request *req;
1048         struct nvme_cmd_info *cmd_rq;
1049
1050         req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_KERNEL, false);
1051         if (IS_ERR(req))
1052                 return PTR_ERR(req);
1053
1054         req->timeout = timeout;
1055         cmd_rq = blk_mq_rq_to_pdu(req);
1056         cmdinfo->req = req;
1057         nvme_set_info(cmd_rq, cmdinfo, async_completion);
1058         cmdinfo->status = -EINTR;
1059
1060         cmd->common.command_id = req->tag;
1061
1062         return nvme_submit_cmd(nvmeq, cmd);
1063 }
1064
1065 static int __nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
1066                                                 u32 *result, unsigned timeout)
1067 {
1068         int res;
1069         struct request *req;
1070
1071         req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_KERNEL, false);
1072         if (IS_ERR(req))
1073                 return PTR_ERR(req);
1074         res = nvme_submit_sync_cmd(req, cmd, result, timeout);
1075         blk_mq_free_request(req);
1076         return res;
1077 }
1078
1079 int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
1080                                                                 u32 *result)
1081 {
1082         return __nvme_submit_admin_cmd(dev, cmd, result, ADMIN_TIMEOUT);
1083 }
1084
1085 int nvme_submit_io_cmd(struct nvme_dev *dev, struct nvme_ns *ns,
1086                                         struct nvme_command *cmd, u32 *result)
1087 {
1088         int res;
1089         struct request *req;
1090
1091         req = blk_mq_alloc_request(ns->queue, WRITE, (GFP_KERNEL|__GFP_WAIT),
1092                                                                         false);
1093         if (IS_ERR(req))
1094                 return PTR_ERR(req);
1095         res = nvme_submit_sync_cmd(req, cmd, result, NVME_IO_TIMEOUT);
1096         blk_mq_free_request(req);
1097         return res;
1098 }
1099
1100 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1101 {
1102         struct nvme_command c;
1103
1104         memset(&c, 0, sizeof(c));
1105         c.delete_queue.opcode = opcode;
1106         c.delete_queue.qid = cpu_to_le16(id);
1107
1108         return nvme_submit_admin_cmd(dev, &c, NULL);
1109 }
1110
1111 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1112                                                 struct nvme_queue *nvmeq)
1113 {
1114         struct nvme_command c;
1115         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
1116
1117         memset(&c, 0, sizeof(c));
1118         c.create_cq.opcode = nvme_admin_create_cq;
1119         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1120         c.create_cq.cqid = cpu_to_le16(qid);
1121         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1122         c.create_cq.cq_flags = cpu_to_le16(flags);
1123         c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
1124
1125         return nvme_submit_admin_cmd(dev, &c, NULL);
1126 }
1127
1128 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1129                                                 struct nvme_queue *nvmeq)
1130 {
1131         struct nvme_command c;
1132         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
1133
1134         memset(&c, 0, sizeof(c));
1135         c.create_sq.opcode = nvme_admin_create_sq;
1136         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1137         c.create_sq.sqid = cpu_to_le16(qid);
1138         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1139         c.create_sq.sq_flags = cpu_to_le16(flags);
1140         c.create_sq.cqid = cpu_to_le16(qid);
1141
1142         return nvme_submit_admin_cmd(dev, &c, NULL);
1143 }
1144
1145 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1146 {
1147         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1148 }
1149
1150 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1151 {
1152         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1153 }
1154
1155 int nvme_identify(struct nvme_dev *dev, unsigned nsid, unsigned cns,
1156                                                         dma_addr_t dma_addr)
1157 {
1158         struct nvme_command c;
1159
1160         memset(&c, 0, sizeof(c));
1161         c.identify.opcode = nvme_admin_identify;
1162         c.identify.nsid = cpu_to_le32(nsid);
1163         c.identify.prp1 = cpu_to_le64(dma_addr);
1164         c.identify.cns = cpu_to_le32(cns);
1165
1166         return nvme_submit_admin_cmd(dev, &c, NULL);
1167 }
1168
1169 int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
1170                                         dma_addr_t dma_addr, u32 *result)
1171 {
1172         struct nvme_command c;
1173
1174         memset(&c, 0, sizeof(c));
1175         c.features.opcode = nvme_admin_get_features;
1176         c.features.nsid = cpu_to_le32(nsid);
1177         c.features.prp1 = cpu_to_le64(dma_addr);
1178         c.features.fid = cpu_to_le32(fid);
1179
1180         return nvme_submit_admin_cmd(dev, &c, result);
1181 }
1182
1183 int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
1184                                         dma_addr_t dma_addr, u32 *result)
1185 {
1186         struct nvme_command c;
1187
1188         memset(&c, 0, sizeof(c));
1189         c.features.opcode = nvme_admin_set_features;
1190         c.features.prp1 = cpu_to_le64(dma_addr);
1191         c.features.fid = cpu_to_le32(fid);
1192         c.features.dword11 = cpu_to_le32(dword11);
1193
1194         return nvme_submit_admin_cmd(dev, &c, result);
1195 }
1196
1197 /**
1198  * nvme_abort_req - Attempt aborting a request
1199  *
1200  * Schedule controller reset if the command was already aborted once before and
1201  * still hasn't been returned to the driver, or if this is the admin queue.
1202  */
1203 static void nvme_abort_req(struct request *req)
1204 {
1205         struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
1206         struct nvme_queue *nvmeq = cmd_rq->nvmeq;
1207         struct nvme_dev *dev = nvmeq->dev;
1208         struct request *abort_req;
1209         struct nvme_cmd_info *abort_cmd;
1210         struct nvme_command cmd;
1211
1212         if (!nvmeq->qid || cmd_rq->aborted) {
1213                 unsigned long flags;
1214
1215                 spin_lock_irqsave(&dev_list_lock, flags);
1216                 if (work_busy(&dev->reset_work))
1217                         goto out;
1218                 list_del_init(&dev->node);
1219                 dev_warn(&dev->pci_dev->dev,
1220                         "I/O %d QID %d timeout, reset controller\n",
1221                                                         req->tag, nvmeq->qid);
1222                 dev->reset_workfn = nvme_reset_failed_dev;
1223                 queue_work(nvme_workq, &dev->reset_work);
1224  out:
1225                 spin_unlock_irqrestore(&dev_list_lock, flags);
1226                 return;
1227         }
1228
1229         if (!dev->abort_limit)
1230                 return;
1231
1232         abort_req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC,
1233                                                                         false);
1234         if (IS_ERR(abort_req))
1235                 return;
1236
1237         abort_cmd = blk_mq_rq_to_pdu(abort_req);
1238         nvme_set_info(abort_cmd, abort_req, abort_completion);
1239
1240         memset(&cmd, 0, sizeof(cmd));
1241         cmd.abort.opcode = nvme_admin_abort_cmd;
1242         cmd.abort.cid = req->tag;
1243         cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1244         cmd.abort.command_id = abort_req->tag;
1245
1246         --dev->abort_limit;
1247         cmd_rq->aborted = 1;
1248
1249         dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", req->tag,
1250                                                         nvmeq->qid);
1251         if (nvme_submit_cmd(dev->queues[0], &cmd) < 0) {
1252                 dev_warn(nvmeq->q_dmadev,
1253                                 "Could not abort I/O %d QID %d",
1254                                 req->tag, nvmeq->qid);
1255                 blk_mq_free_request(abort_req);
1256         }
1257 }
1258
1259 static void nvme_cancel_queue_ios(struct blk_mq_hw_ctx *hctx,
1260                                 struct request *req, void *data, bool reserved)
1261 {
1262         struct nvme_queue *nvmeq = data;
1263         void *ctx;
1264         nvme_completion_fn fn;
1265         struct nvme_cmd_info *cmd;
1266         struct nvme_completion cqe;
1267
1268         if (!blk_mq_request_started(req))
1269                 return;
1270
1271         cmd = blk_mq_rq_to_pdu(req);
1272
1273         if (cmd->ctx == CMD_CTX_CANCELLED)
1274                 return;
1275
1276         if (blk_queue_dying(req->q))
1277                 cqe.status = cpu_to_le16((NVME_SC_ABORT_REQ | NVME_SC_DNR) << 1);
1278         else
1279                 cqe.status = cpu_to_le16(NVME_SC_ABORT_REQ << 1);
1280
1281
1282         dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n",
1283                                                 req->tag, nvmeq->qid);
1284         ctx = cancel_cmd_info(cmd, &fn);
1285         fn(nvmeq, ctx, &cqe);
1286 }
1287
1288 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1289 {
1290         struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
1291         struct nvme_queue *nvmeq = cmd->nvmeq;
1292
1293         dev_warn(nvmeq->q_dmadev, "Timeout I/O %d QID %d\n", req->tag,
1294                                                         nvmeq->qid);
1295         spin_lock_irq(&nvmeq->q_lock);
1296         nvme_abort_req(req);
1297         spin_unlock_irq(&nvmeq->q_lock);
1298
1299         /*
1300          * The aborted req will be completed on receiving the abort req.
1301          * We enable the timer again. If hit twice, it'll cause a device reset,
1302          * as the device then is in a faulty state.
1303          */
1304         return BLK_EH_RESET_TIMER;
1305 }
1306
1307 static void nvme_free_queue(struct nvme_queue *nvmeq)
1308 {
1309         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1310                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1311         dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1312                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1313         kfree(nvmeq);
1314 }
1315
1316 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1317 {
1318         int i;
1319
1320         for (i = dev->queue_count - 1; i >= lowest; i--) {
1321                 struct nvme_queue *nvmeq = dev->queues[i];
1322                 dev->queue_count--;
1323                 dev->queues[i] = NULL;
1324                 nvme_free_queue(nvmeq);
1325         }
1326 }
1327
1328 /**
1329  * nvme_suspend_queue - put queue into suspended state
1330  * @nvmeq - queue to suspend
1331  */
1332 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1333 {
1334         int vector;
1335
1336         spin_lock_irq(&nvmeq->q_lock);
1337         if (nvmeq->cq_vector == -1) {
1338                 spin_unlock_irq(&nvmeq->q_lock);
1339                 return 1;
1340         }
1341         vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
1342         nvmeq->dev->online_queues--;
1343         nvmeq->cq_vector = -1;
1344         spin_unlock_irq(&nvmeq->q_lock);
1345
1346         if (!nvmeq->qid && nvmeq->dev->admin_q)
1347                 blk_mq_freeze_queue_start(nvmeq->dev->admin_q);
1348
1349         irq_set_affinity_hint(vector, NULL);
1350         free_irq(vector, nvmeq);
1351
1352         return 0;
1353 }
1354
1355 static void nvme_clear_queue(struct nvme_queue *nvmeq)
1356 {
1357         struct blk_mq_hw_ctx *hctx = nvmeq->hctx;
1358
1359         spin_lock_irq(&nvmeq->q_lock);
1360         if (hctx && hctx->tags)
1361                 blk_mq_tag_busy_iter(hctx, nvme_cancel_queue_ios, nvmeq);
1362         spin_unlock_irq(&nvmeq->q_lock);
1363 }
1364
1365 static void nvme_disable_queue(struct nvme_dev *dev, int qid)
1366 {
1367         struct nvme_queue *nvmeq = dev->queues[qid];
1368
1369         if (!nvmeq)
1370                 return;
1371         if (nvme_suspend_queue(nvmeq))
1372                 return;
1373
1374         /* Don't tell the adapter to delete the admin queue.
1375          * Don't tell a removed adapter to delete IO queues. */
1376         if (qid && readl(&dev->bar->csts) != -1) {
1377                 adapter_delete_sq(dev, qid);
1378                 adapter_delete_cq(dev, qid);
1379         }
1380
1381         spin_lock_irq(&nvmeq->q_lock);
1382         nvme_process_cq(nvmeq);
1383         spin_unlock_irq(&nvmeq->q_lock);
1384 }
1385
1386 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1387                                                         int depth)
1388 {
1389         struct device *dmadev = &dev->pci_dev->dev;
1390         struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
1391         if (!nvmeq)
1392                 return NULL;
1393
1394         nvmeq->cqes = dma_zalloc_coherent(dmadev, CQ_SIZE(depth),
1395                                           &nvmeq->cq_dma_addr, GFP_KERNEL);
1396         if (!nvmeq->cqes)
1397                 goto free_nvmeq;
1398
1399         nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
1400                                         &nvmeq->sq_dma_addr, GFP_KERNEL);
1401         if (!nvmeq->sq_cmds)
1402                 goto free_cqdma;
1403
1404         nvmeq->q_dmadev = dmadev;
1405         nvmeq->dev = dev;
1406         snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1407                         dev->instance, qid);
1408         spin_lock_init(&nvmeq->q_lock);
1409         nvmeq->cq_head = 0;
1410         nvmeq->cq_phase = 1;
1411         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1412         nvmeq->q_depth = depth;
1413         nvmeq->qid = qid;
1414         dev->queue_count++;
1415         dev->queues[qid] = nvmeq;
1416
1417         return nvmeq;
1418
1419  free_cqdma:
1420         dma_free_coherent(dmadev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1421                                                         nvmeq->cq_dma_addr);
1422  free_nvmeq:
1423         kfree(nvmeq);
1424         return NULL;
1425 }
1426
1427 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1428                                                         const char *name)
1429 {
1430         if (use_threaded_interrupts)
1431                 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
1432                                         nvme_irq_check, nvme_irq, IRQF_SHARED,
1433                                         name, nvmeq);
1434         return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
1435                                 IRQF_SHARED, name, nvmeq);
1436 }
1437
1438 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1439 {
1440         struct nvme_dev *dev = nvmeq->dev;
1441
1442         spin_lock_irq(&nvmeq->q_lock);
1443         nvmeq->sq_tail = 0;
1444         nvmeq->cq_head = 0;
1445         nvmeq->cq_phase = 1;
1446         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1447         memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1448         dev->online_queues++;
1449         spin_unlock_irq(&nvmeq->q_lock);
1450 }
1451
1452 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1453 {
1454         struct nvme_dev *dev = nvmeq->dev;
1455         int result;
1456
1457         nvmeq->cq_vector = qid - 1;
1458         result = adapter_alloc_cq(dev, qid, nvmeq);
1459         if (result < 0)
1460                 return result;
1461
1462         result = adapter_alloc_sq(dev, qid, nvmeq);
1463         if (result < 0)
1464                 goto release_cq;
1465
1466         result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1467         if (result < 0)
1468                 goto release_sq;
1469
1470         nvme_init_queue(nvmeq, qid);
1471         return result;
1472
1473  release_sq:
1474         adapter_delete_sq(dev, qid);
1475  release_cq:
1476         adapter_delete_cq(dev, qid);
1477         return result;
1478 }
1479
1480 static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled)
1481 {
1482         unsigned long timeout;
1483         u32 bit = enabled ? NVME_CSTS_RDY : 0;
1484
1485         timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1486
1487         while ((readl(&dev->bar->csts) & NVME_CSTS_RDY) != bit) {
1488                 msleep(100);
1489                 if (fatal_signal_pending(current))
1490                         return -EINTR;
1491                 if (time_after(jiffies, timeout)) {
1492                         dev_err(&dev->pci_dev->dev,
1493                                 "Device not ready; aborting %s\n", enabled ?
1494                                                 "initialisation" : "reset");
1495                         return -ENODEV;
1496                 }
1497         }
1498
1499         return 0;
1500 }
1501
1502 /*
1503  * If the device has been passed off to us in an enabled state, just clear
1504  * the enabled bit.  The spec says we should set the 'shutdown notification
1505  * bits', but doing so may cause the device to complete commands to the
1506  * admin queue ... and we don't know what memory that might be pointing at!
1507  */
1508 static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap)
1509 {
1510         dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1511         dev->ctrl_config &= ~NVME_CC_ENABLE;
1512         writel(dev->ctrl_config, &dev->bar->cc);
1513
1514         return nvme_wait_ready(dev, cap, false);
1515 }
1516
1517 static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap)
1518 {
1519         dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1520         dev->ctrl_config |= NVME_CC_ENABLE;
1521         writel(dev->ctrl_config, &dev->bar->cc);
1522
1523         return nvme_wait_ready(dev, cap, true);
1524 }
1525
1526 static int nvme_shutdown_ctrl(struct nvme_dev *dev)
1527 {
1528         unsigned long timeout;
1529
1530         dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1531         dev->ctrl_config |= NVME_CC_SHN_NORMAL;
1532
1533         writel(dev->ctrl_config, &dev->bar->cc);
1534
1535         timeout = SHUTDOWN_TIMEOUT + jiffies;
1536         while ((readl(&dev->bar->csts) & NVME_CSTS_SHST_MASK) !=
1537                                                         NVME_CSTS_SHST_CMPLT) {
1538                 msleep(100);
1539                 if (fatal_signal_pending(current))
1540                         return -EINTR;
1541                 if (time_after(jiffies, timeout)) {
1542                         dev_err(&dev->pci_dev->dev,
1543                                 "Device shutdown incomplete; abort shutdown\n");
1544                         return -ENODEV;
1545                 }
1546         }
1547
1548         return 0;
1549 }
1550
1551 static struct blk_mq_ops nvme_mq_admin_ops = {
1552         .queue_rq       = nvme_admin_queue_rq,
1553         .map_queue      = blk_mq_map_queue,
1554         .init_hctx      = nvme_admin_init_hctx,
1555         .exit_hctx      = nvme_exit_hctx,
1556         .init_request   = nvme_admin_init_request,
1557         .timeout        = nvme_timeout,
1558 };
1559
1560 static struct blk_mq_ops nvme_mq_ops = {
1561         .queue_rq       = nvme_queue_rq,
1562         .map_queue      = blk_mq_map_queue,
1563         .init_hctx      = nvme_init_hctx,
1564         .exit_hctx      = nvme_exit_hctx,
1565         .init_request   = nvme_init_request,
1566         .timeout        = nvme_timeout,
1567 };
1568
1569 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1570 {
1571         if (dev->admin_q && !blk_queue_dying(dev->admin_q)) {
1572                 blk_cleanup_queue(dev->admin_q);
1573                 blk_mq_free_tag_set(&dev->admin_tagset);
1574         }
1575 }
1576
1577 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1578 {
1579         if (!dev->admin_q) {
1580                 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1581                 dev->admin_tagset.nr_hw_queues = 1;
1582                 dev->admin_tagset.queue_depth = NVME_AQ_DEPTH - 1;
1583                 dev->admin_tagset.reserved_tags = 1;
1584                 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1585                 dev->admin_tagset.numa_node = dev_to_node(&dev->pci_dev->dev);
1586                 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
1587                 dev->admin_tagset.driver_data = dev;
1588
1589                 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1590                         return -ENOMEM;
1591
1592                 dev->admin_q = blk_mq_init_queue(&dev->admin_tagset);
1593                 if (IS_ERR(dev->admin_q)) {
1594                         blk_mq_free_tag_set(&dev->admin_tagset);
1595                         return -ENOMEM;
1596                 }
1597                 if (!blk_get_queue(dev->admin_q)) {
1598                         nvme_dev_remove_admin(dev);
1599                         return -ENODEV;
1600                 }
1601         } else
1602                 blk_mq_unfreeze_queue(dev->admin_q);
1603
1604         return 0;
1605 }
1606
1607 static int nvme_configure_admin_queue(struct nvme_dev *dev)
1608 {
1609         int result;
1610         u32 aqa;
1611         u64 cap = readq(&dev->bar->cap);
1612         struct nvme_queue *nvmeq;
1613         unsigned page_shift = PAGE_SHIFT;
1614         unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12;
1615         unsigned dev_page_max = NVME_CAP_MPSMAX(cap) + 12;
1616
1617         if (page_shift < dev_page_min) {
1618                 dev_err(&dev->pci_dev->dev,
1619                                 "Minimum device page size (%u) too large for "
1620                                 "host (%u)\n", 1 << dev_page_min,
1621                                 1 << page_shift);
1622                 return -ENODEV;
1623         }
1624         if (page_shift > dev_page_max) {
1625                 dev_info(&dev->pci_dev->dev,
1626                                 "Device maximum page size (%u) smaller than "
1627                                 "host (%u); enabling work-around\n",
1628                                 1 << dev_page_max, 1 << page_shift);
1629                 page_shift = dev_page_max;
1630         }
1631
1632         result = nvme_disable_ctrl(dev, cap);
1633         if (result < 0)
1634                 return result;
1635
1636         nvmeq = dev->queues[0];
1637         if (!nvmeq) {
1638                 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1639                 if (!nvmeq)
1640                         return -ENOMEM;
1641         }
1642
1643         aqa = nvmeq->q_depth - 1;
1644         aqa |= aqa << 16;
1645
1646         dev->page_size = 1 << page_shift;
1647
1648         dev->ctrl_config = NVME_CC_CSS_NVM;
1649         dev->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT;
1650         dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
1651         dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
1652
1653         writel(aqa, &dev->bar->aqa);
1654         writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
1655         writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
1656
1657         result = nvme_enable_ctrl(dev, cap);
1658         if (result)
1659                 goto free_nvmeq;
1660
1661         nvmeq->cq_vector = 0;
1662         result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1663         if (result)
1664                 goto free_nvmeq;
1665
1666         return result;
1667
1668  free_nvmeq:
1669         nvme_free_queues(dev, 0);
1670         return result;
1671 }
1672
1673 struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write,
1674                                 unsigned long addr, unsigned length)
1675 {
1676         int i, err, count, nents, offset;
1677         struct scatterlist *sg;
1678         struct page **pages;
1679         struct nvme_iod *iod;
1680
1681         if (addr & 3)
1682                 return ERR_PTR(-EINVAL);
1683         if (!length || length > INT_MAX - PAGE_SIZE)
1684                 return ERR_PTR(-EINVAL);
1685
1686         offset = offset_in_page(addr);
1687         count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
1688         pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
1689         if (!pages)
1690                 return ERR_PTR(-ENOMEM);
1691
1692         err = get_user_pages_fast(addr, count, 1, pages);
1693         if (err < count) {
1694                 count = err;
1695                 err = -EFAULT;
1696                 goto put_pages;
1697         }
1698
1699         err = -ENOMEM;
1700         iod = __nvme_alloc_iod(count, length, dev, 0, GFP_KERNEL);
1701         if (!iod)
1702                 goto put_pages;
1703
1704         sg = iod->sg;
1705         sg_init_table(sg, count);
1706         for (i = 0; i < count; i++) {
1707                 sg_set_page(&sg[i], pages[i],
1708                             min_t(unsigned, length, PAGE_SIZE - offset),
1709                             offset);
1710                 length -= (PAGE_SIZE - offset);
1711                 offset = 0;
1712         }
1713         sg_mark_end(&sg[i - 1]);
1714         iod->nents = count;
1715
1716         nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
1717                                 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1718         if (!nents)
1719                 goto free_iod;
1720
1721         kfree(pages);
1722         return iod;
1723
1724  free_iod:
1725         kfree(iod);
1726  put_pages:
1727         for (i = 0; i < count; i++)
1728                 put_page(pages[i]);
1729         kfree(pages);
1730         return ERR_PTR(err);
1731 }
1732
1733 void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
1734                         struct nvme_iod *iod)
1735 {
1736         int i;
1737
1738         dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents,
1739                                 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1740
1741         for (i = 0; i < iod->nents; i++)
1742                 put_page(sg_page(&iod->sg[i]));
1743 }
1744
1745 static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1746 {
1747         struct nvme_dev *dev = ns->dev;
1748         struct nvme_user_io io;
1749         struct nvme_command c;
1750         unsigned length, meta_len;
1751         int status, i;
1752         struct nvme_iod *iod, *meta_iod = NULL;
1753         dma_addr_t meta_dma_addr;
1754         void *meta, *uninitialized_var(meta_mem);
1755
1756         if (copy_from_user(&io, uio, sizeof(io)))
1757                 return -EFAULT;
1758         length = (io.nblocks + 1) << ns->lba_shift;
1759         meta_len = (io.nblocks + 1) * ns->ms;
1760
1761         if (meta_len && ((io.metadata & 3) || !io.metadata))
1762                 return -EINVAL;
1763
1764         switch (io.opcode) {
1765         case nvme_cmd_write:
1766         case nvme_cmd_read:
1767         case nvme_cmd_compare:
1768                 iod = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length);
1769                 break;
1770         default:
1771                 return -EINVAL;
1772         }
1773
1774         if (IS_ERR(iod))
1775                 return PTR_ERR(iod);
1776
1777         memset(&c, 0, sizeof(c));
1778         c.rw.opcode = io.opcode;
1779         c.rw.flags = io.flags;
1780         c.rw.nsid = cpu_to_le32(ns->ns_id);
1781         c.rw.slba = cpu_to_le64(io.slba);
1782         c.rw.length = cpu_to_le16(io.nblocks);
1783         c.rw.control = cpu_to_le16(io.control);
1784         c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
1785         c.rw.reftag = cpu_to_le32(io.reftag);
1786         c.rw.apptag = cpu_to_le16(io.apptag);
1787         c.rw.appmask = cpu_to_le16(io.appmask);
1788
1789         if (meta_len) {
1790                 meta_iod = nvme_map_user_pages(dev, io.opcode & 1, io.metadata,
1791                                                                 meta_len);
1792                 if (IS_ERR(meta_iod)) {
1793                         status = PTR_ERR(meta_iod);
1794                         meta_iod = NULL;
1795                         goto unmap;
1796                 }
1797
1798                 meta_mem = dma_alloc_coherent(&dev->pci_dev->dev, meta_len,
1799                                                 &meta_dma_addr, GFP_KERNEL);
1800                 if (!meta_mem) {
1801                         status = -ENOMEM;
1802                         goto unmap;
1803                 }
1804
1805                 if (io.opcode & 1) {
1806                         int meta_offset = 0;
1807
1808                         for (i = 0; i < meta_iod->nents; i++) {
1809                                 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1810                                                 meta_iod->sg[i].offset;
1811                                 memcpy(meta_mem + meta_offset, meta,
1812                                                 meta_iod->sg[i].length);
1813                                 kunmap_atomic(meta);
1814                                 meta_offset += meta_iod->sg[i].length;
1815                         }
1816                 }
1817
1818                 c.rw.metadata = cpu_to_le64(meta_dma_addr);
1819         }
1820
1821         length = nvme_setup_prps(dev, iod, length, GFP_KERNEL);
1822         c.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
1823         c.rw.prp2 = cpu_to_le64(iod->first_dma);
1824
1825         if (length != (io.nblocks + 1) << ns->lba_shift)
1826                 status = -ENOMEM;
1827         else
1828                 status = nvme_submit_io_cmd(dev, ns, &c, NULL);
1829
1830         if (meta_len) {
1831                 if (status == NVME_SC_SUCCESS && !(io.opcode & 1)) {
1832                         int meta_offset = 0;
1833
1834                         for (i = 0; i < meta_iod->nents; i++) {
1835                                 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1836                                                 meta_iod->sg[i].offset;
1837                                 memcpy(meta, meta_mem + meta_offset,
1838                                                 meta_iod->sg[i].length);
1839                                 kunmap_atomic(meta);
1840                                 meta_offset += meta_iod->sg[i].length;
1841                         }
1842                 }
1843
1844                 dma_free_coherent(&dev->pci_dev->dev, meta_len, meta_mem,
1845                                                                 meta_dma_addr);
1846         }
1847
1848  unmap:
1849         nvme_unmap_user_pages(dev, io.opcode & 1, iod);
1850         nvme_free_iod(dev, iod);
1851
1852         if (meta_iod) {
1853                 nvme_unmap_user_pages(dev, io.opcode & 1, meta_iod);
1854                 nvme_free_iod(dev, meta_iod);
1855         }
1856
1857         return status;
1858 }
1859
1860 static int nvme_user_cmd(struct nvme_dev *dev, struct nvme_ns *ns,
1861                         struct nvme_passthru_cmd __user *ucmd)
1862 {
1863         struct nvme_passthru_cmd cmd;
1864         struct nvme_command c;
1865         int status, length;
1866         struct nvme_iod *uninitialized_var(iod);
1867         unsigned timeout;
1868
1869         if (!capable(CAP_SYS_ADMIN))
1870                 return -EACCES;
1871         if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
1872                 return -EFAULT;
1873
1874         memset(&c, 0, sizeof(c));
1875         c.common.opcode = cmd.opcode;
1876         c.common.flags = cmd.flags;
1877         c.common.nsid = cpu_to_le32(cmd.nsid);
1878         c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1879         c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1880         c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1881         c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1882         c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1883         c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1884         c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1885         c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1886
1887         length = cmd.data_len;
1888         if (cmd.data_len) {
1889                 iod = nvme_map_user_pages(dev, cmd.opcode & 1, cmd.addr,
1890                                                                 length);
1891                 if (IS_ERR(iod))
1892                         return PTR_ERR(iod);
1893                 length = nvme_setup_prps(dev, iod, length, GFP_KERNEL);
1894                 c.common.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
1895                 c.common.prp2 = cpu_to_le64(iod->first_dma);
1896         }
1897
1898         timeout = cmd.timeout_ms ? msecs_to_jiffies(cmd.timeout_ms) :
1899                                                                 ADMIN_TIMEOUT;
1900
1901         if (length != cmd.data_len)
1902                 status = -ENOMEM;
1903         else if (ns) {
1904                 struct request *req;
1905
1906                 req = blk_mq_alloc_request(ns->queue, WRITE,
1907                                                 (GFP_KERNEL|__GFP_WAIT), false);
1908                 if (IS_ERR(req))
1909                         status = PTR_ERR(req);
1910                 else {
1911                         status = nvme_submit_sync_cmd(req, &c, &cmd.result,
1912                                                                 timeout);
1913                         blk_mq_free_request(req);
1914                 }
1915         } else
1916                 status = __nvme_submit_admin_cmd(dev, &c, &cmd.result, timeout);
1917
1918         if (cmd.data_len) {
1919                 nvme_unmap_user_pages(dev, cmd.opcode & 1, iod);
1920                 nvme_free_iod(dev, iod);
1921         }
1922
1923         if ((status >= 0) && copy_to_user(&ucmd->result, &cmd.result,
1924                                                         sizeof(cmd.result)))
1925                 status = -EFAULT;
1926
1927         return status;
1928 }
1929
1930 static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1931                                                         unsigned long arg)
1932 {
1933         struct nvme_ns *ns = bdev->bd_disk->private_data;
1934
1935         switch (cmd) {
1936         case NVME_IOCTL_ID:
1937                 force_successful_syscall_return();
1938                 return ns->ns_id;
1939         case NVME_IOCTL_ADMIN_CMD:
1940                 return nvme_user_cmd(ns->dev, NULL, (void __user *)arg);
1941         case NVME_IOCTL_IO_CMD:
1942                 return nvme_user_cmd(ns->dev, ns, (void __user *)arg);
1943         case NVME_IOCTL_SUBMIT_IO:
1944                 return nvme_submit_io(ns, (void __user *)arg);
1945         case SG_GET_VERSION_NUM:
1946                 return nvme_sg_get_version_num((void __user *)arg);
1947         case SG_IO:
1948                 return nvme_sg_io(ns, (void __user *)arg);
1949         default:
1950                 return -ENOTTY;
1951         }
1952 }
1953
1954 #ifdef CONFIG_COMPAT
1955 static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode,
1956                                         unsigned int cmd, unsigned long arg)
1957 {
1958         switch (cmd) {
1959         case SG_IO:
1960                 return -ENOIOCTLCMD;
1961         }
1962         return nvme_ioctl(bdev, mode, cmd, arg);
1963 }
1964 #else
1965 #define nvme_compat_ioctl       NULL
1966 #endif
1967
1968 static int nvme_open(struct block_device *bdev, fmode_t mode)
1969 {
1970         int ret = 0;
1971         struct nvme_ns *ns;
1972
1973         spin_lock(&dev_list_lock);
1974         ns = bdev->bd_disk->private_data;
1975         if (!ns)
1976                 ret = -ENXIO;
1977         else if (!kref_get_unless_zero(&ns->dev->kref))
1978                 ret = -ENXIO;
1979         spin_unlock(&dev_list_lock);
1980
1981         return ret;
1982 }
1983
1984 static void nvme_free_dev(struct kref *kref);
1985
1986 static void nvme_release(struct gendisk *disk, fmode_t mode)
1987 {
1988         struct nvme_ns *ns = disk->private_data;
1989         struct nvme_dev *dev = ns->dev;
1990
1991         kref_put(&dev->kref, nvme_free_dev);
1992 }
1993
1994 static int nvme_getgeo(struct block_device *bd, struct hd_geometry *geo)
1995 {
1996         /* some standard values */
1997         geo->heads = 1 << 6;
1998         geo->sectors = 1 << 5;
1999         geo->cylinders = get_capacity(bd->bd_disk) >> 11;
2000         return 0;
2001 }
2002
2003 static void nvme_config_discard(struct nvme_ns *ns)
2004 {
2005         u32 logical_block_size = queue_logical_block_size(ns->queue);
2006         ns->queue->limits.discard_zeroes_data = 0;
2007         ns->queue->limits.discard_alignment = logical_block_size;
2008         ns->queue->limits.discard_granularity = logical_block_size;
2009         ns->queue->limits.max_discard_sectors = 0xffffffff;
2010         queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
2011 }
2012
2013 static int nvme_revalidate_disk(struct gendisk *disk)
2014 {
2015         struct nvme_ns *ns = disk->private_data;
2016         struct nvme_dev *dev = ns->dev;
2017         struct nvme_id_ns *id;
2018         dma_addr_t dma_addr;
2019         int lbaf, pi_type, old_ms;
2020         unsigned short bs;
2021
2022         id = dma_alloc_coherent(&dev->pci_dev->dev, 4096, &dma_addr,
2023                                                                 GFP_KERNEL);
2024         if (!id) {
2025                 dev_warn(&dev->pci_dev->dev, "%s: Memory alocation failure\n",
2026                                                                 __func__);
2027                 return 0;
2028         }
2029         if (nvme_identify(dev, ns->ns_id, 0, dma_addr)) {
2030                 dev_warn(&dev->pci_dev->dev,
2031                         "identify failed ns:%d, setting capacity to 0\n",
2032                         ns->ns_id);
2033                 memset(id, 0, sizeof(*id));
2034         }
2035
2036         old_ms = ns->ms;
2037         lbaf = id->flbas & NVME_NS_FLBAS_LBA_MASK;
2038         ns->lba_shift = id->lbaf[lbaf].ds;
2039         ns->ms = le16_to_cpu(id->lbaf[lbaf].ms);
2040
2041         /*
2042          * If identify namespace failed, use default 512 byte block size so
2043          * block layer can use before failing read/write for 0 capacity.
2044          */
2045         if (ns->lba_shift == 0)
2046                 ns->lba_shift = 9;
2047         bs = 1 << ns->lba_shift;
2048
2049         /* XXX: PI implementation requires metadata equal t10 pi tuple size */
2050         pi_type = ns->ms == sizeof(struct t10_pi_tuple) ?
2051                                         id->dps & NVME_NS_DPS_PI_MASK : 0;
2052
2053         if (blk_get_integrity(disk) && (ns->pi_type != pi_type ||
2054                                 ns->ms != old_ms ||
2055                                 bs != queue_logical_block_size(disk->queue) ||
2056                                 (ns->ms && id->flbas & NVME_NS_FLBAS_META_EXT)))
2057                 blk_integrity_unregister(disk);
2058
2059         ns->pi_type = pi_type;
2060         blk_queue_logical_block_size(ns->queue, bs);
2061
2062         if (ns->ms && !blk_get_integrity(disk) && (disk->flags & GENHD_FL_UP) &&
2063                                 !(id->flbas & NVME_NS_FLBAS_META_EXT))
2064                 nvme_init_integrity(ns);
2065
2066         if (id->ncap == 0 || (ns->ms && !blk_get_integrity(disk)))
2067                 set_capacity(disk, 0);
2068         else
2069                 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
2070
2071         if (dev->oncs & NVME_CTRL_ONCS_DSM)
2072                 nvme_config_discard(ns);
2073
2074         dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
2075         return 0;
2076 }
2077
2078 static const struct block_device_operations nvme_fops = {
2079         .owner          = THIS_MODULE,
2080         .ioctl          = nvme_ioctl,
2081         .compat_ioctl   = nvme_compat_ioctl,
2082         .open           = nvme_open,
2083         .release        = nvme_release,
2084         .getgeo         = nvme_getgeo,
2085         .revalidate_disk= nvme_revalidate_disk,
2086 };
2087
2088 static int nvme_kthread(void *data)
2089 {
2090         struct nvme_dev *dev, *next;
2091
2092         while (!kthread_should_stop()) {
2093                 set_current_state(TASK_INTERRUPTIBLE);
2094                 spin_lock(&dev_list_lock);
2095                 list_for_each_entry_safe(dev, next, &dev_list, node) {
2096                         int i;
2097                         if (readl(&dev->bar->csts) & NVME_CSTS_CFS) {
2098                                 if (work_busy(&dev->reset_work))
2099                                         continue;
2100                                 list_del_init(&dev->node);
2101                                 dev_warn(&dev->pci_dev->dev,
2102                                         "Failed status: %x, reset controller\n",
2103                                         readl(&dev->bar->csts));
2104                                 dev->reset_workfn = nvme_reset_failed_dev;
2105                                 queue_work(nvme_workq, &dev->reset_work);
2106                                 continue;
2107                         }
2108                         for (i = 0; i < dev->queue_count; i++) {
2109                                 struct nvme_queue *nvmeq = dev->queues[i];
2110                                 if (!nvmeq)
2111                                         continue;
2112                                 spin_lock_irq(&nvmeq->q_lock);
2113                                 nvme_process_cq(nvmeq);
2114
2115                                 while ((i == 0) && (dev->event_limit > 0)) {
2116                                         if (nvme_submit_async_admin_req(dev))
2117                                                 break;
2118                                         dev->event_limit--;
2119                                 }
2120                                 spin_unlock_irq(&nvmeq->q_lock);
2121                         }
2122                 }
2123                 spin_unlock(&dev_list_lock);
2124                 schedule_timeout(round_jiffies_relative(HZ));
2125         }
2126         return 0;
2127 }
2128
2129 static void nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid)
2130 {
2131         struct nvme_ns *ns;
2132         struct gendisk *disk;
2133         int node = dev_to_node(&dev->pci_dev->dev);
2134
2135         ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node);
2136         if (!ns)
2137                 return;
2138
2139         ns->queue = blk_mq_init_queue(&dev->tagset);
2140         if (IS_ERR(ns->queue))
2141                 goto out_free_ns;
2142         queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue);
2143         queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
2144         queue_flag_set_unlocked(QUEUE_FLAG_SG_GAPS, ns->queue);
2145         ns->dev = dev;
2146         ns->queue->queuedata = ns;
2147
2148         disk = alloc_disk_node(0, node);
2149         if (!disk)
2150                 goto out_free_queue;
2151
2152         ns->ns_id = nsid;
2153         ns->disk = disk;
2154         ns->lba_shift = 9; /* set to a default value for 512 until disk is validated */
2155         list_add_tail(&ns->list, &dev->namespaces);
2156
2157         blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
2158         if (dev->max_hw_sectors)
2159                 blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors);
2160         if (dev->stripe_size)
2161                 blk_queue_chunk_sectors(ns->queue, dev->stripe_size >> 9);
2162         if (dev->vwc & NVME_CTRL_VWC_PRESENT)
2163                 blk_queue_flush(ns->queue, REQ_FLUSH | REQ_FUA);
2164
2165         disk->major = nvme_major;
2166         disk->first_minor = 0;
2167         disk->fops = &nvme_fops;
2168         disk->private_data = ns;
2169         disk->queue = ns->queue;
2170         disk->driverfs_dev = dev->device;
2171         disk->flags = GENHD_FL_EXT_DEVT;
2172         sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
2173
2174         /*
2175          * Initialize capacity to 0 until we establish the namespace format and
2176          * setup integrity extentions if necessary. The revalidate_disk after
2177          * add_disk allows the driver to register with integrity if the format
2178          * requires it.
2179          */
2180         set_capacity(disk, 0);
2181         nvme_revalidate_disk(ns->disk);
2182         add_disk(ns->disk);
2183         if (ns->ms)
2184                 revalidate_disk(ns->disk);
2185         return;
2186  out_free_queue:
2187         blk_cleanup_queue(ns->queue);
2188  out_free_ns:
2189         kfree(ns);
2190 }
2191
2192 static void nvme_create_io_queues(struct nvme_dev *dev)
2193 {
2194         unsigned i;
2195
2196         for (i = dev->queue_count; i <= dev->max_qid; i++)
2197                 if (!nvme_alloc_queue(dev, i, dev->q_depth))
2198                         break;
2199
2200         for (i = dev->online_queues; i <= dev->queue_count - 1; i++)
2201                 if (nvme_create_queue(dev->queues[i], i))
2202                         break;
2203 }
2204
2205 static int set_queue_count(struct nvme_dev *dev, int count)
2206 {
2207         int status;
2208         u32 result;
2209         u32 q_count = (count - 1) | ((count - 1) << 16);
2210
2211         status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
2212                                                                 &result);
2213         if (status < 0)
2214                 return status;
2215         if (status > 0) {
2216                 dev_err(&dev->pci_dev->dev, "Could not set queue count (%d)\n",
2217                                                                         status);
2218                 return 0;
2219         }
2220         return min(result & 0xffff, result >> 16) + 1;
2221 }
2222
2223 static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
2224 {
2225         return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
2226 }
2227
2228 static int nvme_setup_io_queues(struct nvme_dev *dev)
2229 {
2230         struct nvme_queue *adminq = dev->queues[0];
2231         struct pci_dev *pdev = dev->pci_dev;
2232         int result, i, vecs, nr_io_queues, size;
2233
2234         nr_io_queues = num_possible_cpus();
2235         result = set_queue_count(dev, nr_io_queues);
2236         if (result <= 0)
2237                 return result;
2238         if (result < nr_io_queues)
2239                 nr_io_queues = result;
2240
2241         size = db_bar_size(dev, nr_io_queues);
2242         if (size > 8192) {
2243                 iounmap(dev->bar);
2244                 do {
2245                         dev->bar = ioremap(pci_resource_start(pdev, 0), size);
2246                         if (dev->bar)
2247                                 break;
2248                         if (!--nr_io_queues)
2249                                 return -ENOMEM;
2250                         size = db_bar_size(dev, nr_io_queues);
2251                 } while (1);
2252                 dev->dbs = ((void __iomem *)dev->bar) + 4096;
2253                 adminq->q_db = dev->dbs;
2254         }
2255
2256         /* Deregister the admin queue's interrupt */
2257         free_irq(dev->entry[0].vector, adminq);
2258
2259         /*
2260          * If we enable msix early due to not intx, disable it again before
2261          * setting up the full range we need.
2262          */
2263         if (!pdev->irq)
2264                 pci_disable_msix(pdev);
2265
2266         for (i = 0; i < nr_io_queues; i++)
2267                 dev->entry[i].entry = i;
2268         vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
2269         if (vecs < 0) {
2270                 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
2271                 if (vecs < 0) {
2272                         vecs = 1;
2273                 } else {
2274                         for (i = 0; i < vecs; i++)
2275                                 dev->entry[i].vector = i + pdev->irq;
2276                 }
2277         }
2278
2279         /*
2280          * Should investigate if there's a performance win from allocating
2281          * more queues than interrupt vectors; it might allow the submission
2282          * path to scale better, even if the receive path is limited by the
2283          * number of interrupts.
2284          */
2285         nr_io_queues = vecs;
2286         dev->max_qid = nr_io_queues;
2287
2288         result = queue_request_irq(dev, adminq, adminq->irqname);
2289         if (result)
2290                 goto free_queues;
2291
2292         /* Free previously allocated queues that are no longer usable */
2293         nvme_free_queues(dev, nr_io_queues + 1);
2294         nvme_create_io_queues(dev);
2295
2296         return 0;
2297
2298  free_queues:
2299         nvme_free_queues(dev, 1);
2300         return result;
2301 }
2302
2303 /*
2304  * Return: error value if an error occurred setting up the queues or calling
2305  * Identify Device.  0 if these succeeded, even if adding some of the
2306  * namespaces failed.  At the moment, these failures are silent.  TBD which
2307  * failures should be reported.
2308  */
2309 static int nvme_dev_add(struct nvme_dev *dev)
2310 {
2311         struct pci_dev *pdev = dev->pci_dev;
2312         int res;
2313         unsigned nn, i;
2314         struct nvme_id_ctrl *ctrl;
2315         void *mem;
2316         dma_addr_t dma_addr;
2317         int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12;
2318
2319         mem = dma_alloc_coherent(&pdev->dev, 4096, &dma_addr, GFP_KERNEL);
2320         if (!mem)
2321                 return -ENOMEM;
2322
2323         res = nvme_identify(dev, 0, 1, dma_addr);
2324         if (res) {
2325                 dev_err(&pdev->dev, "Identify Controller failed (%d)\n", res);
2326                 dma_free_coherent(&dev->pci_dev->dev, 4096, mem, dma_addr);
2327                 return -EIO;
2328         }
2329
2330         ctrl = mem;
2331         nn = le32_to_cpup(&ctrl->nn);
2332         dev->oncs = le16_to_cpup(&ctrl->oncs);
2333         dev->abort_limit = ctrl->acl + 1;
2334         dev->vwc = ctrl->vwc;
2335         memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
2336         memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
2337         memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
2338         if (ctrl->mdts)
2339                 dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9);
2340         if ((pdev->vendor == PCI_VENDOR_ID_INTEL) &&
2341                         (pdev->device == 0x0953) && ctrl->vs[3]) {
2342                 unsigned int max_hw_sectors;
2343
2344                 dev->stripe_size = 1 << (ctrl->vs[3] + shift);
2345                 max_hw_sectors = dev->stripe_size >> (shift - 9);
2346                 if (dev->max_hw_sectors) {
2347                         dev->max_hw_sectors = min(max_hw_sectors,
2348                                                         dev->max_hw_sectors);
2349                 } else
2350                         dev->max_hw_sectors = max_hw_sectors;
2351         }
2352         dma_free_coherent(&dev->pci_dev->dev, 4096, mem, dma_addr);
2353
2354         dev->tagset.ops = &nvme_mq_ops;
2355         dev->tagset.nr_hw_queues = dev->online_queues - 1;
2356         dev->tagset.timeout = NVME_IO_TIMEOUT;
2357         dev->tagset.numa_node = dev_to_node(&dev->pci_dev->dev);
2358         dev->tagset.queue_depth =
2359                                 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
2360         dev->tagset.cmd_size = nvme_cmd_size(dev);
2361         dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2362         dev->tagset.driver_data = dev;
2363
2364         if (blk_mq_alloc_tag_set(&dev->tagset))
2365                 return 0;
2366
2367         for (i = 1; i <= nn; i++)
2368                 nvme_alloc_ns(dev, i);
2369
2370         return 0;
2371 }
2372
2373 static int nvme_dev_map(struct nvme_dev *dev)
2374 {
2375         u64 cap;
2376         int bars, result = -ENOMEM;
2377         struct pci_dev *pdev = dev->pci_dev;
2378
2379         if (pci_enable_device_mem(pdev))
2380                 return result;
2381
2382         dev->entry[0].vector = pdev->irq;
2383         pci_set_master(pdev);
2384         bars = pci_select_bars(pdev, IORESOURCE_MEM);
2385         if (!bars)
2386                 goto disable_pci;
2387
2388         if (pci_request_selected_regions(pdev, bars, "nvme"))
2389                 goto disable_pci;
2390
2391         if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) &&
2392             dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)))
2393                 goto disable;
2394
2395         dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
2396         if (!dev->bar)
2397                 goto disable;
2398
2399         if (readl(&dev->bar->csts) == -1) {
2400                 result = -ENODEV;
2401                 goto unmap;
2402         }
2403
2404         /*
2405          * Some devices don't advertse INTx interrupts, pre-enable a single
2406          * MSIX vec for setup. We'll adjust this later.
2407          */
2408         if (!pdev->irq) {
2409                 result = pci_enable_msix(pdev, dev->entry, 1);
2410                 if (result < 0)
2411                         goto unmap;
2412         }
2413
2414         cap = readq(&dev->bar->cap);
2415         dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
2416         dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
2417         dev->dbs = ((void __iomem *)dev->bar) + 4096;
2418
2419         return 0;
2420
2421  unmap:
2422         iounmap(dev->bar);
2423         dev->bar = NULL;
2424  disable:
2425         pci_release_regions(pdev);
2426  disable_pci:
2427         pci_disable_device(pdev);
2428         return result;
2429 }
2430
2431 static void nvme_dev_unmap(struct nvme_dev *dev)
2432 {
2433         if (dev->pci_dev->msi_enabled)
2434                 pci_disable_msi(dev->pci_dev);
2435         else if (dev->pci_dev->msix_enabled)
2436                 pci_disable_msix(dev->pci_dev);
2437
2438         if (dev->bar) {
2439                 iounmap(dev->bar);
2440                 dev->bar = NULL;
2441                 pci_release_regions(dev->pci_dev);
2442         }
2443
2444         if (pci_is_enabled(dev->pci_dev))
2445                 pci_disable_device(dev->pci_dev);
2446 }
2447
2448 struct nvme_delq_ctx {
2449         struct task_struct *waiter;
2450         struct kthread_worker *worker;
2451         atomic_t refcount;
2452 };
2453
2454 static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev)
2455 {
2456         dq->waiter = current;
2457         mb();
2458
2459         for (;;) {
2460                 set_current_state(TASK_KILLABLE);
2461                 if (!atomic_read(&dq->refcount))
2462                         break;
2463                 if (!schedule_timeout(ADMIN_TIMEOUT) ||
2464                                         fatal_signal_pending(current)) {
2465                         /*
2466                          * Disable the controller first since we can't trust it
2467                          * at this point, but leave the admin queue enabled
2468                          * until all queue deletion requests are flushed.
2469                          * FIXME: This may take a while if there are more h/w
2470                          * queues than admin tags.
2471                          */
2472                         set_current_state(TASK_RUNNING);
2473                         nvme_disable_ctrl(dev, readq(&dev->bar->cap));
2474                         nvme_clear_queue(dev->queues[0]);
2475                         flush_kthread_worker(dq->worker);
2476                         nvme_disable_queue(dev, 0);
2477                         return;
2478                 }
2479         }
2480         set_current_state(TASK_RUNNING);
2481 }
2482
2483 static void nvme_put_dq(struct nvme_delq_ctx *dq)
2484 {
2485         atomic_dec(&dq->refcount);
2486         if (dq->waiter)
2487                 wake_up_process(dq->waiter);
2488 }
2489
2490 static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq)
2491 {
2492         atomic_inc(&dq->refcount);
2493         return dq;
2494 }
2495
2496 static void nvme_del_queue_end(struct nvme_queue *nvmeq)
2497 {
2498         struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx;
2499         nvme_put_dq(dq);
2500 }
2501
2502 static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode,
2503                                                 kthread_work_func_t fn)
2504 {
2505         struct nvme_command c;
2506
2507         memset(&c, 0, sizeof(c));
2508         c.delete_queue.opcode = opcode;
2509         c.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2510
2511         init_kthread_work(&nvmeq->cmdinfo.work, fn);
2512         return nvme_submit_admin_async_cmd(nvmeq->dev, &c, &nvmeq->cmdinfo,
2513                                                                 ADMIN_TIMEOUT);
2514 }
2515
2516 static void nvme_del_cq_work_handler(struct kthread_work *work)
2517 {
2518         struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2519                                                         cmdinfo.work);
2520         nvme_del_queue_end(nvmeq);
2521 }
2522
2523 static int nvme_delete_cq(struct nvme_queue *nvmeq)
2524 {
2525         return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq,
2526                                                 nvme_del_cq_work_handler);
2527 }
2528
2529 static void nvme_del_sq_work_handler(struct kthread_work *work)
2530 {
2531         struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2532                                                         cmdinfo.work);
2533         int status = nvmeq->cmdinfo.status;
2534
2535         if (!status)
2536                 status = nvme_delete_cq(nvmeq);
2537         if (status)
2538                 nvme_del_queue_end(nvmeq);
2539 }
2540
2541 static int nvme_delete_sq(struct nvme_queue *nvmeq)
2542 {
2543         return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq,
2544                                                 nvme_del_sq_work_handler);
2545 }
2546
2547 static void nvme_del_queue_start(struct kthread_work *work)
2548 {
2549         struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2550                                                         cmdinfo.work);
2551         if (nvme_delete_sq(nvmeq))
2552                 nvme_del_queue_end(nvmeq);
2553 }
2554
2555 static void nvme_disable_io_queues(struct nvme_dev *dev)
2556 {
2557         int i;
2558         DEFINE_KTHREAD_WORKER_ONSTACK(worker);
2559         struct nvme_delq_ctx dq;
2560         struct task_struct *kworker_task = kthread_run(kthread_worker_fn,
2561                                         &worker, "nvme%d", dev->instance);
2562
2563         if (IS_ERR(kworker_task)) {
2564                 dev_err(&dev->pci_dev->dev,
2565                         "Failed to create queue del task\n");
2566                 for (i = dev->queue_count - 1; i > 0; i--)
2567                         nvme_disable_queue(dev, i);
2568                 return;
2569         }
2570
2571         dq.waiter = NULL;
2572         atomic_set(&dq.refcount, 0);
2573         dq.worker = &worker;
2574         for (i = dev->queue_count - 1; i > 0; i--) {
2575                 struct nvme_queue *nvmeq = dev->queues[i];
2576
2577                 if (nvme_suspend_queue(nvmeq))
2578                         continue;
2579                 nvmeq->cmdinfo.ctx = nvme_get_dq(&dq);
2580                 nvmeq->cmdinfo.worker = dq.worker;
2581                 init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start);
2582                 queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work);
2583         }
2584         nvme_wait_dq(&dq, dev);
2585         kthread_stop(kworker_task);
2586 }
2587
2588 /*
2589 * Remove the node from the device list and check
2590 * for whether or not we need to stop the nvme_thread.
2591 */
2592 static void nvme_dev_list_remove(struct nvme_dev *dev)
2593 {
2594         struct task_struct *tmp = NULL;
2595
2596         spin_lock(&dev_list_lock);
2597         list_del_init(&dev->node);
2598         if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) {
2599                 tmp = nvme_thread;
2600                 nvme_thread = NULL;
2601         }
2602         spin_unlock(&dev_list_lock);
2603
2604         if (tmp)
2605                 kthread_stop(tmp);
2606 }
2607
2608 static void nvme_freeze_queues(struct nvme_dev *dev)
2609 {
2610         struct nvme_ns *ns;
2611
2612         list_for_each_entry(ns, &dev->namespaces, list) {
2613                 blk_mq_freeze_queue_start(ns->queue);
2614
2615                 spin_lock(ns->queue->queue_lock);
2616                 queue_flag_set(QUEUE_FLAG_STOPPED, ns->queue);
2617                 spin_unlock(ns->queue->queue_lock);
2618
2619                 blk_mq_cancel_requeue_work(ns->queue);
2620                 blk_mq_stop_hw_queues(ns->queue);
2621         }
2622 }
2623
2624 static void nvme_unfreeze_queues(struct nvme_dev *dev)
2625 {
2626         struct nvme_ns *ns;
2627
2628         list_for_each_entry(ns, &dev->namespaces, list) {
2629                 queue_flag_clear_unlocked(QUEUE_FLAG_STOPPED, ns->queue);
2630                 blk_mq_unfreeze_queue(ns->queue);
2631                 blk_mq_start_stopped_hw_queues(ns->queue, true);
2632                 blk_mq_kick_requeue_list(ns->queue);
2633         }
2634 }
2635
2636 static void nvme_dev_shutdown(struct nvme_dev *dev)
2637 {
2638         int i;
2639         u32 csts = -1;
2640
2641         nvme_dev_list_remove(dev);
2642
2643         if (dev->bar) {
2644                 nvme_freeze_queues(dev);
2645                 csts = readl(&dev->bar->csts);
2646         }
2647         if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
2648                 for (i = dev->queue_count - 1; i >= 0; i--) {
2649                         struct nvme_queue *nvmeq = dev->queues[i];
2650                         nvme_suspend_queue(nvmeq);
2651                 }
2652         } else {
2653                 nvme_disable_io_queues(dev);
2654                 nvme_shutdown_ctrl(dev);
2655                 nvme_disable_queue(dev, 0);
2656         }
2657         nvme_dev_unmap(dev);
2658
2659         for (i = dev->queue_count - 1; i >= 0; i--)
2660                 nvme_clear_queue(dev->queues[i]);
2661 }
2662
2663 static void nvme_dev_remove(struct nvme_dev *dev)
2664 {
2665         struct nvme_ns *ns;
2666
2667         list_for_each_entry(ns, &dev->namespaces, list) {
2668                 if (ns->disk->flags & GENHD_FL_UP) {
2669                         if (blk_get_integrity(ns->disk))
2670                                 blk_integrity_unregister(ns->disk);
2671                         del_gendisk(ns->disk);
2672                 }
2673                 if (!blk_queue_dying(ns->queue)) {
2674                         blk_mq_abort_requeue_list(ns->queue);
2675                         blk_cleanup_queue(ns->queue);
2676                 }
2677         }
2678 }
2679
2680 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2681 {
2682         struct device *dmadev = &dev->pci_dev->dev;
2683         dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
2684                                                 PAGE_SIZE, PAGE_SIZE, 0);
2685         if (!dev->prp_page_pool)
2686                 return -ENOMEM;
2687
2688         /* Optimisation for I/Os between 4k and 128k */
2689         dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
2690                                                 256, 256, 0);
2691         if (!dev->prp_small_pool) {
2692                 dma_pool_destroy(dev->prp_page_pool);
2693                 return -ENOMEM;
2694         }
2695         return 0;
2696 }
2697
2698 static void nvme_release_prp_pools(struct nvme_dev *dev)
2699 {
2700         dma_pool_destroy(dev->prp_page_pool);
2701         dma_pool_destroy(dev->prp_small_pool);
2702 }
2703
2704 static DEFINE_IDA(nvme_instance_ida);
2705
2706 static int nvme_set_instance(struct nvme_dev *dev)
2707 {
2708         int instance, error;
2709
2710         do {
2711                 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
2712                         return -ENODEV;
2713
2714                 spin_lock(&dev_list_lock);
2715                 error = ida_get_new(&nvme_instance_ida, &instance);
2716                 spin_unlock(&dev_list_lock);
2717         } while (error == -EAGAIN);
2718
2719         if (error)
2720                 return -ENODEV;
2721
2722         dev->instance = instance;
2723         return 0;
2724 }
2725
2726 static void nvme_release_instance(struct nvme_dev *dev)
2727 {
2728         spin_lock(&dev_list_lock);
2729         ida_remove(&nvme_instance_ida, dev->instance);
2730         spin_unlock(&dev_list_lock);
2731 }
2732
2733 static void nvme_free_namespaces(struct nvme_dev *dev)
2734 {
2735         struct nvme_ns *ns, *next;
2736
2737         list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
2738                 list_del(&ns->list);
2739
2740                 spin_lock(&dev_list_lock);
2741                 ns->disk->private_data = NULL;
2742                 spin_unlock(&dev_list_lock);
2743
2744                 put_disk(ns->disk);
2745                 kfree(ns);
2746         }
2747 }
2748
2749 static void nvme_free_dev(struct kref *kref)
2750 {
2751         struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref);
2752
2753         pci_dev_put(dev->pci_dev);
2754         put_device(dev->device);
2755         nvme_free_namespaces(dev);
2756         nvme_release_instance(dev);
2757         blk_mq_free_tag_set(&dev->tagset);
2758         blk_put_queue(dev->admin_q);
2759         kfree(dev->queues);
2760         kfree(dev->entry);
2761         kfree(dev);
2762 }
2763
2764 static int nvme_dev_open(struct inode *inode, struct file *f)
2765 {
2766         struct nvme_dev *dev;
2767         int instance = iminor(inode);
2768         int ret = -ENODEV;
2769
2770         spin_lock(&dev_list_lock);
2771         list_for_each_entry(dev, &dev_list, node) {
2772                 if (dev->instance == instance) {
2773                         if (!dev->admin_q) {
2774                                 ret = -EWOULDBLOCK;
2775                                 break;
2776                         }
2777                         if (!kref_get_unless_zero(&dev->kref))
2778                                 break;
2779                         f->private_data = dev;
2780                         ret = 0;
2781                         break;
2782                 }
2783         }
2784         spin_unlock(&dev_list_lock);
2785
2786         return ret;
2787 }
2788
2789 static int nvme_dev_release(struct inode *inode, struct file *f)
2790 {
2791         struct nvme_dev *dev = f->private_data;
2792         kref_put(&dev->kref, nvme_free_dev);
2793         return 0;
2794 }
2795
2796 static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
2797 {
2798         struct nvme_dev *dev = f->private_data;
2799         struct nvme_ns *ns;
2800
2801         switch (cmd) {
2802         case NVME_IOCTL_ADMIN_CMD:
2803                 return nvme_user_cmd(dev, NULL, (void __user *)arg);
2804         case NVME_IOCTL_IO_CMD:
2805                 if (list_empty(&dev->namespaces))
2806                         return -ENOTTY;
2807                 ns = list_first_entry(&dev->namespaces, struct nvme_ns, list);
2808                 return nvme_user_cmd(dev, ns, (void __user *)arg);
2809         default:
2810                 return -ENOTTY;
2811         }
2812 }
2813
2814 static const struct file_operations nvme_dev_fops = {
2815         .owner          = THIS_MODULE,
2816         .open           = nvme_dev_open,
2817         .release        = nvme_dev_release,
2818         .unlocked_ioctl = nvme_dev_ioctl,
2819         .compat_ioctl   = nvme_dev_ioctl,
2820 };
2821
2822 static void nvme_set_irq_hints(struct nvme_dev *dev)
2823 {
2824         struct nvme_queue *nvmeq;
2825         int i;
2826
2827         for (i = 0; i < dev->online_queues; i++) {
2828                 nvmeq = dev->queues[i];
2829
2830                 if (!nvmeq->hctx)
2831                         continue;
2832
2833                 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
2834                                                         nvmeq->hctx->cpumask);
2835         }
2836 }
2837
2838 static int nvme_dev_start(struct nvme_dev *dev)
2839 {
2840         int result;
2841         bool start_thread = false;
2842
2843         result = nvme_dev_map(dev);
2844         if (result)
2845                 return result;
2846
2847         result = nvme_configure_admin_queue(dev);
2848         if (result)
2849                 goto unmap;
2850
2851         spin_lock(&dev_list_lock);
2852         if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) {
2853                 start_thread = true;
2854                 nvme_thread = NULL;
2855         }
2856         list_add(&dev->node, &dev_list);
2857         spin_unlock(&dev_list_lock);
2858
2859         if (start_thread) {
2860                 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
2861                 wake_up_all(&nvme_kthread_wait);
2862         } else
2863                 wait_event_killable(nvme_kthread_wait, nvme_thread);
2864
2865         if (IS_ERR_OR_NULL(nvme_thread)) {
2866                 result = nvme_thread ? PTR_ERR(nvme_thread) : -EINTR;
2867                 goto disable;
2868         }
2869
2870         nvme_init_queue(dev->queues[0], 0);
2871         result = nvme_alloc_admin_tags(dev);
2872         if (result)
2873                 goto disable;
2874
2875         result = nvme_setup_io_queues(dev);
2876         if (result)
2877                 goto free_tags;
2878
2879         nvme_set_irq_hints(dev);
2880
2881         dev->event_limit = 1;
2882         return result;
2883
2884  free_tags:
2885         nvme_dev_remove_admin(dev);
2886  disable:
2887         nvme_disable_queue(dev, 0);
2888         nvme_dev_list_remove(dev);
2889  unmap:
2890         nvme_dev_unmap(dev);
2891         return result;
2892 }
2893
2894 static int nvme_remove_dead_ctrl(void *arg)
2895 {
2896         struct nvme_dev *dev = (struct nvme_dev *)arg;
2897         struct pci_dev *pdev = dev->pci_dev;
2898
2899         if (pci_get_drvdata(pdev))
2900                 pci_stop_and_remove_bus_device_locked(pdev);
2901         kref_put(&dev->kref, nvme_free_dev);
2902         return 0;
2903 }
2904
2905 static void nvme_remove_disks(struct work_struct *ws)
2906 {
2907         struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2908
2909         nvme_free_queues(dev, 1);
2910         nvme_dev_remove(dev);
2911 }
2912
2913 static int nvme_dev_resume(struct nvme_dev *dev)
2914 {
2915         int ret;
2916
2917         ret = nvme_dev_start(dev);
2918         if (ret)
2919                 return ret;
2920         if (dev->online_queues < 2) {
2921                 spin_lock(&dev_list_lock);
2922                 dev->reset_workfn = nvme_remove_disks;
2923                 queue_work(nvme_workq, &dev->reset_work);
2924                 spin_unlock(&dev_list_lock);
2925         } else {
2926                 nvme_unfreeze_queues(dev);
2927                 nvme_set_irq_hints(dev);
2928         }
2929         return 0;
2930 }
2931
2932 static void nvme_dev_reset(struct nvme_dev *dev)
2933 {
2934         nvme_dev_shutdown(dev);
2935         if (nvme_dev_resume(dev)) {
2936                 dev_warn(&dev->pci_dev->dev, "Device failed to resume\n");
2937                 kref_get(&dev->kref);
2938                 if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d",
2939                                                         dev->instance))) {
2940                         dev_err(&dev->pci_dev->dev,
2941                                 "Failed to start controller remove task\n");
2942                         kref_put(&dev->kref, nvme_free_dev);
2943                 }
2944         }
2945 }
2946
2947 static void nvme_reset_failed_dev(struct work_struct *ws)
2948 {
2949         struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2950         nvme_dev_reset(dev);
2951 }
2952
2953 static void nvme_reset_workfn(struct work_struct *work)
2954 {
2955         struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
2956         dev->reset_workfn(work);
2957 }
2958
2959 static void nvme_async_probe(struct work_struct *work);
2960 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2961 {
2962         int node, result = -ENOMEM;
2963         struct nvme_dev *dev;
2964
2965         node = dev_to_node(&pdev->dev);
2966         if (node == NUMA_NO_NODE)
2967                 set_dev_node(&pdev->dev, 0);
2968
2969         dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2970         if (!dev)
2971                 return -ENOMEM;
2972         dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry),
2973                                                         GFP_KERNEL, node);
2974         if (!dev->entry)
2975                 goto free;
2976         dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
2977                                                         GFP_KERNEL, node);
2978         if (!dev->queues)
2979                 goto free;
2980
2981         INIT_LIST_HEAD(&dev->namespaces);
2982         dev->reset_workfn = nvme_reset_failed_dev;
2983         INIT_WORK(&dev->reset_work, nvme_reset_workfn);
2984         dev->pci_dev = pci_dev_get(pdev);
2985         pci_set_drvdata(pdev, dev);
2986         result = nvme_set_instance(dev);
2987         if (result)
2988                 goto put_pci;
2989
2990         result = nvme_setup_prp_pools(dev);
2991         if (result)
2992                 goto release;
2993
2994         kref_init(&dev->kref);
2995         dev->device = device_create(nvme_class, &pdev->dev,
2996                                 MKDEV(nvme_char_major, dev->instance),
2997                                 dev, "nvme%d", dev->instance);
2998         if (IS_ERR(dev->device)) {
2999                 result = PTR_ERR(dev->device);
3000                 goto release_pools;
3001         }
3002         get_device(dev->device);
3003
3004         INIT_WORK(&dev->probe_work, nvme_async_probe);
3005         schedule_work(&dev->probe_work);
3006         return 0;
3007
3008  release_pools:
3009         nvme_release_prp_pools(dev);
3010  release:
3011         nvme_release_instance(dev);
3012  put_pci:
3013         pci_dev_put(dev->pci_dev);
3014  free:
3015         kfree(dev->queues);
3016         kfree(dev->entry);
3017         kfree(dev);
3018         return result;
3019 }
3020
3021 static void nvme_async_probe(struct work_struct *work)
3022 {
3023         struct nvme_dev *dev = container_of(work, struct nvme_dev, probe_work);
3024         int result;
3025
3026         result = nvme_dev_start(dev);
3027         if (result)
3028                 goto reset;
3029
3030         if (dev->online_queues > 1)
3031                 result = nvme_dev_add(dev);
3032         if (result)
3033                 goto reset;
3034
3035         nvme_set_irq_hints(dev);
3036         return;
3037  reset:
3038         if (!work_busy(&dev->reset_work)) {
3039                 dev->reset_workfn = nvme_reset_failed_dev;
3040                 queue_work(nvme_workq, &dev->reset_work);
3041         }
3042 }
3043
3044 static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
3045 {
3046         struct nvme_dev *dev = pci_get_drvdata(pdev);
3047
3048         if (prepare)
3049                 nvme_dev_shutdown(dev);
3050         else
3051                 nvme_dev_resume(dev);
3052 }
3053
3054 static void nvme_shutdown(struct pci_dev *pdev)
3055 {
3056         struct nvme_dev *dev = pci_get_drvdata(pdev);
3057         nvme_dev_shutdown(dev);
3058 }
3059
3060 static void nvme_remove(struct pci_dev *pdev)
3061 {
3062         struct nvme_dev *dev = pci_get_drvdata(pdev);
3063
3064         spin_lock(&dev_list_lock);
3065         list_del_init(&dev->node);
3066         spin_unlock(&dev_list_lock);
3067
3068         pci_set_drvdata(pdev, NULL);
3069         flush_work(&dev->probe_work);
3070         flush_work(&dev->reset_work);
3071         nvme_dev_shutdown(dev);
3072         nvme_dev_remove(dev);
3073         nvme_dev_remove_admin(dev);
3074         device_destroy(nvme_class, MKDEV(nvme_char_major, dev->instance));
3075         nvme_free_queues(dev, 0);
3076         nvme_release_prp_pools(dev);
3077         kref_put(&dev->kref, nvme_free_dev);
3078 }
3079
3080 /* These functions are yet to be implemented */
3081 #define nvme_error_detected NULL
3082 #define nvme_dump_registers NULL
3083 #define nvme_link_reset NULL
3084 #define nvme_slot_reset NULL
3085 #define nvme_error_resume NULL
3086
3087 #ifdef CONFIG_PM_SLEEP
3088 static int nvme_suspend(struct device *dev)
3089 {
3090         struct pci_dev *pdev = to_pci_dev(dev);
3091         struct nvme_dev *ndev = pci_get_drvdata(pdev);
3092
3093         nvme_dev_shutdown(ndev);
3094         return 0;
3095 }
3096
3097 static int nvme_resume(struct device *dev)
3098 {
3099         struct pci_dev *pdev = to_pci_dev(dev);
3100         struct nvme_dev *ndev = pci_get_drvdata(pdev);
3101
3102         if (nvme_dev_resume(ndev) && !work_busy(&ndev->reset_work)) {
3103                 ndev->reset_workfn = nvme_reset_failed_dev;
3104                 queue_work(nvme_workq, &ndev->reset_work);
3105         }
3106         return 0;
3107 }
3108 #endif
3109
3110 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
3111
3112 static const struct pci_error_handlers nvme_err_handler = {
3113         .error_detected = nvme_error_detected,
3114         .mmio_enabled   = nvme_dump_registers,
3115         .link_reset     = nvme_link_reset,
3116         .slot_reset     = nvme_slot_reset,
3117         .resume         = nvme_error_resume,
3118         .reset_notify   = nvme_reset_notify,
3119 };
3120
3121 /* Move to pci_ids.h later */
3122 #define PCI_CLASS_STORAGE_EXPRESS       0x010802
3123
3124 static const struct pci_device_id nvme_id_table[] = {
3125         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
3126         { 0, }
3127 };
3128 MODULE_DEVICE_TABLE(pci, nvme_id_table);
3129
3130 static struct pci_driver nvme_driver = {
3131         .name           = "nvme",
3132         .id_table       = nvme_id_table,
3133         .probe          = nvme_probe,
3134         .remove         = nvme_remove,
3135         .shutdown       = nvme_shutdown,
3136         .driver         = {
3137                 .pm     = &nvme_dev_pm_ops,
3138         },
3139         .err_handler    = &nvme_err_handler,
3140 };
3141
3142 static int __init nvme_init(void)
3143 {
3144         int result;
3145
3146         init_waitqueue_head(&nvme_kthread_wait);
3147
3148         nvme_workq = create_singlethread_workqueue("nvme");
3149         if (!nvme_workq)
3150                 return -ENOMEM;
3151
3152         result = register_blkdev(nvme_major, "nvme");
3153         if (result < 0)
3154                 goto kill_workq;
3155         else if (result > 0)
3156                 nvme_major = result;
3157
3158         result = __register_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme",
3159                                                         &nvme_dev_fops);
3160         if (result < 0)
3161                 goto unregister_blkdev;
3162         else if (result > 0)
3163                 nvme_char_major = result;
3164
3165         nvme_class = class_create(THIS_MODULE, "nvme");
3166         if (!nvme_class)
3167                 goto unregister_chrdev;
3168
3169         result = pci_register_driver(&nvme_driver);
3170         if (result)
3171                 goto destroy_class;
3172         return 0;
3173
3174  destroy_class:
3175         class_destroy(nvme_class);
3176  unregister_chrdev:
3177         __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
3178  unregister_blkdev:
3179         unregister_blkdev(nvme_major, "nvme");
3180  kill_workq:
3181         destroy_workqueue(nvme_workq);
3182         return result;
3183 }
3184
3185 static void __exit nvme_exit(void)
3186 {
3187         pci_unregister_driver(&nvme_driver);
3188         unregister_blkdev(nvme_major, "nvme");
3189         destroy_workqueue(nvme_workq);
3190         class_destroy(nvme_class);
3191         __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
3192         BUG_ON(nvme_thread && !IS_ERR(nvme_thread));
3193         _nvme_check_size();
3194 }
3195
3196 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3197 MODULE_LICENSE("GPL");
3198 MODULE_VERSION("1.0");
3199 module_init(nvme_init);
3200 module_exit(nvme_exit);