2 * include/asm-xtensa/timex.h
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
8 * Copyright (C) 2001 - 2008 Tensilica Inc.
11 #ifndef _XTENSA_TIMEX_H
12 #define _XTENSA_TIMEX_H
16 #include <asm/processor.h>
17 #include <linux/stringify.h>
19 #define _INTLEVEL(x) XCHAL_INT ## x ## _LEVEL
20 #define INTLEVEL(x) _INTLEVEL(x)
22 #if XCHAL_NUM_TIMERS > 0 && \
23 INTLEVEL(XCHAL_TIMER0_INTERRUPT) <= XCHAL_EXCM_LEVEL
24 # define LINUX_TIMER 0
25 # define LINUX_TIMER_INT XCHAL_TIMER0_INTERRUPT
26 #elif XCHAL_NUM_TIMERS > 1 && \
27 INTLEVEL(XCHAL_TIMER1_INTERRUPT) <= XCHAL_EXCM_LEVEL
28 # define LINUX_TIMER 1
29 # define LINUX_TIMER_INT XCHAL_TIMER1_INTERRUPT
30 #elif XCHAL_NUM_TIMERS > 2 && \
31 INTLEVEL(XCHAL_TIMER2_INTERRUPT) <= XCHAL_EXCM_LEVEL
32 # define LINUX_TIMER 2
33 # define LINUX_TIMER_INT XCHAL_TIMER2_INTERRUPT
35 # error "Bad timer number for Linux configurations!"
38 #ifdef CONFIG_XTENSA_CALIBRATE_CCOUNT
39 extern unsigned long ccount_per_jiffy;
40 extern unsigned long nsec_per_ccount;
41 #define CCOUNT_PER_JIFFY ccount_per_jiffy
43 #define CCOUNT_PER_JIFFY (CONFIG_XTENSA_CPU_CLOCK*(1000000UL/HZ))
47 typedef unsigned long long cycles_t;
53 extern cycles_t cacheflush_time;
55 #define get_cycles() (0)
62 #define WSR_CCOUNT(r) asm volatile ("wsr %0, ccount" :: "a" (r))
63 #define RSR_CCOUNT(r) asm volatile ("rsr %0, ccount" : "=a" (r))
64 #define WSR_CCOMPARE(x,r) asm volatile ("wsr %0,"__stringify(SREG_CCOMPARE)"+"__stringify(x) :: "a"(r))
65 #define RSR_CCOMPARE(x,r) asm volatile ("rsr %0,"__stringify(SREG_CCOMPARE)"+"__stringify(x) : "=a"(r))
67 static inline unsigned long get_ccount (void)
74 static inline void set_ccount (unsigned long ccount)
79 static inline unsigned long get_linux_timer (void)
82 RSR_CCOMPARE(LINUX_TIMER, ccompare);
86 static inline void set_linux_timer (unsigned long ccompare)
88 WSR_CCOMPARE(LINUX_TIMER, ccompare);
91 #endif /* __KERNEL__ */
92 #endif /* _XTENSA_TIMEX_H */