2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
24 #include "kvm_cache_regs.h"
27 #include <linux/kvm_host.h>
28 #include <linux/types.h>
29 #include <linux/string.h>
31 #include <linux/highmem.h>
32 #include <linux/moduleparam.h>
33 #include <linux/export.h>
34 #include <linux/swap.h>
35 #include <linux/hugetlb.h>
36 #include <linux/compiler.h>
37 #include <linux/srcu.h>
38 #include <linux/slab.h>
39 #include <linux/uaccess.h>
42 #include <asm/cmpxchg.h>
45 #include <asm/kvm_page_track.h>
48 * When setting this variable to true it enables Two-Dimensional-Paging
49 * where the hardware walks 2 page tables:
50 * 1. the guest-virtual to guest-physical
51 * 2. while doing 1. it walks guest-physical to host-physical
52 * If the hardware supports that we don't need to do shadow paging.
54 bool tdp_enabled = false;
58 AUDIT_POST_PAGE_FAULT,
69 module_param(dbg, bool, 0644);
71 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
72 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
73 #define MMU_WARN_ON(x) WARN_ON(x)
75 #define pgprintk(x...) do { } while (0)
76 #define rmap_printk(x...) do { } while (0)
77 #define MMU_WARN_ON(x) do { } while (0)
80 #define PTE_PREFETCH_NUM 8
82 #define PT_FIRST_AVAIL_BITS_SHIFT 10
83 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
85 #define PT64_LEVEL_BITS 9
87 #define PT64_LEVEL_SHIFT(level) \
88 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
90 #define PT64_INDEX(address, level)\
91 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
94 #define PT32_LEVEL_BITS 10
96 #define PT32_LEVEL_SHIFT(level) \
97 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
99 #define PT32_LVL_OFFSET_MASK(level) \
100 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
101 * PT32_LEVEL_BITS))) - 1))
103 #define PT32_INDEX(address, level)\
104 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
107 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
108 #define PT64_DIR_BASE_ADDR_MASK \
109 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
110 #define PT64_LVL_ADDR_MASK(level) \
111 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
112 * PT64_LEVEL_BITS))) - 1))
113 #define PT64_LVL_OFFSET_MASK(level) \
114 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
115 * PT64_LEVEL_BITS))) - 1))
117 #define PT32_BASE_ADDR_MASK PAGE_MASK
118 #define PT32_DIR_BASE_ADDR_MASK \
119 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
120 #define PT32_LVL_ADDR_MASK(level) \
121 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
122 * PT32_LEVEL_BITS))) - 1))
124 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | shadow_user_mask \
125 | shadow_x_mask | shadow_nx_mask)
127 #define ACC_EXEC_MASK 1
128 #define ACC_WRITE_MASK PT_WRITABLE_MASK
129 #define ACC_USER_MASK PT_USER_MASK
130 #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
132 #include <trace/events/kvm.h>
134 #define CREATE_TRACE_POINTS
135 #include "mmutrace.h"
137 #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
138 #define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1))
140 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
142 /* make pte_list_desc fit well in cache line */
143 #define PTE_LIST_EXT 3
145 struct pte_list_desc {
146 u64 *sptes[PTE_LIST_EXT];
147 struct pte_list_desc *more;
150 struct kvm_shadow_walk_iterator {
158 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
159 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
160 shadow_walk_okay(&(_walker)); \
161 shadow_walk_next(&(_walker)))
163 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
164 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
165 shadow_walk_okay(&(_walker)) && \
166 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
167 __shadow_walk_next(&(_walker), spte))
169 static struct kmem_cache *pte_list_desc_cache;
170 static struct kmem_cache *mmu_page_header_cache;
171 static struct percpu_counter kvm_total_used_mmu_pages;
173 static u64 __read_mostly shadow_nx_mask;
174 static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
175 static u64 __read_mostly shadow_user_mask;
176 static u64 __read_mostly shadow_accessed_mask;
177 static u64 __read_mostly shadow_dirty_mask;
178 static u64 __read_mostly shadow_mmio_mask;
180 static void mmu_spte_set(u64 *sptep, u64 spte);
181 static void mmu_free_roots(struct kvm_vcpu *vcpu);
183 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask)
185 shadow_mmio_mask = mmio_mask;
187 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask);
190 * the low bit of the generation number is always presumed to be zero.
191 * This disables mmio caching during memslot updates. The concept is
192 * similar to a seqcount but instead of retrying the access we just punt
193 * and ignore the cache.
195 * spte bits 3-11 are used as bits 1-9 of the generation number,
196 * the bits 52-61 are used as bits 10-19 of the generation number.
198 #define MMIO_SPTE_GEN_LOW_SHIFT 2
199 #define MMIO_SPTE_GEN_HIGH_SHIFT 52
201 #define MMIO_GEN_SHIFT 20
202 #define MMIO_GEN_LOW_SHIFT 10
203 #define MMIO_GEN_LOW_MASK ((1 << MMIO_GEN_LOW_SHIFT) - 2)
204 #define MMIO_GEN_MASK ((1 << MMIO_GEN_SHIFT) - 1)
206 static u64 generation_mmio_spte_mask(unsigned int gen)
210 WARN_ON(gen & ~MMIO_GEN_MASK);
212 mask = (gen & MMIO_GEN_LOW_MASK) << MMIO_SPTE_GEN_LOW_SHIFT;
213 mask |= ((u64)gen >> MMIO_GEN_LOW_SHIFT) << MMIO_SPTE_GEN_HIGH_SHIFT;
217 static unsigned int get_mmio_spte_generation(u64 spte)
221 spte &= ~shadow_mmio_mask;
223 gen = (spte >> MMIO_SPTE_GEN_LOW_SHIFT) & MMIO_GEN_LOW_MASK;
224 gen |= (spte >> MMIO_SPTE_GEN_HIGH_SHIFT) << MMIO_GEN_LOW_SHIFT;
228 static unsigned int kvm_current_mmio_generation(struct kvm_vcpu *vcpu)
230 return kvm_vcpu_memslots(vcpu)->generation & MMIO_GEN_MASK;
233 static void mark_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 gfn,
236 unsigned int gen = kvm_current_mmio_generation(vcpu);
237 u64 mask = generation_mmio_spte_mask(gen);
239 access &= ACC_WRITE_MASK | ACC_USER_MASK;
240 mask |= shadow_mmio_mask | access | gfn << PAGE_SHIFT;
242 trace_mark_mmio_spte(sptep, gfn, access, gen);
243 mmu_spte_set(sptep, mask);
246 static bool is_mmio_spte(u64 spte)
248 return (spte & shadow_mmio_mask) == shadow_mmio_mask;
251 static gfn_t get_mmio_spte_gfn(u64 spte)
253 u64 mask = generation_mmio_spte_mask(MMIO_GEN_MASK) | shadow_mmio_mask;
254 return (spte & ~mask) >> PAGE_SHIFT;
257 static unsigned get_mmio_spte_access(u64 spte)
259 u64 mask = generation_mmio_spte_mask(MMIO_GEN_MASK) | shadow_mmio_mask;
260 return (spte & ~mask) & ~PAGE_MASK;
263 static bool set_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
264 kvm_pfn_t pfn, unsigned access)
266 if (unlikely(is_noslot_pfn(pfn))) {
267 mark_mmio_spte(vcpu, sptep, gfn, access);
274 static bool check_mmio_spte(struct kvm_vcpu *vcpu, u64 spte)
276 unsigned int kvm_gen, spte_gen;
278 kvm_gen = kvm_current_mmio_generation(vcpu);
279 spte_gen = get_mmio_spte_generation(spte);
281 trace_check_mmio_spte(spte, kvm_gen, spte_gen);
282 return likely(kvm_gen == spte_gen);
285 void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
286 u64 dirty_mask, u64 nx_mask, u64 x_mask)
288 shadow_user_mask = user_mask;
289 shadow_accessed_mask = accessed_mask;
290 shadow_dirty_mask = dirty_mask;
291 shadow_nx_mask = nx_mask;
292 shadow_x_mask = x_mask;
294 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
296 static int is_cpuid_PSE36(void)
301 static int is_nx(struct kvm_vcpu *vcpu)
303 return vcpu->arch.efer & EFER_NX;
306 static int is_shadow_present_pte(u64 pte)
308 return pte & PT_PRESENT_MASK && !is_mmio_spte(pte);
311 static int is_large_pte(u64 pte)
313 return pte & PT_PAGE_SIZE_MASK;
316 static int is_last_spte(u64 pte, int level)
318 if (level == PT_PAGE_TABLE_LEVEL)
320 if (is_large_pte(pte))
325 static kvm_pfn_t spte_to_pfn(u64 pte)
327 return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
330 static gfn_t pse36_gfn_delta(u32 gpte)
332 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
334 return (gpte & PT32_DIR_PSE36_MASK) << shift;
338 static void __set_spte(u64 *sptep, u64 spte)
340 WRITE_ONCE(*sptep, spte);
343 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
345 WRITE_ONCE(*sptep, spte);
348 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
350 return xchg(sptep, spte);
353 static u64 __get_spte_lockless(u64 *sptep)
355 return ACCESS_ONCE(*sptep);
366 static void count_spte_clear(u64 *sptep, u64 spte)
368 struct kvm_mmu_page *sp = page_header(__pa(sptep));
370 if (is_shadow_present_pte(spte))
373 /* Ensure the spte is completely set before we increase the count */
375 sp->clear_spte_count++;
378 static void __set_spte(u64 *sptep, u64 spte)
380 union split_spte *ssptep, sspte;
382 ssptep = (union split_spte *)sptep;
383 sspte = (union split_spte)spte;
385 ssptep->spte_high = sspte.spte_high;
388 * If we map the spte from nonpresent to present, We should store
389 * the high bits firstly, then set present bit, so cpu can not
390 * fetch this spte while we are setting the spte.
394 WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
397 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
399 union split_spte *ssptep, sspte;
401 ssptep = (union split_spte *)sptep;
402 sspte = (union split_spte)spte;
404 WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
407 * If we map the spte from present to nonpresent, we should clear
408 * present bit firstly to avoid vcpu fetch the old high bits.
412 ssptep->spte_high = sspte.spte_high;
413 count_spte_clear(sptep, spte);
416 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
418 union split_spte *ssptep, sspte, orig;
420 ssptep = (union split_spte *)sptep;
421 sspte = (union split_spte)spte;
423 /* xchg acts as a barrier before the setting of the high bits */
424 orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
425 orig.spte_high = ssptep->spte_high;
426 ssptep->spte_high = sspte.spte_high;
427 count_spte_clear(sptep, spte);
433 * The idea using the light way get the spte on x86_32 guest is from
434 * gup_get_pte(arch/x86/mm/gup.c).
436 * An spte tlb flush may be pending, because kvm_set_pte_rmapp
437 * coalesces them and we are running out of the MMU lock. Therefore
438 * we need to protect against in-progress updates of the spte.
440 * Reading the spte while an update is in progress may get the old value
441 * for the high part of the spte. The race is fine for a present->non-present
442 * change (because the high part of the spte is ignored for non-present spte),
443 * but for a present->present change we must reread the spte.
445 * All such changes are done in two steps (present->non-present and
446 * non-present->present), hence it is enough to count the number of
447 * present->non-present updates: if it changed while reading the spte,
448 * we might have hit the race. This is done using clear_spte_count.
450 static u64 __get_spte_lockless(u64 *sptep)
452 struct kvm_mmu_page *sp = page_header(__pa(sptep));
453 union split_spte spte, *orig = (union split_spte *)sptep;
457 count = sp->clear_spte_count;
460 spte.spte_low = orig->spte_low;
463 spte.spte_high = orig->spte_high;
466 if (unlikely(spte.spte_low != orig->spte_low ||
467 count != sp->clear_spte_count))
474 static bool spte_is_locklessly_modifiable(u64 spte)
476 return (spte & (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE)) ==
477 (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE);
480 static bool spte_has_volatile_bits(u64 spte)
483 * Always atomically update spte if it can be updated
484 * out of mmu-lock, it can ensure dirty bit is not lost,
485 * also, it can help us to get a stable is_writable_pte()
486 * to ensure tlb flush is not missed.
488 if (spte_is_locklessly_modifiable(spte))
491 if (!shadow_accessed_mask)
494 if (!is_shadow_present_pte(spte))
497 if ((spte & shadow_accessed_mask) &&
498 (!is_writable_pte(spte) || (spte & shadow_dirty_mask)))
504 static bool spte_is_bit_cleared(u64 old_spte, u64 new_spte, u64 bit_mask)
506 return (old_spte & bit_mask) && !(new_spte & bit_mask);
509 static bool spte_is_bit_changed(u64 old_spte, u64 new_spte, u64 bit_mask)
511 return (old_spte & bit_mask) != (new_spte & bit_mask);
514 /* Rules for using mmu_spte_set:
515 * Set the sptep from nonpresent to present.
516 * Note: the sptep being assigned *must* be either not present
517 * or in a state where the hardware will not attempt to update
520 static void mmu_spte_set(u64 *sptep, u64 new_spte)
522 WARN_ON(is_shadow_present_pte(*sptep));
523 __set_spte(sptep, new_spte);
526 /* Rules for using mmu_spte_update:
527 * Update the state bits, it means the mapped pfn is not changged.
529 * Whenever we overwrite a writable spte with a read-only one we
530 * should flush remote TLBs. Otherwise rmap_write_protect
531 * will find a read-only spte, even though the writable spte
532 * might be cached on a CPU's TLB, the return value indicates this
535 static bool mmu_spte_update(u64 *sptep, u64 new_spte)
537 u64 old_spte = *sptep;
540 WARN_ON(!is_shadow_present_pte(new_spte));
542 if (!is_shadow_present_pte(old_spte)) {
543 mmu_spte_set(sptep, new_spte);
547 if (!spte_has_volatile_bits(old_spte))
548 __update_clear_spte_fast(sptep, new_spte);
550 old_spte = __update_clear_spte_slow(sptep, new_spte);
553 * For the spte updated out of mmu-lock is safe, since
554 * we always atomically update it, see the comments in
555 * spte_has_volatile_bits().
557 if (spte_is_locklessly_modifiable(old_spte) &&
558 !is_writable_pte(new_spte))
561 if (!shadow_accessed_mask) {
563 * We don't set page dirty when dropping non-writable spte.
564 * So do it now if the new spte is becoming non-writable.
567 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
572 * Flush TLB when accessed/dirty bits are changed in the page tables,
573 * to guarantee consistency between TLB and page tables.
575 if (spte_is_bit_changed(old_spte, new_spte,
576 shadow_accessed_mask | shadow_dirty_mask))
579 if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask))
580 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
581 if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask))
582 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
588 * Rules for using mmu_spte_clear_track_bits:
589 * It sets the sptep from present to nonpresent, and track the
590 * state bits, it is used to clear the last level sptep.
592 static int mmu_spte_clear_track_bits(u64 *sptep)
595 u64 old_spte = *sptep;
597 if (!spte_has_volatile_bits(old_spte))
598 __update_clear_spte_fast(sptep, 0ull);
600 old_spte = __update_clear_spte_slow(sptep, 0ull);
602 if (!is_shadow_present_pte(old_spte))
605 pfn = spte_to_pfn(old_spte);
608 * KVM does not hold the refcount of the page used by
609 * kvm mmu, before reclaiming the page, we should
610 * unmap it from mmu first.
612 WARN_ON(!kvm_is_reserved_pfn(pfn) && !page_count(pfn_to_page(pfn)));
614 if (!shadow_accessed_mask || old_spte & shadow_accessed_mask)
615 kvm_set_pfn_accessed(pfn);
616 if (old_spte & (shadow_dirty_mask ? shadow_dirty_mask :
618 kvm_set_pfn_dirty(pfn);
623 * Rules for using mmu_spte_clear_no_track:
624 * Directly clear spte without caring the state bits of sptep,
625 * it is used to set the upper level spte.
627 static void mmu_spte_clear_no_track(u64 *sptep)
629 __update_clear_spte_fast(sptep, 0ull);
632 static u64 mmu_spte_get_lockless(u64 *sptep)
634 return __get_spte_lockless(sptep);
637 static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
640 * Prevent page table teardown by making any free-er wait during
641 * kvm_flush_remote_tlbs() IPI to all active vcpus.
646 * Make sure a following spte read is not reordered ahead of the write
649 smp_store_mb(vcpu->mode, READING_SHADOW_PAGE_TABLES);
652 static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
655 * Make sure the write to vcpu->mode is not reordered in front of
656 * reads to sptes. If it does, kvm_commit_zap_page() can see us
657 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
659 smp_store_release(&vcpu->mode, OUTSIDE_GUEST_MODE);
663 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
664 struct kmem_cache *base_cache, int min)
668 if (cache->nobjs >= min)
670 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
671 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
674 cache->objects[cache->nobjs++] = obj;
679 static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache)
684 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc,
685 struct kmem_cache *cache)
688 kmem_cache_free(cache, mc->objects[--mc->nobjs]);
691 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
696 if (cache->nobjs >= min)
698 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
699 page = (void *)__get_free_page(GFP_KERNEL);
702 cache->objects[cache->nobjs++] = page;
707 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
710 free_page((unsigned long)mc->objects[--mc->nobjs]);
713 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
717 r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
718 pte_list_desc_cache, 8 + PTE_PREFETCH_NUM);
721 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
724 r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
725 mmu_page_header_cache, 4);
730 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
732 mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
733 pte_list_desc_cache);
734 mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
735 mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache,
736 mmu_page_header_cache);
739 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc)
744 p = mc->objects[--mc->nobjs];
748 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
750 return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache);
753 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
755 kmem_cache_free(pte_list_desc_cache, pte_list_desc);
758 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
760 if (!sp->role.direct)
761 return sp->gfns[index];
763 return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
766 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
769 BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index));
771 sp->gfns[index] = gfn;
775 * Return the pointer to the large page information for a given gfn,
776 * handling slots that are not large page aligned.
778 static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
779 struct kvm_memory_slot *slot,
784 idx = gfn_to_index(gfn, slot->base_gfn, level);
785 return &slot->arch.lpage_info[level - 2][idx];
788 static void update_gfn_disallow_lpage_count(struct kvm_memory_slot *slot,
789 gfn_t gfn, int count)
791 struct kvm_lpage_info *linfo;
794 for (i = PT_DIRECTORY_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) {
795 linfo = lpage_info_slot(gfn, slot, i);
796 linfo->disallow_lpage += count;
797 WARN_ON(linfo->disallow_lpage < 0);
801 void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
803 update_gfn_disallow_lpage_count(slot, gfn, 1);
806 void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
808 update_gfn_disallow_lpage_count(slot, gfn, -1);
811 static void account_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
813 struct kvm_memslots *slots;
814 struct kvm_memory_slot *slot;
817 kvm->arch.indirect_shadow_pages++;
819 slots = kvm_memslots_for_spte_role(kvm, sp->role);
820 slot = __gfn_to_memslot(slots, gfn);
822 /* the non-leaf shadow pages are keeping readonly. */
823 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
824 return kvm_slot_page_track_add_page(kvm, slot, gfn,
825 KVM_PAGE_TRACK_WRITE);
827 kvm_mmu_gfn_disallow_lpage(slot, gfn);
830 static void unaccount_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
832 struct kvm_memslots *slots;
833 struct kvm_memory_slot *slot;
836 kvm->arch.indirect_shadow_pages--;
838 slots = kvm_memslots_for_spte_role(kvm, sp->role);
839 slot = __gfn_to_memslot(slots, gfn);
840 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
841 return kvm_slot_page_track_remove_page(kvm, slot, gfn,
842 KVM_PAGE_TRACK_WRITE);
844 kvm_mmu_gfn_allow_lpage(slot, gfn);
847 static bool __mmu_gfn_lpage_is_disallowed(gfn_t gfn, int level,
848 struct kvm_memory_slot *slot)
850 struct kvm_lpage_info *linfo;
853 linfo = lpage_info_slot(gfn, slot, level);
854 return !!linfo->disallow_lpage;
860 static bool mmu_gfn_lpage_is_disallowed(struct kvm_vcpu *vcpu, gfn_t gfn,
863 struct kvm_memory_slot *slot;
865 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
866 return __mmu_gfn_lpage_is_disallowed(gfn, level, slot);
869 static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
871 unsigned long page_size;
874 page_size = kvm_host_page_size(kvm, gfn);
876 for (i = PT_PAGE_TABLE_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) {
877 if (page_size >= KVM_HPAGE_SIZE(i))
886 static inline bool memslot_valid_for_gpte(struct kvm_memory_slot *slot,
889 if (!slot || slot->flags & KVM_MEMSLOT_INVALID)
891 if (no_dirty_log && slot->dirty_bitmap)
897 static struct kvm_memory_slot *
898 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
901 struct kvm_memory_slot *slot;
903 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
904 if (!memslot_valid_for_gpte(slot, no_dirty_log))
910 static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn,
911 bool *force_pt_level)
913 int host_level, level, max_level;
914 struct kvm_memory_slot *slot;
916 if (unlikely(*force_pt_level))
917 return PT_PAGE_TABLE_LEVEL;
919 slot = kvm_vcpu_gfn_to_memslot(vcpu, large_gfn);
920 *force_pt_level = !memslot_valid_for_gpte(slot, true);
921 if (unlikely(*force_pt_level))
922 return PT_PAGE_TABLE_LEVEL;
924 host_level = host_mapping_level(vcpu->kvm, large_gfn);
926 if (host_level == PT_PAGE_TABLE_LEVEL)
929 max_level = min(kvm_x86_ops->get_lpage_level(), host_level);
931 for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level)
932 if (__mmu_gfn_lpage_is_disallowed(large_gfn, level, slot))
939 * About rmap_head encoding:
941 * If the bit zero of rmap_head->val is clear, then it points to the only spte
942 * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct
943 * pte_list_desc containing more mappings.
947 * Returns the number of pointers in the rmap chain, not counting the new one.
949 static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
950 struct kvm_rmap_head *rmap_head)
952 struct pte_list_desc *desc;
955 if (!rmap_head->val) {
956 rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte);
957 rmap_head->val = (unsigned long)spte;
958 } else if (!(rmap_head->val & 1)) {
959 rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte);
960 desc = mmu_alloc_pte_list_desc(vcpu);
961 desc->sptes[0] = (u64 *)rmap_head->val;
962 desc->sptes[1] = spte;
963 rmap_head->val = (unsigned long)desc | 1;
966 rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte);
967 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
968 while (desc->sptes[PTE_LIST_EXT-1] && desc->more) {
970 count += PTE_LIST_EXT;
972 if (desc->sptes[PTE_LIST_EXT-1]) {
973 desc->more = mmu_alloc_pte_list_desc(vcpu);
976 for (i = 0; desc->sptes[i]; ++i)
978 desc->sptes[i] = spte;
984 pte_list_desc_remove_entry(struct kvm_rmap_head *rmap_head,
985 struct pte_list_desc *desc, int i,
986 struct pte_list_desc *prev_desc)
990 for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
992 desc->sptes[i] = desc->sptes[j];
993 desc->sptes[j] = NULL;
996 if (!prev_desc && !desc->more)
997 rmap_head->val = (unsigned long)desc->sptes[0];
1000 prev_desc->more = desc->more;
1002 rmap_head->val = (unsigned long)desc->more | 1;
1003 mmu_free_pte_list_desc(desc);
1006 static void pte_list_remove(u64 *spte, struct kvm_rmap_head *rmap_head)
1008 struct pte_list_desc *desc;
1009 struct pte_list_desc *prev_desc;
1012 if (!rmap_head->val) {
1013 printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte);
1015 } else if (!(rmap_head->val & 1)) {
1016 rmap_printk("pte_list_remove: %p 1->0\n", spte);
1017 if ((u64 *)rmap_head->val != spte) {
1018 printk(KERN_ERR "pte_list_remove: %p 1->BUG\n", spte);
1023 rmap_printk("pte_list_remove: %p many->many\n", spte);
1024 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1027 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) {
1028 if (desc->sptes[i] == spte) {
1029 pte_list_desc_remove_entry(rmap_head,
1030 desc, i, prev_desc);
1037 pr_err("pte_list_remove: %p many->many\n", spte);
1042 static struct kvm_rmap_head *__gfn_to_rmap(gfn_t gfn, int level,
1043 struct kvm_memory_slot *slot)
1047 idx = gfn_to_index(gfn, slot->base_gfn, level);
1048 return &slot->arch.rmap[level - PT_PAGE_TABLE_LEVEL][idx];
1051 static struct kvm_rmap_head *gfn_to_rmap(struct kvm *kvm, gfn_t gfn,
1052 struct kvm_mmu_page *sp)
1054 struct kvm_memslots *slots;
1055 struct kvm_memory_slot *slot;
1057 slots = kvm_memslots_for_spte_role(kvm, sp->role);
1058 slot = __gfn_to_memslot(slots, gfn);
1059 return __gfn_to_rmap(gfn, sp->role.level, slot);
1062 static bool rmap_can_add(struct kvm_vcpu *vcpu)
1064 struct kvm_mmu_memory_cache *cache;
1066 cache = &vcpu->arch.mmu_pte_list_desc_cache;
1067 return mmu_memory_cache_free_objects(cache);
1070 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1072 struct kvm_mmu_page *sp;
1073 struct kvm_rmap_head *rmap_head;
1075 sp = page_header(__pa(spte));
1076 kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
1077 rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
1078 return pte_list_add(vcpu, spte, rmap_head);
1081 static void rmap_remove(struct kvm *kvm, u64 *spte)
1083 struct kvm_mmu_page *sp;
1085 struct kvm_rmap_head *rmap_head;
1087 sp = page_header(__pa(spte));
1088 gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
1089 rmap_head = gfn_to_rmap(kvm, gfn, sp);
1090 pte_list_remove(spte, rmap_head);
1094 * Used by the following functions to iterate through the sptes linked by a
1095 * rmap. All fields are private and not assumed to be used outside.
1097 struct rmap_iterator {
1098 /* private fields */
1099 struct pte_list_desc *desc; /* holds the sptep if not NULL */
1100 int pos; /* index of the sptep */
1104 * Iteration must be started by this function. This should also be used after
1105 * removing/dropping sptes from the rmap link because in such cases the
1106 * information in the itererator may not be valid.
1108 * Returns sptep if found, NULL otherwise.
1110 static u64 *rmap_get_first(struct kvm_rmap_head *rmap_head,
1111 struct rmap_iterator *iter)
1115 if (!rmap_head->val)
1118 if (!(rmap_head->val & 1)) {
1120 sptep = (u64 *)rmap_head->val;
1124 iter->desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1126 sptep = iter->desc->sptes[iter->pos];
1128 BUG_ON(!is_shadow_present_pte(*sptep));
1133 * Must be used with a valid iterator: e.g. after rmap_get_first().
1135 * Returns sptep if found, NULL otherwise.
1137 static u64 *rmap_get_next(struct rmap_iterator *iter)
1142 if (iter->pos < PTE_LIST_EXT - 1) {
1144 sptep = iter->desc->sptes[iter->pos];
1149 iter->desc = iter->desc->more;
1153 /* desc->sptes[0] cannot be NULL */
1154 sptep = iter->desc->sptes[iter->pos];
1161 BUG_ON(!is_shadow_present_pte(*sptep));
1165 #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \
1166 for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \
1167 _spte_; _spte_ = rmap_get_next(_iter_))
1169 static void drop_spte(struct kvm *kvm, u64 *sptep)
1171 if (mmu_spte_clear_track_bits(sptep))
1172 rmap_remove(kvm, sptep);
1176 static bool __drop_large_spte(struct kvm *kvm, u64 *sptep)
1178 if (is_large_pte(*sptep)) {
1179 WARN_ON(page_header(__pa(sptep))->role.level ==
1180 PT_PAGE_TABLE_LEVEL);
1181 drop_spte(kvm, sptep);
1189 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1191 if (__drop_large_spte(vcpu->kvm, sptep))
1192 kvm_flush_remote_tlbs(vcpu->kvm);
1196 * Write-protect on the specified @sptep, @pt_protect indicates whether
1197 * spte write-protection is caused by protecting shadow page table.
1199 * Note: write protection is difference between dirty logging and spte
1201 * - for dirty logging, the spte can be set to writable at anytime if
1202 * its dirty bitmap is properly set.
1203 * - for spte protection, the spte can be writable only after unsync-ing
1206 * Return true if tlb need be flushed.
1208 static bool spte_write_protect(struct kvm *kvm, u64 *sptep, bool pt_protect)
1212 if (!is_writable_pte(spte) &&
1213 !(pt_protect && spte_is_locklessly_modifiable(spte)))
1216 rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep);
1219 spte &= ~SPTE_MMU_WRITEABLE;
1220 spte = spte & ~PT_WRITABLE_MASK;
1222 return mmu_spte_update(sptep, spte);
1225 static bool __rmap_write_protect(struct kvm *kvm,
1226 struct kvm_rmap_head *rmap_head,
1230 struct rmap_iterator iter;
1233 for_each_rmap_spte(rmap_head, &iter, sptep)
1234 flush |= spte_write_protect(kvm, sptep, pt_protect);
1239 static bool spte_clear_dirty(struct kvm *kvm, u64 *sptep)
1243 rmap_printk("rmap_clear_dirty: spte %p %llx\n", sptep, *sptep);
1245 spte &= ~shadow_dirty_mask;
1247 return mmu_spte_update(sptep, spte);
1250 static bool __rmap_clear_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1253 struct rmap_iterator iter;
1256 for_each_rmap_spte(rmap_head, &iter, sptep)
1257 flush |= spte_clear_dirty(kvm, sptep);
1262 static bool spte_set_dirty(struct kvm *kvm, u64 *sptep)
1266 rmap_printk("rmap_set_dirty: spte %p %llx\n", sptep, *sptep);
1268 spte |= shadow_dirty_mask;
1270 return mmu_spte_update(sptep, spte);
1273 static bool __rmap_set_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1276 struct rmap_iterator iter;
1279 for_each_rmap_spte(rmap_head, &iter, sptep)
1280 flush |= spte_set_dirty(kvm, sptep);
1286 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1287 * @kvm: kvm instance
1288 * @slot: slot to protect
1289 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1290 * @mask: indicates which pages we should protect
1292 * Used when we do not need to care about huge page mappings: e.g. during dirty
1293 * logging we do not have any such mappings.
1295 static void kvm_mmu_write_protect_pt_masked(struct kvm *kvm,
1296 struct kvm_memory_slot *slot,
1297 gfn_t gfn_offset, unsigned long mask)
1299 struct kvm_rmap_head *rmap_head;
1302 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1303 PT_PAGE_TABLE_LEVEL, slot);
1304 __rmap_write_protect(kvm, rmap_head, false);
1306 /* clear the first set bit */
1312 * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages
1313 * @kvm: kvm instance
1314 * @slot: slot to clear D-bit
1315 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1316 * @mask: indicates which pages we should clear D-bit
1318 * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap.
1320 void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm,
1321 struct kvm_memory_slot *slot,
1322 gfn_t gfn_offset, unsigned long mask)
1324 struct kvm_rmap_head *rmap_head;
1327 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1328 PT_PAGE_TABLE_LEVEL, slot);
1329 __rmap_clear_dirty(kvm, rmap_head);
1331 /* clear the first set bit */
1335 EXPORT_SYMBOL_GPL(kvm_mmu_clear_dirty_pt_masked);
1338 * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected
1341 * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to
1342 * enable dirty logging for them.
1344 * Used when we do not need to care about huge page mappings: e.g. during dirty
1345 * logging we do not have any such mappings.
1347 void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm,
1348 struct kvm_memory_slot *slot,
1349 gfn_t gfn_offset, unsigned long mask)
1351 if (kvm_x86_ops->enable_log_dirty_pt_masked)
1352 kvm_x86_ops->enable_log_dirty_pt_masked(kvm, slot, gfn_offset,
1355 kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask);
1358 bool kvm_mmu_slot_gfn_write_protect(struct kvm *kvm,
1359 struct kvm_memory_slot *slot, u64 gfn)
1361 struct kvm_rmap_head *rmap_head;
1363 bool write_protected = false;
1365 for (i = PT_PAGE_TABLE_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) {
1366 rmap_head = __gfn_to_rmap(gfn, i, slot);
1367 write_protected |= __rmap_write_protect(kvm, rmap_head, true);
1370 return write_protected;
1373 static bool rmap_write_protect(struct kvm_vcpu *vcpu, u64 gfn)
1375 struct kvm_memory_slot *slot;
1377 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1378 return kvm_mmu_slot_gfn_write_protect(vcpu->kvm, slot, gfn);
1381 static bool kvm_zap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1384 struct rmap_iterator iter;
1387 while ((sptep = rmap_get_first(rmap_head, &iter))) {
1388 rmap_printk("%s: spte %p %llx.\n", __func__, sptep, *sptep);
1390 drop_spte(kvm, sptep);
1397 static int kvm_unmap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1398 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1401 return kvm_zap_rmapp(kvm, rmap_head);
1404 static int kvm_set_pte_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1405 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1409 struct rmap_iterator iter;
1412 pte_t *ptep = (pte_t *)data;
1415 WARN_ON(pte_huge(*ptep));
1416 new_pfn = pte_pfn(*ptep);
1419 for_each_rmap_spte(rmap_head, &iter, sptep) {
1420 rmap_printk("kvm_set_pte_rmapp: spte %p %llx gfn %llx (%d)\n",
1421 sptep, *sptep, gfn, level);
1425 if (pte_write(*ptep)) {
1426 drop_spte(kvm, sptep);
1429 new_spte = *sptep & ~PT64_BASE_ADDR_MASK;
1430 new_spte |= (u64)new_pfn << PAGE_SHIFT;
1432 new_spte &= ~PT_WRITABLE_MASK;
1433 new_spte &= ~SPTE_HOST_WRITEABLE;
1434 new_spte &= ~shadow_accessed_mask;
1436 mmu_spte_clear_track_bits(sptep);
1437 mmu_spte_set(sptep, new_spte);
1442 kvm_flush_remote_tlbs(kvm);
1447 struct slot_rmap_walk_iterator {
1449 struct kvm_memory_slot *slot;
1455 /* output fields. */
1457 struct kvm_rmap_head *rmap;
1460 /* private field. */
1461 struct kvm_rmap_head *end_rmap;
1465 rmap_walk_init_level(struct slot_rmap_walk_iterator *iterator, int level)
1467 iterator->level = level;
1468 iterator->gfn = iterator->start_gfn;
1469 iterator->rmap = __gfn_to_rmap(iterator->gfn, level, iterator->slot);
1470 iterator->end_rmap = __gfn_to_rmap(iterator->end_gfn, level,
1475 slot_rmap_walk_init(struct slot_rmap_walk_iterator *iterator,
1476 struct kvm_memory_slot *slot, int start_level,
1477 int end_level, gfn_t start_gfn, gfn_t end_gfn)
1479 iterator->slot = slot;
1480 iterator->start_level = start_level;
1481 iterator->end_level = end_level;
1482 iterator->start_gfn = start_gfn;
1483 iterator->end_gfn = end_gfn;
1485 rmap_walk_init_level(iterator, iterator->start_level);
1488 static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator *iterator)
1490 return !!iterator->rmap;
1493 static void slot_rmap_walk_next(struct slot_rmap_walk_iterator *iterator)
1495 if (++iterator->rmap <= iterator->end_rmap) {
1496 iterator->gfn += (1UL << KVM_HPAGE_GFN_SHIFT(iterator->level));
1500 if (++iterator->level > iterator->end_level) {
1501 iterator->rmap = NULL;
1505 rmap_walk_init_level(iterator, iterator->level);
1508 #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \
1509 _start_gfn, _end_gfn, _iter_) \
1510 for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \
1511 _end_level_, _start_gfn, _end_gfn); \
1512 slot_rmap_walk_okay(_iter_); \
1513 slot_rmap_walk_next(_iter_))
1515 static int kvm_handle_hva_range(struct kvm *kvm,
1516 unsigned long start,
1519 int (*handler)(struct kvm *kvm,
1520 struct kvm_rmap_head *rmap_head,
1521 struct kvm_memory_slot *slot,
1524 unsigned long data))
1526 struct kvm_memslots *slots;
1527 struct kvm_memory_slot *memslot;
1528 struct slot_rmap_walk_iterator iterator;
1532 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1533 slots = __kvm_memslots(kvm, i);
1534 kvm_for_each_memslot(memslot, slots) {
1535 unsigned long hva_start, hva_end;
1536 gfn_t gfn_start, gfn_end;
1538 hva_start = max(start, memslot->userspace_addr);
1539 hva_end = min(end, memslot->userspace_addr +
1540 (memslot->npages << PAGE_SHIFT));
1541 if (hva_start >= hva_end)
1544 * {gfn(page) | page intersects with [hva_start, hva_end)} =
1545 * {gfn_start, gfn_start+1, ..., gfn_end-1}.
1547 gfn_start = hva_to_gfn_memslot(hva_start, memslot);
1548 gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot);
1550 for_each_slot_rmap_range(memslot, PT_PAGE_TABLE_LEVEL,
1551 PT_MAX_HUGEPAGE_LEVEL,
1552 gfn_start, gfn_end - 1,
1554 ret |= handler(kvm, iterator.rmap, memslot,
1555 iterator.gfn, iterator.level, data);
1562 static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
1564 int (*handler)(struct kvm *kvm,
1565 struct kvm_rmap_head *rmap_head,
1566 struct kvm_memory_slot *slot,
1567 gfn_t gfn, int level,
1568 unsigned long data))
1570 return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler);
1573 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
1575 return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp);
1578 int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end)
1580 return kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp);
1583 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
1585 kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
1588 static int kvm_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1589 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1593 struct rmap_iterator uninitialized_var(iter);
1596 BUG_ON(!shadow_accessed_mask);
1598 for_each_rmap_spte(rmap_head, &iter, sptep) {
1599 if (*sptep & shadow_accessed_mask) {
1601 clear_bit((ffs(shadow_accessed_mask) - 1),
1602 (unsigned long *)sptep);
1606 trace_kvm_age_page(gfn, level, slot, young);
1610 static int kvm_test_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1611 struct kvm_memory_slot *slot, gfn_t gfn,
1612 int level, unsigned long data)
1615 struct rmap_iterator iter;
1619 * If there's no access bit in the secondary pte set by the
1620 * hardware it's up to gup-fast/gup to set the access bit in
1621 * the primary pte or in the page structure.
1623 if (!shadow_accessed_mask)
1626 for_each_rmap_spte(rmap_head, &iter, sptep) {
1627 if (*sptep & shadow_accessed_mask) {
1636 #define RMAP_RECYCLE_THRESHOLD 1000
1638 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1640 struct kvm_rmap_head *rmap_head;
1641 struct kvm_mmu_page *sp;
1643 sp = page_header(__pa(spte));
1645 rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
1647 kvm_unmap_rmapp(vcpu->kvm, rmap_head, NULL, gfn, sp->role.level, 0);
1648 kvm_flush_remote_tlbs(vcpu->kvm);
1651 int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end)
1654 * In case of absence of EPT Access and Dirty Bits supports,
1655 * emulate the accessed bit for EPT, by checking if this page has
1656 * an EPT mapping, and clearing it if it does. On the next access,
1657 * a new EPT mapping will be established.
1658 * This has some overhead, but not as much as the cost of swapping
1659 * out actively used pages or breaking up actively used hugepages.
1661 if (!shadow_accessed_mask) {
1663 * We are holding the kvm->mmu_lock, and we are blowing up
1664 * shadow PTEs. MMU notifier consumers need to be kept at bay.
1665 * This is correct as long as we don't decouple the mmu_lock
1666 * protected regions (like invalidate_range_start|end does).
1668 kvm->mmu_notifier_seq++;
1669 return kvm_handle_hva_range(kvm, start, end, 0,
1673 return kvm_handle_hva_range(kvm, start, end, 0, kvm_age_rmapp);
1676 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
1678 return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp);
1682 static int is_empty_shadow_page(u64 *spt)
1687 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
1688 if (is_shadow_present_pte(*pos)) {
1689 printk(KERN_ERR "%s: %p %llx\n", __func__,
1698 * This value is the sum of all of the kvm instances's
1699 * kvm->arch.n_used_mmu_pages values. We need a global,
1700 * aggregate version in order to make the slab shrinker
1703 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr)
1705 kvm->arch.n_used_mmu_pages += nr;
1706 percpu_counter_add(&kvm_total_used_mmu_pages, nr);
1709 static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
1711 MMU_WARN_ON(!is_empty_shadow_page(sp->spt));
1712 hlist_del(&sp->hash_link);
1713 list_del(&sp->link);
1714 free_page((unsigned long)sp->spt);
1715 if (!sp->role.direct)
1716 free_page((unsigned long)sp->gfns);
1717 kmem_cache_free(mmu_page_header_cache, sp);
1720 static unsigned kvm_page_table_hashfn(gfn_t gfn)
1722 return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1);
1725 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
1726 struct kvm_mmu_page *sp, u64 *parent_pte)
1731 pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
1734 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
1737 pte_list_remove(parent_pte, &sp->parent_ptes);
1740 static void drop_parent_pte(struct kvm_mmu_page *sp,
1743 mmu_page_remove_parent_pte(sp, parent_pte);
1744 mmu_spte_clear_no_track(parent_pte);
1747 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, int direct)
1749 struct kvm_mmu_page *sp;
1751 sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache);
1752 sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
1754 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
1755 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
1758 * The active_mmu_pages list is the FIFO list, do not move the
1759 * page until it is zapped. kvm_zap_obsolete_pages depends on
1760 * this feature. See the comments in kvm_zap_obsolete_pages().
1762 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
1763 kvm_mod_used_mmu_pages(vcpu->kvm, +1);
1767 static void mark_unsync(u64 *spte);
1768 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
1771 struct rmap_iterator iter;
1773 for_each_rmap_spte(&sp->parent_ptes, &iter, sptep) {
1778 static void mark_unsync(u64 *spte)
1780 struct kvm_mmu_page *sp;
1783 sp = page_header(__pa(spte));
1784 index = spte - sp->spt;
1785 if (__test_and_set_bit(index, sp->unsync_child_bitmap))
1787 if (sp->unsync_children++)
1789 kvm_mmu_mark_parents_unsync(sp);
1792 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1793 struct kvm_mmu_page *sp)
1798 static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
1802 static void nonpaging_update_pte(struct kvm_vcpu *vcpu,
1803 struct kvm_mmu_page *sp, u64 *spte,
1809 #define KVM_PAGE_ARRAY_NR 16
1811 struct kvm_mmu_pages {
1812 struct mmu_page_and_offset {
1813 struct kvm_mmu_page *sp;
1815 } page[KVM_PAGE_ARRAY_NR];
1819 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1825 for (i=0; i < pvec->nr; i++)
1826 if (pvec->page[i].sp == sp)
1829 pvec->page[pvec->nr].sp = sp;
1830 pvec->page[pvec->nr].idx = idx;
1832 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1835 static inline void clear_unsync_child_bit(struct kvm_mmu_page *sp, int idx)
1837 --sp->unsync_children;
1838 WARN_ON((int)sp->unsync_children < 0);
1839 __clear_bit(idx, sp->unsync_child_bitmap);
1842 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1843 struct kvm_mmu_pages *pvec)
1845 int i, ret, nr_unsync_leaf = 0;
1847 for_each_set_bit(i, sp->unsync_child_bitmap, 512) {
1848 struct kvm_mmu_page *child;
1849 u64 ent = sp->spt[i];
1851 if (!is_shadow_present_pte(ent) || is_large_pte(ent)) {
1852 clear_unsync_child_bit(sp, i);
1856 child = page_header(ent & PT64_BASE_ADDR_MASK);
1858 if (child->unsync_children) {
1859 if (mmu_pages_add(pvec, child, i))
1862 ret = __mmu_unsync_walk(child, pvec);
1864 clear_unsync_child_bit(sp, i);
1866 } else if (ret > 0) {
1867 nr_unsync_leaf += ret;
1870 } else if (child->unsync) {
1872 if (mmu_pages_add(pvec, child, i))
1875 clear_unsync_child_bit(sp, i);
1878 return nr_unsync_leaf;
1881 #define INVALID_INDEX (-1)
1883 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1884 struct kvm_mmu_pages *pvec)
1887 if (!sp->unsync_children)
1890 mmu_pages_add(pvec, sp, INVALID_INDEX);
1891 return __mmu_unsync_walk(sp, pvec);
1894 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1896 WARN_ON(!sp->unsync);
1897 trace_kvm_mmu_sync_page(sp);
1899 --kvm->stat.mmu_unsync;
1902 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1903 struct list_head *invalid_list);
1904 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1905 struct list_head *invalid_list);
1908 * NOTE: we should pay more attention on the zapped-obsolete page
1909 * (is_obsolete_sp(sp) && sp->role.invalid) when you do hash list walk
1910 * since it has been deleted from active_mmu_pages but still can be found
1913 * for_each_gfn_valid_sp() has skipped that kind of pages.
1915 #define for_each_gfn_valid_sp(_kvm, _sp, _gfn) \
1916 hlist_for_each_entry(_sp, \
1917 &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)], hash_link) \
1918 if ((_sp)->gfn != (_gfn) || is_obsolete_sp((_kvm), (_sp)) \
1919 || (_sp)->role.invalid) {} else
1921 #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \
1922 for_each_gfn_valid_sp(_kvm, _sp, _gfn) \
1923 if ((_sp)->role.direct) {} else
1925 /* @sp->gfn should be write-protected at the call site */
1926 static bool __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1927 struct list_head *invalid_list)
1929 if (sp->role.cr4_pae != !!is_pae(vcpu)) {
1930 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1934 if (vcpu->arch.mmu.sync_page(vcpu, sp) == 0) {
1935 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1942 static void kvm_mmu_flush_or_zap(struct kvm_vcpu *vcpu,
1943 struct list_head *invalid_list,
1944 bool remote_flush, bool local_flush)
1946 if (!list_empty(invalid_list)) {
1947 kvm_mmu_commit_zap_page(vcpu->kvm, invalid_list);
1952 kvm_flush_remote_tlbs(vcpu->kvm);
1953 else if (local_flush)
1954 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1957 #ifdef CONFIG_KVM_MMU_AUDIT
1958 #include "mmu_audit.c"
1960 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { }
1961 static void mmu_audit_disable(void) { }
1964 static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp)
1966 return unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen);
1969 static bool kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1970 struct list_head *invalid_list)
1972 kvm_unlink_unsync_page(vcpu->kvm, sp);
1973 return __kvm_sync_page(vcpu, sp, invalid_list);
1976 /* @gfn should be write-protected at the call site */
1977 static bool kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn,
1978 struct list_head *invalid_list)
1980 struct kvm_mmu_page *s;
1983 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
1987 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
1988 ret |= kvm_sync_page(vcpu, s, invalid_list);
1994 struct mmu_page_path {
1995 struct kvm_mmu_page *parent[PT64_ROOT_LEVEL];
1996 unsigned int idx[PT64_ROOT_LEVEL];
1999 #define for_each_sp(pvec, sp, parents, i) \
2000 for (i = mmu_pages_first(&pvec, &parents); \
2001 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
2002 i = mmu_pages_next(&pvec, &parents, i))
2004 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
2005 struct mmu_page_path *parents,
2010 for (n = i+1; n < pvec->nr; n++) {
2011 struct kvm_mmu_page *sp = pvec->page[n].sp;
2012 unsigned idx = pvec->page[n].idx;
2013 int level = sp->role.level;
2015 parents->idx[level-1] = idx;
2016 if (level == PT_PAGE_TABLE_LEVEL)
2019 parents->parent[level-2] = sp;
2025 static int mmu_pages_first(struct kvm_mmu_pages *pvec,
2026 struct mmu_page_path *parents)
2028 struct kvm_mmu_page *sp;
2034 WARN_ON(pvec->page[0].idx != INVALID_INDEX);
2036 sp = pvec->page[0].sp;
2037 level = sp->role.level;
2038 WARN_ON(level == PT_PAGE_TABLE_LEVEL);
2040 parents->parent[level-2] = sp;
2042 /* Also set up a sentinel. Further entries in pvec are all
2043 * children of sp, so this element is never overwritten.
2045 parents->parent[level-1] = NULL;
2046 return mmu_pages_next(pvec, parents, 0);
2049 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
2051 struct kvm_mmu_page *sp;
2052 unsigned int level = 0;
2055 unsigned int idx = parents->idx[level];
2056 sp = parents->parent[level];
2060 WARN_ON(idx == INVALID_INDEX);
2061 clear_unsync_child_bit(sp, idx);
2063 } while (!sp->unsync_children);
2066 static void mmu_sync_children(struct kvm_vcpu *vcpu,
2067 struct kvm_mmu_page *parent)
2070 struct kvm_mmu_page *sp;
2071 struct mmu_page_path parents;
2072 struct kvm_mmu_pages pages;
2073 LIST_HEAD(invalid_list);
2076 while (mmu_unsync_walk(parent, &pages)) {
2077 bool protected = false;
2079 for_each_sp(pages, sp, parents, i)
2080 protected |= rmap_write_protect(vcpu, sp->gfn);
2083 kvm_flush_remote_tlbs(vcpu->kvm);
2087 for_each_sp(pages, sp, parents, i) {
2088 flush |= kvm_sync_page(vcpu, sp, &invalid_list);
2089 mmu_pages_clear_parents(&parents);
2091 if (need_resched() || spin_needbreak(&vcpu->kvm->mmu_lock)) {
2092 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2093 cond_resched_lock(&vcpu->kvm->mmu_lock);
2098 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2101 static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp)
2103 atomic_set(&sp->write_flooding_count, 0);
2106 static void clear_sp_write_flooding_count(u64 *spte)
2108 struct kvm_mmu_page *sp = page_header(__pa(spte));
2110 __clear_sp_write_flooding_count(sp);
2113 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
2120 union kvm_mmu_page_role role;
2122 struct kvm_mmu_page *sp;
2123 bool need_sync = false;
2125 LIST_HEAD(invalid_list);
2127 role = vcpu->arch.mmu.base_role;
2129 role.direct = direct;
2132 role.access = access;
2133 if (!vcpu->arch.mmu.direct_map
2134 && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
2135 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
2136 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
2137 role.quadrant = quadrant;
2139 for_each_gfn_valid_sp(vcpu->kvm, sp, gfn) {
2140 if (!need_sync && sp->unsync)
2143 if (sp->role.word != role.word)
2147 /* The page is good, but __kvm_sync_page might still end
2148 * up zapping it. If so, break in order to rebuild it.
2150 if (!__kvm_sync_page(vcpu, sp, &invalid_list))
2153 WARN_ON(!list_empty(&invalid_list));
2154 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2157 if (sp->unsync_children)
2158 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
2160 __clear_sp_write_flooding_count(sp);
2161 trace_kvm_mmu_get_page(sp, false);
2165 ++vcpu->kvm->stat.mmu_cache_miss;
2167 sp = kvm_mmu_alloc_page(vcpu, direct);
2171 hlist_add_head(&sp->hash_link,
2172 &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]);
2175 * we should do write protection before syncing pages
2176 * otherwise the content of the synced shadow page may
2177 * be inconsistent with guest page table.
2179 account_shadowed(vcpu->kvm, sp);
2180 if (level == PT_PAGE_TABLE_LEVEL &&
2181 rmap_write_protect(vcpu, gfn))
2182 kvm_flush_remote_tlbs(vcpu->kvm);
2184 if (level > PT_PAGE_TABLE_LEVEL && need_sync)
2185 flush |= kvm_sync_pages(vcpu, gfn, &invalid_list);
2187 sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen;
2188 clear_page(sp->spt);
2189 trace_kvm_mmu_get_page(sp, true);
2191 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2195 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
2196 struct kvm_vcpu *vcpu, u64 addr)
2198 iterator->addr = addr;
2199 iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
2200 iterator->level = vcpu->arch.mmu.shadow_root_level;
2202 if (iterator->level == PT64_ROOT_LEVEL &&
2203 vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL &&
2204 !vcpu->arch.mmu.direct_map)
2207 if (iterator->level == PT32E_ROOT_LEVEL) {
2208 iterator->shadow_addr
2209 = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
2210 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
2212 if (!iterator->shadow_addr)
2213 iterator->level = 0;
2217 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
2219 if (iterator->level < PT_PAGE_TABLE_LEVEL)
2222 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
2223 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
2227 static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
2230 if (is_last_spte(spte, iterator->level)) {
2231 iterator->level = 0;
2235 iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
2239 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
2241 return __shadow_walk_next(iterator, *iterator->sptep);
2244 static void link_shadow_page(struct kvm_vcpu *vcpu, u64 *sptep,
2245 struct kvm_mmu_page *sp)
2249 BUILD_BUG_ON(VMX_EPT_READABLE_MASK != PT_PRESENT_MASK ||
2250 VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK);
2252 spte = __pa(sp->spt) | PT_PRESENT_MASK | PT_WRITABLE_MASK |
2253 shadow_user_mask | shadow_x_mask | shadow_accessed_mask;
2255 mmu_spte_set(sptep, spte);
2257 mmu_page_add_parent_pte(vcpu, sp, sptep);
2259 if (sp->unsync_children || sp->unsync)
2263 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2264 unsigned direct_access)
2266 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
2267 struct kvm_mmu_page *child;
2270 * For the direct sp, if the guest pte's dirty bit
2271 * changed form clean to dirty, it will corrupt the
2272 * sp's access: allow writable in the read-only sp,
2273 * so we should update the spte at this point to get
2274 * a new sp with the correct access.
2276 child = page_header(*sptep & PT64_BASE_ADDR_MASK);
2277 if (child->role.access == direct_access)
2280 drop_parent_pte(child, sptep);
2281 kvm_flush_remote_tlbs(vcpu->kvm);
2285 static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
2289 struct kvm_mmu_page *child;
2292 if (is_shadow_present_pte(pte)) {
2293 if (is_last_spte(pte, sp->role.level)) {
2294 drop_spte(kvm, spte);
2295 if (is_large_pte(pte))
2298 child = page_header(pte & PT64_BASE_ADDR_MASK);
2299 drop_parent_pte(child, spte);
2304 if (is_mmio_spte(pte))
2305 mmu_spte_clear_no_track(spte);
2310 static void kvm_mmu_page_unlink_children(struct kvm *kvm,
2311 struct kvm_mmu_page *sp)
2315 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2316 mmu_page_zap_pte(kvm, sp, sp->spt + i);
2319 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
2322 struct rmap_iterator iter;
2324 while ((sptep = rmap_get_first(&sp->parent_ptes, &iter)))
2325 drop_parent_pte(sp, sptep);
2328 static int mmu_zap_unsync_children(struct kvm *kvm,
2329 struct kvm_mmu_page *parent,
2330 struct list_head *invalid_list)
2333 struct mmu_page_path parents;
2334 struct kvm_mmu_pages pages;
2336 if (parent->role.level == PT_PAGE_TABLE_LEVEL)
2339 while (mmu_unsync_walk(parent, &pages)) {
2340 struct kvm_mmu_page *sp;
2342 for_each_sp(pages, sp, parents, i) {
2343 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2344 mmu_pages_clear_parents(&parents);
2352 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2353 struct list_head *invalid_list)
2357 trace_kvm_mmu_prepare_zap_page(sp);
2358 ++kvm->stat.mmu_shadow_zapped;
2359 ret = mmu_zap_unsync_children(kvm, sp, invalid_list);
2360 kvm_mmu_page_unlink_children(kvm, sp);
2361 kvm_mmu_unlink_parents(kvm, sp);
2363 if (!sp->role.invalid && !sp->role.direct)
2364 unaccount_shadowed(kvm, sp);
2367 kvm_unlink_unsync_page(kvm, sp);
2368 if (!sp->root_count) {
2371 list_move(&sp->link, invalid_list);
2372 kvm_mod_used_mmu_pages(kvm, -1);
2374 list_move(&sp->link, &kvm->arch.active_mmu_pages);
2377 * The obsolete pages can not be used on any vcpus.
2378 * See the comments in kvm_mmu_invalidate_zap_all_pages().
2380 if (!sp->role.invalid && !is_obsolete_sp(kvm, sp))
2381 kvm_reload_remote_mmus(kvm);
2384 sp->role.invalid = 1;
2388 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2389 struct list_head *invalid_list)
2391 struct kvm_mmu_page *sp, *nsp;
2393 if (list_empty(invalid_list))
2397 * We need to make sure everyone sees our modifications to
2398 * the page tables and see changes to vcpu->mode here. The barrier
2399 * in the kvm_flush_remote_tlbs() achieves this. This pairs
2400 * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end.
2402 * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit
2403 * guest mode and/or lockless shadow page table walks.
2405 kvm_flush_remote_tlbs(kvm);
2407 list_for_each_entry_safe(sp, nsp, invalid_list, link) {
2408 WARN_ON(!sp->role.invalid || sp->root_count);
2409 kvm_mmu_free_page(sp);
2413 static bool prepare_zap_oldest_mmu_page(struct kvm *kvm,
2414 struct list_head *invalid_list)
2416 struct kvm_mmu_page *sp;
2418 if (list_empty(&kvm->arch.active_mmu_pages))
2421 sp = list_last_entry(&kvm->arch.active_mmu_pages,
2422 struct kvm_mmu_page, link);
2423 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2429 * Changing the number of mmu pages allocated to the vm
2430 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2432 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages)
2434 LIST_HEAD(invalid_list);
2436 spin_lock(&kvm->mmu_lock);
2438 if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
2439 /* Need to free some mmu pages to achieve the goal. */
2440 while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages)
2441 if (!prepare_zap_oldest_mmu_page(kvm, &invalid_list))
2444 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2445 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
2448 kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
2450 spin_unlock(&kvm->mmu_lock);
2453 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
2455 struct kvm_mmu_page *sp;
2456 LIST_HEAD(invalid_list);
2459 pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
2461 spin_lock(&kvm->mmu_lock);
2462 for_each_gfn_indirect_valid_sp(kvm, sp, gfn) {
2463 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
2466 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2468 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2469 spin_unlock(&kvm->mmu_lock);
2473 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page);
2475 static void kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
2477 trace_kvm_mmu_unsync_page(sp);
2478 ++vcpu->kvm->stat.mmu_unsync;
2481 kvm_mmu_mark_parents_unsync(sp);
2484 static bool mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
2487 struct kvm_mmu_page *sp;
2489 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
2492 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
2499 WARN_ON(sp->role.level != PT_PAGE_TABLE_LEVEL);
2500 kvm_unsync_page(vcpu, sp);
2506 static bool kvm_is_mmio_pfn(kvm_pfn_t pfn)
2509 return !is_zero_pfn(pfn) && PageReserved(pfn_to_page(pfn));
2514 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2515 unsigned pte_access, int level,
2516 gfn_t gfn, kvm_pfn_t pfn, bool speculative,
2517 bool can_unsync, bool host_writable)
2522 if (set_mmio_spte(vcpu, sptep, gfn, pfn, pte_access))
2525 spte = PT_PRESENT_MASK;
2527 spte |= shadow_accessed_mask;
2529 if (pte_access & ACC_EXEC_MASK)
2530 spte |= shadow_x_mask;
2532 spte |= shadow_nx_mask;
2534 if (pte_access & ACC_USER_MASK)
2535 spte |= shadow_user_mask;
2537 if (level > PT_PAGE_TABLE_LEVEL)
2538 spte |= PT_PAGE_SIZE_MASK;
2540 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
2541 kvm_is_mmio_pfn(pfn));
2544 spte |= SPTE_HOST_WRITEABLE;
2546 pte_access &= ~ACC_WRITE_MASK;
2548 spte |= (u64)pfn << PAGE_SHIFT;
2550 if (pte_access & ACC_WRITE_MASK) {
2553 * Other vcpu creates new sp in the window between
2554 * mapping_level() and acquiring mmu-lock. We can
2555 * allow guest to retry the access, the mapping can
2556 * be fixed if guest refault.
2558 if (level > PT_PAGE_TABLE_LEVEL &&
2559 mmu_gfn_lpage_is_disallowed(vcpu, gfn, level))
2562 spte |= PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE;
2565 * Optimization: for pte sync, if spte was writable the hash
2566 * lookup is unnecessary (and expensive). Write protection
2567 * is responsibility of mmu_get_page / kvm_sync_page.
2568 * Same reasoning can be applied to dirty page accounting.
2570 if (!can_unsync && is_writable_pte(*sptep))
2573 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
2574 pgprintk("%s: found shadow page for %llx, marking ro\n",
2577 pte_access &= ~ACC_WRITE_MASK;
2578 spte &= ~(PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE);
2582 if (pte_access & ACC_WRITE_MASK) {
2583 kvm_vcpu_mark_page_dirty(vcpu, gfn);
2584 spte |= shadow_dirty_mask;
2588 if (mmu_spte_update(sptep, spte))
2589 kvm_flush_remote_tlbs(vcpu->kvm);
2594 static bool mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, unsigned pte_access,
2595 int write_fault, int level, gfn_t gfn, kvm_pfn_t pfn,
2596 bool speculative, bool host_writable)
2598 int was_rmapped = 0;
2600 bool emulate = false;
2602 pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__,
2603 *sptep, write_fault, gfn);
2605 if (is_shadow_present_pte(*sptep)) {
2607 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2608 * the parent of the now unreachable PTE.
2610 if (level > PT_PAGE_TABLE_LEVEL &&
2611 !is_large_pte(*sptep)) {
2612 struct kvm_mmu_page *child;
2615 child = page_header(pte & PT64_BASE_ADDR_MASK);
2616 drop_parent_pte(child, sptep);
2617 kvm_flush_remote_tlbs(vcpu->kvm);
2618 } else if (pfn != spte_to_pfn(*sptep)) {
2619 pgprintk("hfn old %llx new %llx\n",
2620 spte_to_pfn(*sptep), pfn);
2621 drop_spte(vcpu->kvm, sptep);
2622 kvm_flush_remote_tlbs(vcpu->kvm);
2627 if (set_spte(vcpu, sptep, pte_access, level, gfn, pfn, speculative,
2628 true, host_writable)) {
2631 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2634 if (unlikely(is_mmio_spte(*sptep)))
2637 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
2638 pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n",
2639 is_large_pte(*sptep)? "2MB" : "4kB",
2640 *sptep & PT_PRESENT_MASK ?"RW":"R", gfn,
2642 if (!was_rmapped && is_large_pte(*sptep))
2643 ++vcpu->kvm->stat.lpages;
2645 if (is_shadow_present_pte(*sptep)) {
2647 rmap_count = rmap_add(vcpu, sptep, gfn);
2648 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
2649 rmap_recycle(vcpu, sptep, gfn);
2653 kvm_release_pfn_clean(pfn);
2658 static kvm_pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
2661 struct kvm_memory_slot *slot;
2663 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
2665 return KVM_PFN_ERR_FAULT;
2667 return gfn_to_pfn_memslot_atomic(slot, gfn);
2670 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
2671 struct kvm_mmu_page *sp,
2672 u64 *start, u64 *end)
2674 struct page *pages[PTE_PREFETCH_NUM];
2675 struct kvm_memory_slot *slot;
2676 unsigned access = sp->role.access;
2680 gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
2681 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK);
2685 ret = gfn_to_page_many_atomic(slot, gfn, pages, end - start);
2689 for (i = 0; i < ret; i++, gfn++, start++)
2690 mmu_set_spte(vcpu, start, access, 0, sp->role.level, gfn,
2691 page_to_pfn(pages[i]), true, true);
2696 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
2697 struct kvm_mmu_page *sp, u64 *sptep)
2699 u64 *spte, *start = NULL;
2702 WARN_ON(!sp->role.direct);
2704 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
2707 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
2708 if (is_shadow_present_pte(*spte) || spte == sptep) {
2711 if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
2719 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
2721 struct kvm_mmu_page *sp;
2724 * Since it's no accessed bit on EPT, it's no way to
2725 * distinguish between actually accessed translations
2726 * and prefetched, so disable pte prefetch if EPT is
2729 if (!shadow_accessed_mask)
2732 sp = page_header(__pa(sptep));
2733 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
2736 __direct_pte_prefetch(vcpu, sp, sptep);
2739 static int __direct_map(struct kvm_vcpu *vcpu, int write, int map_writable,
2740 int level, gfn_t gfn, kvm_pfn_t pfn, bool prefault)
2742 struct kvm_shadow_walk_iterator iterator;
2743 struct kvm_mmu_page *sp;
2747 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2750 for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
2751 if (iterator.level == level) {
2752 emulate = mmu_set_spte(vcpu, iterator.sptep, ACC_ALL,
2753 write, level, gfn, pfn, prefault,
2755 direct_pte_prefetch(vcpu, iterator.sptep);
2756 ++vcpu->stat.pf_fixed;
2760 drop_large_spte(vcpu, iterator.sptep);
2761 if (!is_shadow_present_pte(*iterator.sptep)) {
2762 u64 base_addr = iterator.addr;
2764 base_addr &= PT64_LVL_ADDR_MASK(iterator.level);
2765 pseudo_gfn = base_addr >> PAGE_SHIFT;
2766 sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
2767 iterator.level - 1, 1, ACC_ALL);
2769 link_shadow_page(vcpu, iterator.sptep, sp);
2775 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
2779 info.si_signo = SIGBUS;
2781 info.si_code = BUS_MCEERR_AR;
2782 info.si_addr = (void __user *)address;
2783 info.si_addr_lsb = PAGE_SHIFT;
2785 send_sig_info(SIGBUS, &info, tsk);
2788 static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, kvm_pfn_t pfn)
2791 * Do not cache the mmio info caused by writing the readonly gfn
2792 * into the spte otherwise read access on readonly gfn also can
2793 * caused mmio page fault and treat it as mmio access.
2794 * Return 1 to tell kvm to emulate it.
2796 if (pfn == KVM_PFN_ERR_RO_FAULT)
2799 if (pfn == KVM_PFN_ERR_HWPOISON) {
2800 kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu, gfn), current);
2807 static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu,
2808 gfn_t *gfnp, kvm_pfn_t *pfnp,
2811 kvm_pfn_t pfn = *pfnp;
2813 int level = *levelp;
2816 * Check if it's a transparent hugepage. If this would be an
2817 * hugetlbfs page, level wouldn't be set to
2818 * PT_PAGE_TABLE_LEVEL and there would be no adjustment done
2821 if (!is_error_noslot_pfn(pfn) && !kvm_is_reserved_pfn(pfn) &&
2822 level == PT_PAGE_TABLE_LEVEL &&
2823 PageTransCompoundMap(pfn_to_page(pfn)) &&
2824 !mmu_gfn_lpage_is_disallowed(vcpu, gfn, PT_DIRECTORY_LEVEL)) {
2827 * mmu_notifier_retry was successful and we hold the
2828 * mmu_lock here, so the pmd can't become splitting
2829 * from under us, and in turn
2830 * __split_huge_page_refcount() can't run from under
2831 * us and we can safely transfer the refcount from
2832 * PG_tail to PG_head as we switch the pfn to tail to
2835 *levelp = level = PT_DIRECTORY_LEVEL;
2836 mask = KVM_PAGES_PER_HPAGE(level) - 1;
2837 VM_BUG_ON((gfn & mask) != (pfn & mask));
2841 kvm_release_pfn_clean(pfn);
2849 static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn,
2850 kvm_pfn_t pfn, unsigned access, int *ret_val)
2852 /* The pfn is invalid, report the error! */
2853 if (unlikely(is_error_pfn(pfn))) {
2854 *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn);
2858 if (unlikely(is_noslot_pfn(pfn)))
2859 vcpu_cache_mmio_info(vcpu, gva, gfn, access);
2864 static bool page_fault_can_be_fast(u32 error_code)
2867 * Do not fix the mmio spte with invalid generation number which
2868 * need to be updated by slow page fault path.
2870 if (unlikely(error_code & PFERR_RSVD_MASK))
2874 * #PF can be fast only if the shadow page table is present and it
2875 * is caused by write-protect, that means we just need change the
2876 * W bit of the spte which can be done out of mmu-lock.
2878 if (!(error_code & PFERR_PRESENT_MASK) ||
2879 !(error_code & PFERR_WRITE_MASK))
2886 fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
2887 u64 *sptep, u64 spte)
2891 WARN_ON(!sp->role.direct);
2894 * The gfn of direct spte is stable since it is calculated
2897 gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt);
2900 * Theoretically we could also set dirty bit (and flush TLB) here in
2901 * order to eliminate unnecessary PML logging. See comments in
2902 * set_spte. But fast_page_fault is very unlikely to happen with PML
2903 * enabled, so we do not do this. This might result in the same GPA
2904 * to be logged in PML buffer again when the write really happens, and
2905 * eventually to be called by mark_page_dirty twice. But it's also no
2906 * harm. This also avoids the TLB flush needed after setting dirty bit
2907 * so non-PML cases won't be impacted.
2909 * Compare with set_spte where instead shadow_dirty_mask is set.
2911 if (cmpxchg64(sptep, spte, spte | PT_WRITABLE_MASK) == spte)
2912 kvm_vcpu_mark_page_dirty(vcpu, gfn);
2919 * - true: let the vcpu to access on the same address again.
2920 * - false: let the real page fault path to fix it.
2922 static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level,
2925 struct kvm_shadow_walk_iterator iterator;
2926 struct kvm_mmu_page *sp;
2930 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2933 if (!page_fault_can_be_fast(error_code))
2936 walk_shadow_page_lockless_begin(vcpu);
2937 for_each_shadow_entry_lockless(vcpu, gva, iterator, spte)
2938 if (!is_shadow_present_pte(spte) || iterator.level < level)
2942 * If the mapping has been changed, let the vcpu fault on the
2943 * same address again.
2945 if (!is_shadow_present_pte(spte)) {
2950 sp = page_header(__pa(iterator.sptep));
2951 if (!is_last_spte(spte, sp->role.level))
2955 * Check if it is a spurious fault caused by TLB lazily flushed.
2957 * Need not check the access of upper level table entries since
2958 * they are always ACC_ALL.
2960 if (is_writable_pte(spte)) {
2966 * Currently, to simplify the code, only the spte write-protected
2967 * by dirty-log can be fast fixed.
2969 if (!spte_is_locklessly_modifiable(spte))
2973 * Do not fix write-permission on the large spte since we only dirty
2974 * the first page into the dirty-bitmap in fast_pf_fix_direct_spte()
2975 * that means other pages are missed if its slot is dirty-logged.
2977 * Instead, we let the slow page fault path create a normal spte to
2980 * See the comments in kvm_arch_commit_memory_region().
2982 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
2986 * Currently, fast page fault only works for direct mapping since
2987 * the gfn is not stable for indirect shadow page.
2988 * See Documentation/virtual/kvm/locking.txt to get more detail.
2990 ret = fast_pf_fix_direct_spte(vcpu, sp, iterator.sptep, spte);
2992 trace_fast_page_fault(vcpu, gva, error_code, iterator.sptep,
2994 walk_shadow_page_lockless_end(vcpu);
2999 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3000 gva_t gva, kvm_pfn_t *pfn, bool write, bool *writable);
3001 static void make_mmu_pages_available(struct kvm_vcpu *vcpu);
3003 static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, u32 error_code,
3004 gfn_t gfn, bool prefault)
3008 bool force_pt_level = false;
3010 unsigned long mmu_seq;
3011 bool map_writable, write = error_code & PFERR_WRITE_MASK;
3013 level = mapping_level(vcpu, gfn, &force_pt_level);
3014 if (likely(!force_pt_level)) {
3016 * This path builds a PAE pagetable - so we can map
3017 * 2mb pages at maximum. Therefore check if the level
3018 * is larger than that.
3020 if (level > PT_DIRECTORY_LEVEL)
3021 level = PT_DIRECTORY_LEVEL;
3023 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
3026 if (fast_page_fault(vcpu, v, level, error_code))
3029 mmu_seq = vcpu->kvm->mmu_notifier_seq;
3032 if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable))
3035 if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r))
3038 spin_lock(&vcpu->kvm->mmu_lock);
3039 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
3041 make_mmu_pages_available(vcpu);
3042 if (likely(!force_pt_level))
3043 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
3044 r = __direct_map(vcpu, write, map_writable, level, gfn, pfn, prefault);
3045 spin_unlock(&vcpu->kvm->mmu_lock);
3050 spin_unlock(&vcpu->kvm->mmu_lock);
3051 kvm_release_pfn_clean(pfn);
3056 static void mmu_free_roots(struct kvm_vcpu *vcpu)
3059 struct kvm_mmu_page *sp;
3060 LIST_HEAD(invalid_list);
3062 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3065 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL &&
3066 (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL ||
3067 vcpu->arch.mmu.direct_map)) {
3068 hpa_t root = vcpu->arch.mmu.root_hpa;
3070 spin_lock(&vcpu->kvm->mmu_lock);
3071 sp = page_header(root);
3073 if (!sp->root_count && sp->role.invalid) {
3074 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
3075 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3077 spin_unlock(&vcpu->kvm->mmu_lock);
3078 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
3082 spin_lock(&vcpu->kvm->mmu_lock);
3083 for (i = 0; i < 4; ++i) {
3084 hpa_t root = vcpu->arch.mmu.pae_root[i];
3087 root &= PT64_BASE_ADDR_MASK;
3088 sp = page_header(root);
3090 if (!sp->root_count && sp->role.invalid)
3091 kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
3094 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
3096 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3097 spin_unlock(&vcpu->kvm->mmu_lock);
3098 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
3101 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
3105 if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
3106 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3113 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
3115 struct kvm_mmu_page *sp;
3118 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3119 spin_lock(&vcpu->kvm->mmu_lock);
3120 make_mmu_pages_available(vcpu);
3121 sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL, 1, ACC_ALL);
3123 spin_unlock(&vcpu->kvm->mmu_lock);
3124 vcpu->arch.mmu.root_hpa = __pa(sp->spt);
3125 } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) {
3126 for (i = 0; i < 4; ++i) {
3127 hpa_t root = vcpu->arch.mmu.pae_root[i];
3129 MMU_WARN_ON(VALID_PAGE(root));
3130 spin_lock(&vcpu->kvm->mmu_lock);
3131 make_mmu_pages_available(vcpu);
3132 sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT),
3133 i << 30, PT32_ROOT_LEVEL, 1, ACC_ALL);
3134 root = __pa(sp->spt);
3136 spin_unlock(&vcpu->kvm->mmu_lock);
3137 vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
3139 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
3146 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
3148 struct kvm_mmu_page *sp;
3153 root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT;
3155 if (mmu_check_root(vcpu, root_gfn))
3159 * Do we shadow a long mode page table? If so we need to
3160 * write-protect the guests page table root.
3162 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
3163 hpa_t root = vcpu->arch.mmu.root_hpa;
3165 MMU_WARN_ON(VALID_PAGE(root));
3167 spin_lock(&vcpu->kvm->mmu_lock);
3168 make_mmu_pages_available(vcpu);
3169 sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL,
3171 root = __pa(sp->spt);
3173 spin_unlock(&vcpu->kvm->mmu_lock);
3174 vcpu->arch.mmu.root_hpa = root;
3179 * We shadow a 32 bit page table. This may be a legacy 2-level
3180 * or a PAE 3-level page table. In either case we need to be aware that
3181 * the shadow page table may be a PAE or a long mode page table.
3183 pm_mask = PT_PRESENT_MASK;
3184 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL)
3185 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
3187 for (i = 0; i < 4; ++i) {
3188 hpa_t root = vcpu->arch.mmu.pae_root[i];
3190 MMU_WARN_ON(VALID_PAGE(root));
3191 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
3192 pdptr = vcpu->arch.mmu.get_pdptr(vcpu, i);
3193 if (!is_present_gpte(pdptr)) {
3194 vcpu->arch.mmu.pae_root[i] = 0;
3197 root_gfn = pdptr >> PAGE_SHIFT;
3198 if (mmu_check_root(vcpu, root_gfn))
3201 spin_lock(&vcpu->kvm->mmu_lock);
3202 make_mmu_pages_available(vcpu);
3203 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30, PT32_ROOT_LEVEL,
3205 root = __pa(sp->spt);
3207 spin_unlock(&vcpu->kvm->mmu_lock);
3209 vcpu->arch.mmu.pae_root[i] = root | pm_mask;
3211 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
3214 * If we shadow a 32 bit page table with a long mode page
3215 * table we enter this path.
3217 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3218 if (vcpu->arch.mmu.lm_root == NULL) {
3220 * The additional page necessary for this is only
3221 * allocated on demand.
3226 lm_root = (void*)get_zeroed_page(GFP_KERNEL);
3227 if (lm_root == NULL)
3230 lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask;
3232 vcpu->arch.mmu.lm_root = lm_root;
3235 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root);
3241 static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
3243 if (vcpu->arch.mmu.direct_map)
3244 return mmu_alloc_direct_roots(vcpu);
3246 return mmu_alloc_shadow_roots(vcpu);
3249 static void mmu_sync_roots(struct kvm_vcpu *vcpu)
3252 struct kvm_mmu_page *sp;
3254 if (vcpu->arch.mmu.direct_map)
3257 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3260 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
3261 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3262 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
3263 hpa_t root = vcpu->arch.mmu.root_hpa;
3264 sp = page_header(root);
3265 mmu_sync_children(vcpu, sp);
3266 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3269 for (i = 0; i < 4; ++i) {
3270 hpa_t root = vcpu->arch.mmu.pae_root[i];
3272 if (root && VALID_PAGE(root)) {
3273 root &= PT64_BASE_ADDR_MASK;
3274 sp = page_header(root);
3275 mmu_sync_children(vcpu, sp);
3278 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3281 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
3283 spin_lock(&vcpu->kvm->mmu_lock);
3284 mmu_sync_roots(vcpu);
3285 spin_unlock(&vcpu->kvm->mmu_lock);
3287 EXPORT_SYMBOL_GPL(kvm_mmu_sync_roots);
3289 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr,
3290 u32 access, struct x86_exception *exception)
3293 exception->error_code = 0;
3297 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr,
3299 struct x86_exception *exception)
3302 exception->error_code = 0;
3303 return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access, exception);
3307 __is_rsvd_bits_set(struct rsvd_bits_validate *rsvd_check, u64 pte, int level)
3309 int bit7 = (pte >> 7) & 1, low6 = pte & 0x3f;
3311 return (pte & rsvd_check->rsvd_bits_mask[bit7][level-1]) |
3312 ((rsvd_check->bad_mt_xwr & (1ull << low6)) != 0);
3315 static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level)
3317 return __is_rsvd_bits_set(&mmu->guest_rsvd_check, gpte, level);
3320 static bool is_shadow_zero_bits_set(struct kvm_mmu *mmu, u64 spte, int level)
3322 return __is_rsvd_bits_set(&mmu->shadow_zero_check, spte, level);
3325 static bool mmio_info_in_cache(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3328 return vcpu_match_mmio_gpa(vcpu, addr);
3330 return vcpu_match_mmio_gva(vcpu, addr);
3333 /* return true if reserved bit is detected on spte. */
3335 walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr, u64 *sptep)
3337 struct kvm_shadow_walk_iterator iterator;
3338 u64 sptes[PT64_ROOT_LEVEL], spte = 0ull;
3340 bool reserved = false;
3342 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3345 walk_shadow_page_lockless_begin(vcpu);
3347 for (shadow_walk_init(&iterator, vcpu, addr),
3348 leaf = root = iterator.level;
3349 shadow_walk_okay(&iterator);
3350 __shadow_walk_next(&iterator, spte)) {
3351 spte = mmu_spte_get_lockless(iterator.sptep);
3353 sptes[leaf - 1] = spte;
3356 if (!is_shadow_present_pte(spte))
3359 reserved |= is_shadow_zero_bits_set(&vcpu->arch.mmu, spte,
3363 walk_shadow_page_lockless_end(vcpu);
3366 pr_err("%s: detect reserved bits on spte, addr 0x%llx, dump hierarchy:\n",
3368 while (root > leaf) {
3369 pr_err("------ spte 0x%llx level %d.\n",
3370 sptes[root - 1], root);
3379 int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3384 if (mmio_info_in_cache(vcpu, addr, direct))
3385 return RET_MMIO_PF_EMULATE;
3387 reserved = walk_shadow_page_get_mmio_spte(vcpu, addr, &spte);
3388 if (WARN_ON(reserved))
3389 return RET_MMIO_PF_BUG;
3391 if (is_mmio_spte(spte)) {
3392 gfn_t gfn = get_mmio_spte_gfn(spte);
3393 unsigned access = get_mmio_spte_access(spte);
3395 if (!check_mmio_spte(vcpu, spte))
3396 return RET_MMIO_PF_INVALID;
3401 trace_handle_mmio_page_fault(addr, gfn, access);
3402 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
3403 return RET_MMIO_PF_EMULATE;
3407 * If the page table is zapped by other cpus, let CPU fault again on
3410 return RET_MMIO_PF_RETRY;
3412 EXPORT_SYMBOL_GPL(handle_mmio_page_fault);
3414 static bool page_fault_handle_page_track(struct kvm_vcpu *vcpu,
3415 u32 error_code, gfn_t gfn)
3417 if (unlikely(error_code & PFERR_RSVD_MASK))
3420 if (!(error_code & PFERR_PRESENT_MASK) ||
3421 !(error_code & PFERR_WRITE_MASK))
3425 * guest is writing the page which is write tracked which can
3426 * not be fixed by page fault handler.
3428 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
3434 static void shadow_page_table_clear_flood(struct kvm_vcpu *vcpu, gva_t addr)
3436 struct kvm_shadow_walk_iterator iterator;
3439 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3442 walk_shadow_page_lockless_begin(vcpu);
3443 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) {
3444 clear_sp_write_flooding_count(iterator.sptep);
3445 if (!is_shadow_present_pte(spte))
3448 walk_shadow_page_lockless_end(vcpu);
3451 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
3452 u32 error_code, bool prefault)
3454 gfn_t gfn = gva >> PAGE_SHIFT;
3457 pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
3459 if (page_fault_handle_page_track(vcpu, error_code, gfn))
3462 r = mmu_topup_memory_caches(vcpu);
3466 MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3469 return nonpaging_map(vcpu, gva & PAGE_MASK,
3470 error_code, gfn, prefault);
3473 static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn)
3475 struct kvm_arch_async_pf arch;
3477 arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
3479 arch.direct_map = vcpu->arch.mmu.direct_map;
3480 arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu);
3482 return kvm_setup_async_pf(vcpu, gva, kvm_vcpu_gfn_to_hva(vcpu, gfn), &arch);
3485 static bool can_do_async_pf(struct kvm_vcpu *vcpu)
3487 if (unlikely(!lapic_in_kernel(vcpu) ||
3488 kvm_event_needs_reinjection(vcpu)))
3491 return kvm_x86_ops->interrupt_allowed(vcpu);
3494 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3495 gva_t gva, kvm_pfn_t *pfn, bool write, bool *writable)
3497 struct kvm_memory_slot *slot;
3500 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
3502 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, &async, write, writable);
3504 return false; /* *pfn has correct page already */
3506 if (!prefault && can_do_async_pf(vcpu)) {
3507 trace_kvm_try_async_get_page(gva, gfn);
3508 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
3509 trace_kvm_async_pf_doublefault(gva, gfn);
3510 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
3512 } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn))
3516 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, NULL, write, writable);
3521 check_hugepage_cache_consistency(struct kvm_vcpu *vcpu, gfn_t gfn, int level)
3523 int page_num = KVM_PAGES_PER_HPAGE(level);
3525 gfn &= ~(page_num - 1);
3527 return kvm_mtrr_check_gfn_range_consistency(vcpu, gfn, page_num);
3530 static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code,
3536 bool force_pt_level;
3537 gfn_t gfn = gpa >> PAGE_SHIFT;
3538 unsigned long mmu_seq;
3539 int write = error_code & PFERR_WRITE_MASK;
3542 MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3544 if (page_fault_handle_page_track(vcpu, error_code, gfn))
3547 r = mmu_topup_memory_caches(vcpu);
3551 force_pt_level = !check_hugepage_cache_consistency(vcpu, gfn,
3552 PT_DIRECTORY_LEVEL);
3553 level = mapping_level(vcpu, gfn, &force_pt_level);
3554 if (likely(!force_pt_level)) {
3555 if (level > PT_DIRECTORY_LEVEL &&
3556 !check_hugepage_cache_consistency(vcpu, gfn, level))
3557 level = PT_DIRECTORY_LEVEL;
3558 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
3561 if (fast_page_fault(vcpu, gpa, level, error_code))
3564 mmu_seq = vcpu->kvm->mmu_notifier_seq;
3567 if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable))
3570 if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r))
3573 spin_lock(&vcpu->kvm->mmu_lock);
3574 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
3576 make_mmu_pages_available(vcpu);
3577 if (likely(!force_pt_level))
3578 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
3579 r = __direct_map(vcpu, write, map_writable, level, gfn, pfn, prefault);
3580 spin_unlock(&vcpu->kvm->mmu_lock);
3585 spin_unlock(&vcpu->kvm->mmu_lock);
3586 kvm_release_pfn_clean(pfn);
3590 static void nonpaging_init_context(struct kvm_vcpu *vcpu,
3591 struct kvm_mmu *context)
3593 context->page_fault = nonpaging_page_fault;
3594 context->gva_to_gpa = nonpaging_gva_to_gpa;
3595 context->sync_page = nonpaging_sync_page;
3596 context->invlpg = nonpaging_invlpg;
3597 context->update_pte = nonpaging_update_pte;
3598 context->root_level = 0;
3599 context->shadow_root_level = PT32E_ROOT_LEVEL;
3600 context->root_hpa = INVALID_PAGE;
3601 context->direct_map = true;
3602 context->nx = false;
3605 void kvm_mmu_new_cr3(struct kvm_vcpu *vcpu)
3607 mmu_free_roots(vcpu);
3610 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
3612 return kvm_read_cr3(vcpu);
3615 static void inject_page_fault(struct kvm_vcpu *vcpu,
3616 struct x86_exception *fault)
3618 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
3621 static bool sync_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
3622 unsigned access, int *nr_present)
3624 if (unlikely(is_mmio_spte(*sptep))) {
3625 if (gfn != get_mmio_spte_gfn(*sptep)) {
3626 mmu_spte_clear_no_track(sptep);
3631 mark_mmio_spte(vcpu, sptep, gfn, access);
3638 static inline bool is_last_gpte(struct kvm_mmu *mmu,
3639 unsigned level, unsigned gpte)
3642 * PT_PAGE_TABLE_LEVEL always terminates. The RHS has bit 7 set
3643 * iff level <= PT_PAGE_TABLE_LEVEL, which for our purpose means
3644 * level == PT_PAGE_TABLE_LEVEL; set PT_PAGE_SIZE_MASK in gpte then.
3646 gpte |= level - PT_PAGE_TABLE_LEVEL - 1;
3649 * The RHS has bit 7 set iff level < mmu->last_nonleaf_level.
3650 * If it is clear, there are no large pages at this level, so clear
3651 * PT_PAGE_SIZE_MASK in gpte if that is the case.
3653 gpte &= level - mmu->last_nonleaf_level;
3655 return gpte & PT_PAGE_SIZE_MASK;
3658 #define PTTYPE_EPT 18 /* arbitrary */
3659 #define PTTYPE PTTYPE_EPT
3660 #include "paging_tmpl.h"
3664 #include "paging_tmpl.h"
3668 #include "paging_tmpl.h"
3672 __reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
3673 struct rsvd_bits_validate *rsvd_check,
3674 int maxphyaddr, int level, bool nx, bool gbpages,
3677 u64 exb_bit_rsvd = 0;
3678 u64 gbpages_bit_rsvd = 0;
3679 u64 nonleaf_bit8_rsvd = 0;
3681 rsvd_check->bad_mt_xwr = 0;
3684 exb_bit_rsvd = rsvd_bits(63, 63);
3686 gbpages_bit_rsvd = rsvd_bits(7, 7);
3689 * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for
3690 * leaf entries) on AMD CPUs only.
3693 nonleaf_bit8_rsvd = rsvd_bits(8, 8);
3696 case PT32_ROOT_LEVEL:
3697 /* no rsvd bits for 2 level 4K page table entries */
3698 rsvd_check->rsvd_bits_mask[0][1] = 0;
3699 rsvd_check->rsvd_bits_mask[0][0] = 0;
3700 rsvd_check->rsvd_bits_mask[1][0] =
3701 rsvd_check->rsvd_bits_mask[0][0];
3704 rsvd_check->rsvd_bits_mask[1][1] = 0;
3708 if (is_cpuid_PSE36())
3709 /* 36bits PSE 4MB page */
3710 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
3712 /* 32 bits PSE 4MB page */
3713 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
3715 case PT32E_ROOT_LEVEL:
3716 rsvd_check->rsvd_bits_mask[0][2] =
3717 rsvd_bits(maxphyaddr, 63) |
3718 rsvd_bits(5, 8) | rsvd_bits(1, 2); /* PDPTE */
3719 rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3720 rsvd_bits(maxphyaddr, 62); /* PDE */
3721 rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3722 rsvd_bits(maxphyaddr, 62); /* PTE */
3723 rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3724 rsvd_bits(maxphyaddr, 62) |
3725 rsvd_bits(13, 20); /* large page */
3726 rsvd_check->rsvd_bits_mask[1][0] =
3727 rsvd_check->rsvd_bits_mask[0][0];
3729 case PT64_ROOT_LEVEL:
3730 rsvd_check->rsvd_bits_mask[0][3] = exb_bit_rsvd |
3731 nonleaf_bit8_rsvd | rsvd_bits(7, 7) |
3732 rsvd_bits(maxphyaddr, 51);
3733 rsvd_check->rsvd_bits_mask[0][2] = exb_bit_rsvd |
3734 nonleaf_bit8_rsvd | gbpages_bit_rsvd |
3735 rsvd_bits(maxphyaddr, 51);
3736 rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3737 rsvd_bits(maxphyaddr, 51);
3738 rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3739 rsvd_bits(maxphyaddr, 51);
3740 rsvd_check->rsvd_bits_mask[1][3] =
3741 rsvd_check->rsvd_bits_mask[0][3];
3742 rsvd_check->rsvd_bits_mask[1][2] = exb_bit_rsvd |
3743 gbpages_bit_rsvd | rsvd_bits(maxphyaddr, 51) |
3745 rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3746 rsvd_bits(maxphyaddr, 51) |
3747 rsvd_bits(13, 20); /* large page */
3748 rsvd_check->rsvd_bits_mask[1][0] =
3749 rsvd_check->rsvd_bits_mask[0][0];
3754 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
3755 struct kvm_mmu *context)
3757 __reset_rsvds_bits_mask(vcpu, &context->guest_rsvd_check,
3758 cpuid_maxphyaddr(vcpu), context->root_level,
3759 context->nx, guest_cpuid_has_gbpages(vcpu),
3760 is_pse(vcpu), guest_cpuid_is_amd(vcpu));
3764 __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate *rsvd_check,
3765 int maxphyaddr, bool execonly)
3769 rsvd_check->rsvd_bits_mask[0][3] =
3770 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7);
3771 rsvd_check->rsvd_bits_mask[0][2] =
3772 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);
3773 rsvd_check->rsvd_bits_mask[0][1] =
3774 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);
3775 rsvd_check->rsvd_bits_mask[0][0] = rsvd_bits(maxphyaddr, 51);
3778 rsvd_check->rsvd_bits_mask[1][3] = rsvd_check->rsvd_bits_mask[0][3];
3779 rsvd_check->rsvd_bits_mask[1][2] =
3780 rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 29);
3781 rsvd_check->rsvd_bits_mask[1][1] =
3782 rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 20);
3783 rsvd_check->rsvd_bits_mask[1][0] = rsvd_check->rsvd_bits_mask[0][0];
3785 bad_mt_xwr = 0xFFull << (2 * 8); /* bits 3..5 must not be 2 */
3786 bad_mt_xwr |= 0xFFull << (3 * 8); /* bits 3..5 must not be 3 */
3787 bad_mt_xwr |= 0xFFull << (7 * 8); /* bits 3..5 must not be 7 */
3788 bad_mt_xwr |= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */
3789 bad_mt_xwr |= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */
3791 /* bits 0..2 must not be 100 unless VMX capabilities allow it */
3792 bad_mt_xwr |= REPEAT_BYTE(1ull << 4);
3794 rsvd_check->bad_mt_xwr = bad_mt_xwr;
3797 static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu,
3798 struct kvm_mmu *context, bool execonly)
3800 __reset_rsvds_bits_mask_ept(&context->guest_rsvd_check,
3801 cpuid_maxphyaddr(vcpu), execonly);
3805 * the page table on host is the shadow page table for the page
3806 * table in guest or amd nested guest, its mmu features completely
3807 * follow the features in guest.
3810 reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
3812 bool uses_nx = context->nx || context->base_role.smep_andnot_wp;
3815 * Passing "true" to the last argument is okay; it adds a check
3816 * on bit 8 of the SPTEs which KVM doesn't use anyway.
3818 __reset_rsvds_bits_mask(vcpu, &context->shadow_zero_check,
3819 boot_cpu_data.x86_phys_bits,
3820 context->shadow_root_level, uses_nx,
3821 guest_cpuid_has_gbpages(vcpu), is_pse(vcpu),
3824 EXPORT_SYMBOL_GPL(reset_shadow_zero_bits_mask);
3826 static inline bool boot_cpu_is_amd(void)
3828 WARN_ON_ONCE(!tdp_enabled);
3829 return shadow_x_mask == 0;
3833 * the direct page table on host, use as much mmu features as
3834 * possible, however, kvm currently does not do execution-protection.
3837 reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
3838 struct kvm_mmu *context)
3840 if (boot_cpu_is_amd())
3841 __reset_rsvds_bits_mask(vcpu, &context->shadow_zero_check,
3842 boot_cpu_data.x86_phys_bits,
3843 context->shadow_root_level, false,
3844 boot_cpu_has(X86_FEATURE_GBPAGES),
3847 __reset_rsvds_bits_mask_ept(&context->shadow_zero_check,
3848 boot_cpu_data.x86_phys_bits,
3854 * as the comments in reset_shadow_zero_bits_mask() except it
3855 * is the shadow page table for intel nested guest.
3858 reset_ept_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
3859 struct kvm_mmu *context, bool execonly)
3861 __reset_rsvds_bits_mask_ept(&context->shadow_zero_check,
3862 boot_cpu_data.x86_phys_bits, execonly);
3865 static void update_permission_bitmask(struct kvm_vcpu *vcpu,
3866 struct kvm_mmu *mmu, bool ept)
3868 unsigned bit, byte, pfec;
3870 bool fault, x, w, u, wf, uf, ff, smapf, cr4_smap, cr4_smep, smap = 0;
3872 cr4_smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
3873 cr4_smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP);
3874 for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) {
3877 wf = pfec & PFERR_WRITE_MASK;
3878 uf = pfec & PFERR_USER_MASK;
3879 ff = pfec & PFERR_FETCH_MASK;
3881 * PFERR_RSVD_MASK bit is set in PFEC if the access is not
3882 * subject to SMAP restrictions, and cleared otherwise. The
3883 * bit is only meaningful if the SMAP bit is set in CR4.
3885 smapf = !(pfec & PFERR_RSVD_MASK);
3886 for (bit = 0; bit < 8; ++bit) {
3887 x = bit & ACC_EXEC_MASK;
3888 w = bit & ACC_WRITE_MASK;
3889 u = bit & ACC_USER_MASK;
3892 /* Not really needed: !nx will cause pte.nx to fault */
3894 /* Allow supervisor writes if !cr0.wp */
3895 w |= !is_write_protection(vcpu) && !uf;
3896 /* Disallow supervisor fetches of user code if cr4.smep */
3897 x &= !(cr4_smep && u && !uf);
3900 * SMAP:kernel-mode data accesses from user-mode
3901 * mappings should fault. A fault is considered
3902 * as a SMAP violation if all of the following
3903 * conditions are ture:
3904 * - X86_CR4_SMAP is set in CR4
3905 * - An user page is accessed
3906 * - Page fault in kernel mode
3907 * - if CPL = 3 or X86_EFLAGS_AC is clear
3909 * Here, we cover the first three conditions.
3910 * The fourth is computed dynamically in
3911 * permission_fault() and is in smapf.
3913 * Also, SMAP does not affect instruction
3914 * fetches, add the !ff check here to make it
3917 smap = cr4_smap && u && !uf && !ff;
3919 /* Not really needed: no U/S accesses on ept */
3922 fault = (ff && !x) || (uf && !u) || (wf && !w) ||
3924 map |= fault << bit;
3926 mmu->permissions[byte] = map;
3931 * PKU is an additional mechanism by which the paging controls access to
3932 * user-mode addresses based on the value in the PKRU register. Protection
3933 * key violations are reported through a bit in the page fault error code.
3934 * Unlike other bits of the error code, the PK bit is not known at the
3935 * call site of e.g. gva_to_gpa; it must be computed directly in
3936 * permission_fault based on two bits of PKRU, on some machine state (CR4,
3937 * CR0, EFER, CPL), and on other bits of the error code and the page tables.
3939 * In particular the following conditions come from the error code, the
3940 * page tables and the machine state:
3941 * - PK is always zero unless CR4.PKE=1 and EFER.LMA=1
3942 * - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch)
3943 * - PK is always zero if U=0 in the page tables
3944 * - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access.
3946 * The PKRU bitmask caches the result of these four conditions. The error
3947 * code (minus the P bit) and the page table's U bit form an index into the
3948 * PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed
3949 * with the two bits of the PKRU register corresponding to the protection key.
3950 * For the first three conditions above the bits will be 00, thus masking
3951 * away both AD and WD. For all reads or if the last condition holds, WD
3952 * only will be masked away.
3954 static void update_pkru_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
3965 /* PKEY is enabled only if CR4.PKE and EFER.LMA are both set. */
3966 if (!kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || !is_long_mode(vcpu)) {
3971 wp = is_write_protection(vcpu);
3973 for (bit = 0; bit < ARRAY_SIZE(mmu->permissions); ++bit) {
3974 unsigned pfec, pkey_bits;
3975 bool check_pkey, check_write, ff, uf, wf, pte_user;
3978 ff = pfec & PFERR_FETCH_MASK;
3979 uf = pfec & PFERR_USER_MASK;
3980 wf = pfec & PFERR_WRITE_MASK;
3982 /* PFEC.RSVD is replaced by ACC_USER_MASK. */
3983 pte_user = pfec & PFERR_RSVD_MASK;
3986 * Only need to check the access which is not an
3987 * instruction fetch and is to a user page.
3989 check_pkey = (!ff && pte_user);
3991 * write access is controlled by PKRU if it is a
3992 * user access or CR0.WP = 1.
3994 check_write = check_pkey && wf && (uf || wp);
3996 /* PKRU.AD stops both read and write access. */
3997 pkey_bits = !!check_pkey;
3998 /* PKRU.WD stops write access. */
3999 pkey_bits |= (!!check_write) << 1;
4001 mmu->pkru_mask |= (pkey_bits & 3) << pfec;
4005 static void update_last_nonleaf_level(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
4007 unsigned root_level = mmu->root_level;
4009 mmu->last_nonleaf_level = root_level;
4010 if (root_level == PT32_ROOT_LEVEL && is_pse(vcpu))
4011 mmu->last_nonleaf_level++;
4014 static void paging64_init_context_common(struct kvm_vcpu *vcpu,
4015 struct kvm_mmu *context,
4018 context->nx = is_nx(vcpu);
4019 context->root_level = level;
4021 reset_rsvds_bits_mask(vcpu, context);
4022 update_permission_bitmask(vcpu, context, false);
4023 update_pkru_bitmask(vcpu, context, false);
4024 update_last_nonleaf_level(vcpu, context);
4026 MMU_WARN_ON(!is_pae(vcpu));
4027 context->page_fault = paging64_page_fault;
4028 context->gva_to_gpa = paging64_gva_to_gpa;
4029 context->sync_page = paging64_sync_page;
4030 context->invlpg = paging64_invlpg;
4031 context->update_pte = paging64_update_pte;
4032 context->shadow_root_level = level;
4033 context->root_hpa = INVALID_PAGE;
4034 context->direct_map = false;
4037 static void paging64_init_context(struct kvm_vcpu *vcpu,
4038 struct kvm_mmu *context)
4040 paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL);
4043 static void paging32_init_context(struct kvm_vcpu *vcpu,
4044 struct kvm_mmu *context)
4046 context->nx = false;
4047 context->root_level = PT32_ROOT_LEVEL;
4049 reset_rsvds_bits_mask(vcpu, context);
4050 update_permission_bitmask(vcpu, context, false);
4051 update_pkru_bitmask(vcpu, context, false);
4052 update_last_nonleaf_level(vcpu, context);
4054 context->page_fault = paging32_page_fault;
4055 context->gva_to_gpa = paging32_gva_to_gpa;
4056 context->sync_page = paging32_sync_page;
4057 context->invlpg = paging32_invlpg;
4058 context->update_pte = paging32_update_pte;
4059 context->shadow_root_level = PT32E_ROOT_LEVEL;
4060 context->root_hpa = INVALID_PAGE;
4061 context->direct_map = false;
4064 static void paging32E_init_context(struct kvm_vcpu *vcpu,
4065 struct kvm_mmu *context)
4067 paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
4070 static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
4072 struct kvm_mmu *context = &vcpu->arch.mmu;
4074 context->base_role.word = 0;
4075 context->base_role.smm = is_smm(vcpu);
4076 context->page_fault = tdp_page_fault;
4077 context->sync_page = nonpaging_sync_page;
4078 context->invlpg = nonpaging_invlpg;
4079 context->update_pte = nonpaging_update_pte;
4080 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
4081 context->root_hpa = INVALID_PAGE;
4082 context->direct_map = true;
4083 context->set_cr3 = kvm_x86_ops->set_tdp_cr3;
4084 context->get_cr3 = get_cr3;
4085 context->get_pdptr = kvm_pdptr_read;
4086 context->inject_page_fault = kvm_inject_page_fault;
4088 if (!is_paging(vcpu)) {
4089 context->nx = false;
4090 context->gva_to_gpa = nonpaging_gva_to_gpa;
4091 context->root_level = 0;
4092 } else if (is_long_mode(vcpu)) {
4093 context->nx = is_nx(vcpu);
4094 context->root_level = PT64_ROOT_LEVEL;
4095 reset_rsvds_bits_mask(vcpu, context);
4096 context->gva_to_gpa = paging64_gva_to_gpa;
4097 } else if (is_pae(vcpu)) {
4098 context->nx = is_nx(vcpu);
4099 context->root_level = PT32E_ROOT_LEVEL;
4100 reset_rsvds_bits_mask(vcpu, context);
4101 context->gva_to_gpa = paging64_gva_to_gpa;
4103 context->nx = false;
4104 context->root_level = PT32_ROOT_LEVEL;
4105 reset_rsvds_bits_mask(vcpu, context);
4106 context->gva_to_gpa = paging32_gva_to_gpa;
4109 update_permission_bitmask(vcpu, context, false);
4110 update_pkru_bitmask(vcpu, context, false);
4111 update_last_nonleaf_level(vcpu, context);
4112 reset_tdp_shadow_zero_bits_mask(vcpu, context);
4115 void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu)
4117 bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
4118 bool smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP);
4119 struct kvm_mmu *context = &vcpu->arch.mmu;
4121 MMU_WARN_ON(VALID_PAGE(context->root_hpa));
4123 if (!is_paging(vcpu))
4124 nonpaging_init_context(vcpu, context);
4125 else if (is_long_mode(vcpu))
4126 paging64_init_context(vcpu, context);
4127 else if (is_pae(vcpu))
4128 paging32E_init_context(vcpu, context);
4130 paging32_init_context(vcpu, context);
4132 context->base_role.nxe = is_nx(vcpu);
4133 context->base_role.cr4_pae = !!is_pae(vcpu);
4134 context->base_role.cr0_wp = is_write_protection(vcpu);
4135 context->base_role.smep_andnot_wp
4136 = smep && !is_write_protection(vcpu);
4137 context->base_role.smap_andnot_wp
4138 = smap && !is_write_protection(vcpu);
4139 context->base_role.smm = is_smm(vcpu);
4140 reset_shadow_zero_bits_mask(vcpu, context);
4142 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu);
4144 void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly)
4146 struct kvm_mmu *context = &vcpu->arch.mmu;
4148 MMU_WARN_ON(VALID_PAGE(context->root_hpa));
4150 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
4153 context->page_fault = ept_page_fault;
4154 context->gva_to_gpa = ept_gva_to_gpa;
4155 context->sync_page = ept_sync_page;
4156 context->invlpg = ept_invlpg;
4157 context->update_pte = ept_update_pte;
4158 context->root_level = context->shadow_root_level;
4159 context->root_hpa = INVALID_PAGE;
4160 context->direct_map = false;
4162 update_permission_bitmask(vcpu, context, true);
4163 update_pkru_bitmask(vcpu, context, true);
4164 reset_rsvds_bits_mask_ept(vcpu, context, execonly);
4165 reset_ept_shadow_zero_bits_mask(vcpu, context, execonly);
4167 EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu);
4169 static void init_kvm_softmmu(struct kvm_vcpu *vcpu)
4171 struct kvm_mmu *context = &vcpu->arch.mmu;
4173 kvm_init_shadow_mmu(vcpu);
4174 context->set_cr3 = kvm_x86_ops->set_cr3;
4175 context->get_cr3 = get_cr3;
4176 context->get_pdptr = kvm_pdptr_read;
4177 context->inject_page_fault = kvm_inject_page_fault;
4180 static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
4182 struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
4184 g_context->get_cr3 = get_cr3;
4185 g_context->get_pdptr = kvm_pdptr_read;
4186 g_context->inject_page_fault = kvm_inject_page_fault;
4189 * Note that arch.mmu.gva_to_gpa translates l2_gpa to l1_gpa using
4190 * L1's nested page tables (e.g. EPT12). The nested translation
4191 * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using
4192 * L2's page tables as the first level of translation and L1's
4193 * nested page tables as the second level of translation. Basically
4194 * the gva_to_gpa functions between mmu and nested_mmu are swapped.
4196 if (!is_paging(vcpu)) {
4197 g_context->nx = false;
4198 g_context->root_level = 0;
4199 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
4200 } else if (is_long_mode(vcpu)) {
4201 g_context->nx = is_nx(vcpu);
4202 g_context->root_level = PT64_ROOT_LEVEL;
4203 reset_rsvds_bits_mask(vcpu, g_context);
4204 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
4205 } else if (is_pae(vcpu)) {
4206 g_context->nx = is_nx(vcpu);
4207 g_context->root_level = PT32E_ROOT_LEVEL;
4208 reset_rsvds_bits_mask(vcpu, g_context);
4209 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
4211 g_context->nx = false;
4212 g_context->root_level = PT32_ROOT_LEVEL;
4213 reset_rsvds_bits_mask(vcpu, g_context);
4214 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
4217 update_permission_bitmask(vcpu, g_context, false);
4218 update_pkru_bitmask(vcpu, g_context, false);
4219 update_last_nonleaf_level(vcpu, g_context);
4222 static void init_kvm_mmu(struct kvm_vcpu *vcpu)
4224 if (mmu_is_nested(vcpu))
4225 init_kvm_nested_mmu(vcpu);
4226 else if (tdp_enabled)
4227 init_kvm_tdp_mmu(vcpu);
4229 init_kvm_softmmu(vcpu);
4232 void kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
4234 kvm_mmu_unload(vcpu);
4237 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
4239 int kvm_mmu_load(struct kvm_vcpu *vcpu)
4243 r = mmu_topup_memory_caches(vcpu);
4246 r = mmu_alloc_roots(vcpu);
4247 kvm_mmu_sync_roots(vcpu);
4250 /* set_cr3() should ensure TLB has been flushed */
4251 vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
4255 EXPORT_SYMBOL_GPL(kvm_mmu_load);
4257 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
4259 mmu_free_roots(vcpu);
4260 WARN_ON(VALID_PAGE(vcpu->arch.mmu.root_hpa));
4262 EXPORT_SYMBOL_GPL(kvm_mmu_unload);
4264 static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
4265 struct kvm_mmu_page *sp, u64 *spte,
4268 if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
4269 ++vcpu->kvm->stat.mmu_pde_zapped;
4273 ++vcpu->kvm->stat.mmu_pte_updated;
4274 vcpu->arch.mmu.update_pte(vcpu, sp, spte, new);
4277 static bool need_remote_flush(u64 old, u64 new)
4279 if (!is_shadow_present_pte(old))
4281 if (!is_shadow_present_pte(new))
4283 if ((old ^ new) & PT64_BASE_ADDR_MASK)
4285 old ^= shadow_nx_mask;
4286 new ^= shadow_nx_mask;
4287 return (old & ~new & PT64_PERM_MASK) != 0;
4290 static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa,
4291 const u8 *new, int *bytes)
4297 * Assume that the pte write on a page table of the same type
4298 * as the current vcpu paging mode since we update the sptes only
4299 * when they have the same mode.
4301 if (is_pae(vcpu) && *bytes == 4) {
4302 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
4305 r = kvm_vcpu_read_guest(vcpu, *gpa, &gentry, 8);
4308 new = (const u8 *)&gentry;
4313 gentry = *(const u32 *)new;
4316 gentry = *(const u64 *)new;
4327 * If we're seeing too many writes to a page, it may no longer be a page table,
4328 * or we may be forking, in which case it is better to unmap the page.
4330 static bool detect_write_flooding(struct kvm_mmu_page *sp)
4333 * Skip write-flooding detected for the sp whose level is 1, because
4334 * it can become unsync, then the guest page is not write-protected.
4336 if (sp->role.level == PT_PAGE_TABLE_LEVEL)
4339 atomic_inc(&sp->write_flooding_count);
4340 return atomic_read(&sp->write_flooding_count) >= 3;
4344 * Misaligned accesses are too much trouble to fix up; also, they usually
4345 * indicate a page is not used as a page table.
4347 static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa,
4350 unsigned offset, pte_size, misaligned;
4352 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
4353 gpa, bytes, sp->role.word);
4355 offset = offset_in_page(gpa);
4356 pte_size = sp->role.cr4_pae ? 8 : 4;
4359 * Sometimes, the OS only writes the last one bytes to update status
4360 * bits, for example, in linux, andb instruction is used in clear_bit().
4362 if (!(offset & (pte_size - 1)) && bytes == 1)
4365 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
4366 misaligned |= bytes < 4;
4371 static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte)
4373 unsigned page_offset, quadrant;
4377 page_offset = offset_in_page(gpa);
4378 level = sp->role.level;
4380 if (!sp->role.cr4_pae) {
4381 page_offset <<= 1; /* 32->64 */
4383 * A 32-bit pde maps 4MB while the shadow pdes map
4384 * only 2MB. So we need to double the offset again
4385 * and zap two pdes instead of one.
4387 if (level == PT32_ROOT_LEVEL) {
4388 page_offset &= ~7; /* kill rounding error */
4392 quadrant = page_offset >> PAGE_SHIFT;
4393 page_offset &= ~PAGE_MASK;
4394 if (quadrant != sp->role.quadrant)
4398 spte = &sp->spt[page_offset / sizeof(*spte)];
4402 static void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
4403 const u8 *new, int bytes)
4405 gfn_t gfn = gpa >> PAGE_SHIFT;
4406 struct kvm_mmu_page *sp;
4407 LIST_HEAD(invalid_list);
4408 u64 entry, gentry, *spte;
4410 bool remote_flush, local_flush;
4411 union kvm_mmu_page_role mask = { };
4416 mask.smep_andnot_wp = 1;
4417 mask.smap_andnot_wp = 1;
4421 * If we don't have indirect shadow pages, it means no page is
4422 * write-protected, so we can exit simply.
4424 if (!ACCESS_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
4427 remote_flush = local_flush = false;
4429 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
4431 gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, new, &bytes);
4434 * No need to care whether allocation memory is successful
4435 * or not since pte prefetch is skiped if it does not have
4436 * enough objects in the cache.
4438 mmu_topup_memory_caches(vcpu);
4440 spin_lock(&vcpu->kvm->mmu_lock);
4441 ++vcpu->kvm->stat.mmu_pte_write;
4442 kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
4444 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
4445 if (detect_write_misaligned(sp, gpa, bytes) ||
4446 detect_write_flooding(sp)) {
4447 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
4448 ++vcpu->kvm->stat.mmu_flooded;
4452 spte = get_written_sptes(sp, gpa, &npte);
4459 mmu_page_zap_pte(vcpu->kvm, sp, spte);
4461 !((sp->role.word ^ vcpu->arch.mmu.base_role.word)
4462 & mask.word) && rmap_can_add(vcpu))
4463 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
4464 if (need_remote_flush(entry, *spte))
4465 remote_flush = true;
4469 kvm_mmu_flush_or_zap(vcpu, &invalid_list, remote_flush, local_flush);
4470 kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
4471 spin_unlock(&vcpu->kvm->mmu_lock);
4474 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
4479 if (vcpu->arch.mmu.direct_map)
4482 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
4484 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4488 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
4490 static void make_mmu_pages_available(struct kvm_vcpu *vcpu)
4492 LIST_HEAD(invalid_list);
4494 if (likely(kvm_mmu_available_pages(vcpu->kvm) >= KVM_MIN_FREE_MMU_PAGES))
4497 while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES) {
4498 if (!prepare_zap_oldest_mmu_page(vcpu->kvm, &invalid_list))
4501 ++vcpu->kvm->stat.mmu_recycled;
4503 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
4506 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code,
4507 void *insn, int insn_len)
4509 int r, emulation_type = EMULTYPE_RETRY;
4510 enum emulation_result er;
4511 bool direct = vcpu->arch.mmu.direct_map || mmu_is_nested(vcpu);
4513 if (unlikely(error_code & PFERR_RSVD_MASK)) {
4514 r = handle_mmio_page_fault(vcpu, cr2, direct);
4515 if (r == RET_MMIO_PF_EMULATE) {
4519 if (r == RET_MMIO_PF_RETRY)
4525 r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code, false);
4531 if (mmio_info_in_cache(vcpu, cr2, direct))
4534 er = x86_emulate_instruction(vcpu, cr2, emulation_type, insn, insn_len);
4539 case EMULATE_USER_EXIT:
4540 ++vcpu->stat.mmio_exits;
4548 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
4550 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
4552 vcpu->arch.mmu.invlpg(vcpu, gva);
4553 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
4554 ++vcpu->stat.invlpg;
4556 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
4558 void kvm_enable_tdp(void)
4562 EXPORT_SYMBOL_GPL(kvm_enable_tdp);
4564 void kvm_disable_tdp(void)
4566 tdp_enabled = false;
4568 EXPORT_SYMBOL_GPL(kvm_disable_tdp);
4570 static void free_mmu_pages(struct kvm_vcpu *vcpu)
4572 free_page((unsigned long)vcpu->arch.mmu.pae_root);
4573 if (vcpu->arch.mmu.lm_root != NULL)
4574 free_page((unsigned long)vcpu->arch.mmu.lm_root);
4577 static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
4583 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
4584 * Therefore we need to allocate shadow page tables in the first
4585 * 4GB of memory, which happens to fit the DMA32 zone.
4587 page = alloc_page(GFP_KERNEL | __GFP_DMA32);
4591 vcpu->arch.mmu.pae_root = page_address(page);
4592 for (i = 0; i < 4; ++i)
4593 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
4598 int kvm_mmu_create(struct kvm_vcpu *vcpu)
4600 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
4601 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
4602 vcpu->arch.mmu.translate_gpa = translate_gpa;
4603 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
4605 return alloc_mmu_pages(vcpu);
4608 void kvm_mmu_setup(struct kvm_vcpu *vcpu)
4610 MMU_WARN_ON(VALID_PAGE(vcpu->arch.mmu.root_hpa));
4615 void kvm_mmu_init_vm(struct kvm *kvm)
4617 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
4619 node->track_write = kvm_mmu_pte_write;
4620 kvm_page_track_register_notifier(kvm, node);
4623 void kvm_mmu_uninit_vm(struct kvm *kvm)
4625 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
4627 kvm_page_track_unregister_notifier(kvm, node);
4630 /* The return value indicates if tlb flush on all vcpus is needed. */
4631 typedef bool (*slot_level_handler) (struct kvm *kvm, struct kvm_rmap_head *rmap_head);
4633 /* The caller should hold mmu-lock before calling this function. */
4635 slot_handle_level_range(struct kvm *kvm, struct kvm_memory_slot *memslot,
4636 slot_level_handler fn, int start_level, int end_level,
4637 gfn_t start_gfn, gfn_t end_gfn, bool lock_flush_tlb)
4639 struct slot_rmap_walk_iterator iterator;
4642 for_each_slot_rmap_range(memslot, start_level, end_level, start_gfn,
4643 end_gfn, &iterator) {
4645 flush |= fn(kvm, iterator.rmap);
4647 if (need_resched() || spin_needbreak(&kvm->mmu_lock)) {
4648 if (flush && lock_flush_tlb) {
4649 kvm_flush_remote_tlbs(kvm);
4652 cond_resched_lock(&kvm->mmu_lock);
4656 if (flush && lock_flush_tlb) {
4657 kvm_flush_remote_tlbs(kvm);
4665 slot_handle_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
4666 slot_level_handler fn, int start_level, int end_level,
4667 bool lock_flush_tlb)
4669 return slot_handle_level_range(kvm, memslot, fn, start_level,
4670 end_level, memslot->base_gfn,
4671 memslot->base_gfn + memslot->npages - 1,
4676 slot_handle_all_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
4677 slot_level_handler fn, bool lock_flush_tlb)
4679 return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL,
4680 PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb);
4684 slot_handle_large_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
4685 slot_level_handler fn, bool lock_flush_tlb)
4687 return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL + 1,
4688 PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb);
4692 slot_handle_leaf(struct kvm *kvm, struct kvm_memory_slot *memslot,
4693 slot_level_handler fn, bool lock_flush_tlb)
4695 return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL,
4696 PT_PAGE_TABLE_LEVEL, lock_flush_tlb);
4699 void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end)
4701 struct kvm_memslots *slots;
4702 struct kvm_memory_slot *memslot;
4705 spin_lock(&kvm->mmu_lock);
4706 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
4707 slots = __kvm_memslots(kvm, i);
4708 kvm_for_each_memslot(memslot, slots) {
4711 start = max(gfn_start, memslot->base_gfn);
4712 end = min(gfn_end, memslot->base_gfn + memslot->npages);
4716 slot_handle_level_range(kvm, memslot, kvm_zap_rmapp,
4717 PT_PAGE_TABLE_LEVEL, PT_MAX_HUGEPAGE_LEVEL,
4718 start, end - 1, true);
4722 spin_unlock(&kvm->mmu_lock);
4725 static bool slot_rmap_write_protect(struct kvm *kvm,
4726 struct kvm_rmap_head *rmap_head)
4728 return __rmap_write_protect(kvm, rmap_head, false);
4731 void kvm_mmu_slot_remove_write_access(struct kvm *kvm,
4732 struct kvm_memory_slot *memslot)
4736 spin_lock(&kvm->mmu_lock);
4737 flush = slot_handle_all_level(kvm, memslot, slot_rmap_write_protect,
4739 spin_unlock(&kvm->mmu_lock);
4742 * kvm_mmu_slot_remove_write_access() and kvm_vm_ioctl_get_dirty_log()
4743 * which do tlb flush out of mmu-lock should be serialized by
4744 * kvm->slots_lock otherwise tlb flush would be missed.
4746 lockdep_assert_held(&kvm->slots_lock);
4749 * We can flush all the TLBs out of the mmu lock without TLB
4750 * corruption since we just change the spte from writable to
4751 * readonly so that we only need to care the case of changing
4752 * spte from present to present (changing the spte from present
4753 * to nonpresent will flush all the TLBs immediately), in other
4754 * words, the only case we care is mmu_spte_update() where we
4755 * haved checked SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE
4756 * instead of PT_WRITABLE_MASK, that means it does not depend
4757 * on PT_WRITABLE_MASK anymore.
4760 kvm_flush_remote_tlbs(kvm);
4763 static bool kvm_mmu_zap_collapsible_spte(struct kvm *kvm,
4764 struct kvm_rmap_head *rmap_head)
4767 struct rmap_iterator iter;
4768 int need_tlb_flush = 0;
4770 struct kvm_mmu_page *sp;
4773 for_each_rmap_spte(rmap_head, &iter, sptep) {
4774 sp = page_header(__pa(sptep));
4775 pfn = spte_to_pfn(*sptep);
4778 * We cannot do huge page mapping for indirect shadow pages,
4779 * which are found on the last rmap (level = 1) when not using
4780 * tdp; such shadow pages are synced with the page table in
4781 * the guest, and the guest page table is using 4K page size
4782 * mapping if the indirect sp has level = 1.
4784 if (sp->role.direct &&
4785 !kvm_is_reserved_pfn(pfn) &&
4786 PageTransCompoundMap(pfn_to_page(pfn))) {
4787 drop_spte(kvm, sptep);
4793 return need_tlb_flush;
4796 void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm,
4797 const struct kvm_memory_slot *memslot)
4799 /* FIXME: const-ify all uses of struct kvm_memory_slot. */
4800 spin_lock(&kvm->mmu_lock);
4801 slot_handle_leaf(kvm, (struct kvm_memory_slot *)memslot,
4802 kvm_mmu_zap_collapsible_spte, true);
4803 spin_unlock(&kvm->mmu_lock);
4806 void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm,
4807 struct kvm_memory_slot *memslot)
4811 spin_lock(&kvm->mmu_lock);
4812 flush = slot_handle_leaf(kvm, memslot, __rmap_clear_dirty, false);
4813 spin_unlock(&kvm->mmu_lock);
4815 lockdep_assert_held(&kvm->slots_lock);
4818 * It's also safe to flush TLBs out of mmu lock here as currently this
4819 * function is only used for dirty logging, in which case flushing TLB
4820 * out of mmu lock also guarantees no dirty pages will be lost in
4824 kvm_flush_remote_tlbs(kvm);
4826 EXPORT_SYMBOL_GPL(kvm_mmu_slot_leaf_clear_dirty);
4828 void kvm_mmu_slot_largepage_remove_write_access(struct kvm *kvm,
4829 struct kvm_memory_slot *memslot)
4833 spin_lock(&kvm->mmu_lock);
4834 flush = slot_handle_large_level(kvm, memslot, slot_rmap_write_protect,
4836 spin_unlock(&kvm->mmu_lock);
4838 /* see kvm_mmu_slot_remove_write_access */
4839 lockdep_assert_held(&kvm->slots_lock);
4842 kvm_flush_remote_tlbs(kvm);
4844 EXPORT_SYMBOL_GPL(kvm_mmu_slot_largepage_remove_write_access);
4846 void kvm_mmu_slot_set_dirty(struct kvm *kvm,
4847 struct kvm_memory_slot *memslot)
4851 spin_lock(&kvm->mmu_lock);
4852 flush = slot_handle_all_level(kvm, memslot, __rmap_set_dirty, false);
4853 spin_unlock(&kvm->mmu_lock);
4855 lockdep_assert_held(&kvm->slots_lock);
4857 /* see kvm_mmu_slot_leaf_clear_dirty */
4859 kvm_flush_remote_tlbs(kvm);
4861 EXPORT_SYMBOL_GPL(kvm_mmu_slot_set_dirty);
4863 #define BATCH_ZAP_PAGES 10
4864 static void kvm_zap_obsolete_pages(struct kvm *kvm)
4866 struct kvm_mmu_page *sp, *node;
4870 list_for_each_entry_safe_reverse(sp, node,
4871 &kvm->arch.active_mmu_pages, link) {
4875 * No obsolete page exists before new created page since
4876 * active_mmu_pages is the FIFO list.
4878 if (!is_obsolete_sp(kvm, sp))
4882 * Since we are reversely walking the list and the invalid
4883 * list will be moved to the head, skip the invalid page
4884 * can help us to avoid the infinity list walking.
4886 if (sp->role.invalid)
4890 * Need not flush tlb since we only zap the sp with invalid
4891 * generation number.
4893 if (batch >= BATCH_ZAP_PAGES &&
4894 cond_resched_lock(&kvm->mmu_lock)) {
4899 ret = kvm_mmu_prepare_zap_page(kvm, sp,
4900 &kvm->arch.zapped_obsolete_pages);
4908 * Should flush tlb before free page tables since lockless-walking
4909 * may use the pages.
4911 kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages);
4915 * Fast invalidate all shadow pages and use lock-break technique
4916 * to zap obsolete pages.
4918 * It's required when memslot is being deleted or VM is being
4919 * destroyed, in these cases, we should ensure that KVM MMU does
4920 * not use any resource of the being-deleted slot or all slots
4921 * after calling the function.
4923 void kvm_mmu_invalidate_zap_all_pages(struct kvm *kvm)
4925 spin_lock(&kvm->mmu_lock);
4926 trace_kvm_mmu_invalidate_zap_all_pages(kvm);
4927 kvm->arch.mmu_valid_gen++;
4930 * Notify all vcpus to reload its shadow page table
4931 * and flush TLB. Then all vcpus will switch to new
4932 * shadow page table with the new mmu_valid_gen.
4934 * Note: we should do this under the protection of
4935 * mmu-lock, otherwise, vcpu would purge shadow page
4936 * but miss tlb flush.
4938 kvm_reload_remote_mmus(kvm);
4940 kvm_zap_obsolete_pages(kvm);
4941 spin_unlock(&kvm->mmu_lock);
4944 static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm)
4946 return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages));
4949 void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, struct kvm_memslots *slots)
4952 * The very rare case: if the generation-number is round,
4953 * zap all shadow pages.
4955 if (unlikely((slots->generation & MMIO_GEN_MASK) == 0)) {
4956 printk_ratelimited(KERN_DEBUG "kvm: zapping shadow pages for mmio generation wraparound\n");
4957 kvm_mmu_invalidate_zap_all_pages(kvm);
4961 static unsigned long
4962 mmu_shrink_scan(struct shrinker *shrink, struct shrink_control *sc)
4965 int nr_to_scan = sc->nr_to_scan;
4966 unsigned long freed = 0;
4968 spin_lock(&kvm_lock);
4970 list_for_each_entry(kvm, &vm_list, vm_list) {
4972 LIST_HEAD(invalid_list);
4975 * Never scan more than sc->nr_to_scan VM instances.
4976 * Will not hit this condition practically since we do not try
4977 * to shrink more than one VM and it is very unlikely to see
4978 * !n_used_mmu_pages so many times.
4983 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
4984 * here. We may skip a VM instance errorneosly, but we do not
4985 * want to shrink a VM that only started to populate its MMU
4988 if (!kvm->arch.n_used_mmu_pages &&
4989 !kvm_has_zapped_obsolete_pages(kvm))
4992 idx = srcu_read_lock(&kvm->srcu);
4993 spin_lock(&kvm->mmu_lock);
4995 if (kvm_has_zapped_obsolete_pages(kvm)) {
4996 kvm_mmu_commit_zap_page(kvm,
4997 &kvm->arch.zapped_obsolete_pages);
5001 if (prepare_zap_oldest_mmu_page(kvm, &invalid_list))
5003 kvm_mmu_commit_zap_page(kvm, &invalid_list);
5006 spin_unlock(&kvm->mmu_lock);
5007 srcu_read_unlock(&kvm->srcu, idx);
5010 * unfair on small ones
5011 * per-vm shrinkers cry out
5012 * sadness comes quickly
5014 list_move_tail(&kvm->vm_list, &vm_list);
5018 spin_unlock(&kvm_lock);
5022 static unsigned long
5023 mmu_shrink_count(struct shrinker *shrink, struct shrink_control *sc)
5025 return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
5028 static struct shrinker mmu_shrinker = {
5029 .count_objects = mmu_shrink_count,
5030 .scan_objects = mmu_shrink_scan,
5031 .seeks = DEFAULT_SEEKS * 10,
5034 static void mmu_destroy_caches(void)
5036 if (pte_list_desc_cache)
5037 kmem_cache_destroy(pte_list_desc_cache);
5038 if (mmu_page_header_cache)
5039 kmem_cache_destroy(mmu_page_header_cache);
5042 int kvm_mmu_module_init(void)
5044 pte_list_desc_cache = kmem_cache_create("pte_list_desc",
5045 sizeof(struct pte_list_desc),
5047 if (!pte_list_desc_cache)
5050 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
5051 sizeof(struct kvm_mmu_page),
5053 if (!mmu_page_header_cache)
5056 if (percpu_counter_init(&kvm_total_used_mmu_pages, 0, GFP_KERNEL))
5059 register_shrinker(&mmu_shrinker);
5064 mmu_destroy_caches();
5069 * Caculate mmu pages needed for kvm.
5071 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
5073 unsigned int nr_mmu_pages;
5074 unsigned int nr_pages = 0;
5075 struct kvm_memslots *slots;
5076 struct kvm_memory_slot *memslot;
5079 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
5080 slots = __kvm_memslots(kvm, i);
5082 kvm_for_each_memslot(memslot, slots)
5083 nr_pages += memslot->npages;
5086 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
5087 nr_mmu_pages = max(nr_mmu_pages,
5088 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
5090 return nr_mmu_pages;
5093 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
5095 kvm_mmu_unload(vcpu);
5096 free_mmu_pages(vcpu);
5097 mmu_free_memory_caches(vcpu);
5100 void kvm_mmu_module_exit(void)
5102 mmu_destroy_caches();
5103 percpu_counter_destroy(&kvm_total_used_mmu_pages);
5104 unregister_shrinker(&mmu_shrinker);
5105 mmu_audit_disable();