1 #include <linux/errno.h>
2 #include <linux/kernel.h>
5 #include <linux/prctl.h>
6 #include <linux/slab.h>
7 #include <linux/sched.h>
8 #include <linux/module.h>
10 #include <linux/clockchips.h>
11 #include <linux/random.h>
12 #include <trace/events/power.h>
13 #include <asm/system.h>
15 #include <asm/syscalls.h>
17 #include <asm/uaccess.h>
21 unsigned long idle_halt;
22 EXPORT_SYMBOL(idle_halt);
23 unsigned long idle_nomwait;
24 EXPORT_SYMBOL(idle_nomwait);
26 struct kmem_cache *task_xstate_cachep;
28 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
31 if (src->thread.xstate) {
32 dst->thread.xstate = kmem_cache_alloc(task_xstate_cachep,
34 if (!dst->thread.xstate)
36 WARN_ON((unsigned long)dst->thread.xstate & 15);
37 memcpy(dst->thread.xstate, src->thread.xstate, xstate_size);
42 void free_thread_xstate(struct task_struct *tsk)
44 if (tsk->thread.xstate) {
45 kmem_cache_free(task_xstate_cachep, tsk->thread.xstate);
46 tsk->thread.xstate = NULL;
49 WARN(tsk->thread.ds_ctx, "leaking DS context\n");
52 void free_thread_info(struct thread_info *ti)
54 free_thread_xstate(ti->task);
55 free_pages((unsigned long)ti, get_order(THREAD_SIZE));
58 void arch_task_cache_init(void)
61 kmem_cache_create("task_xstate", xstate_size,
62 __alignof__(union thread_xstate),
63 SLAB_PANIC | SLAB_NOTRACK, NULL);
67 * Free current thread data structures etc..
69 void exit_thread(void)
71 struct task_struct *me = current;
72 struct thread_struct *t = &me->thread;
73 unsigned long *bp = t->io_bitmap_ptr;
76 struct tss_struct *tss = &per_cpu(init_tss, get_cpu());
78 t->io_bitmap_ptr = NULL;
79 clear_thread_flag(TIF_IO_BITMAP);
81 * Careful, clear this in the TSS too:
83 memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
90 void flush_thread(void)
92 struct task_struct *tsk = current;
95 if (test_tsk_thread_flag(tsk, TIF_ABI_PENDING)) {
96 clear_tsk_thread_flag(tsk, TIF_ABI_PENDING);
97 if (test_tsk_thread_flag(tsk, TIF_IA32)) {
98 clear_tsk_thread_flag(tsk, TIF_IA32);
100 set_tsk_thread_flag(tsk, TIF_IA32);
101 current_thread_info()->status |= TS_COMPAT;
106 clear_tsk_thread_flag(tsk, TIF_DEBUG);
108 tsk->thread.debugreg0 = 0;
109 tsk->thread.debugreg1 = 0;
110 tsk->thread.debugreg2 = 0;
111 tsk->thread.debugreg3 = 0;
112 tsk->thread.debugreg6 = 0;
113 tsk->thread.debugreg7 = 0;
114 memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
116 * Forget coprocessor state..
118 tsk->fpu_counter = 0;
123 static void hard_disable_TSC(void)
125 write_cr4(read_cr4() | X86_CR4_TSD);
128 void disable_TSC(void)
131 if (!test_and_set_thread_flag(TIF_NOTSC))
133 * Must flip the CPU state synchronously with
134 * TIF_NOTSC in the current running context.
140 static void hard_enable_TSC(void)
142 write_cr4(read_cr4() & ~X86_CR4_TSD);
145 static void enable_TSC(void)
148 if (test_and_clear_thread_flag(TIF_NOTSC))
150 * Must flip the CPU state synchronously with
151 * TIF_NOTSC in the current running context.
157 int get_tsc_mode(unsigned long adr)
161 if (test_thread_flag(TIF_NOTSC))
162 val = PR_TSC_SIGSEGV;
166 return put_user(val, (unsigned int __user *)adr);
169 int set_tsc_mode(unsigned int val)
171 if (val == PR_TSC_SIGSEGV)
173 else if (val == PR_TSC_ENABLE)
181 void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
182 struct tss_struct *tss)
184 struct thread_struct *prev, *next;
186 prev = &prev_p->thread;
187 next = &next_p->thread;
189 if (test_tsk_thread_flag(next_p, TIF_DS_AREA_MSR) ||
190 test_tsk_thread_flag(prev_p, TIF_DS_AREA_MSR))
191 ds_switch_to(prev_p, next_p);
192 else if (next->debugctlmsr != prev->debugctlmsr)
193 update_debugctlmsr(next->debugctlmsr);
195 if (test_tsk_thread_flag(next_p, TIF_DEBUG)) {
196 set_debugreg(next->debugreg0, 0);
197 set_debugreg(next->debugreg1, 1);
198 set_debugreg(next->debugreg2, 2);
199 set_debugreg(next->debugreg3, 3);
201 set_debugreg(next->debugreg6, 6);
202 set_debugreg(next->debugreg7, 7);
205 if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
206 test_tsk_thread_flag(next_p, TIF_NOTSC)) {
207 /* prev and next are different */
208 if (test_tsk_thread_flag(next_p, TIF_NOTSC))
214 if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
216 * Copy the relevant range of the IO bitmap.
217 * Normally this is 128 bytes or less:
219 memcpy(tss->io_bitmap, next->io_bitmap_ptr,
220 max(prev->io_bitmap_max, next->io_bitmap_max));
221 } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) {
223 * Clear any possible leftover bits:
225 memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
229 int sys_fork(struct pt_regs *regs)
231 return do_fork(SIGCHLD, regs->sp, regs, 0, NULL, NULL);
235 * This is trivial, and on the face of it looks like it
236 * could equally well be done in user mode.
238 * Not so, for quite unobvious reasons - register pressure.
239 * In user mode vfork() cannot have a stack frame, and if
240 * done by calling the "clone()" system call directly, you
241 * do not have enough call-clobbered registers to hold all
242 * the information you need.
244 int sys_vfork(struct pt_regs *regs)
246 return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs->sp, regs, 0,
252 * Idle related variables and functions
254 unsigned long boot_option_idle_override = 0;
255 EXPORT_SYMBOL(boot_option_idle_override);
258 * Powermanagement idle function, if any..
260 void (*pm_idle)(void);
261 EXPORT_SYMBOL(pm_idle);
265 * This halt magic was a workaround for ancient floppy DMA
266 * wreckage. It should be safe to remove.
268 static int hlt_counter;
269 void disable_hlt(void)
273 EXPORT_SYMBOL(disable_hlt);
275 void enable_hlt(void)
279 EXPORT_SYMBOL(enable_hlt);
281 static inline int hlt_use_halt(void)
283 return (!hlt_counter && boot_cpu_data.hlt_works_ok);
286 static inline int hlt_use_halt(void)
293 * We use this if we don't have any better
296 void default_idle(void)
298 if (hlt_use_halt()) {
299 trace_power_start(POWER_CSTATE, 1);
300 current_thread_info()->status &= ~TS_POLLING;
302 * TS_POLLING-cleared state must be visible before we
308 safe_halt(); /* enables interrupts racelessly */
311 current_thread_info()->status |= TS_POLLING;
315 /* loop is done by the caller */
319 #ifdef CONFIG_APM_MODULE
320 EXPORT_SYMBOL(default_idle);
323 void stop_this_cpu(void *dummy)
329 set_cpu_online(smp_processor_id(), false);
330 disable_local_APIC();
333 if (hlt_works(smp_processor_id()))
338 static void do_nothing(void *unused)
343 * cpu_idle_wait - Used to ensure that all the CPUs discard old value of
344 * pm_idle and update to new pm_idle value. Required while changing pm_idle
345 * handler on SMP systems.
347 * Caller must have changed pm_idle to the new value before the call. Old
348 * pm_idle value will not be used by any CPU after the return of this function.
350 void cpu_idle_wait(void)
353 /* kick all the CPUs so that they exit out of pm_idle */
354 smp_call_function(do_nothing, NULL, 1);
356 EXPORT_SYMBOL_GPL(cpu_idle_wait);
359 * This uses new MONITOR/MWAIT instructions on P4 processors with PNI,
360 * which can obviate IPI to trigger checking of need_resched.
361 * We execute MONITOR against need_resched and enter optimized wait state
362 * through MWAIT. Whenever someone changes need_resched, we would be woken
363 * up from MWAIT (without an IPI).
365 * New with Core Duo processors, MWAIT can take some hints based on CPU
368 void mwait_idle_with_hints(unsigned long ax, unsigned long cx)
370 trace_power_start(POWER_CSTATE, (ax>>4)+1);
371 if (!need_resched()) {
372 if (cpu_has(¤t_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
373 clflush((void *)¤t_thread_info()->flags);
375 __monitor((void *)¤t_thread_info()->flags, 0, 0);
383 /* Default MONITOR/MWAIT with no hints, used for default C1 state */
384 static void mwait_idle(void)
386 if (!need_resched()) {
387 trace_power_start(POWER_CSTATE, 1);
388 if (cpu_has(¤t_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
389 clflush((void *)¤t_thread_info()->flags);
391 __monitor((void *)¤t_thread_info()->flags, 0, 0);
403 * On SMP it's slightly faster (but much more power-consuming!)
404 * to poll the ->work.need_resched flag instead of waiting for the
405 * cross-CPU IPI to arrive. Use this option with caution.
407 static void poll_idle(void)
409 trace_power_start(POWER_CSTATE, 0);
411 while (!need_resched())
417 * mwait selection logic:
419 * It depends on the CPU. For AMD CPUs that support MWAIT this is
420 * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings
421 * then depend on a clock divisor and current Pstate of the core. If
422 * all cores of a processor are in halt state (C1) the processor can
423 * enter the C1E (C1 enhanced) state. If mwait is used this will never
426 * idle=mwait overrides this decision and forces the usage of mwait.
428 static int __cpuinitdata force_mwait;
430 #define MWAIT_INFO 0x05
431 #define MWAIT_ECX_EXTENDED_INFO 0x01
432 #define MWAIT_EDX_C1 0xf0
434 static int __cpuinit mwait_usable(const struct cpuinfo_x86 *c)
436 u32 eax, ebx, ecx, edx;
441 if (c->cpuid_level < MWAIT_INFO)
444 cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx);
445 /* Check, whether EDX has extended info about MWAIT */
446 if (!(ecx & MWAIT_ECX_EXTENDED_INFO))
450 * edx enumeratios MONITOR/MWAIT extensions. Check, whether
453 return (edx & MWAIT_EDX_C1);
457 * Check for AMD CPUs, which have potentially C1E support
459 static int __cpuinit check_c1e_idle(const struct cpuinfo_x86 *c)
461 if (c->x86_vendor != X86_VENDOR_AMD)
467 /* Family 0x0f models < rev F do not have C1E */
468 if (c->x86 == 0x0f && c->x86_model < 0x40)
474 static cpumask_var_t c1e_mask;
475 static int c1e_detected;
477 void c1e_remove_cpu(int cpu)
479 if (c1e_mask != NULL)
480 cpumask_clear_cpu(cpu, c1e_mask);
484 * C1E aware idle routine. We check for C1E active in the interrupt
485 * pending message MSR. If we detect C1E, then we handle it the same
486 * way as C3 power states (local apic timer and TSC stop)
488 static void c1e_idle(void)
496 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
497 if (lo & K8_INTP_C1E_ACTIVE_MASK) {
499 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
500 mark_tsc_unstable("TSC halt in AMD C1E");
501 printk(KERN_INFO "System has AMD C1E enabled\n");
502 set_cpu_cap(&boot_cpu_data, X86_FEATURE_AMDC1E);
507 int cpu = smp_processor_id();
509 if (!cpumask_test_cpu(cpu, c1e_mask)) {
510 cpumask_set_cpu(cpu, c1e_mask);
512 * Force broadcast so ACPI can not interfere.
514 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
516 printk(KERN_INFO "Switch to broadcast mode on CPU%d\n",
519 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
524 * The switch back from broadcast mode needs to be
525 * called with interrupts disabled.
528 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
534 void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
537 if (pm_idle == poll_idle && smp_num_siblings > 1) {
538 printk(KERN_WARNING "WARNING: polling idle and HT enabled,"
539 " performance may degrade.\n");
545 if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) {
547 * One CPU supports mwait => All CPUs supports mwait
549 printk(KERN_INFO "using mwait in idle threads.\n");
550 pm_idle = mwait_idle;
551 } else if (check_c1e_idle(c)) {
552 printk(KERN_INFO "using C1E aware idle routine\n");
555 pm_idle = default_idle;
558 void __init init_c1e_mask(void)
560 /* If we're using c1e_idle, we need to allocate c1e_mask. */
561 if (pm_idle == c1e_idle) {
562 alloc_cpumask_var(&c1e_mask, GFP_KERNEL);
563 cpumask_clear(c1e_mask);
567 static int __init idle_setup(char *str)
572 if (!strcmp(str, "poll")) {
573 printk("using polling idle threads.\n");
575 } else if (!strcmp(str, "mwait"))
577 else if (!strcmp(str, "halt")) {
579 * When the boot option of idle=halt is added, halt is
580 * forced to be used for CPU idle. In such case CPU C2/C3
581 * won't be used again.
582 * To continue to load the CPU idle driver, don't touch
583 * the boot_option_idle_override.
585 pm_idle = default_idle;
588 } else if (!strcmp(str, "nomwait")) {
590 * If the boot option of "idle=nomwait" is added,
591 * it means that mwait will be disabled for CPU C2/C3
592 * states. In such case it won't touch the variable
593 * of boot_option_idle_override.
600 boot_option_idle_override = 1;
603 early_param("idle", idle_setup);
605 unsigned long arch_align_stack(unsigned long sp)
607 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
608 sp -= get_random_int() % 8192;
612 unsigned long arch_randomize_brk(struct mm_struct *mm)
614 unsigned long range_end = mm->brk + 0x02000000;
615 return randomize_range(mm->brk, range_end, 0) ? : mm->brk;