2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
13 #include <linux/thread_info.h>
14 #include <linux/capability.h>
15 #include <linux/miscdevice.h>
16 #include <linux/ratelimit.h>
17 #include <linux/kallsyms.h>
18 #include <linux/rcupdate.h>
19 #include <linux/kobject.h>
20 #include <linux/uaccess.h>
21 #include <linux/kdebug.h>
22 #include <linux/kernel.h>
23 #include <linux/percpu.h>
24 #include <linux/string.h>
25 #include <linux/device.h>
26 #include <linux/syscore_ops.h>
27 #include <linux/delay.h>
28 #include <linux/ctype.h>
29 #include <linux/sched.h>
30 #include <linux/sysfs.h>
31 #include <linux/types.h>
32 #include <linux/slab.h>
33 #include <linux/init.h>
34 #include <linux/kmod.h>
35 #include <linux/poll.h>
36 #include <linux/nmi.h>
37 #include <linux/cpu.h>
38 #include <linux/smp.h>
41 #include <linux/debugfs.h>
42 #include <linux/irq_work.h>
43 #include <linux/export.h>
45 #include <asm/processor.h>
46 #include <asm/traps.h>
47 #include <asm/tlbflush.h>
51 #include "mce-internal.h"
53 static DEFINE_MUTEX(mce_chrdev_read_mutex);
55 #define rcu_dereference_check_mce(p) \
57 rcu_lockdep_assert(rcu_read_lock_sched_held() || \
58 lockdep_is_held(&mce_chrdev_read_mutex), \
59 "suspicious rcu_dereference_check_mce() usage"); \
60 smp_load_acquire(&(p)); \
63 #define CREATE_TRACE_POINTS
64 #include <trace/events/mce.h>
66 #define SPINUNIT 100 /* 100ns */
68 DEFINE_PER_CPU(unsigned, mce_exception_count);
70 struct mce_bank *mce_banks __read_mostly;
71 struct mce_vendor_flags mce_flags __read_mostly;
73 struct mca_config mca_cfg __read_mostly = {
77 * 0: always panic on uncorrected errors, log corrected errors
78 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
79 * 2: SIGBUS or log uncorrected errors (if possible), log corr. errors
80 * 3: never panic or SIGBUS, log all errors (for testing only)
86 /* User mode helper program triggered by machine check event */
87 static unsigned long mce_need_notify;
88 static char mce_helper[128];
89 static char *mce_helper_argv[2] = { mce_helper, NULL };
91 static DECLARE_WAIT_QUEUE_HEAD(mce_chrdev_wait);
93 static DEFINE_PER_CPU(struct mce, mces_seen);
94 static int cpu_missing;
97 * MCA banks polled by the period polling timer for corrected events.
98 * With Intel CMCI, this only has MCA banks which do not support CMCI (if any).
100 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
101 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
105 * MCA banks controlled through firmware first for corrected errors.
106 * This is a global list of banks for which we won't enable CMCI and we
107 * won't poll. Firmware controls these banks and is responsible for
108 * reporting corrected errors through GHES. Uncorrected/recoverable
109 * errors are still notified through a machine check.
111 mce_banks_t mce_banks_ce_disabled;
113 static DEFINE_PER_CPU(struct work_struct, mce_work);
115 static void (*quirk_no_way_out)(int bank, struct mce *m, struct pt_regs *regs);
118 * CPU/chipset specific EDAC code can register a notifier call here to print
119 * MCE errors in a human-readable form.
121 static ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain);
123 /* Do initial initialization of a struct mce */
124 void mce_setup(struct mce *m)
126 memset(m, 0, sizeof(struct mce));
127 m->cpu = m->extcpu = smp_processor_id();
129 /* We hope get_seconds stays lockless */
130 m->time = get_seconds();
131 m->cpuvendor = boot_cpu_data.x86_vendor;
132 m->cpuid = cpuid_eax(1);
133 m->socketid = cpu_data(m->extcpu).phys_proc_id;
134 m->apicid = cpu_data(m->extcpu).initial_apicid;
135 rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap);
138 DEFINE_PER_CPU(struct mce, injectm);
139 EXPORT_PER_CPU_SYMBOL_GPL(injectm);
142 * Lockless MCE logging infrastructure.
143 * This avoids deadlocks on printk locks without having to break locks. Also
144 * separate MCEs from kernel messages to avoid bogus bug reports.
147 static struct mce_log mcelog = {
148 .signature = MCE_LOG_SIGNATURE,
150 .recordlen = sizeof(struct mce),
153 void mce_log(struct mce *mce)
155 unsigned next, entry;
157 /* Emit the trace record: */
158 trace_mce_record(mce);
160 atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, mce);
165 entry = rcu_dereference_check_mce(mcelog.next);
169 * When the buffer fills up discard new entries.
170 * Assume that the earlier errors are the more
173 if (entry >= MCE_LOG_LEN) {
174 set_bit(MCE_OVERFLOW,
175 (unsigned long *)&mcelog.flags);
178 /* Old left over entry. Skip: */
179 if (mcelog.entry[entry].finished) {
187 if (cmpxchg(&mcelog.next, entry, next) == entry)
190 memcpy(mcelog.entry + entry, mce, sizeof(struct mce));
192 mcelog.entry[entry].finished = 1;
196 set_bit(0, &mce_need_notify);
199 static void drain_mcelog_buffer(void)
201 unsigned int next, i, prev = 0;
203 next = ACCESS_ONCE(mcelog.next);
208 /* drain what was logged during boot */
209 for (i = prev; i < next; i++) {
210 unsigned long start = jiffies;
211 unsigned retries = 1;
213 m = &mcelog.entry[i];
215 while (!m->finished) {
216 if (time_after_eq(jiffies, start + 2*retries))
221 if (!m->finished && retries >= 4) {
222 pr_err("skipping error being logged currently!\n");
227 atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m);
230 memset(mcelog.entry + prev, 0, (next - prev) * sizeof(*m));
232 next = cmpxchg(&mcelog.next, prev, 0);
233 } while (next != prev);
237 void mce_register_decode_chain(struct notifier_block *nb)
239 atomic_notifier_chain_register(&x86_mce_decoder_chain, nb);
240 drain_mcelog_buffer();
242 EXPORT_SYMBOL_GPL(mce_register_decode_chain);
244 void mce_unregister_decode_chain(struct notifier_block *nb)
246 atomic_notifier_chain_unregister(&x86_mce_decoder_chain, nb);
248 EXPORT_SYMBOL_GPL(mce_unregister_decode_chain);
250 static void print_mce(struct mce *m)
254 pr_emerg(HW_ERR "CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n",
255 m->extcpu, m->mcgstatus, m->bank, m->status);
258 pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ",
259 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
262 if (m->cs == __KERNEL_CS)
263 print_symbol("{%s}", m->ip);
267 pr_emerg(HW_ERR "TSC %llx ", m->tsc);
269 pr_cont("ADDR %llx ", m->addr);
271 pr_cont("MISC %llx ", m->misc);
275 * Note this output is parsed by external tools and old fields
276 * should not be changed.
278 pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n",
279 m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid,
280 cpu_data(m->extcpu).microcode);
283 * Print out human-readable details about the MCE error,
284 * (if the CPU has an implementation for that)
286 ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m);
287 if (ret == NOTIFY_STOP)
290 pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n");
293 #define PANIC_TIMEOUT 5 /* 5 seconds */
295 static atomic_t mce_panicked;
297 static int fake_panic;
298 static atomic_t mce_fake_panicked;
300 /* Panic in progress. Enable interrupts and wait for final IPI */
301 static void wait_for_panic(void)
303 long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
307 while (timeout-- > 0)
309 if (panic_timeout == 0)
310 panic_timeout = mca_cfg.panic_timeout;
311 panic("Panicing machine check CPU died");
314 static void mce_panic(const char *msg, struct mce *final, char *exp)
320 * Make sure only one CPU runs in machine check panic
322 if (atomic_inc_return(&mce_panicked) > 1)
329 /* Don't log too much for fake panic */
330 if (atomic_inc_return(&mce_fake_panicked) > 1)
333 /* First print corrected ones that are still unlogged */
334 for (i = 0; i < MCE_LOG_LEN; i++) {
335 struct mce *m = &mcelog.entry[i];
336 if (!(m->status & MCI_STATUS_VAL))
338 if (!(m->status & MCI_STATUS_UC)) {
341 apei_err = apei_write_mce(m);
344 /* Now print uncorrected but with the final one last */
345 for (i = 0; i < MCE_LOG_LEN; i++) {
346 struct mce *m = &mcelog.entry[i];
347 if (!(m->status & MCI_STATUS_VAL))
349 if (!(m->status & MCI_STATUS_UC))
351 if (!final || memcmp(m, final, sizeof(struct mce))) {
354 apei_err = apei_write_mce(m);
360 apei_err = apei_write_mce(final);
363 pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n");
365 pr_emerg(HW_ERR "Machine check: %s\n", exp);
367 if (panic_timeout == 0)
368 panic_timeout = mca_cfg.panic_timeout;
371 pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg);
374 /* Support code for software error injection */
376 static int msr_to_offset(u32 msr)
378 unsigned bank = __this_cpu_read(injectm.bank);
380 if (msr == mca_cfg.rip_msr)
381 return offsetof(struct mce, ip);
382 if (msr == MSR_IA32_MCx_STATUS(bank))
383 return offsetof(struct mce, status);
384 if (msr == MSR_IA32_MCx_ADDR(bank))
385 return offsetof(struct mce, addr);
386 if (msr == MSR_IA32_MCx_MISC(bank))
387 return offsetof(struct mce, misc);
388 if (msr == MSR_IA32_MCG_STATUS)
389 return offsetof(struct mce, mcgstatus);
393 /* MSR access wrappers used for error injection */
394 static u64 mce_rdmsrl(u32 msr)
398 if (__this_cpu_read(injectm.finished)) {
399 int offset = msr_to_offset(msr);
403 return *(u64 *)((char *)this_cpu_ptr(&injectm) + offset);
406 if (rdmsrl_safe(msr, &v)) {
407 WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr);
409 * Return zero in case the access faulted. This should
410 * not happen normally but can happen if the CPU does
411 * something weird, or if the code is buggy.
419 static void mce_wrmsrl(u32 msr, u64 v)
421 if (__this_cpu_read(injectm.finished)) {
422 int offset = msr_to_offset(msr);
425 *(u64 *)((char *)this_cpu_ptr(&injectm) + offset) = v;
432 * Collect all global (w.r.t. this processor) status about this machine
433 * check into our "mce" struct so that we can use it later to assess
434 * the severity of the problem as we read per-bank specific details.
436 static inline void mce_gather_info(struct mce *m, struct pt_regs *regs)
440 m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
443 * Get the address of the instruction at the time of
444 * the machine check error.
446 if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) {
451 * When in VM86 mode make the cs look like ring 3
452 * always. This is a lie, but it's better than passing
453 * the additional vm86 bit around everywhere.
455 if (v8086_mode(regs))
458 /* Use accurate RIP reporting if available. */
460 m->ip = mce_rdmsrl(mca_cfg.rip_msr);
465 * Simple lockless ring to communicate PFNs from the exception handler with the
466 * process context work function. This is vastly simplified because there's
467 * only a single reader and a single writer.
469 #define MCE_RING_SIZE 16 /* we use one entry less */
472 unsigned short start;
474 unsigned long ring[MCE_RING_SIZE];
476 static DEFINE_PER_CPU(struct mce_ring, mce_ring);
478 /* Runs with CPU affinity in workqueue */
479 static int mce_ring_empty(void)
481 struct mce_ring *r = this_cpu_ptr(&mce_ring);
483 return r->start == r->end;
486 static int mce_ring_get(unsigned long *pfn)
493 r = this_cpu_ptr(&mce_ring);
494 if (r->start == r->end)
496 *pfn = r->ring[r->start];
497 r->start = (r->start + 1) % MCE_RING_SIZE;
504 /* Always runs in MCE context with preempt off */
505 static int mce_ring_add(unsigned long pfn)
507 struct mce_ring *r = this_cpu_ptr(&mce_ring);
510 next = (r->end + 1) % MCE_RING_SIZE;
511 if (next == r->start)
513 r->ring[r->end] = pfn;
519 int mce_available(struct cpuinfo_x86 *c)
521 if (mca_cfg.disabled)
523 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
526 static void mce_schedule_work(void)
528 if (!mce_ring_empty())
529 schedule_work(this_cpu_ptr(&mce_work));
532 static DEFINE_PER_CPU(struct irq_work, mce_irq_work);
534 static void mce_irq_work_cb(struct irq_work *entry)
540 static void mce_report_event(struct pt_regs *regs)
542 if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) {
545 * Triggering the work queue here is just an insurance
546 * policy in case the syscall exit notify handler
547 * doesn't run soon enough or ends up running on the
548 * wrong CPU (can happen when audit sleeps)
554 irq_work_queue(this_cpu_ptr(&mce_irq_work));
558 * Read ADDR and MISC registers.
560 static void mce_read_aux(struct mce *m, int i)
562 if (m->status & MCI_STATUS_MISCV)
563 m->misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
564 if (m->status & MCI_STATUS_ADDRV) {
565 m->addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
568 * Mask the reported address by the reported granularity.
570 if (mca_cfg.ser && (m->status & MCI_STATUS_MISCV)) {
571 u8 shift = MCI_MISC_ADDR_LSB(m->misc);
578 static bool memory_error(struct mce *m)
580 struct cpuinfo_x86 *c = &boot_cpu_data;
582 if (c->x86_vendor == X86_VENDOR_AMD) {
587 } else if (c->x86_vendor == X86_VENDOR_INTEL) {
589 * Intel SDM Volume 3B - 15.9.2 Compound Error Codes
591 * Bit 7 of the MCACOD field of IA32_MCi_STATUS is used for
592 * indicating a memory error. Bit 8 is used for indicating a
593 * cache hierarchy error. The combination of bit 2 and bit 3
594 * is used for indicating a `generic' cache hierarchy error
595 * But we can't just blindly check the above bits, because if
596 * bit 11 is set, then it is a bus/interconnect error - and
597 * either way the above bits just gives more detail on what
598 * bus/interconnect error happened. Note that bit 12 can be
599 * ignored, as it's the "filter" bit.
601 return (m->status & 0xef80) == BIT(7) ||
602 (m->status & 0xef00) == BIT(8) ||
603 (m->status & 0xeffc) == 0xc;
609 DEFINE_PER_CPU(unsigned, mce_poll_count);
612 * Poll for corrected events or events that happened before reset.
613 * Those are just logged through /dev/mcelog.
615 * This is executed in standard interrupt context.
617 * Note: spec recommends to panic for fatal unsignalled
618 * errors here. However this would be quite problematic --
619 * we would need to reimplement the Monarch handling and
620 * it would mess up the exclusion between exception handler
621 * and poll hander -- * so we skip this for now.
622 * These cases should not happen anyways, or only when the CPU
623 * is already totally * confused. In this case it's likely it will
624 * not fully execute the machine check handler either.
626 bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
628 bool error_logged = false;
633 this_cpu_inc(mce_poll_count);
635 mce_gather_info(&m, NULL);
637 for (i = 0; i < mca_cfg.banks; i++) {
638 if (!mce_banks[i].ctl || !test_bit(i, *b))
647 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
648 if (!(m.status & MCI_STATUS_VAL))
653 * Uncorrected or signalled events are handled by the exception
654 * handler when it is enabled, so don't process those here.
656 * TBD do the same check for MCI_STATUS_EN here?
658 if (!(flags & MCP_UC) &&
659 (m.status & (mca_cfg.ser ? MCI_STATUS_S : MCI_STATUS_UC)))
664 if (!(flags & MCP_TIMESTAMP))
667 severity = mce_severity(&m, mca_cfg.tolerant, NULL, false);
670 * In the cases where we don't have a valid address after all,
671 * do not add it into the ring buffer.
673 if (severity == MCE_DEFERRED_SEVERITY && memory_error(&m)) {
674 if (m.status & MCI_STATUS_ADDRV) {
675 mce_ring_add(m.addr >> PAGE_SHIFT);
681 * Don't get the IP here because it's unlikely to
682 * have anything to do with the actual error location.
684 if (!(flags & MCP_DONTLOG) && !mca_cfg.dont_log_ce) {
690 * Clear state for this bank.
692 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
696 * Don't clear MCG_STATUS here because it's only defined for
704 EXPORT_SYMBOL_GPL(machine_check_poll);
707 * Do a quick check if any of the events requires a panic.
708 * This decides if we keep the events around or clear them.
710 static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp,
711 struct pt_regs *regs)
716 for (i = 0; i < mca_cfg.banks; i++) {
717 m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
718 if (m->status & MCI_STATUS_VAL) {
719 __set_bit(i, validp);
720 if (quirk_no_way_out)
721 quirk_no_way_out(i, m, regs);
724 if (mce_severity(m, mca_cfg.tolerant, &tmp, true) >= MCE_PANIC_SEVERITY) {
733 * Variable to establish order between CPUs while scanning.
734 * Each CPU spins initially until executing is equal its number.
736 static atomic_t mce_executing;
739 * Defines order of CPUs on entry. First CPU becomes Monarch.
741 static atomic_t mce_callin;
744 * Check if a timeout waiting for other CPUs happened.
746 static int mce_timed_out(u64 *t, const char *msg)
749 * The others already did panic for some reason.
750 * Bail out like in a timeout.
751 * rmb() to tell the compiler that system_state
752 * might have been modified by someone else.
755 if (atomic_read(&mce_panicked))
757 if (!mca_cfg.monarch_timeout)
759 if ((s64)*t < SPINUNIT) {
760 if (mca_cfg.tolerant <= 1)
761 mce_panic(msg, NULL, NULL);
767 touch_nmi_watchdog();
772 * The Monarch's reign. The Monarch is the CPU who entered
773 * the machine check handler first. It waits for the others to
774 * raise the exception too and then grades them. When any
775 * error is fatal panic. Only then let the others continue.
777 * The other CPUs entering the MCE handler will be controlled by the
778 * Monarch. They are called Subjects.
780 * This way we prevent any potential data corruption in a unrecoverable case
781 * and also makes sure always all CPU's errors are examined.
783 * Also this detects the case of a machine check event coming from outer
784 * space (not detected by any CPUs) In this case some external agent wants
785 * us to shut down, so panic too.
787 * The other CPUs might still decide to panic if the handler happens
788 * in a unrecoverable place, but in this case the system is in a semi-stable
789 * state and won't corrupt anything by itself. It's ok to let the others
790 * continue for a bit first.
792 * All the spin loops have timeouts; when a timeout happens a CPU
793 * typically elects itself to be Monarch.
795 static void mce_reign(void)
798 struct mce *m = NULL;
799 int global_worst = 0;
804 * This CPU is the Monarch and the other CPUs have run
805 * through their handlers.
806 * Grade the severity of the errors of all the CPUs.
808 for_each_possible_cpu(cpu) {
809 int severity = mce_severity(&per_cpu(mces_seen, cpu),
812 if (severity > global_worst) {
814 global_worst = severity;
815 m = &per_cpu(mces_seen, cpu);
820 * Cannot recover? Panic here then.
821 * This dumps all the mces in the log buffer and stops the
824 if (m && global_worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3)
825 mce_panic("Fatal machine check", m, msg);
828 * For UC somewhere we let the CPU who detects it handle it.
829 * Also must let continue the others, otherwise the handling
830 * CPU could deadlock on a lock.
834 * No machine check event found. Must be some external
835 * source or one CPU is hung. Panic.
837 if (global_worst <= MCE_KEEP_SEVERITY && mca_cfg.tolerant < 3)
838 mce_panic("Fatal machine check from unknown source", NULL, NULL);
841 * Now clear all the mces_seen so that they don't reappear on
844 for_each_possible_cpu(cpu)
845 memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce));
848 static atomic_t global_nwo;
851 * Start of Monarch synchronization. This waits until all CPUs have
852 * entered the exception handler and then determines if any of them
853 * saw a fatal event that requires panic. Then it executes them
854 * in the entry order.
855 * TBD double check parallel CPU hotunplug
857 static int mce_start(int *no_way_out)
860 int cpus = num_online_cpus();
861 u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC;
866 atomic_add(*no_way_out, &global_nwo);
868 * global_nwo should be updated before mce_callin
871 order = atomic_inc_return(&mce_callin);
876 while (atomic_read(&mce_callin) != cpus) {
877 if (mce_timed_out(&timeout,
878 "Timeout: Not all CPUs entered broadcast exception handler")) {
879 atomic_set(&global_nwo, 0);
886 * mce_callin should be read before global_nwo
892 * Monarch: Starts executing now, the others wait.
894 atomic_set(&mce_executing, 1);
897 * Subject: Now start the scanning loop one by one in
898 * the original callin order.
899 * This way when there are any shared banks it will be
900 * only seen by one CPU before cleared, avoiding duplicates.
902 while (atomic_read(&mce_executing) < order) {
903 if (mce_timed_out(&timeout,
904 "Timeout: Subject CPUs unable to finish machine check processing")) {
905 atomic_set(&global_nwo, 0);
913 * Cache the global no_way_out state.
915 *no_way_out = atomic_read(&global_nwo);
921 * Synchronize between CPUs after main scanning loop.
922 * This invokes the bulk of the Monarch processing.
924 static int mce_end(int order)
927 u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC;
935 * Allow others to run.
937 atomic_inc(&mce_executing);
940 /* CHECKME: Can this race with a parallel hotplug? */
941 int cpus = num_online_cpus();
944 * Monarch: Wait for everyone to go through their scanning
947 while (atomic_read(&mce_executing) <= cpus) {
948 if (mce_timed_out(&timeout,
949 "Timeout: Monarch CPU unable to finish machine check processing"))
959 * Subject: Wait for Monarch to finish.
961 while (atomic_read(&mce_executing) != 0) {
962 if (mce_timed_out(&timeout,
963 "Timeout: Monarch CPU did not finish machine check processing"))
969 * Don't reset anything. That's done by the Monarch.
975 * Reset all global state.
978 atomic_set(&global_nwo, 0);
979 atomic_set(&mce_callin, 0);
983 * Let others run again.
985 atomic_set(&mce_executing, 0);
990 * Check if the address reported by the CPU is in a format we can parse.
991 * It would be possible to add code for most other cases, but all would
992 * be somewhat complicated (e.g. segment offset would require an instruction
993 * parser). So only support physical addresses up to page granuality for now.
995 static int mce_usable_address(struct mce *m)
997 if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV))
999 if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT)
1001 if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS)
1006 static void mce_clear_state(unsigned long *toclear)
1010 for (i = 0; i < mca_cfg.banks; i++) {
1011 if (test_bit(i, toclear))
1012 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
1017 * The actual machine check handler. This only handles real
1018 * exceptions when something got corrupted coming in through int 18.
1020 * This is executed in NMI context not subject to normal locking rules. This
1021 * implies that most kernel services cannot be safely used. Don't even
1022 * think about putting a printk in there!
1024 * On Intel systems this is entered on all CPUs in parallel through
1025 * MCE broadcast. However some CPUs might be broken beyond repair,
1026 * so be always careful when synchronizing with others.
1028 void do_machine_check(struct pt_regs *regs, long error_code)
1030 struct mca_config *cfg = &mca_cfg;
1031 struct mce m, *final;
1032 enum ctx_state prev_state;
1037 * Establish sequential order between the CPUs entering the machine
1042 * If no_way_out gets set, there is no safe way to recover from this
1043 * MCE. If mca_cfg.tolerant is cranked up, we'll try anyway.
1047 * If kill_it gets set, there might be a way to recover from this
1051 DECLARE_BITMAP(toclear, MAX_NR_BANKS);
1052 DECLARE_BITMAP(valid_banks, MAX_NR_BANKS);
1053 char *msg = "Unknown";
1054 u64 recover_paddr = ~0ull;
1055 int flags = MF_ACTION_REQUIRED;
1058 prev_state = ist_enter(regs);
1060 this_cpu_inc(mce_exception_count);
1065 mce_gather_info(&m, regs);
1067 final = this_cpu_ptr(&mces_seen);
1070 memset(valid_banks, 0, sizeof(valid_banks));
1071 no_way_out = mce_no_way_out(&m, &msg, valid_banks, regs);
1076 * When no restart IP might need to kill or panic.
1077 * Assume the worst for now, but if we find the
1078 * severity is MCE_AR_SEVERITY we have other options.
1080 if (!(m.mcgstatus & MCG_STATUS_RIPV))
1084 * Check if this MCE is signaled to only this logical processor
1086 if (m.mcgstatus & MCG_STATUS_LMCES)
1090 * Go through all the banks in exclusion of the other CPUs.
1091 * This way we don't report duplicated events on shared banks
1092 * because the first one to see it will clear it.
1093 * If this is a Local MCE, then no need to perform rendezvous.
1095 order = mce_start(&no_way_out);
1098 for (i = 0; i < cfg->banks; i++) {
1099 __clear_bit(i, toclear);
1100 if (!test_bit(i, valid_banks))
1102 if (!mce_banks[i].ctl)
1109 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
1110 if ((m.status & MCI_STATUS_VAL) == 0)
1114 * Non uncorrected or non signaled errors are handled by
1115 * machine_check_poll. Leave them alone, unless this panics.
1117 if (!(m.status & (cfg->ser ? MCI_STATUS_S : MCI_STATUS_UC)) &&
1122 * Set taint even when machine check was not enabled.
1124 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
1126 severity = mce_severity(&m, cfg->tolerant, NULL, true);
1129 * When machine check was for corrected/deferred handler don't
1130 * touch, unless we're panicing.
1132 if ((severity == MCE_KEEP_SEVERITY ||
1133 severity == MCE_UCNA_SEVERITY) && !no_way_out)
1135 __set_bit(i, toclear);
1136 if (severity == MCE_NO_SEVERITY) {
1138 * Machine check event was not enabled. Clear, but
1144 mce_read_aux(&m, i);
1147 * Action optional error. Queue address for later processing.
1148 * When the ring overflows we just ignore the AO error.
1149 * RED-PEN add some logging mechanism when
1150 * usable_address or mce_add_ring fails.
1151 * RED-PEN don't ignore overflow for mca_cfg.tolerant == 0
1153 if (severity == MCE_AO_SEVERITY && mce_usable_address(&m))
1154 mce_ring_add(m.addr >> PAGE_SHIFT);
1158 if (severity > worst) {
1164 /* mce_clear_state will clear *final, save locally for use later */
1168 mce_clear_state(toclear);
1171 * Do most of the synchronization with other CPUs.
1172 * When there's any problem use only local no_way_out state.
1175 if (mce_end(order) < 0)
1176 no_way_out = worst >= MCE_PANIC_SEVERITY;
1179 * Local MCE skipped calling mce_reign()
1180 * If we found a fatal error, we need to panic here.
1182 if (worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3)
1183 mce_panic("Machine check from unknown source",
1188 * At insane "tolerant" levels we take no action. Otherwise
1189 * we only die if we have no other choice. For less serious
1190 * issues we try to recover, or limit damage to the current
1193 if (cfg->tolerant < 3) {
1195 mce_panic("Fatal machine check on current CPU", &m, msg);
1196 if (worst == MCE_AR_SEVERITY) {
1197 recover_paddr = m.addr;
1198 if (!(m.mcgstatus & MCG_STATUS_RIPV))
1199 flags |= MF_MUST_KILL;
1200 } else if (kill_it) {
1201 force_sig(SIGBUS, current);
1206 mce_report_event(regs);
1207 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1211 if (recover_paddr == ~0ull)
1214 pr_err("Uncorrected hardware memory error in user-access at %llx",
1217 * We must call memory_failure() here even if the current process is
1218 * doomed. We still need to mark the page as poisoned and alert any
1219 * other users of the page.
1221 ist_begin_non_atomic(regs);
1223 if (memory_failure(recover_paddr >> PAGE_SHIFT, MCE_VECTOR, flags) < 0) {
1224 pr_err("Memory error not recovered");
1225 force_sig(SIGBUS, current);
1227 local_irq_disable();
1228 ist_end_non_atomic();
1230 ist_exit(regs, prev_state);
1232 EXPORT_SYMBOL_GPL(do_machine_check);
1234 #ifndef CONFIG_MEMORY_FAILURE
1235 int memory_failure(unsigned long pfn, int vector, int flags)
1237 /* mce_severity() should not hand us an ACTION_REQUIRED error */
1238 BUG_ON(flags & MF_ACTION_REQUIRED);
1239 pr_err("Uncorrected memory error in page 0x%lx ignored\n"
1240 "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n",
1248 * Action optional processing happens here (picking up
1249 * from the list of faulting pages that do_machine_check()
1250 * placed into the "ring").
1252 static void mce_process_work(struct work_struct *dummy)
1256 while (mce_ring_get(&pfn))
1257 memory_failure(pfn, MCE_VECTOR, 0);
1260 #ifdef CONFIG_X86_MCE_INTEL
1262 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
1263 * @cpu: The CPU on which the event occurred.
1264 * @status: Event status information
1266 * This function should be called by the thermal interrupt after the
1267 * event has been processed and the decision was made to log the event
1270 * The status parameter will be saved to the 'status' field of 'struct mce'
1271 * and historically has been the register value of the
1272 * MSR_IA32_THERMAL_STATUS (Intel) msr.
1274 void mce_log_therm_throt_event(__u64 status)
1279 m.bank = MCE_THERMAL_BANK;
1283 #endif /* CONFIG_X86_MCE_INTEL */
1286 * Periodic polling timer for "silent" machine check errors. If the
1287 * poller finds an MCE, poll 2x faster. When the poller finds no more
1288 * errors, poll 2x slower (up to check_interval seconds).
1290 static unsigned long check_interval = INITIAL_CHECK_INTERVAL;
1292 static DEFINE_PER_CPU(unsigned long, mce_next_interval); /* in jiffies */
1293 static DEFINE_PER_CPU(struct timer_list, mce_timer);
1295 static unsigned long mce_adjust_timer_default(unsigned long interval)
1300 static unsigned long (*mce_adjust_timer)(unsigned long interval) = mce_adjust_timer_default;
1302 static void __restart_timer(struct timer_list *t, unsigned long interval)
1304 unsigned long when = jiffies + interval;
1305 unsigned long flags;
1307 local_irq_save(flags);
1309 if (timer_pending(t)) {
1310 if (time_before(when, t->expires))
1311 mod_timer_pinned(t, when);
1313 t->expires = round_jiffies(when);
1314 add_timer_on(t, smp_processor_id());
1317 local_irq_restore(flags);
1320 static void mce_timer_fn(unsigned long data)
1322 struct timer_list *t = this_cpu_ptr(&mce_timer);
1323 int cpu = smp_processor_id();
1326 WARN_ON(cpu != data);
1328 iv = __this_cpu_read(mce_next_interval);
1330 if (mce_available(this_cpu_ptr(&cpu_info))) {
1331 machine_check_poll(MCP_TIMESTAMP, this_cpu_ptr(&mce_poll_banks));
1333 if (mce_intel_cmci_poll()) {
1334 iv = mce_adjust_timer(iv);
1340 * Alert userspace if needed. If we logged an MCE, reduce the polling
1341 * interval, otherwise increase the polling interval.
1343 if (mce_notify_irq())
1344 iv = max(iv / 2, (unsigned long) HZ/100);
1346 iv = min(iv * 2, round_jiffies_relative(check_interval * HZ));
1349 __this_cpu_write(mce_next_interval, iv);
1350 __restart_timer(t, iv);
1354 * Ensure that the timer is firing in @interval from now.
1356 void mce_timer_kick(unsigned long interval)
1358 struct timer_list *t = this_cpu_ptr(&mce_timer);
1359 unsigned long iv = __this_cpu_read(mce_next_interval);
1361 __restart_timer(t, interval);
1364 __this_cpu_write(mce_next_interval, interval);
1367 /* Must not be called in IRQ context where del_timer_sync() can deadlock */
1368 static void mce_timer_delete_all(void)
1372 for_each_online_cpu(cpu)
1373 del_timer_sync(&per_cpu(mce_timer, cpu));
1376 static void mce_do_trigger(struct work_struct *work)
1378 call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT);
1381 static DECLARE_WORK(mce_trigger_work, mce_do_trigger);
1384 * Notify the user(s) about new machine check events.
1385 * Can be called from interrupt context, but not from machine check/NMI
1388 int mce_notify_irq(void)
1390 /* Not more than two messages every minute */
1391 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
1393 if (test_and_clear_bit(0, &mce_need_notify)) {
1394 /* wake processes polling /dev/mcelog */
1395 wake_up_interruptible(&mce_chrdev_wait);
1398 schedule_work(&mce_trigger_work);
1400 if (__ratelimit(&ratelimit))
1401 pr_info(HW_ERR "Machine check events logged\n");
1407 EXPORT_SYMBOL_GPL(mce_notify_irq);
1409 static int __mcheck_cpu_mce_banks_init(void)
1412 u8 num_banks = mca_cfg.banks;
1414 mce_banks = kzalloc(num_banks * sizeof(struct mce_bank), GFP_KERNEL);
1418 for (i = 0; i < num_banks; i++) {
1419 struct mce_bank *b = &mce_banks[i];
1428 * Initialize Machine Checks for a CPU.
1430 static int __mcheck_cpu_cap_init(void)
1435 rdmsrl(MSR_IA32_MCG_CAP, cap);
1437 b = cap & MCG_BANKCNT_MASK;
1439 pr_info("CPU supports %d MCE banks\n", b);
1441 if (b > MAX_NR_BANKS) {
1442 pr_warn("Using only %u machine check banks out of %u\n",
1447 /* Don't support asymmetric configurations today */
1448 WARN_ON(mca_cfg.banks != 0 && b != mca_cfg.banks);
1452 int err = __mcheck_cpu_mce_banks_init();
1458 /* Use accurate RIP reporting if available. */
1459 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
1460 mca_cfg.rip_msr = MSR_IA32_MCG_EIP;
1462 if (cap & MCG_SER_P)
1468 static void __mcheck_cpu_init_generic(void)
1470 enum mcp_flags m_fl = 0;
1471 mce_banks_t all_banks;
1475 if (!mca_cfg.bootlog)
1479 * Log the machine checks left over from the previous reset.
1481 bitmap_fill(all_banks, MAX_NR_BANKS);
1482 machine_check_poll(MCP_UC | m_fl, &all_banks);
1484 cr4_set_bits(X86_CR4_MCE);
1486 rdmsrl(MSR_IA32_MCG_CAP, cap);
1487 if (cap & MCG_CTL_P)
1488 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
1490 for (i = 0; i < mca_cfg.banks; i++) {
1491 struct mce_bank *b = &mce_banks[i];
1495 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
1496 wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
1501 * During IFU recovery Sandy Bridge -EP4S processors set the RIPV and
1502 * EIPV bits in MCG_STATUS to zero on the affected logical processor (SDM
1503 * Vol 3B Table 15-20). But this confuses both the code that determines
1504 * whether the machine check occurred in kernel or user mode, and also
1505 * the severity assessment code. Pretend that EIPV was set, and take the
1506 * ip/cs values from the pt_regs that mce_gather_info() ignored earlier.
1508 static void quirk_sandybridge_ifu(int bank, struct mce *m, struct pt_regs *regs)
1512 if ((m->mcgstatus & (MCG_STATUS_EIPV|MCG_STATUS_RIPV)) != 0)
1514 if ((m->status & (MCI_STATUS_OVER|MCI_STATUS_UC|
1515 MCI_STATUS_EN|MCI_STATUS_MISCV|MCI_STATUS_ADDRV|
1516 MCI_STATUS_PCC|MCI_STATUS_S|MCI_STATUS_AR|
1518 (MCI_STATUS_UC|MCI_STATUS_EN|
1519 MCI_STATUS_MISCV|MCI_STATUS_ADDRV|MCI_STATUS_S|
1520 MCI_STATUS_AR|MCACOD_INSTR))
1523 m->mcgstatus |= MCG_STATUS_EIPV;
1528 /* Add per CPU specific workarounds here */
1529 static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
1531 struct mca_config *cfg = &mca_cfg;
1533 if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
1534 pr_info("unknown CPU type - not enabling MCE support\n");
1538 /* This should be disabled by the BIOS, but isn't always */
1539 if (c->x86_vendor == X86_VENDOR_AMD) {
1540 if (c->x86 == 15 && cfg->banks > 4) {
1542 * disable GART TBL walk error reporting, which
1543 * trips off incorrectly with the IOMMU & 3ware
1546 clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
1548 if (c->x86 <= 17 && cfg->bootlog < 0) {
1550 * Lots of broken BIOS around that don't clear them
1551 * by default and leave crap in there. Don't log:
1556 * Various K7s with broken bank 0 around. Always disable
1559 if (c->x86 == 6 && cfg->banks > 0)
1560 mce_banks[0].ctl = 0;
1563 * overflow_recov is supported for F15h Models 00h-0fh
1564 * even though we don't have a CPUID bit for it.
1566 if (c->x86 == 0x15 && c->x86_model <= 0xf)
1567 mce_flags.overflow_recov = 1;
1570 * Turn off MC4_MISC thresholding banks on those models since
1571 * they're not supported there.
1573 if (c->x86 == 0x15 &&
1574 (c->x86_model >= 0x10 && c->x86_model <= 0x1f)) {
1579 0x00000413, /* MC4_MISC0 */
1580 0xc0000408, /* MC4_MISC1 */
1583 rdmsrl(MSR_K7_HWCR, hwcr);
1585 /* McStatusWrEn has to be set */
1586 need_toggle = !(hwcr & BIT(18));
1589 wrmsrl(MSR_K7_HWCR, hwcr | BIT(18));
1591 /* Clear CntP bit safely */
1592 for (i = 0; i < ARRAY_SIZE(msrs); i++)
1593 msr_clear_bit(msrs[i], 62);
1595 /* restore old settings */
1597 wrmsrl(MSR_K7_HWCR, hwcr);
1601 if (c->x86_vendor == X86_VENDOR_INTEL) {
1603 * SDM documents that on family 6 bank 0 should not be written
1604 * because it aliases to another special BIOS controlled
1606 * But it's not aliased anymore on model 0x1a+
1607 * Don't ignore bank 0 completely because there could be a
1608 * valid event later, merely don't write CTL0.
1611 if (c->x86 == 6 && c->x86_model < 0x1A && cfg->banks > 0)
1612 mce_banks[0].init = 0;
1615 * All newer Intel systems support MCE broadcasting. Enable
1616 * synchronization with a one second timeout.
1618 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1619 cfg->monarch_timeout < 0)
1620 cfg->monarch_timeout = USEC_PER_SEC;
1623 * There are also broken BIOSes on some Pentium M and
1626 if (c->x86 == 6 && c->x86_model <= 13 && cfg->bootlog < 0)
1629 if (c->x86 == 6 && c->x86_model == 45)
1630 quirk_no_way_out = quirk_sandybridge_ifu;
1632 if (cfg->monarch_timeout < 0)
1633 cfg->monarch_timeout = 0;
1634 if (cfg->bootlog != 0)
1635 cfg->panic_timeout = 30;
1640 static int __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c)
1645 switch (c->x86_vendor) {
1646 case X86_VENDOR_INTEL:
1647 intel_p5_mcheck_init(c);
1650 case X86_VENDOR_CENTAUR:
1651 winchip_mcheck_init(c);
1659 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
1661 switch (c->x86_vendor) {
1662 case X86_VENDOR_INTEL:
1663 mce_intel_feature_init(c);
1664 mce_adjust_timer = cmci_intel_adjust_timer;
1667 case X86_VENDOR_AMD: {
1668 u32 ebx = cpuid_ebx(0x80000007);
1670 mce_amd_feature_init(c);
1671 mce_flags.overflow_recov = !!(ebx & BIT(0));
1672 mce_flags.succor = !!(ebx & BIT(1));
1681 static void mce_start_timer(unsigned int cpu, struct timer_list *t)
1683 unsigned long iv = check_interval * HZ;
1685 if (mca_cfg.ignore_ce || !iv)
1688 per_cpu(mce_next_interval, cpu) = iv;
1690 t->expires = round_jiffies(jiffies + iv);
1691 add_timer_on(t, cpu);
1694 static void __mcheck_cpu_init_timer(void)
1696 struct timer_list *t = this_cpu_ptr(&mce_timer);
1697 unsigned int cpu = smp_processor_id();
1699 setup_timer(t, mce_timer_fn, cpu);
1700 mce_start_timer(cpu, t);
1703 /* Handle unconfigured int18 (should never happen) */
1704 static void unexpected_machine_check(struct pt_regs *regs, long error_code)
1706 pr_err("CPU#%d: Unexpected int18 (Machine Check)\n",
1707 smp_processor_id());
1710 /* Call the installed machine check handler for this CPU setup. */
1711 void (*machine_check_vector)(struct pt_regs *, long error_code) =
1712 unexpected_machine_check;
1715 * Called for each booted CPU to set up machine checks.
1716 * Must be called with preempt off:
1718 void mcheck_cpu_init(struct cpuinfo_x86 *c)
1720 if (mca_cfg.disabled)
1723 if (__mcheck_cpu_ancient_init(c))
1726 if (!mce_available(c))
1729 if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) {
1730 mca_cfg.disabled = true;
1734 machine_check_vector = do_machine_check;
1736 __mcheck_cpu_init_generic();
1737 __mcheck_cpu_init_vendor(c);
1738 __mcheck_cpu_init_timer();
1739 INIT_WORK(this_cpu_ptr(&mce_work), mce_process_work);
1740 init_irq_work(this_cpu_ptr(&mce_irq_work), &mce_irq_work_cb);
1744 * mce_chrdev: Character device /dev/mcelog to read and clear the MCE log.
1747 static DEFINE_SPINLOCK(mce_chrdev_state_lock);
1748 static int mce_chrdev_open_count; /* #times opened */
1749 static int mce_chrdev_open_exclu; /* already open exclusive? */
1751 static int mce_chrdev_open(struct inode *inode, struct file *file)
1753 spin_lock(&mce_chrdev_state_lock);
1755 if (mce_chrdev_open_exclu ||
1756 (mce_chrdev_open_count && (file->f_flags & O_EXCL))) {
1757 spin_unlock(&mce_chrdev_state_lock);
1762 if (file->f_flags & O_EXCL)
1763 mce_chrdev_open_exclu = 1;
1764 mce_chrdev_open_count++;
1766 spin_unlock(&mce_chrdev_state_lock);
1768 return nonseekable_open(inode, file);
1771 static int mce_chrdev_release(struct inode *inode, struct file *file)
1773 spin_lock(&mce_chrdev_state_lock);
1775 mce_chrdev_open_count--;
1776 mce_chrdev_open_exclu = 0;
1778 spin_unlock(&mce_chrdev_state_lock);
1783 static void collect_tscs(void *data)
1785 unsigned long *cpu_tsc = (unsigned long *)data;
1787 rdtscll(cpu_tsc[smp_processor_id()]);
1790 static int mce_apei_read_done;
1792 /* Collect MCE record of previous boot in persistent storage via APEI ERST. */
1793 static int __mce_read_apei(char __user **ubuf, size_t usize)
1799 if (usize < sizeof(struct mce))
1802 rc = apei_read_mce(&m, &record_id);
1803 /* Error or no more MCE record */
1805 mce_apei_read_done = 1;
1807 * When ERST is disabled, mce_chrdev_read() should return
1808 * "no record" instead of "no device."
1815 if (copy_to_user(*ubuf, &m, sizeof(struct mce)))
1818 * In fact, we should have cleared the record after that has
1819 * been flushed to the disk or sent to network in
1820 * /sbin/mcelog, but we have no interface to support that now,
1821 * so just clear it to avoid duplication.
1823 rc = apei_clear_mce(record_id);
1825 mce_apei_read_done = 1;
1828 *ubuf += sizeof(struct mce);
1833 static ssize_t mce_chrdev_read(struct file *filp, char __user *ubuf,
1834 size_t usize, loff_t *off)
1836 char __user *buf = ubuf;
1837 unsigned long *cpu_tsc;
1838 unsigned prev, next;
1841 cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL);
1845 mutex_lock(&mce_chrdev_read_mutex);
1847 if (!mce_apei_read_done) {
1848 err = __mce_read_apei(&buf, usize);
1849 if (err || buf != ubuf)
1853 next = rcu_dereference_check_mce(mcelog.next);
1855 /* Only supports full reads right now */
1857 if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce))
1863 for (i = prev; i < next; i++) {
1864 unsigned long start = jiffies;
1865 struct mce *m = &mcelog.entry[i];
1867 while (!m->finished) {
1868 if (time_after_eq(jiffies, start + 2)) {
1869 memset(m, 0, sizeof(*m));
1875 err |= copy_to_user(buf, m, sizeof(*m));
1881 memset(mcelog.entry + prev, 0,
1882 (next - prev) * sizeof(struct mce));
1884 next = cmpxchg(&mcelog.next, prev, 0);
1885 } while (next != prev);
1887 synchronize_sched();
1890 * Collect entries that were still getting written before the
1893 on_each_cpu(collect_tscs, cpu_tsc, 1);
1895 for (i = next; i < MCE_LOG_LEN; i++) {
1896 struct mce *m = &mcelog.entry[i];
1898 if (m->finished && m->tsc < cpu_tsc[m->cpu]) {
1899 err |= copy_to_user(buf, m, sizeof(*m));
1902 memset(m, 0, sizeof(*m));
1910 mutex_unlock(&mce_chrdev_read_mutex);
1913 return err ? err : buf - ubuf;
1916 static unsigned int mce_chrdev_poll(struct file *file, poll_table *wait)
1918 poll_wait(file, &mce_chrdev_wait, wait);
1919 if (READ_ONCE(mcelog.next))
1920 return POLLIN | POLLRDNORM;
1921 if (!mce_apei_read_done && apei_check_mce())
1922 return POLLIN | POLLRDNORM;
1926 static long mce_chrdev_ioctl(struct file *f, unsigned int cmd,
1929 int __user *p = (int __user *)arg;
1931 if (!capable(CAP_SYS_ADMIN))
1935 case MCE_GET_RECORD_LEN:
1936 return put_user(sizeof(struct mce), p);
1937 case MCE_GET_LOG_LEN:
1938 return put_user(MCE_LOG_LEN, p);
1939 case MCE_GETCLEAR_FLAGS: {
1943 flags = mcelog.flags;
1944 } while (cmpxchg(&mcelog.flags, flags, 0) != flags);
1946 return put_user(flags, p);
1953 static ssize_t (*mce_write)(struct file *filp, const char __user *ubuf,
1954 size_t usize, loff_t *off);
1956 void register_mce_write_callback(ssize_t (*fn)(struct file *filp,
1957 const char __user *ubuf,
1958 size_t usize, loff_t *off))
1962 EXPORT_SYMBOL_GPL(register_mce_write_callback);
1964 static ssize_t mce_chrdev_write(struct file *filp, const char __user *ubuf,
1965 size_t usize, loff_t *off)
1968 return mce_write(filp, ubuf, usize, off);
1973 static const struct file_operations mce_chrdev_ops = {
1974 .open = mce_chrdev_open,
1975 .release = mce_chrdev_release,
1976 .read = mce_chrdev_read,
1977 .write = mce_chrdev_write,
1978 .poll = mce_chrdev_poll,
1979 .unlocked_ioctl = mce_chrdev_ioctl,
1980 .llseek = no_llseek,
1983 static struct miscdevice mce_chrdev_device = {
1989 static void __mce_disable_bank(void *arg)
1991 int bank = *((int *)arg);
1992 __clear_bit(bank, this_cpu_ptr(mce_poll_banks));
1993 cmci_disable_bank(bank);
1996 void mce_disable_bank(int bank)
1998 if (bank >= mca_cfg.banks) {
2000 "Ignoring request to disable invalid MCA bank %d.\n",
2004 set_bit(bank, mce_banks_ce_disabled);
2005 on_each_cpu(__mce_disable_bank, &bank, 1);
2009 * mce=off Disables machine check
2010 * mce=no_cmci Disables CMCI
2011 * mce=no_lmce Disables LMCE
2012 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
2013 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
2014 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
2015 * monarchtimeout is how long to wait for other CPUs on machine
2016 * check, or 0 to not wait
2017 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
2018 * mce=nobootlog Don't log MCEs from before booting.
2019 * mce=bios_cmci_threshold Don't program the CMCI threshold
2021 static int __init mcheck_enable(char *str)
2023 struct mca_config *cfg = &mca_cfg;
2031 if (!strcmp(str, "off"))
2032 cfg->disabled = true;
2033 else if (!strcmp(str, "no_cmci"))
2034 cfg->cmci_disabled = true;
2035 else if (!strcmp(str, "no_lmce"))
2036 cfg->lmce_disabled = true;
2037 else if (!strcmp(str, "dont_log_ce"))
2038 cfg->dont_log_ce = true;
2039 else if (!strcmp(str, "ignore_ce"))
2040 cfg->ignore_ce = true;
2041 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
2042 cfg->bootlog = (str[0] == 'b');
2043 else if (!strcmp(str, "bios_cmci_threshold"))
2044 cfg->bios_cmci_threshold = true;
2045 else if (isdigit(str[0])) {
2046 if (get_option(&str, &cfg->tolerant) == 2)
2047 get_option(&str, &(cfg->monarch_timeout));
2049 pr_info("mce argument %s ignored. Please use /sys\n", str);
2054 __setup("mce", mcheck_enable);
2056 int __init mcheck_init(void)
2058 mcheck_intel_therm_init();
2059 mcheck_vendor_init_severity();
2065 * mce_syscore: PM support
2069 * Disable machine checks on suspend and shutdown. We can't really handle
2072 static int mce_disable_error_reporting(void)
2076 for (i = 0; i < mca_cfg.banks; i++) {
2077 struct mce_bank *b = &mce_banks[i];
2080 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
2085 static int mce_syscore_suspend(void)
2087 return mce_disable_error_reporting();
2090 static void mce_syscore_shutdown(void)
2092 mce_disable_error_reporting();
2096 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
2097 * Only one CPU is active at this time, the others get re-added later using
2100 static void mce_syscore_resume(void)
2102 __mcheck_cpu_init_generic();
2103 __mcheck_cpu_init_vendor(raw_cpu_ptr(&cpu_info));
2106 static struct syscore_ops mce_syscore_ops = {
2107 .suspend = mce_syscore_suspend,
2108 .shutdown = mce_syscore_shutdown,
2109 .resume = mce_syscore_resume,
2113 * mce_device: Sysfs support
2116 static void mce_cpu_restart(void *data)
2118 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2120 __mcheck_cpu_init_generic();
2121 __mcheck_cpu_init_timer();
2124 /* Reinit MCEs after user configuration changes */
2125 static void mce_restart(void)
2127 mce_timer_delete_all();
2128 on_each_cpu(mce_cpu_restart, NULL, 1);
2131 /* Toggle features for corrected errors */
2132 static void mce_disable_cmci(void *data)
2134 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2139 static void mce_enable_ce(void *all)
2141 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2146 __mcheck_cpu_init_timer();
2149 static struct bus_type mce_subsys = {
2150 .name = "machinecheck",
2151 .dev_name = "machinecheck",
2154 DEFINE_PER_CPU(struct device *, mce_device);
2156 void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
2158 static inline struct mce_bank *attr_to_bank(struct device_attribute *attr)
2160 return container_of(attr, struct mce_bank, attr);
2163 static ssize_t show_bank(struct device *s, struct device_attribute *attr,
2166 return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl);
2169 static ssize_t set_bank(struct device *s, struct device_attribute *attr,
2170 const char *buf, size_t size)
2174 if (kstrtou64(buf, 0, &new) < 0)
2177 attr_to_bank(attr)->ctl = new;
2184 show_trigger(struct device *s, struct device_attribute *attr, char *buf)
2186 strcpy(buf, mce_helper);
2188 return strlen(mce_helper) + 1;
2191 static ssize_t set_trigger(struct device *s, struct device_attribute *attr,
2192 const char *buf, size_t siz)
2196 strncpy(mce_helper, buf, sizeof(mce_helper));
2197 mce_helper[sizeof(mce_helper)-1] = 0;
2198 p = strchr(mce_helper, '\n');
2203 return strlen(mce_helper) + !!p;
2206 static ssize_t set_ignore_ce(struct device *s,
2207 struct device_attribute *attr,
2208 const char *buf, size_t size)
2212 if (kstrtou64(buf, 0, &new) < 0)
2215 if (mca_cfg.ignore_ce ^ !!new) {
2217 /* disable ce features */
2218 mce_timer_delete_all();
2219 on_each_cpu(mce_disable_cmci, NULL, 1);
2220 mca_cfg.ignore_ce = true;
2222 /* enable ce features */
2223 mca_cfg.ignore_ce = false;
2224 on_each_cpu(mce_enable_ce, (void *)1, 1);
2230 static ssize_t set_cmci_disabled(struct device *s,
2231 struct device_attribute *attr,
2232 const char *buf, size_t size)
2236 if (kstrtou64(buf, 0, &new) < 0)
2239 if (mca_cfg.cmci_disabled ^ !!new) {
2242 on_each_cpu(mce_disable_cmci, NULL, 1);
2243 mca_cfg.cmci_disabled = true;
2246 mca_cfg.cmci_disabled = false;
2247 on_each_cpu(mce_enable_ce, NULL, 1);
2253 static ssize_t store_int_with_restart(struct device *s,
2254 struct device_attribute *attr,
2255 const char *buf, size_t size)
2257 ssize_t ret = device_store_int(s, attr, buf, size);
2262 static DEVICE_ATTR(trigger, 0644, show_trigger, set_trigger);
2263 static DEVICE_INT_ATTR(tolerant, 0644, mca_cfg.tolerant);
2264 static DEVICE_INT_ATTR(monarch_timeout, 0644, mca_cfg.monarch_timeout);
2265 static DEVICE_BOOL_ATTR(dont_log_ce, 0644, mca_cfg.dont_log_ce);
2267 static struct dev_ext_attribute dev_attr_check_interval = {
2268 __ATTR(check_interval, 0644, device_show_int, store_int_with_restart),
2272 static struct dev_ext_attribute dev_attr_ignore_ce = {
2273 __ATTR(ignore_ce, 0644, device_show_bool, set_ignore_ce),
2277 static struct dev_ext_attribute dev_attr_cmci_disabled = {
2278 __ATTR(cmci_disabled, 0644, device_show_bool, set_cmci_disabled),
2279 &mca_cfg.cmci_disabled
2282 static struct device_attribute *mce_device_attrs[] = {
2283 &dev_attr_tolerant.attr,
2284 &dev_attr_check_interval.attr,
2286 &dev_attr_monarch_timeout.attr,
2287 &dev_attr_dont_log_ce.attr,
2288 &dev_attr_ignore_ce.attr,
2289 &dev_attr_cmci_disabled.attr,
2293 static cpumask_var_t mce_device_initialized;
2295 static void mce_device_release(struct device *dev)
2300 /* Per cpu device init. All of the cpus still share the same ctrl bank: */
2301 static int mce_device_create(unsigned int cpu)
2307 if (!mce_available(&boot_cpu_data))
2310 dev = kzalloc(sizeof *dev, GFP_KERNEL);
2314 dev->bus = &mce_subsys;
2315 dev->release = &mce_device_release;
2317 err = device_register(dev);
2323 for (i = 0; mce_device_attrs[i]; i++) {
2324 err = device_create_file(dev, mce_device_attrs[i]);
2328 for (j = 0; j < mca_cfg.banks; j++) {
2329 err = device_create_file(dev, &mce_banks[j].attr);
2333 cpumask_set_cpu(cpu, mce_device_initialized);
2334 per_cpu(mce_device, cpu) = dev;
2339 device_remove_file(dev, &mce_banks[j].attr);
2342 device_remove_file(dev, mce_device_attrs[i]);
2344 device_unregister(dev);
2349 static void mce_device_remove(unsigned int cpu)
2351 struct device *dev = per_cpu(mce_device, cpu);
2354 if (!cpumask_test_cpu(cpu, mce_device_initialized))
2357 for (i = 0; mce_device_attrs[i]; i++)
2358 device_remove_file(dev, mce_device_attrs[i]);
2360 for (i = 0; i < mca_cfg.banks; i++)
2361 device_remove_file(dev, &mce_banks[i].attr);
2363 device_unregister(dev);
2364 cpumask_clear_cpu(cpu, mce_device_initialized);
2365 per_cpu(mce_device, cpu) = NULL;
2368 /* Make sure there are no machine checks on offlined CPUs. */
2369 static void mce_disable_cpu(void *h)
2371 unsigned long action = *(unsigned long *)h;
2374 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2377 if (!(action & CPU_TASKS_FROZEN))
2379 for (i = 0; i < mca_cfg.banks; i++) {
2380 struct mce_bank *b = &mce_banks[i];
2383 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
2387 static void mce_reenable_cpu(void *h)
2389 unsigned long action = *(unsigned long *)h;
2392 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2395 if (!(action & CPU_TASKS_FROZEN))
2397 for (i = 0; i < mca_cfg.banks; i++) {
2398 struct mce_bank *b = &mce_banks[i];
2401 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
2405 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
2407 mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
2409 unsigned int cpu = (unsigned long)hcpu;
2410 struct timer_list *t = &per_cpu(mce_timer, cpu);
2412 switch (action & ~CPU_TASKS_FROZEN) {
2414 mce_device_create(cpu);
2415 if (threshold_cpu_callback)
2416 threshold_cpu_callback(action, cpu);
2419 if (threshold_cpu_callback)
2420 threshold_cpu_callback(action, cpu);
2421 mce_device_remove(cpu);
2422 mce_intel_hcpu_update(cpu);
2424 /* intentionally ignoring frozen here */
2425 if (!(action & CPU_TASKS_FROZEN))
2428 case CPU_DOWN_PREPARE:
2429 smp_call_function_single(cpu, mce_disable_cpu, &action, 1);
2432 case CPU_DOWN_FAILED:
2433 smp_call_function_single(cpu, mce_reenable_cpu, &action, 1);
2434 mce_start_timer(cpu, t);
2441 static struct notifier_block mce_cpu_notifier = {
2442 .notifier_call = mce_cpu_callback,
2445 static __init void mce_init_banks(void)
2449 for (i = 0; i < mca_cfg.banks; i++) {
2450 struct mce_bank *b = &mce_banks[i];
2451 struct device_attribute *a = &b->attr;
2453 sysfs_attr_init(&a->attr);
2454 a->attr.name = b->attrname;
2455 snprintf(b->attrname, ATTR_LEN, "bank%d", i);
2457 a->attr.mode = 0644;
2458 a->show = show_bank;
2459 a->store = set_bank;
2463 static __init int mcheck_init_device(void)
2468 if (!mce_available(&boot_cpu_data)) {
2473 if (!zalloc_cpumask_var(&mce_device_initialized, GFP_KERNEL)) {
2480 err = subsys_system_register(&mce_subsys, NULL);
2484 cpu_notifier_register_begin();
2485 for_each_online_cpu(i) {
2486 err = mce_device_create(i);
2489 * Register notifier anyway (and do not unreg it) so
2490 * that we don't leave undeleted timers, see notifier
2493 __register_hotcpu_notifier(&mce_cpu_notifier);
2494 cpu_notifier_register_done();
2495 goto err_device_create;
2499 __register_hotcpu_notifier(&mce_cpu_notifier);
2500 cpu_notifier_register_done();
2502 register_syscore_ops(&mce_syscore_ops);
2504 /* register character device /dev/mcelog */
2505 err = misc_register(&mce_chrdev_device);
2512 unregister_syscore_ops(&mce_syscore_ops);
2516 * We didn't keep track of which devices were created above, but
2517 * even if we had, the set of online cpus might have changed.
2518 * Play safe and remove for every possible cpu, since
2519 * mce_device_remove() will do the right thing.
2521 for_each_possible_cpu(i)
2522 mce_device_remove(i);
2525 free_cpumask_var(mce_device_initialized);
2528 pr_err("Unable to init device /dev/mcelog (rc: %d)\n", err);
2532 device_initcall_sync(mcheck_init_device);
2535 * Old style boot options parsing. Only for compatibility.
2537 static int __init mcheck_disable(char *str)
2539 mca_cfg.disabled = true;
2542 __setup("nomce", mcheck_disable);
2544 #ifdef CONFIG_DEBUG_FS
2545 struct dentry *mce_get_debugfs_dir(void)
2547 static struct dentry *dmce;
2550 dmce = debugfs_create_dir("mce", NULL);
2555 static void mce_reset(void)
2558 atomic_set(&mce_fake_panicked, 0);
2559 atomic_set(&mce_executing, 0);
2560 atomic_set(&mce_callin, 0);
2561 atomic_set(&global_nwo, 0);
2564 static int fake_panic_get(void *data, u64 *val)
2570 static int fake_panic_set(void *data, u64 val)
2577 DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get,
2578 fake_panic_set, "%llu\n");
2580 static int __init mcheck_debugfs_init(void)
2582 struct dentry *dmce, *ffake_panic;
2584 dmce = mce_get_debugfs_dir();
2587 ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL,
2594 late_initcall(mcheck_debugfs_init);