arch/x86/kernel/cpu/bugs.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  *  Copyright (C) 1994  Linus Torvalds
   4  *
   5  *  Cyrix stuff, June 1998 by:
   6  *      - Rafael R. Reilova (moved everything from head.S),
   7  *        <rreilova@ececs.uc.edu>
   8  *      - Channing Corn (tests & fixes),
   9  *      - Andrew D. Balsa (code cleanup).
  10  */
  11 #include <linux/init.h>
  12 #include <linux/utsname.h>
  13 #include <linux/cpu.h>
  14 #include <linux/module.h>
  15 #include <linux/nospec.h>
  16 #include <linux/prctl.h>
  17 #include <linux/sched/smt.h>
  18
  19 #include <asm/spec-ctrl.h>
  20 #include <asm/cmdline.h>
  21 #include <asm/bugs.h>
  22 #include <asm/processor.h>
  23 #include <asm/processor-flags.h>
  24 #include <asm/fpu/internal.h>
  25 #include <asm/msr.h>
  26 #include <asm/vmx.h>
  27 #include <asm/paravirt.h>
  28 #include <asm/alternative.h>
  29 #include <asm/pgtable.h>
  30 #include <asm/set_memory.h>
  31 #include <asm/intel-family.h>
  32 #include <asm/e820/api.h>
  33 #include <asm/hypervisor.h>
  34
  35 #include "cpu.h"
  36
  37 static void __init spectre_v2_select_mitigation(void);
  38 static void __init ssb_select_mitigation(void);
  39 static void __init l1tf_select_mitigation(void);
  40
  41 /* The base value of the SPEC_CTRL MSR that always has to be preserved. */
  42 u64 x86_spec_ctrl_base;
  43 EXPORT_SYMBOL_GPL(x86_spec_ctrl_base);
  44 static DEFINE_MUTEX(spec_ctrl_mutex);
  45
  46 /*
  47  * The vendor and possibly platform specific bits which can be modified in
  48  * x86_spec_ctrl_base.
  49  */
  50 static u64 __ro_after_init x86_spec_ctrl_mask = SPEC_CTRL_IBRS;
  51
  52 /*
  53  * AMD specific MSR info for Speculative Store Bypass control.
  54  * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu().
  55  */
  56 u64 __ro_after_init x86_amd_ls_cfg_base;
  57 u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask;
  58
  59 /* Control conditional STIPB in switch_to() */
  60 DEFINE_STATIC_KEY_FALSE(switch_to_cond_stibp);
  61 /* Control conditional IBPB in switch_mm() */
  62 DEFINE_STATIC_KEY_FALSE(switch_mm_cond_ibpb);
  63 /* Control unconditional IBPB in switch_mm() */
  64 DEFINE_STATIC_KEY_FALSE(switch_mm_always_ibpb);
  65
  66 void __init check_bugs(void)
  67 {
  68         identify_boot_cpu();
  69
  70         /*
  71          * identify_boot_cpu() initialized SMT support information, let the
  72          * core code know.
  73          */
  74         cpu_smt_check_topology_early();
  75
  76         if (!IS_ENABLED(CONFIG_SMP)) {
  77                 pr_info("CPU: ");
  78                 print_cpu_info(&boot_cpu_data);
  79         }
  80
  81         /*
  82          * Read the SPEC_CTRL MSR to account for reserved bits which may
  83          * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
  84          * init code as it is not enumerated and depends on the family.
  85          */
  86         if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
  87                 rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
  88
  89         /* Allow STIBP in MSR_SPEC_CTRL if supported */
  90         if (boot_cpu_has(X86_FEATURE_STIBP))
  91                 x86_spec_ctrl_mask |= SPEC_CTRL_STIBP;
  92
  93         /* Select the proper spectre mitigation before patching alternatives */
  94         spectre_v2_select_mitigation();
  95
  96         /*
  97          * Select proper mitigation for any exposure to the Speculative Store
  98          * Bypass vulnerability.
  99          */
 100         ssb_select_mitigation();
 101
 102         l1tf_select_mitigation();
 103
 104 #ifdef CONFIG_X86_32
 105         /*
 106          * Check whether we are able to run this kernel safely on SMP.
 107          *
 108          * - i386 is no longer supported.
 109          * - In order to run on anything without a TSC, we need to be
 110          *   compiled for a i486.
 111          */
 112         if (boot_cpu_data.x86 < 4)
 113                 panic("Kernel requires i486+ for 'invlpg' and other features");
 114
 115         init_utsname()->machine[1] =
 116                 '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86);
 117         alternative_instructions();
 118
 119         fpu__init_check_bugs();
 120 #else /* CONFIG_X86_64 */
 121         alternative_instructions();
 122
 123         /*
 124          * Make sure the first 2MB area is not mapped by huge pages
 125          * There are typically fixed size MTRRs in there and overlapping
 126          * MTRRs into large pages causes slow downs.
 127          *
 128          * Right now we don't do that with gbpages because there seems
 129          * very little benefit for that case.
 130          */
 131         if (!direct_gbpages)
 132                 set_memory_4k((unsigned long)__va(0), 1);
 133 #endif
 134 }
 135
 136 void
 137 x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest)
 138 {
 139         u64 msrval, guestval, hostval = x86_spec_ctrl_base;
 140         struct thread_info *ti = current_thread_info();
 141
 142         /* Is MSR_SPEC_CTRL implemented ? */
 143         if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) {
 144                 /*
 145                  * Restrict guest_spec_ctrl to supported values. Clear the
 146                  * modifiable bits in the host base value and or the
 147                  * modifiable bits from the guest value.
 148                  */
 149                 guestval = hostval & ~x86_spec_ctrl_mask;
 150                 guestval |= guest_spec_ctrl & x86_spec_ctrl_mask;
 151
 152                 /* SSBD controlled in MSR_SPEC_CTRL */
 153                 if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) ||
 154                     static_cpu_has(X86_FEATURE_AMD_SSBD))
 155                         hostval |= ssbd_tif_to_spec_ctrl(ti->flags);
 156
 157                 /* Conditional STIBP enabled? */
 158                 if (static_branch_unlikely(&switch_to_cond_stibp))
 159                         hostval |= stibp_tif_to_spec_ctrl(ti->flags);
 160
 161                 if (hostval != guestval) {
 162                         msrval = setguest ? guestval : hostval;
 163                         wrmsrl(MSR_IA32_SPEC_CTRL, msrval);
 164                 }
 165         }
 166
 167         /*
 168          * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update
 169          * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported.
 170          */
 171         if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) &&
 172             !static_cpu_has(X86_FEATURE_VIRT_SSBD))
 173                 return;
 174
 175         /*
 176          * If the host has SSBD mitigation enabled, force it in the host's
 177          * virtual MSR value. If its not permanently enabled, evaluate
 178          * current's TIF_SSBD thread flag.
 179          */
 180         if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE))
 181                 hostval = SPEC_CTRL_SSBD;
 182         else
 183                 hostval = ssbd_tif_to_spec_ctrl(ti->flags);
 184
 185         /* Sanitize the guest value */
 186         guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD;
 187
 188         if (hostval != guestval) {
 189                 unsigned long tif;
 190
 191                 tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) :
 192                                  ssbd_spec_ctrl_to_tif(hostval);
 193
 194                 speculation_ctrl_update(tif);
 195         }
 196 }
 197 EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl);
 198
 199 static void x86_amd_ssb_disable(void)
 200 {
 201         u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask;
 202
 203         if (boot_cpu_has(X86_FEATURE_VIRT_SSBD))
 204                 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD);
 205         else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD))
 206                 wrmsrl(MSR_AMD64_LS_CFG, msrval);
 207 }
 208
 209 #undef pr_fmt
 210 #define pr_fmt(fmt)     "Spectre V2 : " fmt
 211
 212 static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init =
 213         SPECTRE_V2_NONE;
 214
 215 static enum spectre_v2_user_mitigation spectre_v2_user __ro_after_init =
 216         SPECTRE_V2_USER_NONE;
 217
 218 #ifdef RETPOLINE
 219 static bool spectre_v2_bad_module;
 220
 221 bool retpoline_module_ok(bool has_retpoline)
 222 {
 223         if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline)
 224                 return true;
 225
 226         pr_err("System may be vulnerable to spectre v2\n");
 227         spectre_v2_bad_module = true;
 228         return false;
 229 }
 230
 231 static inline const char *spectre_v2_module_string(void)
 232 {
 233         return spectre_v2_bad_module ? " - vulnerable module loaded" : "";
 234 }
 235 #else
 236 static inline const char *spectre_v2_module_string(void) { return ""; }
 237 #endif
 238
 239 static inline bool match_option(const char *arg, int arglen, const char *opt)
 240 {
 241         int len = strlen(opt);
 242
 243         return len == arglen && !strncmp(arg, opt, len);
 244 }
 245
 246 /* The kernel command line selection for spectre v2 */
 247 enum spectre_v2_mitigation_cmd {
 248         SPECTRE_V2_CMD_NONE,
 249         SPECTRE_V2_CMD_AUTO,
 250         SPECTRE_V2_CMD_FORCE,
 251         SPECTRE_V2_CMD_RETPOLINE,
 252         SPECTRE_V2_CMD_RETPOLINE_GENERIC,
 253         SPECTRE_V2_CMD_RETPOLINE_AMD,
 254 };
 255
 256 enum spectre_v2_user_cmd {
 257         SPECTRE_V2_USER_CMD_NONE,
 258         SPECTRE_V2_USER_CMD_AUTO,
 259         SPECTRE_V2_USER_CMD_FORCE,
 260         SPECTRE_V2_USER_CMD_PRCTL,
 261         SPECTRE_V2_USER_CMD_PRCTL_IBPB,
 262         SPECTRE_V2_USER_CMD_SECCOMP,
 263         SPECTRE_V2_USER_CMD_SECCOMP_IBPB,
 264 };
 265
 266 static const char * const spectre_v2_user_strings[] = {
 267         [SPECTRE_V2_USER_NONE]          = "User space: Vulnerable",
 268         [SPECTRE_V2_USER_STRICT]        = "User space: Mitigation: STIBP protection",
 269         [SPECTRE_V2_USER_PRCTL]         = "User space: Mitigation: STIBP via prctl",
 270         [SPECTRE_V2_USER_SECCOMP]       = "User space: Mitigation: STIBP via seccomp and prctl",
 271 };
 272
 273 static const struct {
 274         const char                      *option;
 275         enum spectre_v2_user_cmd        cmd;
 276         bool                            secure;
 277 } v2_user_options[] __initdata = {
 278         { "auto",               SPECTRE_V2_USER_CMD_AUTO,               false },
 279         { "off",                SPECTRE_V2_USER_CMD_NONE,               false },
 280         { "on",                 SPECTRE_V2_USER_CMD_FORCE,              true  },
 281         { "prctl",              SPECTRE_V2_USER_CMD_PRCTL,              false },
 282         { "prctl,ibpb",         SPECTRE_V2_USER_CMD_PRCTL_IBPB,         false },
 283         { "seccomp",            SPECTRE_V2_USER_CMD_SECCOMP,            false },
 284         { "seccomp,ibpb",       SPECTRE_V2_USER_CMD_SECCOMP_IBPB,       false },
 285 };
 286
 287 static void __init spec_v2_user_print_cond(const char *reason, bool secure)
 288 {
 289         if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure)
 290                 pr_info("spectre_v2_user=%s forced on command line.\n", reason);
 291 }
 292
 293 static enum spectre_v2_user_cmd __init
 294 spectre_v2_parse_user_cmdline(enum spectre_v2_mitigation_cmd v2_cmd)
 295 {
 296         char arg[20];
 297         int ret, i;
 298
 299         switch (v2_cmd) {
 300         case SPECTRE_V2_CMD_NONE:
 301                 return SPECTRE_V2_USER_CMD_NONE;
 302         case SPECTRE_V2_CMD_FORCE:
 303                 return SPECTRE_V2_USER_CMD_FORCE;
 304         default:
 305                 break;
 306         }
 307
 308         ret = cmdline_find_option(boot_command_line, "spectre_v2_user",
 309                                   arg, sizeof(arg));
 310         if (ret < 0)
 311                 return SPECTRE_V2_USER_CMD_AUTO;
 312
 313         for (i = 0; i < ARRAY_SIZE(v2_user_options); i++) {
 314                 if (match_option(arg, ret, v2_user_options[i].option)) {
 315                         spec_v2_user_print_cond(v2_user_options[i].option,
 316                                                 v2_user_options[i].secure);
 317                         return v2_user_options[i].cmd;
 318                 }
 319         }
 320
 321         pr_err("Unknown user space protection option (%s). Switching to AUTO select\n", arg);
 322         return SPECTRE_V2_USER_CMD_AUTO;
 323 }
 324
 325 static void __init
 326 spectre_v2_user_select_mitigation(enum spectre_v2_mitigation_cmd v2_cmd)
 327 {
 328         enum spectre_v2_user_mitigation mode = SPECTRE_V2_USER_NONE;
 329         bool smt_possible = IS_ENABLED(CONFIG_SMP);
 330         enum spectre_v2_user_cmd cmd;
 331
 332         if (!boot_cpu_has(X86_FEATURE_IBPB) && !boot_cpu_has(X86_FEATURE_STIBP))
 333                 return;
 334
 335         if (cpu_smt_control == CPU_SMT_FORCE_DISABLED ||
 336             cpu_smt_control == CPU_SMT_NOT_SUPPORTED)
 337                 smt_possible = false;
 338
 339         cmd = spectre_v2_parse_user_cmdline(v2_cmd);
 340         switch (cmd) {
 341         case SPECTRE_V2_USER_CMD_NONE:
 342                 goto set_mode;
 343         case SPECTRE_V2_USER_CMD_FORCE:
 344                 mode = SPECTRE_V2_USER_STRICT;
 345                 break;
 346         case SPECTRE_V2_USER_CMD_PRCTL:
 347         case SPECTRE_V2_USER_CMD_PRCTL_IBPB:
 348                 mode = SPECTRE_V2_USER_PRCTL;
 349                 break;
 350         case SPECTRE_V2_USER_CMD_AUTO:
 351         case SPECTRE_V2_USER_CMD_SECCOMP:
 352         case SPECTRE_V2_USER_CMD_SECCOMP_IBPB:
 353                 if (IS_ENABLED(CONFIG_SECCOMP))
 354                         mode = SPECTRE_V2_USER_SECCOMP;
 355                 else
 356                         mode = SPECTRE_V2_USER_PRCTL;
 357                 break;
 358         }
 359
 360         /* Initialize Indirect Branch Prediction Barrier */
 361         if (boot_cpu_has(X86_FEATURE_IBPB)) {
 362                 setup_force_cpu_cap(X86_FEATURE_USE_IBPB);
 363
 364                 switch (cmd) {
 365                 case SPECTRE_V2_USER_CMD_FORCE:
 366                 case SPECTRE_V2_USER_CMD_PRCTL_IBPB:
 367                 case SPECTRE_V2_USER_CMD_SECCOMP_IBPB:
 368                         static_branch_enable(&switch_mm_always_ibpb);
 369                         break;
 370                 case SPECTRE_V2_USER_CMD_PRCTL:
 371                 case SPECTRE_V2_USER_CMD_AUTO:
 372                 case SPECTRE_V2_USER_CMD_SECCOMP:
 373                         static_branch_enable(&switch_mm_cond_ibpb);
 374                         break;
 375                 default:
 376                         break;
 377                 }
 378
 379                 pr_info("mitigation: Enabling %s Indirect Branch Prediction Barrier\n",
 380                         static_key_enabled(&switch_mm_always_ibpb) ?
 381                         "always-on" : "conditional");
 382         }
 383
 384         /* If enhanced IBRS is enabled no STIPB required */
 385         if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED)
 386                 return;
 387
 388         /*
 389          * If SMT is not possible or STIBP is not available clear the STIPB
 390          * mode.
 391          */
 392         if (!smt_possible || !boot_cpu_has(X86_FEATURE_STIBP))
 393                 mode = SPECTRE_V2_USER_NONE;
 394 set_mode:
 395         spectre_v2_user = mode;
 396         /* Only print the STIBP mode when SMT possible */
 397         if (smt_possible)
 398                 pr_info("%s\n", spectre_v2_user_strings[mode]);
 399 }
 400
 401 static const char * const spectre_v2_strings[] = {
 402         [SPECTRE_V2_NONE]                       = "Vulnerable",
 403         [SPECTRE_V2_RETPOLINE_GENERIC]          = "Mitigation: Full generic retpoline",
 404         [SPECTRE_V2_RETPOLINE_AMD]              = "Mitigation: Full AMD retpoline",
 405         [SPECTRE_V2_IBRS_ENHANCED]              = "Mitigation: Enhanced IBRS",
 406 };
 407
 408 static const struct {
 409         const char *option;
 410         enum spectre_v2_mitigation_cmd cmd;
 411         bool secure;
 412 } mitigation_options[] __initdata = {
 413         { "off",                SPECTRE_V2_CMD_NONE,              false },
 414         { "on",                 SPECTRE_V2_CMD_FORCE,             true  },
 415         { "retpoline",          SPECTRE_V2_CMD_RETPOLINE,         false },
 416         { "retpoline,amd",      SPECTRE_V2_CMD_RETPOLINE_AMD,     false },
 417         { "retpoline,generic",  SPECTRE_V2_CMD_RETPOLINE_GENERIC, false },
 418         { "auto",               SPECTRE_V2_CMD_AUTO,              false },
 419 };
 420
 421 static void __init spec_v2_print_cond(const char *reason, bool secure)
 422 {
 423         if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure)
 424                 pr_info("%s selected on command line.\n", reason);
 425 }
 426
 427 static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void)
 428 {
 429         enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO;
 430         char arg[20];
 431         int ret, i;
 432
 433         if (cmdline_find_option_bool(boot_command_line, "nospectre_v2"))
 434                 return SPECTRE_V2_CMD_NONE;
 435
 436         ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg));
 437         if (ret < 0)
 438                 return SPECTRE_V2_CMD_AUTO;
 439
 440         for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) {
 441                 if (!match_option(arg, ret, mitigation_options[i].option))
 442                         continue;
 443                 cmd = mitigation_options[i].cmd;
 444                 break;
 445         }
 446
 447         if (i >= ARRAY_SIZE(mitigation_options)) {
 448                 pr_err("unknown option (%s). Switching to AUTO select\n", arg);
 449                 return SPECTRE_V2_CMD_AUTO;
 450         }
 451
 452         if ((cmd == SPECTRE_V2_CMD_RETPOLINE ||
 453              cmd == SPECTRE_V2_CMD_RETPOLINE_AMD ||
 454              cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC) &&
 455             !IS_ENABLED(CONFIG_RETPOLINE)) {
 456                 pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options[i].option);
 457                 return SPECTRE_V2_CMD_AUTO;
 458         }
 459
 460         if (cmd == SPECTRE_V2_CMD_RETPOLINE_AMD &&
 461             boot_cpu_data.x86_vendor != X86_VENDOR_HYGON &&
 462             boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
 463                 pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n");
 464                 return SPECTRE_V2_CMD_AUTO;
 465         }
 466
 467         spec_v2_print_cond(mitigation_options[i].option,
 468                            mitigation_options[i].secure);
 469         return cmd;
 470 }
 471
 472 static void __init spectre_v2_select_mitigation(void)
 473 {
 474         enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline();
 475         enum spectre_v2_mitigation mode = SPECTRE_V2_NONE;
 476
 477         /*
 478          * If the CPU is not affected and the command line mode is NONE or AUTO
 479          * then nothing to do.
 480          */
 481         if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) &&
 482             (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO))
 483                 return;
 484
 485         switch (cmd) {
 486         case SPECTRE_V2_CMD_NONE:
 487                 return;
 488
 489         case SPECTRE_V2_CMD_FORCE:
 490         case SPECTRE_V2_CMD_AUTO:
 491                 if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) {
 492                         mode = SPECTRE_V2_IBRS_ENHANCED;
 493                         /* Force it so VMEXIT will restore correctly */
 494                         x86_spec_ctrl_base |= SPEC_CTRL_IBRS;
 495                         wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
 496                         goto specv2_set_mode;
 497                 }
 498                 if (IS_ENABLED(CONFIG_RETPOLINE))
 499                         goto retpoline_auto;
 500                 break;
 501         case SPECTRE_V2_CMD_RETPOLINE_AMD:
 502                 if (IS_ENABLED(CONFIG_RETPOLINE))
 503                         goto retpoline_amd;
 504                 break;
 505         case SPECTRE_V2_CMD_RETPOLINE_GENERIC:
 506                 if (IS_ENABLED(CONFIG_RETPOLINE))
 507                         goto retpoline_generic;
 508                 break;
 509         case SPECTRE_V2_CMD_RETPOLINE:
 510                 if (IS_ENABLED(CONFIG_RETPOLINE))
 511                         goto retpoline_auto;
 512                 break;
 513         }
 514         pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!");
 515         return;
 516
 517 retpoline_auto:
 518         if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
 519             boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
 520         retpoline_amd:
 521                 if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) {
 522                         pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n");
 523                         goto retpoline_generic;
 524                 }
 525                 mode = SPECTRE_V2_RETPOLINE_AMD;
 526                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD);
 527                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
 528         } else {
 529         retpoline_generic:
 530                 mode = SPECTRE_V2_RETPOLINE_GENERIC;
 531                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
 532         }
 533
 534 specv2_set_mode:
 535         spectre_v2_enabled = mode;
 536         pr_info("%s\n", spectre_v2_strings[mode]);
 537
 538         /*
 539          * If spectre v2 protection has been enabled, unconditionally fill
 540          * RSB during a context switch; this protects against two independent
 541          * issues:
 542          *
 543          *      - RSB underflow (and switch to BTB) on Skylake+
 544          *      - SpectreRSB variant of spectre v2 on X86_BUG_SPECTRE_V2 CPUs
 545          */
 546         setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW);
 547         pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n");
 548
 549         /*
 550          * Retpoline means the kernel is safe because it has no indirect
 551          * branches. Enhanced IBRS protects firmware too, so, enable restricted
 552          * speculation around firmware calls only when Enhanced IBRS isn't
 553          * supported.
 554          *
 555          * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because
 556          * the user might select retpoline on the kernel command line and if
 557          * the CPU supports Enhanced IBRS, kernel might un-intentionally not
 558          * enable IBRS around firmware calls.
 559          */
 560         if (boot_cpu_has(X86_FEATURE_IBRS) && mode != SPECTRE_V2_IBRS_ENHANCED) {
 561                 setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW);
 562                 pr_info("Enabling Restricted Speculation for firmware calls\n");
 563         }
 564
 565         /* Set up IBPB and STIBP depending on the general spectre V2 command */
 566         spectre_v2_user_select_mitigation(cmd);
 567
 568         /* Enable STIBP if appropriate */
 569         arch_smt_update();
 570 }
 571
 572 static void update_stibp_msr(void * __unused)
 573 {
 574         wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
 575 }
 576
 577 /* Update x86_spec_ctrl_base in case SMT state changed. */
 578 static void update_stibp_strict(void)
 579 {
 580         u64 mask = x86_spec_ctrl_base & ~SPEC_CTRL_STIBP;
 581
 582         if (sched_smt_active())
 583                 mask |= SPEC_CTRL_STIBP;
 584
 585         if (mask == x86_spec_ctrl_base)
 586                 return;
 587
 588         pr_info("Update user space SMT mitigation: STIBP %s\n",
 589                 mask & SPEC_CTRL_STIBP ? "always-on" : "off");
 590         x86_spec_ctrl_base = mask;
 591         on_each_cpu(update_stibp_msr, NULL, 1);
 592 }
 593
 594 /* Update the static key controlling the evaluation of TIF_SPEC_IB */
 595 static void update_indir_branch_cond(void)
 596 {
 597         if (sched_smt_active())
 598                 static_branch_enable(&switch_to_cond_stibp);
 599         else
 600                 static_branch_disable(&switch_to_cond_stibp);
 601 }
 602
 603 void arch_smt_update(void)
 604 {
 605         /* Enhanced IBRS implies STIBP. No update required. */
 606         if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED)
 607                 return;
 608
 609         mutex_lock(&spec_ctrl_mutex);
 610
 611         switch (spectre_v2_user) {
 612         case SPECTRE_V2_USER_NONE:
 613                 break;
 614         case SPECTRE_V2_USER_STRICT:
 615                 update_stibp_strict();
 616                 break;
 617         case SPECTRE_V2_USER_PRCTL:
 618         case SPECTRE_V2_USER_SECCOMP:
 619                 update_indir_branch_cond();
 620                 break;
 621         }
 622
 623         mutex_unlock(&spec_ctrl_mutex);
 624 }
 625
 626 #undef pr_fmt
 627 #define pr_fmt(fmt)     "Speculative Store Bypass: " fmt
 628
 629 static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE;
 630
 631 /* The kernel command line selection */
 632 enum ssb_mitigation_cmd {
 633         SPEC_STORE_BYPASS_CMD_NONE,
 634         SPEC_STORE_BYPASS_CMD_AUTO,
 635         SPEC_STORE_BYPASS_CMD_ON,
 636         SPEC_STORE_BYPASS_CMD_PRCTL,
 637         SPEC_STORE_BYPASS_CMD_SECCOMP,
 638 };
 639
 640 static const char * const ssb_strings[] = {
 641         [SPEC_STORE_BYPASS_NONE]        = "Vulnerable",
 642         [SPEC_STORE_BYPASS_DISABLE]     = "Mitigation: Speculative Store Bypass disabled",
 643         [SPEC_STORE_BYPASS_PRCTL]       = "Mitigation: Speculative Store Bypass disabled via prctl",
 644         [SPEC_STORE_BYPASS_SECCOMP]     = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp",
 645 };
 646
 647 static const struct {
 648         const char *option;
 649         enum ssb_mitigation_cmd cmd;
 650 } ssb_mitigation_options[]  __initdata = {
 651         { "auto",       SPEC_STORE_BYPASS_CMD_AUTO },    /* Platform decides */
 652         { "on",         SPEC_STORE_BYPASS_CMD_ON },      /* Disable Speculative Store Bypass */
 653         { "off",        SPEC_STORE_BYPASS_CMD_NONE },    /* Don't touch Speculative Store Bypass */
 654         { "prctl",      SPEC_STORE_BYPASS_CMD_PRCTL },   /* Disable Speculative Store Bypass via prctl */
 655         { "seccomp",    SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */
 656 };
 657
 658 static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void)
 659 {
 660         enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO;
 661         char arg[20];
 662         int ret, i;
 663
 664         if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable")) {
 665                 return SPEC_STORE_BYPASS_CMD_NONE;
 666         } else {
 667                 ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable",
 668                                           arg, sizeof(arg));
 669                 if (ret < 0)
 670                         return SPEC_STORE_BYPASS_CMD_AUTO;
 671
 672                 for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) {
 673                         if (!match_option(arg, ret, ssb_mitigation_options[i].option))
 674                                 continue;
 675
 676                         cmd = ssb_mitigation_options[i].cmd;
 677                         break;
 678                 }
 679
 680                 if (i >= ARRAY_SIZE(ssb_mitigation_options)) {
 681                         pr_err("unknown option (%s). Switching to AUTO select\n", arg);
 682                         return SPEC_STORE_BYPASS_CMD_AUTO;
 683                 }
 684         }
 685
 686         return cmd;
 687 }
 688
 689 static enum ssb_mitigation __init __ssb_select_mitigation(void)
 690 {
 691         enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE;
 692         enum ssb_mitigation_cmd cmd;
 693
 694         if (!boot_cpu_has(X86_FEATURE_SSBD))
 695                 return mode;
 696
 697         cmd = ssb_parse_cmdline();
 698         if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) &&
 699             (cmd == SPEC_STORE_BYPASS_CMD_NONE ||
 700              cmd == SPEC_STORE_BYPASS_CMD_AUTO))
 701                 return mode;
 702
 703         switch (cmd) {
 704         case SPEC_STORE_BYPASS_CMD_AUTO:
 705         case SPEC_STORE_BYPASS_CMD_SECCOMP:
 706                 /*
 707                  * Choose prctl+seccomp as the default mode if seccomp is
 708                  * enabled.
 709                  */
 710                 if (IS_ENABLED(CONFIG_SECCOMP))
 711                         mode = SPEC_STORE_BYPASS_SECCOMP;
 712                 else
 713                         mode = SPEC_STORE_BYPASS_PRCTL;
 714                 break;
 715         case SPEC_STORE_BYPASS_CMD_ON:
 716                 mode = SPEC_STORE_BYPASS_DISABLE;
 717                 break;
 718         case SPEC_STORE_BYPASS_CMD_PRCTL:
 719                 mode = SPEC_STORE_BYPASS_PRCTL;
 720                 break;
 721         case SPEC_STORE_BYPASS_CMD_NONE:
 722                 break;
 723         }
 724
 725         /*
 726          * We have three CPU feature flags that are in play here:
 727          *  - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
 728          *  - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass
 729          *  - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation
 730          */
 731         if (mode == SPEC_STORE_BYPASS_DISABLE) {
 732                 setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE);
 733                 /*
 734                  * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may
 735                  * use a completely different MSR and bit dependent on family.
 736                  */
 737                 if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) &&
 738                     !static_cpu_has(X86_FEATURE_AMD_SSBD)) {
 739                         x86_amd_ssb_disable();
 740                 } else {
 741                         x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
 742                         x86_spec_ctrl_mask |= SPEC_CTRL_SSBD;
 743                         wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
 744                 }
 745         }
 746
 747         return mode;
 748 }
 749
 750 static void ssb_select_mitigation(void)
 751 {
 752         ssb_mode = __ssb_select_mitigation();
 753
 754         if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
 755                 pr_info("%s\n", ssb_strings[ssb_mode]);
 756 }
 757
 758 #undef pr_fmt
 759 #define pr_fmt(fmt)     "Speculation prctl: " fmt
 760
 761 static void task_update_spec_tif(struct task_struct *tsk)
 762 {
 763         /* Force the update of the real TIF bits */
 764         set_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE);
 765
 766         /*
 767          * Immediately update the speculation control MSRs for the current
 768          * task, but for a non-current task delay setting the CPU
 769          * mitigation until it is scheduled next.
 770          *
 771          * This can only happen for SECCOMP mitigation. For PRCTL it's
 772          * always the current task.
 773          */
 774         if (tsk == current)
 775                 speculation_ctrl_update_current();
 776 }
 777
 778 static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl)
 779 {
 780         if (ssb_mode != SPEC_STORE_BYPASS_PRCTL &&
 781             ssb_mode != SPEC_STORE_BYPASS_SECCOMP)
 782                 return -ENXIO;
 783
 784         switch (ctrl) {
 785         case PR_SPEC_ENABLE:
 786                 /* If speculation is force disabled, enable is not allowed */
 787                 if (task_spec_ssb_force_disable(task))
 788                         return -EPERM;
 789                 task_clear_spec_ssb_disable(task);
 790                 task_update_spec_tif(task);
 791                 break;
 792         case PR_SPEC_DISABLE:
 793                 task_set_spec_ssb_disable(task);
 794                 task_update_spec_tif(task);
 795                 break;
 796         case PR_SPEC_FORCE_DISABLE:
 797                 task_set_spec_ssb_disable(task);
 798                 task_set_spec_ssb_force_disable(task);
 799                 task_update_spec_tif(task);
 800                 break;
 801         default:
 802                 return -ERANGE;
 803         }
 804         return 0;
 805 }
 806
 807 static int ib_prctl_set(struct task_struct *task, unsigned long ctrl)
 808 {
 809         switch (ctrl) {
 810         case PR_SPEC_ENABLE:
 811                 if (spectre_v2_user == SPECTRE_V2_USER_NONE)
 812                         return 0;
 813                 /*
 814                  * Indirect branch speculation is always disabled in strict
 815                  * mode.
 816                  */
 817                 if (spectre_v2_user == SPECTRE_V2_USER_STRICT)
 818                         return -EPERM;
 819                 task_clear_spec_ib_disable(task);
 820                 task_update_spec_tif(task);
 821                 break;
 822         case PR_SPEC_DISABLE:
 823         case PR_SPEC_FORCE_DISABLE:
 824                 /*
 825                  * Indirect branch speculation is always allowed when
 826                  * mitigation is force disabled.
 827                  */
 828                 if (spectre_v2_user == SPECTRE_V2_USER_NONE)
 829                         return -EPERM;
 830                 if (spectre_v2_user == SPECTRE_V2_USER_STRICT)
 831                         return 0;
 832                 task_set_spec_ib_disable(task);
 833                 if (ctrl == PR_SPEC_FORCE_DISABLE)
 834                         task_set_spec_ib_force_disable(task);
 835                 task_update_spec_tif(task);
 836                 break;
 837         default:
 838                 return -ERANGE;
 839         }
 840         return 0;
 841 }
 842
 843 int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which,
 844                              unsigned long ctrl)
 845 {
 846         switch (which) {
 847         case PR_SPEC_STORE_BYPASS:
 848                 return ssb_prctl_set(task, ctrl);
 849         case PR_SPEC_INDIRECT_BRANCH:
 850                 return ib_prctl_set(task, ctrl);
 851         default:
 852                 return -ENODEV;
 853         }
 854 }
 855
 856 #ifdef CONFIG_SECCOMP
 857 void arch_seccomp_spec_mitigate(struct task_struct *task)
 858 {
 859         if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP)
 860                 ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE);
 861         if (spectre_v2_user == SPECTRE_V2_USER_SECCOMP)
 862                 ib_prctl_set(task, PR_SPEC_FORCE_DISABLE);
 863 }
 864 #endif
 865
 866 static int ssb_prctl_get(struct task_struct *task)
 867 {
 868         switch (ssb_mode) {
 869         case SPEC_STORE_BYPASS_DISABLE:
 870                 return PR_SPEC_DISABLE;
 871         case SPEC_STORE_BYPASS_SECCOMP:
 872         case SPEC_STORE_BYPASS_PRCTL:
 873                 if (task_spec_ssb_force_disable(task))
 874                         return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
 875                 if (task_spec_ssb_disable(task))
 876                         return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
 877                 return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
 878         default:
 879                 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
 880                         return PR_SPEC_ENABLE;
 881                 return PR_SPEC_NOT_AFFECTED;
 882         }
 883 }
 884
 885 static int ib_prctl_get(struct task_struct *task)
 886 {
 887         if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
 888                 return PR_SPEC_NOT_AFFECTED;
 889
 890         switch (spectre_v2_user) {
 891         case SPECTRE_V2_USER_NONE:
 892                 return PR_SPEC_ENABLE;
 893         case SPECTRE_V2_USER_PRCTL:
 894         case SPECTRE_V2_USER_SECCOMP:
 895                 if (task_spec_ib_force_disable(task))
 896                         return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
 897                 if (task_spec_ib_disable(task))
 898                         return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
 899                 return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
 900         case SPECTRE_V2_USER_STRICT:
 901                 return PR_SPEC_DISABLE;
 902         default:
 903                 return PR_SPEC_NOT_AFFECTED;
 904         }
 905 }
 906
 907 int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which)
 908 {
 909         switch (which) {
 910         case PR_SPEC_STORE_BYPASS:
 911                 return ssb_prctl_get(task);
 912         case PR_SPEC_INDIRECT_BRANCH:
 913                 return ib_prctl_get(task);
 914         default:
 915                 return -ENODEV;
 916         }
 917 }
 918
 919 void x86_spec_ctrl_setup_ap(void)
 920 {
 921         if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
 922                 wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
 923
 924         if (ssb_mode == SPEC_STORE_BYPASS_DISABLE)
 925                 x86_amd_ssb_disable();
 926 }
 927
 928 #undef pr_fmt
 929 #define pr_fmt(fmt)     "L1TF: " fmt
 930
 931 /* Default mitigation for L1TF-affected CPUs */
 932 enum l1tf_mitigations l1tf_mitigation __ro_after_init = L1TF_MITIGATION_FLUSH;
 933 #if IS_ENABLED(CONFIG_KVM_INTEL)
 934 EXPORT_SYMBOL_GPL(l1tf_mitigation);
 935 #endif
 936 enum vmx_l1d_flush_state l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
 937 EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation);
 938
 939 /*
 940  * These CPUs all support 44bits physical address space internally in the
 941  * cache but CPUID can report a smaller number of physical address bits.
 942  *
 943  * The L1TF mitigation uses the top most address bit for the inversion of
 944  * non present PTEs. When the installed memory reaches into the top most
 945  * address bit due to memory holes, which has been observed on machines
 946  * which report 36bits physical address bits and have 32G RAM installed,
 947  * then the mitigation range check in l1tf_select_mitigation() triggers.
 948  * This is a false positive because the mitigation is still possible due to
 949  * the fact that the cache uses 44bit internally. Use the cache bits
 950  * instead of the reported physical bits and adjust them on the affected
 951  * machines to 44bit if the reported bits are less than 44.
 952  */
 953 static void override_cache_bits(struct cpuinfo_x86 *c)
 954 {
 955         if (c->x86 != 6)
 956                 return;
 957
 958         switch (c->x86_model) {
 959         case INTEL_FAM6_NEHALEM:
 960         case INTEL_FAM6_WESTMERE:
 961         case INTEL_FAM6_SANDYBRIDGE:
 962         case INTEL_FAM6_IVYBRIDGE:
 963         case INTEL_FAM6_HASWELL_CORE:
 964         case INTEL_FAM6_HASWELL_ULT:
 965         case INTEL_FAM6_HASWELL_GT3E:
 966         case INTEL_FAM6_BROADWELL_CORE:
 967         case INTEL_FAM6_BROADWELL_GT3E:
 968         case INTEL_FAM6_SKYLAKE_MOBILE:
 969         case INTEL_FAM6_SKYLAKE_DESKTOP:
 970         case INTEL_FAM6_KABYLAKE_MOBILE:
 971         case INTEL_FAM6_KABYLAKE_DESKTOP:
 972                 if (c->x86_cache_bits < 44)
 973                         c->x86_cache_bits = 44;
 974                 break;
 975         }
 976 }
 977
 978 static void __init l1tf_select_mitigation(void)
 979 {
 980         u64 half_pa;
 981
 982         if (!boot_cpu_has_bug(X86_BUG_L1TF))
 983                 return;
 984
 985         override_cache_bits(&boot_cpu_data);
 986
 987         switch (l1tf_mitigation) {
 988         case L1TF_MITIGATION_OFF:
 989         case L1TF_MITIGATION_FLUSH_NOWARN:
 990         case L1TF_MITIGATION_FLUSH:
 991                 break;
 992         case L1TF_MITIGATION_FLUSH_NOSMT:
 993         case L1TF_MITIGATION_FULL:
 994                 cpu_smt_disable(false);
 995                 break;
 996         case L1TF_MITIGATION_FULL_FORCE:
 997                 cpu_smt_disable(true);
 998                 break;
 999         }
1000
1001 #if CONFIG_PGTABLE_LEVELS == 2
1002         pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n");
1003         return;
1004 #endif
1005
1006         half_pa = (u64)l1tf_pfn_limit() << PAGE_SHIFT;
1007         if (e820__mapped_any(half_pa, ULLONG_MAX - half_pa, E820_TYPE_RAM)) {
1008                 pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n");
1009                 pr_info("You may make it effective by booting the kernel with mem=%llu parameter.\n",
1010                                 half_pa);
1011                 pr_info("However, doing so will make a part of your RAM unusable.\n");
1012                 pr_info("Reading https://www.kernel.org/doc/html/latest/admin-guide/l1tf.html might help you decide.\n");
1013                 return;
1014         }
1015
1016         setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV);
1017 }
1018
1019 static int __init l1tf_cmdline(char *str)
1020 {
1021         if (!boot_cpu_has_bug(X86_BUG_L1TF))
1022                 return 0;
1023
1024         if (!str)
1025                 return -EINVAL;
1026
1027         if (!strcmp(str, "off"))
1028                 l1tf_mitigation = L1TF_MITIGATION_OFF;
1029         else if (!strcmp(str, "flush,nowarn"))
1030                 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOWARN;
1031         else if (!strcmp(str, "flush"))
1032                 l1tf_mitigation = L1TF_MITIGATION_FLUSH;
1033         else if (!strcmp(str, "flush,nosmt"))
1034                 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT;
1035         else if (!strcmp(str, "full"))
1036                 l1tf_mitigation = L1TF_MITIGATION_FULL;
1037         else if (!strcmp(str, "full,force"))
1038                 l1tf_mitigation = L1TF_MITIGATION_FULL_FORCE;
1039
1040         return 0;
1041 }
1042 early_param("l1tf", l1tf_cmdline);
1043
1044 #undef pr_fmt
1045
1046 #ifdef CONFIG_SYSFS
1047
1048 #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion"
1049
1050 #if IS_ENABLED(CONFIG_KVM_INTEL)
1051 static const char * const l1tf_vmx_states[] = {
1052         [VMENTER_L1D_FLUSH_AUTO]                = "auto",
1053         [VMENTER_L1D_FLUSH_NEVER]               = "vulnerable",
1054         [VMENTER_L1D_FLUSH_COND]                = "conditional cache flushes",
1055         [VMENTER_L1D_FLUSH_ALWAYS]              = "cache flushes",
1056         [VMENTER_L1D_FLUSH_EPT_DISABLED]        = "EPT disabled",
1057         [VMENTER_L1D_FLUSH_NOT_REQUIRED]        = "flush not necessary"
1058 };
1059
1060 static ssize_t l1tf_show_state(char *buf)
1061 {
1062         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO)
1063                 return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG);
1064
1065         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_EPT_DISABLED ||
1066             (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER &&
1067              sched_smt_active())) {
1068                 return sprintf(buf, "%s; VMX: %s\n", L1TF_DEFAULT_MSG,
1069                                l1tf_vmx_states[l1tf_vmx_mitigation]);
1070         }
1071
1072         return sprintf(buf, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG,
1073                        l1tf_vmx_states[l1tf_vmx_mitigation],
1074                        sched_smt_active() ? "vulnerable" : "disabled");
1075 }
1076 #else
1077 static ssize_t l1tf_show_state(char *buf)
1078 {
1079         return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG);
1080 }
1081 #endif
1082
1083 static char *stibp_state(void)
1084 {
1085         if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED)
1086                 return "";
1087
1088         switch (spectre_v2_user) {
1089         case SPECTRE_V2_USER_NONE:
1090                 return ", STIBP: disabled";
1091         case SPECTRE_V2_USER_STRICT:
1092                 return ", STIBP: forced";
1093         case SPECTRE_V2_USER_PRCTL:
1094         case SPECTRE_V2_USER_SECCOMP:
1095                 if (static_key_enabled(&switch_to_cond_stibp))
1096                         return ", STIBP: conditional";
1097         }
1098         return "";
1099 }
1100
1101 static char *ibpb_state(void)
1102 {
1103         if (boot_cpu_has(X86_FEATURE_IBPB)) {
1104                 if (static_key_enabled(&switch_mm_always_ibpb))
1105                         return ", IBPB: always-on";
1106                 if (static_key_enabled(&switch_mm_cond_ibpb))
1107                         return ", IBPB: conditional";
1108                 return ", IBPB: disabled";
1109         }
1110         return "";
1111 }
1112
1113 static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr,
1114                                char *buf, unsigned int bug)
1115 {
1116         if (!boot_cpu_has_bug(bug))
1117                 return sprintf(buf, "Not affected\n");
1118
1119         switch (bug) {
1120         case X86_BUG_CPU_MELTDOWN:
1121                 if (boot_cpu_has(X86_FEATURE_PTI))
1122                         return sprintf(buf, "Mitigation: PTI\n");
1123
1124                 if (hypervisor_is_type(X86_HYPER_XEN_PV))
1125                         return sprintf(buf, "Unknown (XEN PV detected, hypervisor mitigation required)\n");
1126
1127                 break;
1128
1129         case X86_BUG_SPECTRE_V1:
1130                 return sprintf(buf, "Mitigation: __user pointer sanitization\n");
1131
1132         case X86_BUG_SPECTRE_V2:
1133                 return sprintf(buf, "%s%s%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled],
1134                                ibpb_state(),
1135                                boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "",
1136                                stibp_state(),
1137                                boot_cpu_has(X86_FEATURE_RSB_CTXSW) ? ", RSB filling" : "",
1138                                spectre_v2_module_string());
1139
1140         case X86_BUG_SPEC_STORE_BYPASS:
1141                 return sprintf(buf, "%s\n", ssb_strings[ssb_mode]);
1142
1143         case X86_BUG_L1TF:
1144                 if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV))
1145                         return l1tf_show_state(buf);
1146                 break;
1147         default:
1148                 break;
1149         }
1150
1151         return sprintf(buf, "Vulnerable\n");
1152 }
1153
1154 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf)
1155 {
1156         return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN);
1157 }
1158
1159 ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf)
1160 {
1161         return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1);
1162 }
1163
1164 ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf)
1165 {
1166         return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2);
1167 }
1168
1169 ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf)
1170 {
1171         return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS);
1172 }
1173
1174 ssize_t cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf)
1175 {
1176         return cpu_show_common(dev, attr, buf, X86_BUG_L1TF);
1177 }
1178 #endif