2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
22 * Historical information which is worth to be preserved:
26 * We used to have a workaround for a bug in SiS chips which
27 * required to rewrite the index register for a read-modify-write
28 * operation as the chip lost the index information which was
29 * setup for the read already. We cache the data now, so that
30 * workaround has been removed.
34 #include <linux/interrupt.h>
35 #include <linux/init.h>
36 #include <linux/delay.h>
37 #include <linux/sched.h>
38 #include <linux/pci.h>
39 #include <linux/mc146818rtc.h>
40 #include <linux/compiler.h>
41 #include <linux/acpi.h>
42 #include <linux/module.h>
43 #include <linux/syscore_ops.h>
44 #include <linux/irqdomain.h>
45 #include <linux/freezer.h>
46 #include <linux/kthread.h>
47 #include <linux/jiffies.h> /* time_after() */
48 #include <linux/slab.h>
49 #include <linux/bootmem.h>
56 #include <asm/proto.h>
59 #include <asm/timer.h>
60 #include <asm/i8259.h>
61 #include <asm/setup.h>
62 #include <asm/irq_remapping.h>
63 #include <asm/hw_irq.h>
67 #define for_each_ioapic(idx) \
68 for ((idx) = 0; (idx) < nr_ioapics; (idx)++)
69 #define for_each_ioapic_reverse(idx) \
70 for ((idx) = nr_ioapics - 1; (idx) >= 0; (idx)--)
71 #define for_each_pin(idx, pin) \
72 for ((pin) = 0; (pin) < ioapics[(idx)].nr_registers; (pin)++)
73 #define for_each_ioapic_pin(idx, pin) \
74 for_each_ioapic((idx)) \
75 for_each_pin((idx), (pin))
76 #define for_each_irq_pin(entry, head) \
77 list_for_each_entry(entry, &head, list)
79 static DEFINE_RAW_SPINLOCK(ioapic_lock);
80 static DEFINE_MUTEX(ioapic_mutex);
81 static unsigned int ioapic_dynirq_base;
82 static int ioapic_initialized;
85 struct list_head list;
90 struct list_head irq_2_pin;
91 struct IO_APIC_route_entry entry;
98 struct mp_ioapic_gsi {
103 static struct ioapic {
105 * # of IRQ routing registers
109 * Saved state during suspend/resume, or while enabling intr-remap.
111 struct IO_APIC_route_entry *saved_registers;
112 /* I/O APIC config */
113 struct mpc_ioapic mp_config;
114 /* IO APIC gsi routing info */
115 struct mp_ioapic_gsi gsi_config;
116 struct ioapic_domain_cfg irqdomain_cfg;
117 struct irq_domain *irqdomain;
118 struct resource *iomem_res;
119 } ioapics[MAX_IO_APICS];
121 #define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver
123 int mpc_ioapic_id(int ioapic_idx)
125 return ioapics[ioapic_idx].mp_config.apicid;
128 unsigned int mpc_ioapic_addr(int ioapic_idx)
130 return ioapics[ioapic_idx].mp_config.apicaddr;
133 static inline struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic_idx)
135 return &ioapics[ioapic_idx].gsi_config;
138 static inline int mp_ioapic_pin_count(int ioapic)
140 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic);
142 return gsi_cfg->gsi_end - gsi_cfg->gsi_base + 1;
145 static inline u32 mp_pin_to_gsi(int ioapic, int pin)
147 return mp_ioapic_gsi_routing(ioapic)->gsi_base + pin;
150 static inline bool mp_is_legacy_irq(int irq)
152 return irq >= 0 && irq < nr_legacy_irqs();
156 * Initialize all legacy IRQs and all pins on the first IOAPIC
157 * if we have legacy interrupt controller. Kernel boot option "pirq="
158 * may rely on non-legacy pins on the first IOAPIC.
160 static inline int mp_init_irq_at_boot(int ioapic, int irq)
162 if (!nr_legacy_irqs())
165 return ioapic == 0 || mp_is_legacy_irq(irq);
168 static inline struct irq_domain *mp_ioapic_irqdomain(int ioapic)
170 return ioapics[ioapic].irqdomain;
175 /* The one past the highest gsi number used */
178 /* MP IRQ source entries */
179 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
181 /* # of MP IRQ source entries */
185 int mp_bus_id_to_type[MAX_MP_BUSSES];
188 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
190 int skip_ioapic_setup;
193 * disable_ioapic_support() - disables ioapic support at runtime
195 void disable_ioapic_support(void)
199 noioapicreroute = -1;
201 skip_ioapic_setup = 1;
204 static int __init parse_noapic(char *str)
206 /* disable IO-APIC */
207 disable_ioapic_support();
210 early_param("noapic", parse_noapic);
212 /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */
213 void mp_save_irq(struct mpc_intsrc *m)
217 apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x,"
218 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
219 m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus,
220 m->srcbusirq, m->dstapic, m->dstirq);
222 for (i = 0; i < mp_irq_entries; i++) {
223 if (!memcmp(&mp_irqs[i], m, sizeof(*m)))
227 memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m));
228 if (++mp_irq_entries == MAX_IRQ_SOURCES)
229 panic("Max # of irq sources exceeded!!\n");
232 static void alloc_ioapic_saved_registers(int idx)
236 if (ioapics[idx].saved_registers)
239 size = sizeof(struct IO_APIC_route_entry) * ioapics[idx].nr_registers;
240 ioapics[idx].saved_registers = kzalloc(size, GFP_KERNEL);
241 if (!ioapics[idx].saved_registers)
242 pr_err("IOAPIC %d: suspend/resume impossible!\n", idx);
245 static void free_ioapic_saved_registers(int idx)
247 kfree(ioapics[idx].saved_registers);
248 ioapics[idx].saved_registers = NULL;
251 int __init arch_early_ioapic_init(void)
255 if (!nr_legacy_irqs())
259 alloc_ioapic_saved_registers(i);
266 unsigned int unused[3];
268 unsigned int unused2[11];
272 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
274 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
275 + (mpc_ioapic_addr(idx) & ~PAGE_MASK);
278 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
280 struct io_apic __iomem *io_apic = io_apic_base(apic);
281 writel(vector, &io_apic->eoi);
284 unsigned int native_io_apic_read(unsigned int apic, unsigned int reg)
286 struct io_apic __iomem *io_apic = io_apic_base(apic);
287 writel(reg, &io_apic->index);
288 return readl(&io_apic->data);
291 static void io_apic_write(unsigned int apic, unsigned int reg,
294 struct io_apic __iomem *io_apic = io_apic_base(apic);
296 writel(reg, &io_apic->index);
297 writel(value, &io_apic->data);
301 struct { u32 w1, w2; };
302 struct IO_APIC_route_entry entry;
305 static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin)
307 union entry_union eu;
309 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
310 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
315 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
317 union entry_union eu;
320 raw_spin_lock_irqsave(&ioapic_lock, flags);
321 eu.entry = __ioapic_read_entry(apic, pin);
322 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
328 * When we write a new IO APIC routing entry, we need to write the high
329 * word first! If the mask bit in the low word is clear, we will enable
330 * the interrupt, and we need to make sure the entry is fully populated
331 * before that happens.
333 static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
335 union entry_union eu = {{0, 0}};
338 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
339 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
342 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
346 raw_spin_lock_irqsave(&ioapic_lock, flags);
347 __ioapic_write_entry(apic, pin, e);
348 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
352 * When we mask an IO APIC routing entry, we need to write the low
353 * word first, in order to set the mask bit before we change the
356 static void ioapic_mask_entry(int apic, int pin)
359 union entry_union eu = { .entry.mask = IOAPIC_MASKED };
361 raw_spin_lock_irqsave(&ioapic_lock, flags);
362 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
363 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
364 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
368 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
369 * shared ISA-space IRQs, so we have to support them. We are super
370 * fast in the common case, and fast for shared ISA-space IRQs.
372 static int __add_pin_to_irq_node(struct mp_chip_data *data,
373 int node, int apic, int pin)
375 struct irq_pin_list *entry;
377 /* don't allow duplicates */
378 for_each_irq_pin(entry, data->irq_2_pin)
379 if (entry->apic == apic && entry->pin == pin)
382 entry = kzalloc_node(sizeof(struct irq_pin_list), GFP_ATOMIC, node);
384 pr_err("can not alloc irq_pin_list (%d,%d,%d)\n",
390 list_add_tail(&entry->list, &data->irq_2_pin);
395 static void __remove_pin_from_irq(struct mp_chip_data *data, int apic, int pin)
397 struct irq_pin_list *tmp, *entry;
399 list_for_each_entry_safe(entry, tmp, &data->irq_2_pin, list)
400 if (entry->apic == apic && entry->pin == pin) {
401 list_del(&entry->list);
407 static void add_pin_to_irq_node(struct mp_chip_data *data,
408 int node, int apic, int pin)
410 if (__add_pin_to_irq_node(data, node, apic, pin))
411 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
415 * Reroute an IRQ to a different pin.
417 static void __init replace_pin_at_irq_node(struct mp_chip_data *data, int node,
418 int oldapic, int oldpin,
419 int newapic, int newpin)
421 struct irq_pin_list *entry;
423 for_each_irq_pin(entry, data->irq_2_pin) {
424 if (entry->apic == oldapic && entry->pin == oldpin) {
425 entry->apic = newapic;
427 /* every one is different, right? */
432 /* old apic/pin didn't exist, so just add new ones */
433 add_pin_to_irq_node(data, node, newapic, newpin);
436 static void io_apic_modify_irq(struct mp_chip_data *data,
437 int mask_and, int mask_or,
438 void (*final)(struct irq_pin_list *entry))
440 union entry_union eu;
441 struct irq_pin_list *entry;
443 eu.entry = data->entry;
446 data->entry = eu.entry;
448 for_each_irq_pin(entry, data->irq_2_pin) {
449 io_apic_write(entry->apic, 0x10 + 2 * entry->pin, eu.w1);
455 static void io_apic_sync(struct irq_pin_list *entry)
458 * Synchronize the IO-APIC and the CPU by doing
459 * a dummy read from the IO-APIC
461 struct io_apic __iomem *io_apic;
463 io_apic = io_apic_base(entry->apic);
464 readl(&io_apic->data);
467 static void mask_ioapic_irq(struct irq_data *irq_data)
469 struct mp_chip_data *data = irq_data->chip_data;
472 raw_spin_lock_irqsave(&ioapic_lock, flags);
473 io_apic_modify_irq(data, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
474 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
477 static void __unmask_ioapic(struct mp_chip_data *data)
479 io_apic_modify_irq(data, ~IO_APIC_REDIR_MASKED, 0, NULL);
482 static void unmask_ioapic_irq(struct irq_data *irq_data)
484 struct mp_chip_data *data = irq_data->chip_data;
487 raw_spin_lock_irqsave(&ioapic_lock, flags);
488 __unmask_ioapic(data);
489 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
493 * IO-APIC versions below 0x20 don't support EOI register.
494 * For the record, here is the information about various versions:
496 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
497 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
500 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
501 * version as 0x2. This is an error with documentation and these ICH chips
502 * use io-apic's of version 0x20.
504 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
505 * Otherwise, we simulate the EOI message manually by changing the trigger
506 * mode to edge and then back to level, with RTE being masked during this.
508 static void __eoi_ioapic_pin(int apic, int pin, int vector)
510 if (mpc_ioapic_ver(apic) >= 0x20) {
511 io_apic_eoi(apic, vector);
513 struct IO_APIC_route_entry entry, entry1;
515 entry = entry1 = __ioapic_read_entry(apic, pin);
518 * Mask the entry and change the trigger mode to edge.
520 entry1.mask = IOAPIC_MASKED;
521 entry1.trigger = IOAPIC_EDGE;
523 __ioapic_write_entry(apic, pin, entry1);
526 * Restore the previous level triggered entry.
528 __ioapic_write_entry(apic, pin, entry);
532 void eoi_ioapic_pin(int vector, struct mp_chip_data *data)
535 struct irq_pin_list *entry;
537 raw_spin_lock_irqsave(&ioapic_lock, flags);
538 for_each_irq_pin(entry, data->irq_2_pin)
539 __eoi_ioapic_pin(entry->apic, entry->pin, vector);
540 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
543 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
545 struct IO_APIC_route_entry entry;
547 /* Check delivery_mode to be sure we're not clearing an SMI pin */
548 entry = ioapic_read_entry(apic, pin);
549 if (entry.delivery_mode == dest_SMI)
553 * Make sure the entry is masked and re-read the contents to check
554 * if it is a level triggered pin and if the remote-IRR is set.
556 if (entry.mask == IOAPIC_UNMASKED) {
557 entry.mask = IOAPIC_MASKED;
558 ioapic_write_entry(apic, pin, entry);
559 entry = ioapic_read_entry(apic, pin);
566 * Make sure the trigger mode is set to level. Explicit EOI
567 * doesn't clear the remote-IRR if the trigger mode is not
570 if (entry.trigger == IOAPIC_EDGE) {
571 entry.trigger = IOAPIC_LEVEL;
572 ioapic_write_entry(apic, pin, entry);
574 raw_spin_lock_irqsave(&ioapic_lock, flags);
575 __eoi_ioapic_pin(apic, pin, entry.vector);
576 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
580 * Clear the rest of the bits in the IO-APIC RTE except for the mask
583 ioapic_mask_entry(apic, pin);
584 entry = ioapic_read_entry(apic, pin);
586 pr_err("Unable to reset IRR for apic: %d, pin :%d\n",
587 mpc_ioapic_id(apic), pin);
590 static void clear_IO_APIC (void)
594 for_each_ioapic_pin(apic, pin)
595 clear_IO_APIC_pin(apic, pin);
600 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
601 * specific CPU-side IRQs.
605 static int pirq_entries[MAX_PIRQS] = {
606 [0 ... MAX_PIRQS - 1] = -1
609 static int __init ioapic_pirq_setup(char *str)
612 int ints[MAX_PIRQS+1];
614 get_options(str, ARRAY_SIZE(ints), ints);
616 apic_printk(APIC_VERBOSE, KERN_INFO
617 "PIRQ redirection, working around broken MP-BIOS.\n");
619 if (ints[0] < MAX_PIRQS)
622 for (i = 0; i < max; i++) {
623 apic_printk(APIC_VERBOSE, KERN_DEBUG
624 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
626 * PIRQs are mapped upside down, usually.
628 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
633 __setup("pirq=", ioapic_pirq_setup);
634 #endif /* CONFIG_X86_32 */
637 * Saves all the IO-APIC RTE's
639 int save_ioapic_entries(void)
644 for_each_ioapic(apic) {
645 if (!ioapics[apic].saved_registers) {
650 for_each_pin(apic, pin)
651 ioapics[apic].saved_registers[pin] =
652 ioapic_read_entry(apic, pin);
659 * Mask all IO APIC entries.
661 void mask_ioapic_entries(void)
665 for_each_ioapic(apic) {
666 if (!ioapics[apic].saved_registers)
669 for_each_pin(apic, pin) {
670 struct IO_APIC_route_entry entry;
672 entry = ioapics[apic].saved_registers[pin];
673 if (entry.mask == IOAPIC_UNMASKED) {
674 entry.mask = IOAPIC_MASKED;
675 ioapic_write_entry(apic, pin, entry);
682 * Restore IO APIC entries which was saved in the ioapic structure.
684 int restore_ioapic_entries(void)
688 for_each_ioapic(apic) {
689 if (!ioapics[apic].saved_registers)
692 for_each_pin(apic, pin)
693 ioapic_write_entry(apic, pin,
694 ioapics[apic].saved_registers[pin]);
700 * Find the IRQ entry number of a certain pin.
702 static int find_irq_entry(int ioapic_idx, int pin, int type)
706 for (i = 0; i < mp_irq_entries; i++)
707 if (mp_irqs[i].irqtype == type &&
708 (mp_irqs[i].dstapic == mpc_ioapic_id(ioapic_idx) ||
709 mp_irqs[i].dstapic == MP_APIC_ALL) &&
710 mp_irqs[i].dstirq == pin)
717 * Find the pin to which IRQ[irq] (ISA) is connected
719 static int __init find_isa_irq_pin(int irq, int type)
723 for (i = 0; i < mp_irq_entries; i++) {
724 int lbus = mp_irqs[i].srcbus;
726 if (test_bit(lbus, mp_bus_not_pci) &&
727 (mp_irqs[i].irqtype == type) &&
728 (mp_irqs[i].srcbusirq == irq))
730 return mp_irqs[i].dstirq;
735 static int __init find_isa_irq_apic(int irq, int type)
739 for (i = 0; i < mp_irq_entries; i++) {
740 int lbus = mp_irqs[i].srcbus;
742 if (test_bit(lbus, mp_bus_not_pci) &&
743 (mp_irqs[i].irqtype == type) &&
744 (mp_irqs[i].srcbusirq == irq))
748 if (i < mp_irq_entries) {
751 for_each_ioapic(ioapic_idx)
752 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic)
761 * EISA Edge/Level control register, ELCR
763 static int EISA_ELCR(unsigned int irq)
765 if (irq < nr_legacy_irqs()) {
766 unsigned int port = 0x4d0 + (irq >> 3);
767 return (inb(port) >> (irq & 7)) & 1;
769 apic_printk(APIC_VERBOSE, KERN_INFO
770 "Broken MPtable reports ISA irq %d\n", irq);
776 /* ISA interrupts are always active high edge triggered,
777 * when listed as conforming in the MP table. */
779 #define default_ISA_trigger(idx) (IOAPIC_EDGE)
780 #define default_ISA_polarity(idx) (IOAPIC_POL_HIGH)
782 /* EISA interrupts are always polarity zero and can be edge or level
783 * trigger depending on the ELCR value. If an interrupt is listed as
784 * EISA conforming in the MP table, that means its trigger type must
785 * be read in from the ELCR */
787 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
788 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
790 /* PCI interrupts are always active low level triggered,
791 * when listed as conforming in the MP table. */
793 #define default_PCI_trigger(idx) (IOAPIC_LEVEL)
794 #define default_PCI_polarity(idx) (IOAPIC_POL_LOW)
796 static int irq_polarity(int idx)
798 int bus = mp_irqs[idx].srcbus;
802 * Determine IRQ line polarity (high active or low active):
804 switch (mp_irqs[idx].irqflag & 3)
806 case 0: /* conforms, ie. bus-type dependent polarity */
807 if (test_bit(bus, mp_bus_not_pci))
808 polarity = default_ISA_polarity(idx);
810 polarity = default_PCI_polarity(idx);
812 case 1: /* high active */
814 polarity = IOAPIC_POL_HIGH;
817 case 2: /* reserved */
819 pr_warn("broken BIOS!!\n");
820 polarity = IOAPIC_POL_LOW;
823 case 3: /* low active */
825 polarity = IOAPIC_POL_LOW;
828 default: /* invalid */
830 pr_warn("broken BIOS!!\n");
831 polarity = IOAPIC_POL_LOW;
838 static int irq_trigger(int idx)
840 int bus = mp_irqs[idx].srcbus;
844 * Determine IRQ trigger mode (edge or level sensitive):
846 switch ((mp_irqs[idx].irqflag>>2) & 3)
848 case 0: /* conforms, ie. bus-type dependent */
849 if (test_bit(bus, mp_bus_not_pci))
850 trigger = default_ISA_trigger(idx);
852 trigger = default_PCI_trigger(idx);
854 switch (mp_bus_id_to_type[bus]) {
855 case MP_BUS_ISA: /* ISA pin */
857 /* set before the switch */
860 case MP_BUS_EISA: /* EISA pin */
862 trigger = default_EISA_trigger(idx);
865 case MP_BUS_PCI: /* PCI pin */
867 /* set before the switch */
872 pr_warn("broken BIOS!!\n");
873 trigger = IOAPIC_LEVEL;
881 trigger = IOAPIC_EDGE;
884 case 2: /* reserved */
886 pr_warn("broken BIOS!!\n");
887 trigger = IOAPIC_LEVEL;
892 trigger = IOAPIC_LEVEL;
895 default: /* invalid */
897 pr_warn("broken BIOS!!\n");
898 trigger = IOAPIC_EDGE;
905 void ioapic_set_alloc_attr(struct irq_alloc_info *info, int node,
906 int trigger, int polarity)
908 init_irq_alloc_info(info, NULL);
909 info->type = X86_IRQ_ALLOC_TYPE_IOAPIC;
910 info->ioapic_node = node;
911 info->ioapic_trigger = trigger;
912 info->ioapic_polarity = polarity;
913 info->ioapic_valid = 1;
917 int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity);
920 static void ioapic_copy_alloc_attr(struct irq_alloc_info *dst,
921 struct irq_alloc_info *src,
922 u32 gsi, int ioapic_idx, int pin)
924 int trigger, polarity;
926 copy_irq_alloc_info(dst, src);
927 dst->type = X86_IRQ_ALLOC_TYPE_IOAPIC;
928 dst->ioapic_id = mpc_ioapic_id(ioapic_idx);
929 dst->ioapic_pin = pin;
930 dst->ioapic_valid = 1;
931 if (src && src->ioapic_valid) {
932 dst->ioapic_node = src->ioapic_node;
933 dst->ioapic_trigger = src->ioapic_trigger;
934 dst->ioapic_polarity = src->ioapic_polarity;
936 dst->ioapic_node = NUMA_NO_NODE;
937 if (acpi_get_override_irq(gsi, &trigger, &polarity) >= 0) {
938 dst->ioapic_trigger = trigger;
939 dst->ioapic_polarity = polarity;
942 * PCI interrupts are always active low level
945 dst->ioapic_trigger = IOAPIC_LEVEL;
946 dst->ioapic_polarity = IOAPIC_POL_LOW;
951 static int ioapic_alloc_attr_node(struct irq_alloc_info *info)
953 return (info && info->ioapic_valid) ? info->ioapic_node : NUMA_NO_NODE;
956 static void mp_register_handler(unsigned int irq, unsigned long trigger)
958 irq_flow_handler_t hdl;
962 irq_set_status_flags(irq, IRQ_LEVEL);
965 irq_clear_status_flags(irq, IRQ_LEVEL);
969 hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq;
970 __irq_set_handler(irq, hdl, 0, fasteoi ? "fasteoi" : "edge");
973 static bool mp_check_pin_attr(int irq, struct irq_alloc_info *info)
975 struct mp_chip_data *data = irq_get_chip_data(irq);
978 * setup_IO_APIC_irqs() programs all legacy IRQs with default trigger
979 * and polarity attirbutes. So allow the first user to reprogram the
980 * pin with real trigger and polarity attributes.
982 if (irq < nr_legacy_irqs() && data->count == 1) {
983 if (info->ioapic_trigger != data->trigger)
984 mp_register_handler(irq, data->trigger);
985 data->entry.trigger = data->trigger = info->ioapic_trigger;
986 data->entry.polarity = data->polarity = info->ioapic_polarity;
989 return data->trigger == info->ioapic_trigger &&
990 data->polarity == info->ioapic_polarity;
993 static int alloc_irq_from_domain(struct irq_domain *domain, int ioapic, u32 gsi,
994 struct irq_alloc_info *info)
998 int type = ioapics[ioapic].irqdomain_cfg.type;
1001 case IOAPIC_DOMAIN_LEGACY:
1003 * Dynamically allocate IRQ number for non-ISA IRQs in the first
1004 * 16 GSIs on some weird platforms.
1006 if (!ioapic_initialized || gsi >= nr_legacy_irqs())
1008 legacy = mp_is_legacy_irq(irq);
1010 case IOAPIC_DOMAIN_STRICT:
1013 case IOAPIC_DOMAIN_DYNAMIC:
1016 WARN(1, "ioapic: unknown irqdomain type %d\n", type);
1020 return __irq_domain_alloc_irqs(domain, irq, 1,
1021 ioapic_alloc_attr_node(info),
1026 * Need special handling for ISA IRQs because there may be multiple IOAPIC pins
1027 * sharing the same ISA IRQ number and irqdomain only supports 1:1 mapping
1028 * between IOAPIC pin and IRQ number. A typical IOAPIC has 24 pins, pin 0-15 are
1029 * used for legacy IRQs and pin 16-23 are used for PCI IRQs (PIRQ A-H).
1030 * When ACPI is disabled, only legacy IRQ numbers (IRQ0-15) are available, and
1031 * some BIOSes may use MP Interrupt Source records to override IRQ numbers for
1032 * PIRQs instead of reprogramming the interrupt routing logic. Thus there may be
1033 * multiple pins sharing the same legacy IRQ number when ACPI is disabled.
1035 static int alloc_isa_irq_from_domain(struct irq_domain *domain,
1036 int irq, int ioapic, int pin,
1037 struct irq_alloc_info *info)
1039 struct mp_chip_data *data;
1040 struct irq_data *irq_data = irq_get_irq_data(irq);
1041 int node = ioapic_alloc_attr_node(info);
1044 * Legacy ISA IRQ has already been allocated, just add pin to
1045 * the pin list assoicated with this IRQ and program the IOAPIC
1046 * entry. The IOAPIC entry
1048 if (irq_data && irq_data->parent_data) {
1049 if (!mp_check_pin_attr(irq, info))
1051 if (__add_pin_to_irq_node(irq_data->chip_data, node, ioapic,
1055 irq = __irq_domain_alloc_irqs(domain, irq, 1, node, info, true);
1057 irq_data = irq_domain_get_irq_data(domain, irq);
1058 data = irq_data->chip_data;
1059 data->isa_irq = true;
1066 static int mp_map_pin_to_irq(u32 gsi, int idx, int ioapic, int pin,
1067 unsigned int flags, struct irq_alloc_info *info)
1070 bool legacy = false;
1071 struct irq_alloc_info tmp;
1072 struct mp_chip_data *data;
1073 struct irq_domain *domain = mp_ioapic_irqdomain(ioapic);
1078 if (idx >= 0 && test_bit(mp_irqs[idx].srcbus, mp_bus_not_pci)) {
1079 irq = mp_irqs[idx].srcbusirq;
1080 legacy = mp_is_legacy_irq(irq);
1083 mutex_lock(&ioapic_mutex);
1084 if (!(flags & IOAPIC_MAP_ALLOC)) {
1086 irq = irq_find_mapping(domain, pin);
1091 ioapic_copy_alloc_attr(&tmp, info, gsi, ioapic, pin);
1093 irq = alloc_isa_irq_from_domain(domain, irq,
1095 else if ((irq = irq_find_mapping(domain, pin)) == 0)
1096 irq = alloc_irq_from_domain(domain, ioapic, gsi, &tmp);
1097 else if (!mp_check_pin_attr(irq, &tmp))
1100 data = irq_get_chip_data(irq);
1104 mutex_unlock(&ioapic_mutex);
1109 static int pin_2_irq(int idx, int ioapic, int pin, unsigned int flags)
1111 u32 gsi = mp_pin_to_gsi(ioapic, pin);
1114 * Debugging check, we are in big trouble if this message pops up!
1116 if (mp_irqs[idx].dstirq != pin)
1117 pr_err("broken BIOS or MPTABLE parser, ayiee!!\n");
1119 #ifdef CONFIG_X86_32
1121 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1123 if ((pin >= 16) && (pin <= 23)) {
1124 if (pirq_entries[pin-16] != -1) {
1125 if (!pirq_entries[pin-16]) {
1126 apic_printk(APIC_VERBOSE, KERN_DEBUG
1127 "disabling PIRQ%d\n", pin-16);
1129 int irq = pirq_entries[pin-16];
1130 apic_printk(APIC_VERBOSE, KERN_DEBUG
1131 "using PIRQ%d -> IRQ %d\n",
1139 return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, NULL);
1142 int mp_map_gsi_to_irq(u32 gsi, unsigned int flags, struct irq_alloc_info *info)
1144 int ioapic, pin, idx;
1146 ioapic = mp_find_ioapic(gsi);
1150 pin = mp_find_ioapic_pin(ioapic, gsi);
1151 idx = find_irq_entry(ioapic, pin, mp_INT);
1152 if ((flags & IOAPIC_MAP_CHECK) && idx < 0)
1155 return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, info);
1158 void mp_unmap_irq(int irq)
1160 struct irq_data *irq_data = irq_get_irq_data(irq);
1161 struct mp_chip_data *data;
1163 if (!irq_data || !irq_data->domain)
1166 data = irq_data->chip_data;
1167 if (!data || data->isa_irq)
1170 mutex_lock(&ioapic_mutex);
1171 if (--data->count == 0)
1172 irq_domain_free_irqs(irq, 1);
1173 mutex_unlock(&ioapic_mutex);
1177 * Find a specific PCI IRQ entry.
1178 * Not an __init, possibly needed by modules
1180 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
1182 int irq, i, best_ioapic = -1, best_idx = -1;
1184 apic_printk(APIC_DEBUG,
1185 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1187 if (test_bit(bus, mp_bus_not_pci)) {
1188 apic_printk(APIC_VERBOSE,
1189 "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1193 for (i = 0; i < mp_irq_entries; i++) {
1194 int lbus = mp_irqs[i].srcbus;
1195 int ioapic_idx, found = 0;
1197 if (bus != lbus || mp_irqs[i].irqtype != mp_INT ||
1198 slot != ((mp_irqs[i].srcbusirq >> 2) & 0x1f))
1201 for_each_ioapic(ioapic_idx)
1202 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic ||
1203 mp_irqs[i].dstapic == MP_APIC_ALL) {
1211 irq = pin_2_irq(i, ioapic_idx, mp_irqs[i].dstirq, 0);
1212 if (irq > 0 && !IO_APIC_IRQ(irq))
1215 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1217 best_ioapic = ioapic_idx;
1222 * Use the first all-but-pin matching entry as a
1223 * best-guess fuzzy result for broken mptables.
1227 best_ioapic = ioapic_idx;
1234 return pin_2_irq(best_idx, best_ioapic, mp_irqs[best_idx].dstirq,
1237 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1239 static struct irq_chip ioapic_chip, ioapic_ir_chip;
1241 #ifdef CONFIG_X86_32
1242 static inline int IO_APIC_irq_trigger(int irq)
1246 for_each_ioapic_pin(apic, pin) {
1247 idx = find_irq_entry(apic, pin, mp_INT);
1248 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin, 0)))
1249 return irq_trigger(idx);
1252 * nonexistent IRQs are edge default
1257 static inline int IO_APIC_irq_trigger(int irq)
1263 static void __init setup_IO_APIC_irqs(void)
1265 unsigned int ioapic, pin;
1268 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1270 for_each_ioapic_pin(ioapic, pin) {
1271 idx = find_irq_entry(ioapic, pin, mp_INT);
1273 apic_printk(APIC_VERBOSE,
1274 KERN_DEBUG " apic %d pin %d not connected\n",
1275 mpc_ioapic_id(ioapic), pin);
1277 pin_2_irq(idx, ioapic, pin,
1278 ioapic ? 0 : IOAPIC_MAP_ALLOC);
1282 void ioapic_zap_locks(void)
1284 raw_spin_lock_init(&ioapic_lock);
1287 static void io_apic_print_entries(unsigned int apic, unsigned int nr_entries)
1291 struct IO_APIC_route_entry entry;
1292 struct IR_IO_APIC_route_entry *ir_entry = (void *)&entry;
1294 printk(KERN_DEBUG "IOAPIC %d:\n", apic);
1295 for (i = 0; i <= nr_entries; i++) {
1296 entry = ioapic_read_entry(apic, i);
1297 snprintf(buf, sizeof(buf),
1298 " pin%02x, %s, %s, %s, V(%02X), IRR(%1d), S(%1d)",
1300 entry.mask == IOAPIC_MASKED ? "disabled" : "enabled ",
1301 entry.trigger == IOAPIC_LEVEL ? "level" : "edge ",
1302 entry.polarity == IOAPIC_POL_LOW ? "low " : "high",
1303 entry.vector, entry.irr, entry.delivery_status);
1304 if (ir_entry->format)
1305 printk(KERN_DEBUG "%s, remapped, I(%04X), Z(%X)\n",
1306 buf, (ir_entry->index << 15) | ir_entry->index,
1309 printk(KERN_DEBUG "%s, %s, D(%02X), M(%1d)\n",
1311 entry.dest_mode == IOAPIC_DEST_MODE_LOGICAL ?
1312 "logical " : "physical",
1313 entry.dest, entry.delivery_mode);
1317 static void __init print_IO_APIC(int ioapic_idx)
1319 union IO_APIC_reg_00 reg_00;
1320 union IO_APIC_reg_01 reg_01;
1321 union IO_APIC_reg_02 reg_02;
1322 union IO_APIC_reg_03 reg_03;
1323 unsigned long flags;
1325 raw_spin_lock_irqsave(&ioapic_lock, flags);
1326 reg_00.raw = io_apic_read(ioapic_idx, 0);
1327 reg_01.raw = io_apic_read(ioapic_idx, 1);
1328 if (reg_01.bits.version >= 0x10)
1329 reg_02.raw = io_apic_read(ioapic_idx, 2);
1330 if (reg_01.bits.version >= 0x20)
1331 reg_03.raw = io_apic_read(ioapic_idx, 3);
1332 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1334 printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx));
1335 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1336 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1337 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1338 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1340 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1341 printk(KERN_DEBUG "....... : max redirection entries: %02X\n",
1342 reg_01.bits.entries);
1344 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1345 printk(KERN_DEBUG "....... : IO APIC version: %02X\n",
1346 reg_01.bits.version);
1349 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1350 * but the value of reg_02 is read as the previous read register
1351 * value, so ignore it if reg_02 == reg_01.
1353 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1354 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1355 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1359 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1360 * or reg_03, but the value of reg_0[23] is read as the previous read
1361 * register value, so ignore it if reg_03 == reg_0[12].
1363 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1364 reg_03.raw != reg_01.raw) {
1365 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1366 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1369 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1370 io_apic_print_entries(ioapic_idx, reg_01.bits.entries);
1373 void __init print_IO_APICs(void)
1378 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1379 for_each_ioapic(ioapic_idx)
1380 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1381 mpc_ioapic_id(ioapic_idx),
1382 ioapics[ioapic_idx].nr_registers);
1385 * We are a bit conservative about what we expect. We have to
1386 * know about every hardware change ASAP.
1388 printk(KERN_INFO "testing the IO APIC.......................\n");
1390 for_each_ioapic(ioapic_idx)
1391 print_IO_APIC(ioapic_idx);
1393 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1394 for_each_active_irq(irq) {
1395 struct irq_pin_list *entry;
1396 struct irq_chip *chip;
1397 struct mp_chip_data *data;
1399 chip = irq_get_chip(irq);
1400 if (chip != &ioapic_chip && chip != &ioapic_ir_chip)
1402 data = irq_get_chip_data(irq);
1405 if (list_empty(&data->irq_2_pin))
1408 printk(KERN_DEBUG "IRQ%d ", irq);
1409 for_each_irq_pin(entry, data->irq_2_pin)
1410 pr_cont("-> %d:%d", entry->apic, entry->pin);
1414 printk(KERN_INFO ".................................... done.\n");
1417 /* Where if anywhere is the i8259 connect in external int mode */
1418 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1420 void __init enable_IO_APIC(void)
1422 int i8259_apic, i8259_pin;
1425 if (skip_ioapic_setup)
1428 if (!nr_legacy_irqs() || !nr_ioapics)
1431 for_each_ioapic_pin(apic, pin) {
1432 /* See if any of the pins is in ExtINT mode */
1433 struct IO_APIC_route_entry entry = ioapic_read_entry(apic, pin);
1435 /* If the interrupt line is enabled and in ExtInt mode
1436 * I have found the pin where the i8259 is connected.
1438 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1439 ioapic_i8259.apic = apic;
1440 ioapic_i8259.pin = pin;
1445 /* Look to see what if the MP table has reported the ExtINT */
1446 /* If we could not find the appropriate pin by looking at the ioapic
1447 * the i8259 probably is not connected the ioapic but give the
1448 * mptable a chance anyway.
1450 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1451 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1452 /* Trust the MP table if nothing is setup in the hardware */
1453 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1454 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1455 ioapic_i8259.pin = i8259_pin;
1456 ioapic_i8259.apic = i8259_apic;
1458 /* Complain if the MP table and the hardware disagree */
1459 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1460 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1462 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1466 * Do not trust the IO-APIC being empty at bootup
1471 void native_disable_io_apic(void)
1474 * If the i8259 is routed through an IOAPIC
1475 * Put that IOAPIC in virtual wire mode
1476 * so legacy interrupts can be delivered.
1478 if (ioapic_i8259.pin != -1) {
1479 struct IO_APIC_route_entry entry;
1481 memset(&entry, 0, sizeof(entry));
1482 entry.mask = IOAPIC_UNMASKED;
1483 entry.trigger = IOAPIC_EDGE;
1484 entry.polarity = IOAPIC_POL_HIGH;
1485 entry.dest_mode = IOAPIC_DEST_MODE_PHYSICAL;
1486 entry.delivery_mode = dest_ExtINT;
1487 entry.dest = read_apic_id();
1490 * Add it to the IO-APIC irq-routing table:
1492 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1495 if (cpu_has_apic || apic_from_smp_config())
1496 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1500 * Not an __init, needed by the reboot code
1502 void disable_IO_APIC(void)
1505 * Clear the IO-APIC before rebooting:
1509 if (!nr_legacy_irqs())
1512 x86_io_apic_ops.disable();
1515 #ifdef CONFIG_X86_32
1517 * function to set the IO-APIC physical IDs based on the
1518 * values stored in the MPC table.
1520 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1522 void __init setup_ioapic_ids_from_mpc_nocheck(void)
1524 union IO_APIC_reg_00 reg_00;
1525 physid_mask_t phys_id_present_map;
1528 unsigned char old_id;
1529 unsigned long flags;
1532 * This is broken; anything with a real cpu count has to
1533 * circumvent this idiocy regardless.
1535 apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map);
1538 * Set the IOAPIC ID to the value stored in the MPC table.
1540 for_each_ioapic(ioapic_idx) {
1541 /* Read the register 0 value */
1542 raw_spin_lock_irqsave(&ioapic_lock, flags);
1543 reg_00.raw = io_apic_read(ioapic_idx, 0);
1544 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1546 old_id = mpc_ioapic_id(ioapic_idx);
1548 if (mpc_ioapic_id(ioapic_idx) >= get_physical_broadcast()) {
1549 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1550 ioapic_idx, mpc_ioapic_id(ioapic_idx));
1551 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1553 ioapics[ioapic_idx].mp_config.apicid = reg_00.bits.ID;
1557 * Sanity check, is the ID really free? Every APIC in a
1558 * system must have a unique ID or we get lots of nice
1559 * 'stuck on smp_invalidate_needed IPI wait' messages.
1561 if (apic->check_apicid_used(&phys_id_present_map,
1562 mpc_ioapic_id(ioapic_idx))) {
1563 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1564 ioapic_idx, mpc_ioapic_id(ioapic_idx));
1565 for (i = 0; i < get_physical_broadcast(); i++)
1566 if (!physid_isset(i, phys_id_present_map))
1568 if (i >= get_physical_broadcast())
1569 panic("Max APIC ID exceeded!\n");
1570 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1572 physid_set(i, phys_id_present_map);
1573 ioapics[ioapic_idx].mp_config.apicid = i;
1576 apic->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx),
1578 apic_printk(APIC_VERBOSE, "Setting %d in the "
1579 "phys_id_present_map\n",
1580 mpc_ioapic_id(ioapic_idx));
1581 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1585 * We need to adjust the IRQ routing table
1586 * if the ID changed.
1588 if (old_id != mpc_ioapic_id(ioapic_idx))
1589 for (i = 0; i < mp_irq_entries; i++)
1590 if (mp_irqs[i].dstapic == old_id)
1592 = mpc_ioapic_id(ioapic_idx);
1595 * Update the ID register according to the right value
1596 * from the MPC table if they are different.
1598 if (mpc_ioapic_id(ioapic_idx) == reg_00.bits.ID)
1601 apic_printk(APIC_VERBOSE, KERN_INFO
1602 "...changing IO-APIC physical APIC ID to %d ...",
1603 mpc_ioapic_id(ioapic_idx));
1605 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
1606 raw_spin_lock_irqsave(&ioapic_lock, flags);
1607 io_apic_write(ioapic_idx, 0, reg_00.raw);
1608 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1613 raw_spin_lock_irqsave(&ioapic_lock, flags);
1614 reg_00.raw = io_apic_read(ioapic_idx, 0);
1615 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1616 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx))
1617 pr_cont("could not set ID!\n");
1619 apic_printk(APIC_VERBOSE, " ok.\n");
1623 void __init setup_ioapic_ids_from_mpc(void)
1629 * Don't check I/O APIC IDs for xAPIC systems. They have
1630 * no meaning without the serial APIC bus.
1632 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1633 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1635 setup_ioapic_ids_from_mpc_nocheck();
1639 int no_timer_check __initdata;
1641 static int __init notimercheck(char *s)
1646 __setup("no_timer_check", notimercheck);
1649 * There is a nasty bug in some older SMP boards, their mptable lies
1650 * about the timer IRQ. We do the following to work around the situation:
1652 * - timer IRQ defaults to IO-APIC IRQ
1653 * - if this function detects that timer IRQs are defunct, then we fall
1654 * back to ISA timer IRQs
1656 static int __init timer_irq_works(void)
1658 unsigned long t1 = jiffies;
1659 unsigned long flags;
1664 local_save_flags(flags);
1666 /* Let ten ticks pass... */
1667 mdelay((10 * 1000) / HZ);
1668 local_irq_restore(flags);
1671 * Expect a few ticks at least, to be sure some possible
1672 * glue logic does not lock up after one or two first
1673 * ticks in a non-ExtINT mode. Also the local APIC
1674 * might have cached one ExtINT interrupt. Finally, at
1675 * least one tick may be lost due to delays.
1679 if (time_after(jiffies, t1 + 4))
1685 * In the SMP+IOAPIC case it might happen that there are an unspecified
1686 * number of pending IRQ events unhandled. These cases are very rare,
1687 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1688 * better to do it this way as thus we do not have to be aware of
1689 * 'pending' interrupts in the IRQ path, except at this point.
1692 * Edge triggered needs to resend any interrupt
1693 * that was delayed but this is now handled in the device
1698 * Starting up a edge-triggered IO-APIC interrupt is
1699 * nasty - we need to make sure that we get the edge.
1700 * If it is already asserted for some reason, we need
1701 * return 1 to indicate that is was pending.
1703 * This is not complete - we should be able to fake
1704 * an edge even if it isn't on the 8259A...
1706 static unsigned int startup_ioapic_irq(struct irq_data *data)
1708 int was_pending = 0, irq = data->irq;
1709 unsigned long flags;
1711 raw_spin_lock_irqsave(&ioapic_lock, flags);
1712 if (irq < nr_legacy_irqs()) {
1713 legacy_pic->mask(irq);
1714 if (legacy_pic->irq_pending(irq))
1717 __unmask_ioapic(data->chip_data);
1718 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1723 atomic_t irq_mis_count;
1725 #ifdef CONFIG_GENERIC_PENDING_IRQ
1726 static bool io_apic_level_ack_pending(struct mp_chip_data *data)
1728 struct irq_pin_list *entry;
1729 unsigned long flags;
1731 raw_spin_lock_irqsave(&ioapic_lock, flags);
1732 for_each_irq_pin(entry, data->irq_2_pin) {
1737 reg = io_apic_read(entry->apic, 0x10 + pin*2);
1738 /* Is the remote IRR bit set? */
1739 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
1740 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1744 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1749 static inline bool ioapic_irqd_mask(struct irq_data *data)
1751 /* If we are moving the irq we need to mask it */
1752 if (unlikely(irqd_is_setaffinity_pending(data))) {
1753 mask_ioapic_irq(data);
1759 static inline void ioapic_irqd_unmask(struct irq_data *data, bool masked)
1761 if (unlikely(masked)) {
1762 /* Only migrate the irq if the ack has been received.
1764 * On rare occasions the broadcast level triggered ack gets
1765 * delayed going to ioapics, and if we reprogram the
1766 * vector while Remote IRR is still set the irq will never
1769 * To prevent this scenario we read the Remote IRR bit
1770 * of the ioapic. This has two effects.
1771 * - On any sane system the read of the ioapic will
1772 * flush writes (and acks) going to the ioapic from
1774 * - We get to see if the ACK has actually been delivered.
1776 * Based on failed experiments of reprogramming the
1777 * ioapic entry from outside of irq context starting
1778 * with masking the ioapic entry and then polling until
1779 * Remote IRR was clear before reprogramming the
1780 * ioapic I don't trust the Remote IRR bit to be
1781 * completey accurate.
1783 * However there appears to be no other way to plug
1784 * this race, so if the Remote IRR bit is not
1785 * accurate and is causing problems then it is a hardware bug
1786 * and you can go talk to the chipset vendor about it.
1788 if (!io_apic_level_ack_pending(data->chip_data))
1789 irq_move_masked_irq(data);
1790 unmask_ioapic_irq(data);
1794 static inline bool ioapic_irqd_mask(struct irq_data *data)
1798 static inline void ioapic_irqd_unmask(struct irq_data *data, bool masked)
1803 static void ioapic_ack_level(struct irq_data *irq_data)
1805 struct irq_cfg *cfg = irqd_cfg(irq_data);
1810 irq_complete_move(cfg);
1811 masked = ioapic_irqd_mask(irq_data);
1814 * It appears there is an erratum which affects at least version 0x11
1815 * of I/O APIC (that's the 82093AA and cores integrated into various
1816 * chipsets). Under certain conditions a level-triggered interrupt is
1817 * erroneously delivered as edge-triggered one but the respective IRR
1818 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1819 * message but it will never arrive and further interrupts are blocked
1820 * from the source. The exact reason is so far unknown, but the
1821 * phenomenon was observed when two consecutive interrupt requests
1822 * from a given source get delivered to the same CPU and the source is
1823 * temporarily disabled in between.
1825 * A workaround is to simulate an EOI message manually. We achieve it
1826 * by setting the trigger mode to edge and then to level when the edge
1827 * trigger mode gets detected in the TMR of a local APIC for a
1828 * level-triggered interrupt. We mask the source for the time of the
1829 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1830 * The idea is from Manfred Spraul. --macro
1832 * Also in the case when cpu goes offline, fixup_irqs() will forward
1833 * any unhandled interrupt on the offlined cpu to the new cpu
1834 * destination that is handling the corresponding interrupt. This
1835 * interrupt forwarding is done via IPI's. Hence, in this case also
1836 * level-triggered io-apic interrupt will be seen as an edge
1837 * interrupt in the IRR. And we can't rely on the cpu's EOI
1838 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
1839 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
1840 * supporting EOI register, we do an explicit EOI to clear the
1841 * remote IRR and on IO-APIC's which don't have an EOI register,
1842 * we use the above logic (mask+edge followed by unmask+level) from
1843 * Manfred Spraul to clear the remote IRR.
1846 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1849 * We must acknowledge the irq before we move it or the acknowledge will
1850 * not propagate properly.
1855 * Tail end of clearing remote IRR bit (either by delivering the EOI
1856 * message via io-apic EOI register write or simulating it using
1857 * mask+edge followed by unnask+level logic) manually when the
1858 * level triggered interrupt is seen as the edge triggered interrupt
1861 if (!(v & (1 << (i & 0x1f)))) {
1862 atomic_inc(&irq_mis_count);
1863 eoi_ioapic_pin(cfg->vector, irq_data->chip_data);
1866 ioapic_irqd_unmask(irq_data, masked);
1869 static void ioapic_ir_ack_level(struct irq_data *irq_data)
1871 struct mp_chip_data *data = irq_data->chip_data;
1874 * Intr-remapping uses pin number as the virtual vector
1875 * in the RTE. Actual vector is programmed in
1876 * intr-remapping table entry. Hence for the io-apic
1877 * EOI we use the pin number.
1880 eoi_ioapic_pin(data->entry.vector, data);
1883 static int ioapic_set_affinity(struct irq_data *irq_data,
1884 const struct cpumask *mask, bool force)
1886 struct irq_data *parent = irq_data->parent_data;
1887 struct mp_chip_data *data = irq_data->chip_data;
1888 struct irq_pin_list *entry;
1889 struct irq_cfg *cfg;
1890 unsigned long flags;
1893 ret = parent->chip->irq_set_affinity(parent, mask, force);
1894 raw_spin_lock_irqsave(&ioapic_lock, flags);
1895 if (ret >= 0 && ret != IRQ_SET_MASK_OK_DONE) {
1896 cfg = irqd_cfg(irq_data);
1897 data->entry.dest = cfg->dest_apicid;
1898 data->entry.vector = cfg->vector;
1899 for_each_irq_pin(entry, data->irq_2_pin)
1900 __ioapic_write_entry(entry->apic, entry->pin,
1903 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1908 static struct irq_chip ioapic_chip __read_mostly = {
1910 .irq_startup = startup_ioapic_irq,
1911 .irq_mask = mask_ioapic_irq,
1912 .irq_unmask = unmask_ioapic_irq,
1913 .irq_ack = irq_chip_ack_parent,
1914 .irq_eoi = ioapic_ack_level,
1915 .irq_set_affinity = ioapic_set_affinity,
1916 .flags = IRQCHIP_SKIP_SET_WAKE,
1919 static struct irq_chip ioapic_ir_chip __read_mostly = {
1920 .name = "IR-IO-APIC",
1921 .irq_startup = startup_ioapic_irq,
1922 .irq_mask = mask_ioapic_irq,
1923 .irq_unmask = unmask_ioapic_irq,
1924 .irq_ack = irq_chip_ack_parent,
1925 .irq_eoi = ioapic_ir_ack_level,
1926 .irq_set_affinity = ioapic_set_affinity,
1927 .flags = IRQCHIP_SKIP_SET_WAKE,
1930 static inline void init_IO_APIC_traps(void)
1932 struct irq_cfg *cfg;
1935 for_each_active_irq(irq) {
1937 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
1939 * Hmm.. We don't have an entry for this,
1940 * so default to an old-fashioned 8259
1941 * interrupt if we can..
1943 if (irq < nr_legacy_irqs())
1944 legacy_pic->make_irq(irq);
1946 /* Strange. Oh, well.. */
1947 irq_set_chip(irq, &no_irq_chip);
1953 * The local APIC irq-chip implementation:
1956 static void mask_lapic_irq(struct irq_data *data)
1960 v = apic_read(APIC_LVT0);
1961 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1964 static void unmask_lapic_irq(struct irq_data *data)
1968 v = apic_read(APIC_LVT0);
1969 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1972 static void ack_lapic_irq(struct irq_data *data)
1977 static struct irq_chip lapic_chip __read_mostly = {
1978 .name = "local-APIC",
1979 .irq_mask = mask_lapic_irq,
1980 .irq_unmask = unmask_lapic_irq,
1981 .irq_ack = ack_lapic_irq,
1984 static void lapic_register_intr(int irq)
1986 irq_clear_status_flags(irq, IRQ_LEVEL);
1987 irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
1992 * This looks a bit hackish but it's about the only one way of sending
1993 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1994 * not support the ExtINT mode, unfortunately. We need to send these
1995 * cycles as some i82489DX-based boards have glue logic that keeps the
1996 * 8259A interrupt line asserted until INTA. --macro
1998 static inline void __init unlock_ExtINT_logic(void)
2001 struct IO_APIC_route_entry entry0, entry1;
2002 unsigned char save_control, save_freq_select;
2004 pin = find_isa_irq_pin(8, mp_INT);
2009 apic = find_isa_irq_apic(8, mp_INT);
2015 entry0 = ioapic_read_entry(apic, pin);
2016 clear_IO_APIC_pin(apic, pin);
2018 memset(&entry1, 0, sizeof(entry1));
2020 entry1.dest_mode = IOAPIC_DEST_MODE_PHYSICAL;
2021 entry1.mask = IOAPIC_UNMASKED;
2022 entry1.dest = hard_smp_processor_id();
2023 entry1.delivery_mode = dest_ExtINT;
2024 entry1.polarity = entry0.polarity;
2025 entry1.trigger = IOAPIC_EDGE;
2028 ioapic_write_entry(apic, pin, entry1);
2030 save_control = CMOS_READ(RTC_CONTROL);
2031 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2032 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2034 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2039 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2043 CMOS_WRITE(save_control, RTC_CONTROL);
2044 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2045 clear_IO_APIC_pin(apic, pin);
2047 ioapic_write_entry(apic, pin, entry0);
2050 static int disable_timer_pin_1 __initdata;
2051 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2052 static int __init disable_timer_pin_setup(char *arg)
2054 disable_timer_pin_1 = 1;
2057 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2059 static int mp_alloc_timer_irq(int ioapic, int pin)
2062 struct irq_domain *domain = mp_ioapic_irqdomain(ioapic);
2065 struct irq_alloc_info info;
2067 ioapic_set_alloc_attr(&info, NUMA_NO_NODE, 0, 0);
2068 info.ioapic_id = mpc_ioapic_id(ioapic);
2069 info.ioapic_pin = pin;
2070 mutex_lock(&ioapic_mutex);
2071 irq = alloc_isa_irq_from_domain(domain, 0, ioapic, pin, &info);
2072 mutex_unlock(&ioapic_mutex);
2079 * This code may look a bit paranoid, but it's supposed to cooperate with
2080 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2081 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2082 * fanatically on his truly buggy board.
2084 * FIXME: really need to revamp this for all platforms.
2086 static inline void __init check_timer(void)
2088 struct irq_data *irq_data = irq_get_irq_data(0);
2089 struct mp_chip_data *data = irq_data->chip_data;
2090 struct irq_cfg *cfg = irqd_cfg(irq_data);
2091 int node = cpu_to_node(0);
2092 int apic1, pin1, apic2, pin2;
2093 unsigned long flags;
2096 local_irq_save(flags);
2099 * get/set the timer IRQ vector:
2101 legacy_pic->mask(0);
2104 * As IRQ0 is to be enabled in the 8259A, the virtual
2105 * wire has to be disabled in the local APIC. Also
2106 * timer interrupts need to be acknowledged manually in
2107 * the 8259A for the i82489DX when using the NMI
2108 * watchdog as that APIC treats NMIs as level-triggered.
2109 * The AEOI mode will finish them in the 8259A
2112 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2113 legacy_pic->init(1);
2115 pin1 = find_isa_irq_pin(0, mp_INT);
2116 apic1 = find_isa_irq_apic(0, mp_INT);
2117 pin2 = ioapic_i8259.pin;
2118 apic2 = ioapic_i8259.apic;
2120 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2121 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2122 cfg->vector, apic1, pin1, apic2, pin2);
2125 * Some BIOS writers are clueless and report the ExtINTA
2126 * I/O APIC input from the cascaded 8259A as the timer
2127 * interrupt input. So just in case, if only one pin
2128 * was found above, try it both directly and through the
2132 panic_if_irq_remap("BIOS bug: timer not connected to IO-APIC");
2136 } else if (pin2 == -1) {
2142 /* Ok, does IRQ0 through the IOAPIC work? */
2144 mp_alloc_timer_irq(apic1, pin1);
2147 * for edge trigger, it's already unmasked,
2148 * so only need to unmask if it is level-trigger
2149 * do we really have level trigger timer?
2152 idx = find_irq_entry(apic1, pin1, mp_INT);
2153 if (idx != -1 && irq_trigger(idx))
2154 unmask_ioapic_irq(irq_get_chip_data(0));
2156 irq_domain_activate_irq(irq_data);
2157 if (timer_irq_works()) {
2158 if (disable_timer_pin_1 > 0)
2159 clear_IO_APIC_pin(0, pin1);
2162 panic_if_irq_remap("timer doesn't work through Interrupt-remapped IO-APIC");
2163 local_irq_disable();
2164 clear_IO_APIC_pin(apic1, pin1);
2166 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2167 "8254 timer not connected to IO-APIC\n");
2169 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2170 "(IRQ0) through the 8259A ...\n");
2171 apic_printk(APIC_QUIET, KERN_INFO
2172 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2174 * legacy devices should be connected to IO APIC #0
2176 replace_pin_at_irq_node(data, node, apic1, pin1, apic2, pin2);
2177 irq_domain_activate_irq(irq_data);
2178 legacy_pic->unmask(0);
2179 if (timer_irq_works()) {
2180 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2184 * Cleanup, just in case ...
2186 local_irq_disable();
2187 legacy_pic->mask(0);
2188 clear_IO_APIC_pin(apic2, pin2);
2189 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2192 apic_printk(APIC_QUIET, KERN_INFO
2193 "...trying to set up timer as Virtual Wire IRQ...\n");
2195 lapic_register_intr(0);
2196 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2197 legacy_pic->unmask(0);
2199 if (timer_irq_works()) {
2200 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2203 local_irq_disable();
2204 legacy_pic->mask(0);
2205 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2206 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2208 apic_printk(APIC_QUIET, KERN_INFO
2209 "...trying to set up timer as ExtINT IRQ...\n");
2211 legacy_pic->init(0);
2212 legacy_pic->make_irq(0);
2213 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2215 unlock_ExtINT_logic();
2217 if (timer_irq_works()) {
2218 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2221 local_irq_disable();
2222 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2223 if (apic_is_x2apic_enabled())
2224 apic_printk(APIC_QUIET, KERN_INFO
2225 "Perhaps problem with the pre-enabled x2apic mode\n"
2226 "Try booting with x2apic and interrupt-remapping disabled in the bios.\n");
2227 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2228 "report. Then try booting with the 'noapic' option.\n");
2230 local_irq_restore(flags);
2234 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2235 * to devices. However there may be an I/O APIC pin available for
2236 * this interrupt regardless. The pin may be left unconnected, but
2237 * typically it will be reused as an ExtINT cascade interrupt for
2238 * the master 8259A. In the MPS case such a pin will normally be
2239 * reported as an ExtINT interrupt in the MP table. With ACPI
2240 * there is no provision for ExtINT interrupts, and in the absence
2241 * of an override it would be treated as an ordinary ISA I/O APIC
2242 * interrupt, that is edge-triggered and unmasked by default. We
2243 * used to do this, but it caused problems on some systems because
2244 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2245 * the same ExtINT cascade interrupt to drive the local APIC of the
2246 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2247 * the I/O APIC in all cases now. No actual device should request
2248 * it anyway. --macro
2250 #define PIC_IRQS (1UL << PIC_CASCADE_IR)
2252 static int mp_irqdomain_create(int ioapic)
2254 struct irq_alloc_info info;
2255 struct irq_domain *parent;
2256 int hwirqs = mp_ioapic_pin_count(ioapic);
2257 struct ioapic *ip = &ioapics[ioapic];
2258 struct ioapic_domain_cfg *cfg = &ip->irqdomain_cfg;
2259 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2261 if (cfg->type == IOAPIC_DOMAIN_INVALID)
2264 init_irq_alloc_info(&info, NULL);
2265 info.type = X86_IRQ_ALLOC_TYPE_IOAPIC;
2266 info.ioapic_id = mpc_ioapic_id(ioapic);
2267 parent = irq_remapping_get_ir_irq_domain(&info);
2269 parent = x86_vector_domain;
2271 ip->irqdomain = irq_domain_add_linear(cfg->dev, hwirqs, cfg->ops,
2272 (void *)(long)ioapic);
2276 ip->irqdomain->parent = parent;
2278 if (cfg->type == IOAPIC_DOMAIN_LEGACY ||
2279 cfg->type == IOAPIC_DOMAIN_STRICT)
2280 ioapic_dynirq_base = max(ioapic_dynirq_base,
2281 gsi_cfg->gsi_end + 1);
2286 static void ioapic_destroy_irqdomain(int idx)
2288 if (ioapics[idx].irqdomain) {
2289 irq_domain_remove(ioapics[idx].irqdomain);
2290 ioapics[idx].irqdomain = NULL;
2294 void __init setup_IO_APIC(void)
2298 if (skip_ioapic_setup || !nr_ioapics)
2301 io_apic_irqs = nr_legacy_irqs() ? ~PIC_IRQS : ~0UL;
2303 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2304 for_each_ioapic(ioapic)
2305 BUG_ON(mp_irqdomain_create(ioapic));
2308 * Set up IO-APIC IRQ routing.
2310 x86_init.mpparse.setup_ioapic_ids();
2313 setup_IO_APIC_irqs();
2314 init_IO_APIC_traps();
2315 if (nr_legacy_irqs())
2318 ioapic_initialized = 1;
2321 static void resume_ioapic_id(int ioapic_idx)
2323 unsigned long flags;
2324 union IO_APIC_reg_00 reg_00;
2326 raw_spin_lock_irqsave(&ioapic_lock, flags);
2327 reg_00.raw = io_apic_read(ioapic_idx, 0);
2328 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) {
2329 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
2330 io_apic_write(ioapic_idx, 0, reg_00.raw);
2332 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2335 static void ioapic_resume(void)
2339 for_each_ioapic_reverse(ioapic_idx)
2340 resume_ioapic_id(ioapic_idx);
2342 restore_ioapic_entries();
2345 static struct syscore_ops ioapic_syscore_ops = {
2346 .suspend = save_ioapic_entries,
2347 .resume = ioapic_resume,
2350 static int __init ioapic_init_ops(void)
2352 register_syscore_ops(&ioapic_syscore_ops);
2357 device_initcall(ioapic_init_ops);
2359 static int io_apic_get_redir_entries(int ioapic)
2361 union IO_APIC_reg_01 reg_01;
2362 unsigned long flags;
2364 raw_spin_lock_irqsave(&ioapic_lock, flags);
2365 reg_01.raw = io_apic_read(ioapic, 1);
2366 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2368 /* The register returns the maximum index redir index
2369 * supported, which is one less than the total number of redir
2372 return reg_01.bits.entries + 1;
2375 unsigned int arch_dynirq_lower_bound(unsigned int from)
2378 * dmar_alloc_hwirq() may be called before setup_IO_APIC(), so use
2379 * gsi_top if ioapic_dynirq_base hasn't been initialized yet.
2381 return ioapic_initialized ? ioapic_dynirq_base : gsi_top;
2384 #ifdef CONFIG_X86_32
2385 static int io_apic_get_unique_id(int ioapic, int apic_id)
2387 union IO_APIC_reg_00 reg_00;
2388 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2390 unsigned long flags;
2394 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2395 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2396 * supports up to 16 on one shared APIC bus.
2398 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2399 * advantage of new APIC bus architecture.
2402 if (physids_empty(apic_id_map))
2403 apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map);
2405 raw_spin_lock_irqsave(&ioapic_lock, flags);
2406 reg_00.raw = io_apic_read(ioapic, 0);
2407 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2409 if (apic_id >= get_physical_broadcast()) {
2410 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2411 "%d\n", ioapic, apic_id, reg_00.bits.ID);
2412 apic_id = reg_00.bits.ID;
2416 * Every APIC in a system must have a unique ID or we get lots of nice
2417 * 'stuck on smp_invalidate_needed IPI wait' messages.
2419 if (apic->check_apicid_used(&apic_id_map, apic_id)) {
2421 for (i = 0; i < get_physical_broadcast(); i++) {
2422 if (!apic->check_apicid_used(&apic_id_map, i))
2426 if (i == get_physical_broadcast())
2427 panic("Max apic_id exceeded!\n");
2429 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2430 "trying %d\n", ioapic, apic_id, i);
2435 apic->apicid_to_cpu_present(apic_id, &tmp);
2436 physids_or(apic_id_map, apic_id_map, tmp);
2438 if (reg_00.bits.ID != apic_id) {
2439 reg_00.bits.ID = apic_id;
2441 raw_spin_lock_irqsave(&ioapic_lock, flags);
2442 io_apic_write(ioapic, 0, reg_00.raw);
2443 reg_00.raw = io_apic_read(ioapic, 0);
2444 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2447 if (reg_00.bits.ID != apic_id) {
2448 pr_err("IOAPIC[%d]: Unable to change apic_id!\n",
2454 apic_printk(APIC_VERBOSE, KERN_INFO
2455 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2460 static u8 io_apic_unique_id(int idx, u8 id)
2462 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
2463 !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2464 return io_apic_get_unique_id(idx, id);
2469 static u8 io_apic_unique_id(int idx, u8 id)
2471 union IO_APIC_reg_00 reg_00;
2472 DECLARE_BITMAP(used, 256);
2473 unsigned long flags;
2477 bitmap_zero(used, 256);
2479 __set_bit(mpc_ioapic_id(i), used);
2481 /* Hand out the requested id if available */
2482 if (!test_bit(id, used))
2486 * Read the current id from the ioapic and keep it if
2489 raw_spin_lock_irqsave(&ioapic_lock, flags);
2490 reg_00.raw = io_apic_read(idx, 0);
2491 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2492 new_id = reg_00.bits.ID;
2493 if (!test_bit(new_id, used)) {
2494 apic_printk(APIC_VERBOSE, KERN_INFO
2495 "IOAPIC[%d]: Using reg apic_id %d instead of %d\n",
2501 * Get the next free id and write it to the ioapic.
2503 new_id = find_first_zero_bit(used, 256);
2504 reg_00.bits.ID = new_id;
2505 raw_spin_lock_irqsave(&ioapic_lock, flags);
2506 io_apic_write(idx, 0, reg_00.raw);
2507 reg_00.raw = io_apic_read(idx, 0);
2508 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2510 BUG_ON(reg_00.bits.ID != new_id);
2516 static int io_apic_get_version(int ioapic)
2518 union IO_APIC_reg_01 reg_01;
2519 unsigned long flags;
2521 raw_spin_lock_irqsave(&ioapic_lock, flags);
2522 reg_01.raw = io_apic_read(ioapic, 1);
2523 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2525 return reg_01.bits.version;
2528 int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity)
2530 int ioapic, pin, idx;
2532 if (skip_ioapic_setup)
2535 ioapic = mp_find_ioapic(gsi);
2539 pin = mp_find_ioapic_pin(ioapic, gsi);
2543 idx = find_irq_entry(ioapic, pin, mp_INT);
2547 *trigger = irq_trigger(idx);
2548 *polarity = irq_polarity(idx);
2553 * This function currently is only a helper for the i386 smp boot process where
2554 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2555 * so mask in all cases should simply be apic->target_cpus()
2558 void __init setup_ioapic_dest(void)
2560 int pin, ioapic, irq, irq_entry;
2561 const struct cpumask *mask;
2562 struct irq_data *idata;
2564 if (skip_ioapic_setup == 1)
2567 for_each_ioapic_pin(ioapic, pin) {
2568 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2569 if (irq_entry == -1)
2572 irq = pin_2_irq(irq_entry, ioapic, pin, 0);
2573 if (irq < 0 || !mp_init_irq_at_boot(ioapic, irq))
2576 idata = irq_get_irq_data(irq);
2579 * Honour affinities which have been set in early boot
2581 if (!irqd_can_balance(idata) || irqd_affinity_was_set(idata))
2582 mask = idata->affinity;
2584 mask = apic->target_cpus();
2586 irq_set_affinity(irq, mask);
2592 #define IOAPIC_RESOURCE_NAME_SIZE 11
2594 static struct resource *ioapic_resources;
2596 static struct resource * __init ioapic_setup_resources(void)
2599 struct resource *res;
2608 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
2611 mem = alloc_bootmem(n);
2614 mem += sizeof(struct resource) * num;
2617 for_each_ioapic(i) {
2618 res[num].name = mem;
2619 res[num].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
2620 snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
2621 mem += IOAPIC_RESOURCE_NAME_SIZE;
2623 ioapics[i].iomem_res = res;
2626 ioapic_resources = res;
2631 void __init io_apic_init_mappings(void)
2633 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
2634 struct resource *ioapic_res;
2637 ioapic_res = ioapic_setup_resources();
2638 for_each_ioapic(i) {
2639 if (smp_found_config) {
2640 ioapic_phys = mpc_ioapic_addr(i);
2641 #ifdef CONFIG_X86_32
2644 "WARNING: bogus zero IO-APIC "
2645 "address found in MPTABLE, "
2646 "disabling IO/APIC support!\n");
2647 smp_found_config = 0;
2648 skip_ioapic_setup = 1;
2649 goto fake_ioapic_page;
2653 #ifdef CONFIG_X86_32
2656 ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
2657 ioapic_phys = __pa(ioapic_phys);
2659 set_fixmap_nocache(idx, ioapic_phys);
2660 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
2661 __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK),
2665 ioapic_res->start = ioapic_phys;
2666 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
2671 void __init ioapic_insert_resources(void)
2674 struct resource *r = ioapic_resources;
2679 "IO APIC resources couldn't be allocated.\n");
2683 for_each_ioapic(i) {
2684 insert_resource(&iomem_resource, r);
2689 int mp_find_ioapic(u32 gsi)
2693 if (nr_ioapics == 0)
2696 /* Find the IOAPIC that manages this GSI. */
2697 for_each_ioapic(i) {
2698 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i);
2699 if (gsi >= gsi_cfg->gsi_base && gsi <= gsi_cfg->gsi_end)
2703 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
2707 int mp_find_ioapic_pin(int ioapic, u32 gsi)
2709 struct mp_ioapic_gsi *gsi_cfg;
2711 if (WARN_ON(ioapic < 0))
2714 gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2715 if (WARN_ON(gsi > gsi_cfg->gsi_end))
2718 return gsi - gsi_cfg->gsi_base;
2721 static int bad_ioapic_register(int idx)
2723 union IO_APIC_reg_00 reg_00;
2724 union IO_APIC_reg_01 reg_01;
2725 union IO_APIC_reg_02 reg_02;
2727 reg_00.raw = io_apic_read(idx, 0);
2728 reg_01.raw = io_apic_read(idx, 1);
2729 reg_02.raw = io_apic_read(idx, 2);
2731 if (reg_00.raw == -1 && reg_01.raw == -1 && reg_02.raw == -1) {
2732 pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n",
2733 mpc_ioapic_addr(idx));
2740 static int find_free_ioapic_entry(void)
2744 for (idx = 0; idx < MAX_IO_APICS; idx++)
2745 if (ioapics[idx].nr_registers == 0)
2748 return MAX_IO_APICS;
2752 * mp_register_ioapic - Register an IOAPIC device
2753 * @id: hardware IOAPIC ID
2754 * @address: physical address of IOAPIC register area
2755 * @gsi_base: base of GSI associated with the IOAPIC
2756 * @cfg: configuration information for the IOAPIC
2758 int mp_register_ioapic(int id, u32 address, u32 gsi_base,
2759 struct ioapic_domain_cfg *cfg)
2761 bool hotplug = !!ioapic_initialized;
2762 struct mp_ioapic_gsi *gsi_cfg;
2763 int idx, ioapic, entries;
2767 pr_warn("Bogus (zero) I/O APIC address found, skipping!\n");
2770 for_each_ioapic(ioapic)
2771 if (ioapics[ioapic].mp_config.apicaddr == address) {
2772 pr_warn("address 0x%x conflicts with IOAPIC%d\n",
2777 idx = find_free_ioapic_entry();
2778 if (idx >= MAX_IO_APICS) {
2779 pr_warn("Max # of I/O APICs (%d) exceeded (found %d), skipping\n",
2784 ioapics[idx].mp_config.type = MP_IOAPIC;
2785 ioapics[idx].mp_config.flags = MPC_APIC_USABLE;
2786 ioapics[idx].mp_config.apicaddr = address;
2788 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
2789 if (bad_ioapic_register(idx)) {
2790 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2794 ioapics[idx].mp_config.apicid = io_apic_unique_id(idx, id);
2795 ioapics[idx].mp_config.apicver = io_apic_get_version(idx);
2798 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
2799 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
2801 entries = io_apic_get_redir_entries(idx);
2802 gsi_end = gsi_base + entries - 1;
2803 for_each_ioapic(ioapic) {
2804 gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2805 if ((gsi_base >= gsi_cfg->gsi_base &&
2806 gsi_base <= gsi_cfg->gsi_end) ||
2807 (gsi_end >= gsi_cfg->gsi_base &&
2808 gsi_end <= gsi_cfg->gsi_end)) {
2809 pr_warn("GSI range [%u-%u] for new IOAPIC conflicts with GSI[%u-%u]\n",
2811 gsi_cfg->gsi_base, gsi_cfg->gsi_end);
2812 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2816 gsi_cfg = mp_ioapic_gsi_routing(idx);
2817 gsi_cfg->gsi_base = gsi_base;
2818 gsi_cfg->gsi_end = gsi_end;
2820 ioapics[idx].irqdomain = NULL;
2821 ioapics[idx].irqdomain_cfg = *cfg;
2824 * If mp_register_ioapic() is called during early boot stage when
2825 * walking ACPI/SFI/DT tables, it's too early to create irqdomain,
2826 * we are still using bootmem allocator. So delay it to setup_IO_APIC().
2829 if (mp_irqdomain_create(idx)) {
2830 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2833 alloc_ioapic_saved_registers(idx);
2836 if (gsi_cfg->gsi_end >= gsi_top)
2837 gsi_top = gsi_cfg->gsi_end + 1;
2838 if (nr_ioapics <= idx)
2839 nr_ioapics = idx + 1;
2841 /* Set nr_registers to mark entry present */
2842 ioapics[idx].nr_registers = entries;
2844 pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n",
2845 idx, mpc_ioapic_id(idx),
2846 mpc_ioapic_ver(idx), mpc_ioapic_addr(idx),
2847 gsi_cfg->gsi_base, gsi_cfg->gsi_end);
2852 int mp_unregister_ioapic(u32 gsi_base)
2857 for_each_ioapic(ioapic)
2858 if (ioapics[ioapic].gsi_config.gsi_base == gsi_base) {
2863 pr_warn("can't find IOAPIC for GSI %d\n", gsi_base);
2867 for_each_pin(ioapic, pin) {
2868 u32 gsi = mp_pin_to_gsi(ioapic, pin);
2869 int irq = mp_map_gsi_to_irq(gsi, 0, NULL);
2870 struct mp_chip_data *data;
2873 data = irq_get_chip_data(irq);
2874 if (data && data->count) {
2875 pr_warn("pin%d on IOAPIC%d is still in use.\n",
2882 /* Mark entry not present */
2883 ioapics[ioapic].nr_registers = 0;
2884 ioapic_destroy_irqdomain(ioapic);
2885 free_ioapic_saved_registers(ioapic);
2886 if (ioapics[ioapic].iomem_res)
2887 release_resource(ioapics[ioapic].iomem_res);
2888 clear_fixmap(FIX_IO_APIC_BASE_0 + ioapic);
2889 memset(&ioapics[ioapic], 0, sizeof(ioapics[ioapic]));
2894 int mp_ioapic_registered(u32 gsi_base)
2898 for_each_ioapic(ioapic)
2899 if (ioapics[ioapic].gsi_config.gsi_base == gsi_base)
2905 static void mp_irqdomain_get_attr(u32 gsi, struct mp_chip_data *data,
2906 struct irq_alloc_info *info)
2908 if (info && info->ioapic_valid) {
2909 data->trigger = info->ioapic_trigger;
2910 data->polarity = info->ioapic_polarity;
2911 } else if (acpi_get_override_irq(gsi, &data->trigger,
2912 &data->polarity) < 0) {
2913 /* PCI interrupts are always active low level triggered. */
2914 data->trigger = IOAPIC_LEVEL;
2915 data->polarity = IOAPIC_POL_LOW;
2919 static void mp_setup_entry(struct irq_cfg *cfg, struct mp_chip_data *data,
2920 struct IO_APIC_route_entry *entry)
2922 memset(entry, 0, sizeof(*entry));
2923 entry->delivery_mode = apic->irq_delivery_mode;
2924 entry->dest_mode = apic->irq_dest_mode;
2925 entry->dest = cfg->dest_apicid;
2926 entry->vector = cfg->vector;
2927 entry->trigger = data->trigger;
2928 entry->polarity = data->polarity;
2930 * Mask level triggered irqs. Edge triggered irqs are masked
2931 * by the irq core code in case they fire.
2933 if (data->trigger == IOAPIC_LEVEL)
2934 entry->mask = IOAPIC_MASKED;
2936 entry->mask = IOAPIC_UNMASKED;
2939 int mp_irqdomain_alloc(struct irq_domain *domain, unsigned int virq,
2940 unsigned int nr_irqs, void *arg)
2942 int ret, ioapic, pin;
2943 struct irq_cfg *cfg;
2944 struct irq_data *irq_data;
2945 struct mp_chip_data *data;
2946 struct irq_alloc_info *info = arg;
2948 if (!info || nr_irqs > 1)
2950 irq_data = irq_domain_get_irq_data(domain, virq);
2954 ioapic = mp_irqdomain_ioapic_idx(domain);
2955 pin = info->ioapic_pin;
2956 if (irq_find_mapping(domain, (irq_hw_number_t)pin) > 0)
2959 data = kzalloc(sizeof(*data), GFP_KERNEL);
2963 info->ioapic_entry = &data->entry;
2964 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, info);
2970 INIT_LIST_HEAD(&data->irq_2_pin);
2971 irq_data->hwirq = info->ioapic_pin;
2972 irq_data->chip = (domain->parent == x86_vector_domain) ?
2973 &ioapic_chip : &ioapic_ir_chip;
2974 irq_data->chip_data = data;
2975 mp_irqdomain_get_attr(mp_pin_to_gsi(ioapic, pin), data, info);
2977 cfg = irqd_cfg(irq_data);
2978 add_pin_to_irq_node(data, ioapic_alloc_attr_node(info), ioapic, pin);
2979 if (info->ioapic_entry)
2980 mp_setup_entry(cfg, data, info->ioapic_entry);
2981 mp_register_handler(virq, data->trigger);
2982 if (virq < nr_legacy_irqs())
2983 legacy_pic->mask(virq);
2985 apic_printk(APIC_VERBOSE, KERN_DEBUG
2986 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i Dest:%d)\n",
2987 ioapic, mpc_ioapic_id(ioapic), pin, cfg->vector,
2988 virq, data->trigger, data->polarity, cfg->dest_apicid);
2993 void mp_irqdomain_free(struct irq_domain *domain, unsigned int virq,
2994 unsigned int nr_irqs)
2996 struct irq_data *irq_data;
2997 struct mp_chip_data *data;
2999 BUG_ON(nr_irqs != 1);
3000 irq_data = irq_domain_get_irq_data(domain, virq);
3001 if (irq_data && irq_data->chip_data) {
3002 data = irq_data->chip_data;
3003 __remove_pin_from_irq(data, mp_irqdomain_ioapic_idx(domain),
3004 (int)irq_data->hwirq);
3005 WARN_ON(!list_empty(&data->irq_2_pin));
3006 kfree(irq_data->chip_data);
3008 irq_domain_free_irqs_top(domain, virq, nr_irqs);
3011 void mp_irqdomain_activate(struct irq_domain *domain,
3012 struct irq_data *irq_data)
3014 unsigned long flags;
3015 struct irq_pin_list *entry;
3016 struct mp_chip_data *data = irq_data->chip_data;
3018 raw_spin_lock_irqsave(&ioapic_lock, flags);
3019 for_each_irq_pin(entry, data->irq_2_pin)
3020 __ioapic_write_entry(entry->apic, entry->pin, data->entry);
3021 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3024 void mp_irqdomain_deactivate(struct irq_domain *domain,
3025 struct irq_data *irq_data)
3027 /* It won't be called for IRQ with multiple IOAPIC pins associated */
3028 ioapic_mask_entry(mp_irqdomain_ioapic_idx(domain),
3029 (int)irq_data->hwirq);
3032 int mp_irqdomain_ioapic_idx(struct irq_domain *domain)
3034 return (int)(long)domain->host_data;