arch/mips/kvm/vz.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * KVM/MIPS: Support for hardware virtualization extensions
   7  *
   8  * Copyright (C) 2012  MIPS Technologies, Inc.  All rights reserved.
   9  * Authors: Yann Le Du <ledu@kymasys.com>
  10  */
  11
  12 #include <linux/errno.h>
  13 #include <linux/err.h>
  14 #include <linux/module.h>
  15 #include <linux/preempt.h>
  16 #include <linux/vmalloc.h>
  17 #include <asm/cacheflush.h>
  18 #include <asm/cacheops.h>
  19 #include <asm/cmpxchg.h>
  20 #include <asm/fpu.h>
  21 #include <asm/hazards.h>
  22 #include <asm/inst.h>
  23 #include <asm/mmu_context.h>
  24 #include <asm/r4kcache.h>
  25 #include <asm/time.h>
  26 #include <asm/tlb.h>
  27 #include <asm/tlbex.h>
  28
  29 #include <linux/kvm_host.h>
  30
  31 #include "interrupt.h"
  32
  33 #include "trace.h"
  34
  35 /* Pointers to last VCPU loaded on each physical CPU */
  36 static struct kvm_vcpu *last_vcpu[NR_CPUS];
  37 /* Pointers to last VCPU executed on each physical CPU */
  38 static struct kvm_vcpu *last_exec_vcpu[NR_CPUS];
  39
  40 /*
  41  * Number of guest VTLB entries to use, so we can catch inconsistency between
  42  * CPUs.
  43  */
  44 static unsigned int kvm_vz_guest_vtlb_size;
  45
  46 static inline long kvm_vz_read_gc0_ebase(void)
  47 {
  48         if (sizeof(long) == 8 && cpu_has_ebase_wg)
  49                 return read_gc0_ebase_64();
  50         else
  51                 return read_gc0_ebase();
  52 }
  53
  54 static inline void kvm_vz_write_gc0_ebase(long v)
  55 {
  56         /*
  57          * First write with WG=1 to write upper bits, then write again in case
  58          * WG should be left at 0.
  59          * write_gc0_ebase_64() is no longer UNDEFINED since R6.
  60          */
  61         if (sizeof(long) == 8 &&
  62             (cpu_has_mips64r6 || cpu_has_ebase_wg)) {
  63                 write_gc0_ebase_64(v | MIPS_EBASE_WG);
  64                 write_gc0_ebase_64(v);
  65         } else {
  66                 write_gc0_ebase(v | MIPS_EBASE_WG);
  67                 write_gc0_ebase(v);
  68         }
  69 }
  70
  71 /*
  72  * These Config bits may be writable by the guest:
  73  * Config:      [K23, KU] (!TLB), K0
  74  * Config1:     (none)
  75  * Config2:     [TU, SU] (impl)
  76  * Config3:     ISAOnExc
  77  * Config4:     FTLBPageSize
  78  * Config5:     K, CV, MSAEn, UFE, FRE, SBRI, UFR
  79  */
  80
  81 static inline unsigned int kvm_vz_config_guest_wrmask(struct kvm_vcpu *vcpu)
  82 {
  83         return CONF_CM_CMASK;
  84 }
  85
  86 static inline unsigned int kvm_vz_config1_guest_wrmask(struct kvm_vcpu *vcpu)
  87 {
  88         return 0;
  89 }
  90
  91 static inline unsigned int kvm_vz_config2_guest_wrmask(struct kvm_vcpu *vcpu)
  92 {
  93         return 0;
  94 }
  95
  96 static inline unsigned int kvm_vz_config3_guest_wrmask(struct kvm_vcpu *vcpu)
  97 {
  98         return MIPS_CONF3_ISA_OE;
  99 }
 100
 101 static inline unsigned int kvm_vz_config4_guest_wrmask(struct kvm_vcpu *vcpu)
 102 {
 103         /* no need to be exact */
 104         return MIPS_CONF4_VFTLBPAGESIZE;
 105 }
 106
 107 static inline unsigned int kvm_vz_config5_guest_wrmask(struct kvm_vcpu *vcpu)
 108 {
 109         unsigned int mask = MIPS_CONF5_K | MIPS_CONF5_CV | MIPS_CONF5_SBRI;
 110
 111         /* Permit MSAEn changes if MSA supported and enabled */
 112         if (kvm_mips_guest_has_msa(&vcpu->arch))
 113                 mask |= MIPS_CONF5_MSAEN;
 114
 115         /*
 116          * Permit guest FPU mode changes if FPU is enabled and the relevant
 117          * feature exists according to FIR register.
 118          */
 119         if (kvm_mips_guest_has_fpu(&vcpu->arch)) {
 120                 if (cpu_has_ufr)
 121                         mask |= MIPS_CONF5_UFR;
 122                 if (cpu_has_fre)
 123                         mask |= MIPS_CONF5_FRE | MIPS_CONF5_UFE;
 124         }
 125
 126         return mask;
 127 }
 128
 129 /*
 130  * VZ optionally allows these additional Config bits to be written by root:
 131  * Config:      M, [MT]
 132  * Config1:     M, [MMUSize-1, C2, MD, PC, WR, CA], FP
 133  * Config2:     M
 134  * Config3:     M, MSAP, [BPG], ULRI, [DSP2P, DSPP], CTXTC, [ITL, LPA, VEIC,
 135  *              VInt, SP, CDMM, MT, SM, TL]
 136  * Config4:     M, [VTLBSizeExt, MMUSizeExt]
 137  * Config5:     MRP
 138  */
 139
 140 static inline unsigned int kvm_vz_config_user_wrmask(struct kvm_vcpu *vcpu)
 141 {
 142         return kvm_vz_config_guest_wrmask(vcpu) | MIPS_CONF_M;
 143 }
 144
 145 static inline unsigned int kvm_vz_config1_user_wrmask(struct kvm_vcpu *vcpu)
 146 {
 147         unsigned int mask = kvm_vz_config1_guest_wrmask(vcpu) | MIPS_CONF_M;
 148
 149         /* Permit FPU to be present if FPU is supported */
 150         if (kvm_mips_guest_can_have_fpu(&vcpu->arch))
 151                 mask |= MIPS_CONF1_FP;
 152
 153         return mask;
 154 }
 155
 156 static inline unsigned int kvm_vz_config2_user_wrmask(struct kvm_vcpu *vcpu)
 157 {
 158         return kvm_vz_config2_guest_wrmask(vcpu) | MIPS_CONF_M;
 159 }
 160
 161 static inline unsigned int kvm_vz_config3_user_wrmask(struct kvm_vcpu *vcpu)
 162 {
 163         unsigned int mask = kvm_vz_config3_guest_wrmask(vcpu) | MIPS_CONF_M |
 164                 MIPS_CONF3_ULRI | MIPS_CONF3_CTXTC;
 165
 166         /* Permit MSA to be present if MSA is supported */
 167         if (kvm_mips_guest_can_have_msa(&vcpu->arch))
 168                 mask |= MIPS_CONF3_MSA;
 169
 170         return mask;
 171 }
 172
 173 static inline unsigned int kvm_vz_config4_user_wrmask(struct kvm_vcpu *vcpu)
 174 {
 175         return kvm_vz_config4_guest_wrmask(vcpu) | MIPS_CONF_M;
 176 }
 177
 178 static inline unsigned int kvm_vz_config5_user_wrmask(struct kvm_vcpu *vcpu)
 179 {
 180         return kvm_vz_config5_guest_wrmask(vcpu) | MIPS_CONF5_MRP;
 181 }
 182
 183 static gpa_t kvm_vz_gva_to_gpa_cb(gva_t gva)
 184 {
 185         /* VZ guest has already converted gva to gpa */
 186         return gva;
 187 }
 188
 189 static void kvm_vz_queue_irq(struct kvm_vcpu *vcpu, unsigned int priority)
 190 {
 191         set_bit(priority, &vcpu->arch.pending_exceptions);
 192         clear_bit(priority, &vcpu->arch.pending_exceptions_clr);
 193 }
 194
 195 static void kvm_vz_dequeue_irq(struct kvm_vcpu *vcpu, unsigned int priority)
 196 {
 197         clear_bit(priority, &vcpu->arch.pending_exceptions);
 198         set_bit(priority, &vcpu->arch.pending_exceptions_clr);
 199 }
 200
 201 static void kvm_vz_queue_timer_int_cb(struct kvm_vcpu *vcpu)
 202 {
 203         /*
 204          * timer expiry is asynchronous to vcpu execution therefore defer guest
 205          * cp0 accesses
 206          */
 207         kvm_vz_queue_irq(vcpu, MIPS_EXC_INT_TIMER);
 208 }
 209
 210 static void kvm_vz_dequeue_timer_int_cb(struct kvm_vcpu *vcpu)
 211 {
 212         /*
 213          * timer expiry is asynchronous to vcpu execution therefore defer guest
 214          * cp0 accesses
 215          */
 216         kvm_vz_dequeue_irq(vcpu, MIPS_EXC_INT_TIMER);
 217 }
 218
 219 static void kvm_vz_queue_io_int_cb(struct kvm_vcpu *vcpu,
 220                                    struct kvm_mips_interrupt *irq)
 221 {
 222         int intr = (int)irq->irq;
 223
 224         /*
 225          * interrupts are asynchronous to vcpu execution therefore defer guest
 226          * cp0 accesses
 227          */
 228         switch (intr) {
 229         case 2:
 230                 kvm_vz_queue_irq(vcpu, MIPS_EXC_INT_IO);
 231                 break;
 232
 233         case 3:
 234                 kvm_vz_queue_irq(vcpu, MIPS_EXC_INT_IPI_1);
 235                 break;
 236
 237         case 4:
 238                 kvm_vz_queue_irq(vcpu, MIPS_EXC_INT_IPI_2);
 239                 break;
 240
 241         default:
 242                 break;
 243         }
 244
 245 }
 246
 247 static void kvm_vz_dequeue_io_int_cb(struct kvm_vcpu *vcpu,
 248                                      struct kvm_mips_interrupt *irq)
 249 {
 250         int intr = (int)irq->irq;
 251
 252         /*
 253          * interrupts are asynchronous to vcpu execution therefore defer guest
 254          * cp0 accesses
 255          */
 256         switch (intr) {
 257         case -2:
 258                 kvm_vz_dequeue_irq(vcpu, MIPS_EXC_INT_IO);
 259                 break;
 260
 261         case -3:
 262                 kvm_vz_dequeue_irq(vcpu, MIPS_EXC_INT_IPI_1);
 263                 break;
 264
 265         case -4:
 266                 kvm_vz_dequeue_irq(vcpu, MIPS_EXC_INT_IPI_2);
 267                 break;
 268
 269         default:
 270                 break;
 271         }
 272
 273 }
 274
 275 static u32 kvm_vz_priority_to_irq[MIPS_EXC_MAX] = {
 276         [MIPS_EXC_INT_TIMER] = C_IRQ5,
 277         [MIPS_EXC_INT_IO]    = C_IRQ0,
 278         [MIPS_EXC_INT_IPI_1] = C_IRQ1,
 279         [MIPS_EXC_INT_IPI_2] = C_IRQ2,
 280 };
 281
 282 static int kvm_vz_irq_deliver_cb(struct kvm_vcpu *vcpu, unsigned int priority,
 283                                  u32 cause)
 284 {
 285         u32 irq = (priority < MIPS_EXC_MAX) ?
 286                 kvm_vz_priority_to_irq[priority] : 0;
 287
 288         switch (priority) {
 289         case MIPS_EXC_INT_TIMER:
 290                 set_gc0_cause(C_TI);
 291                 break;
 292
 293         case MIPS_EXC_INT_IO:
 294         case MIPS_EXC_INT_IPI_1:
 295         case MIPS_EXC_INT_IPI_2:
 296                 if (cpu_has_guestctl2)
 297                         set_c0_guestctl2(irq);
 298                 else
 299                         set_gc0_cause(irq);
 300                 break;
 301
 302         default:
 303                 break;
 304         }
 305
 306         clear_bit(priority, &vcpu->arch.pending_exceptions);
 307         return 1;
 308 }
 309
 310 static int kvm_vz_irq_clear_cb(struct kvm_vcpu *vcpu, unsigned int priority,
 311                                u32 cause)
 312 {
 313         u32 irq = (priority < MIPS_EXC_MAX) ?
 314                 kvm_vz_priority_to_irq[priority] : 0;
 315
 316         switch (priority) {
 317         case MIPS_EXC_INT_TIMER:
 318                 /*
 319                  * Call to kvm_write_c0_guest_compare() clears Cause.TI in
 320                  * kvm_mips_emulate_CP0(). Explicitly clear irq associated with
 321                  * Cause.IP[IPTI] if GuestCtl2 virtual interrupt register not
 322                  * supported or if not using GuestCtl2 Hardware Clear.
 323                  */
 324                 if (cpu_has_guestctl2) {
 325                         if (!(read_c0_guestctl2() & (irq << 14)))
 326                                 clear_c0_guestctl2(irq);
 327                 } else {
 328                         clear_gc0_cause(irq);
 329                 }
 330                 break;
 331
 332         case MIPS_EXC_INT_IO:
 333         case MIPS_EXC_INT_IPI_1:
 334         case MIPS_EXC_INT_IPI_2:
 335                 /* Clear GuestCtl2.VIP irq if not using Hardware Clear */
 336                 if (cpu_has_guestctl2) {
 337                         if (!(read_c0_guestctl2() & (irq << 14)))
 338                                 clear_c0_guestctl2(irq);
 339                 } else {
 340                         clear_gc0_cause(irq);
 341                 }
 342                 break;
 343
 344         default:
 345                 break;
 346         }
 347
 348         clear_bit(priority, &vcpu->arch.pending_exceptions_clr);
 349         return 1;
 350 }
 351
 352 /*
 353  * VZ guest timer handling.
 354  */
 355
 356 /**
 357  * kvm_vz_should_use_htimer() - Find whether to use the VZ hard guest timer.
 358  * @vcpu:       Virtual CPU.
 359  *
 360  * Returns:     true if the VZ GTOffset & real guest CP0_Count should be used
 361  *              instead of software emulation of guest timer.
 362  *              false otherwise.
 363  */
 364 static bool kvm_vz_should_use_htimer(struct kvm_vcpu *vcpu)
 365 {
 366         if (kvm_mips_count_disabled(vcpu))
 367                 return false;
 368
 369         /* Chosen frequency must match real frequency */
 370         if (mips_hpt_frequency != vcpu->arch.count_hz)
 371                 return false;
 372
 373         /* We don't support a CP0_GTOffset with fewer bits than CP0_Count */
 374         if (current_cpu_data.gtoffset_mask != 0xffffffff)
 375                 return false;
 376
 377         return true;
 378 }
 379
 380 /**
 381  * _kvm_vz_restore_stimer() - Restore soft timer state.
 382  * @vcpu:       Virtual CPU.
 383  * @compare:    CP0_Compare register value, restored by caller.
 384  * @cause:      CP0_Cause register to restore.
 385  *
 386  * Restore VZ state relating to the soft timer. The hard timer can be enabled
 387  * later.
 388  */
 389 static void _kvm_vz_restore_stimer(struct kvm_vcpu *vcpu, u32 compare,
 390                                    u32 cause)
 391 {
 392         /*
 393          * Avoid spurious counter interrupts by setting Guest CP0_Count to just
 394          * after Guest CP0_Compare.
 395          */
 396         write_c0_gtoffset(compare - read_c0_count());
 397
 398         back_to_back_c0_hazard();
 399         write_gc0_cause(cause);
 400 }
 401
 402 /**
 403  * _kvm_vz_restore_htimer() - Restore hard timer state.
 404  * @vcpu:       Virtual CPU.
 405  * @compare:    CP0_Compare register value, restored by caller.
 406  * @cause:      CP0_Cause register to restore.
 407  *
 408  * Restore hard timer Guest.Count & Guest.Cause taking care to preserve the
 409  * value of Guest.CP0_Cause.TI while restoring Guest.CP0_Cause.
 410  */
 411 static void _kvm_vz_restore_htimer(struct kvm_vcpu *vcpu,
 412                                    u32 compare, u32 cause)
 413 {
 414         u32 start_count, after_count;
 415         ktime_t freeze_time;
 416         unsigned long flags;
 417
 418         /*
 419          * Freeze the soft-timer and sync the guest CP0_Count with it. We do
 420          * this with interrupts disabled to avoid latency.
 421          */
 422         local_irq_save(flags);
 423         freeze_time = kvm_mips_freeze_hrtimer(vcpu, &start_count);
 424         write_c0_gtoffset(start_count - read_c0_count());
 425         local_irq_restore(flags);
 426
 427         /* restore guest CP0_Cause, as TI may already be set */
 428         back_to_back_c0_hazard();
 429         write_gc0_cause(cause);
 430
 431         /*
 432          * The above sequence isn't atomic and would result in lost timer
 433          * interrupts if we're not careful. Detect if a timer interrupt is due
 434          * and assert it.
 435          */
 436         back_to_back_c0_hazard();
 437         after_count = read_gc0_count();
 438         if (after_count - start_count > compare - start_count - 1)
 439                 kvm_vz_queue_irq(vcpu, MIPS_EXC_INT_TIMER);
 440 }
 441
 442 /**
 443  * kvm_vz_restore_timer() - Restore timer state.
 444  * @vcpu:       Virtual CPU.
 445  *
 446  * Restore soft timer state from saved context.
 447  */
 448 static void kvm_vz_restore_timer(struct kvm_vcpu *vcpu)
 449 {
 450         struct mips_coproc *cop0 = vcpu->arch.cop0;
 451         u32 cause, compare;
 452
 453         compare = kvm_read_sw_gc0_compare(cop0);
 454         cause = kvm_read_sw_gc0_cause(cop0);
 455
 456         write_gc0_compare(compare);
 457         _kvm_vz_restore_stimer(vcpu, compare, cause);
 458 }
 459
 460 /**
 461  * kvm_vz_acquire_htimer() - Switch to hard timer state.
 462  * @vcpu:       Virtual CPU.
 463  *
 464  * Restore hard timer state on top of existing soft timer state if possible.
 465  *
 466  * Since hard timer won't remain active over preemption, preemption should be
 467  * disabled by the caller.
 468  */
 469 void kvm_vz_acquire_htimer(struct kvm_vcpu *vcpu)
 470 {
 471         u32 gctl0;
 472
 473         gctl0 = read_c0_guestctl0();
 474         if (!(gctl0 & MIPS_GCTL0_GT) && kvm_vz_should_use_htimer(vcpu)) {
 475                 /* enable guest access to hard timer */
 476                 write_c0_guestctl0(gctl0 | MIPS_GCTL0_GT);
 477
 478                 _kvm_vz_restore_htimer(vcpu, read_gc0_compare(),
 479                                        read_gc0_cause());
 480         }
 481 }
 482
 483 /**
 484  * _kvm_vz_save_htimer() - Switch to software emulation of guest timer.
 485  * @vcpu:       Virtual CPU.
 486  * @compare:    Pointer to write compare value to.
 487  * @cause:      Pointer to write cause value to.
 488  *
 489  * Save VZ guest timer state and switch to software emulation of guest CP0
 490  * timer. The hard timer must already be in use, so preemption should be
 491  * disabled.
 492  */
 493 static void _kvm_vz_save_htimer(struct kvm_vcpu *vcpu,
 494                                 u32 *out_compare, u32 *out_cause)
 495 {
 496         u32 cause, compare, before_count, end_count;
 497         ktime_t before_time;
 498
 499         compare = read_gc0_compare();
 500         *out_compare = compare;
 501
 502         before_time = ktime_get();
 503
 504         /*
 505          * Record the CP0_Count *prior* to saving CP0_Cause, so we have a time
 506          * at which no pending timer interrupt is missing.
 507          */
 508         before_count = read_gc0_count();
 509         back_to_back_c0_hazard();
 510         cause = read_gc0_cause();
 511         *out_cause = cause;
 512
 513         /*
 514          * Record a final CP0_Count which we will transfer to the soft-timer.
 515          * This is recorded *after* saving CP0_Cause, so we don't get any timer
 516          * interrupts from just after the final CP0_Count point.
 517          */
 518         back_to_back_c0_hazard();
 519         end_count = read_gc0_count();
 520
 521         /*
 522          * The above sequence isn't atomic, so we could miss a timer interrupt
 523          * between reading CP0_Cause and end_count. Detect and record any timer
 524          * interrupt due between before_count and end_count.
 525          */
 526         if (end_count - before_count > compare - before_count - 1)
 527                 kvm_vz_queue_irq(vcpu, MIPS_EXC_INT_TIMER);
 528
 529         /*
 530          * Restore soft-timer, ignoring a small amount of negative drift due to
 531          * delay between freeze_hrtimer and setting CP0_GTOffset.
 532          */
 533         kvm_mips_restore_hrtimer(vcpu, before_time, end_count, -0x10000);
 534 }
 535
 536 /**
 537  * kvm_vz_save_timer() - Save guest timer state.
 538  * @vcpu:       Virtual CPU.
 539  *
 540  * Save VZ guest timer state and switch to soft guest timer if hard timer was in
 541  * use.
 542  */
 543 static void kvm_vz_save_timer(struct kvm_vcpu *vcpu)
 544 {
 545         struct mips_coproc *cop0 = vcpu->arch.cop0;
 546         u32 gctl0, compare, cause;
 547
 548         gctl0 = read_c0_guestctl0();
 549         if (gctl0 & MIPS_GCTL0_GT) {
 550                 /* disable guest use of hard timer */
 551                 write_c0_guestctl0(gctl0 & ~MIPS_GCTL0_GT);
 552
 553                 /* save hard timer state */
 554                 _kvm_vz_save_htimer(vcpu, &compare, &cause);
 555         } else {
 556                 compare = read_gc0_compare();
 557                 cause = read_gc0_cause();
 558         }
 559
 560         /* save timer-related state to VCPU context */
 561         kvm_write_sw_gc0_cause(cop0, cause);
 562         kvm_write_sw_gc0_compare(cop0, compare);
 563 }
 564
 565 /**
 566  * kvm_vz_lose_htimer() - Ensure hard guest timer is not in use.
 567  * @vcpu:       Virtual CPU.
 568  *
 569  * Transfers the state of the hard guest timer to the soft guest timer, leaving
 570  * guest state intact so it can continue to be used with the soft timer.
 571  */
 572 void kvm_vz_lose_htimer(struct kvm_vcpu *vcpu)
 573 {
 574         u32 gctl0, compare, cause;
 575
 576         preempt_disable();
 577         gctl0 = read_c0_guestctl0();
 578         if (gctl0 & MIPS_GCTL0_GT) {
 579                 /* disable guest use of timer */
 580                 write_c0_guestctl0(gctl0 & ~MIPS_GCTL0_GT);
 581
 582                 /* switch to soft timer */
 583                 _kvm_vz_save_htimer(vcpu, &compare, &cause);
 584
 585                 /* leave soft timer in usable state */
 586                 _kvm_vz_restore_stimer(vcpu, compare, cause);
 587         }
 588         preempt_enable();
 589 }
 590
 591 /**
 592  * is_eva_access() - Find whether an instruction is an EVA memory accessor.
 593  * @inst:       32-bit instruction encoding.
 594  *
 595  * Finds whether @inst encodes an EVA memory access instruction, which would
 596  * indicate that emulation of it should access the user mode address space
 597  * instead of the kernel mode address space. This matters for MUSUK segments
 598  * which are TLB mapped for user mode but unmapped for kernel mode.
 599  *
 600  * Returns:     Whether @inst encodes an EVA accessor instruction.
 601  */
 602 static bool is_eva_access(union mips_instruction inst)
 603 {
 604         if (inst.spec3_format.opcode != spec3_op)
 605                 return false;
 606
 607         switch (inst.spec3_format.func) {
 608         case lwle_op:
 609         case lwre_op:
 610         case cachee_op:
 611         case sbe_op:
 612         case she_op:
 613         case sce_op:
 614         case swe_op:
 615         case swle_op:
 616         case swre_op:
 617         case prefe_op:
 618         case lbue_op:
 619         case lhue_op:
 620         case lbe_op:
 621         case lhe_op:
 622         case lle_op:
 623         case lwe_op:
 624                 return true;
 625         default:
 626                 return false;
 627         }
 628 }
 629
 630 /**
 631  * is_eva_am_mapped() - Find whether an access mode is mapped.
 632  * @vcpu:       KVM VCPU state.
 633  * @am:         3-bit encoded access mode.
 634  * @eu:         Segment becomes unmapped and uncached when Status.ERL=1.
 635  *
 636  * Decode @am to find whether it encodes a mapped segment for the current VCPU
 637  * state. Where necessary @eu and the actual instruction causing the fault are
 638  * taken into account to make the decision.
 639  *
 640  * Returns:     Whether the VCPU faulted on a TLB mapped address.
 641  */
 642 static bool is_eva_am_mapped(struct kvm_vcpu *vcpu, unsigned int am, bool eu)
 643 {
 644         u32 am_lookup;
 645         int err;
 646
 647         /*
 648          * Interpret access control mode. We assume address errors will already
 649          * have been caught by the guest, leaving us with:
 650          *      AM      UM  SM  KM  31..24 23..16
 651          * UK    0 000          Unm   0      0
 652          * MK    1 001          TLB   1
 653          * MSK   2 010      TLB TLB   1
 654          * MUSK  3 011  TLB TLB TLB   1
 655          * MUSUK 4 100  TLB TLB Unm   0      1
 656          * USK   5 101      Unm Unm   0      0
 657          * -     6 110                0      0
 658          * UUSK  7 111  Unm Unm Unm   0      0
 659          *
 660          * We shift a magic value by AM across the sign bit to find if always
 661          * TLB mapped, and if not shift by 8 again to find if it depends on KM.
 662          */
 663         am_lookup = 0x70080000 << am;
 664         if ((s32)am_lookup < 0) {
 665                 /*
 666                  * MK, MSK, MUSK
 667                  * Always TLB mapped, unless SegCtl.EU && ERL
 668                  */
 669                 if (!eu || !(read_gc0_status() & ST0_ERL))
 670                         return true;
 671         } else {
 672                 am_lookup <<= 8;
 673                 if ((s32)am_lookup < 0) {
 674                         union mips_instruction inst;
 675                         unsigned int status;
 676                         u32 *opc;
 677
 678                         /*
 679                          * MUSUK
 680                          * TLB mapped if not in kernel mode
 681                          */
 682                         status = read_gc0_status();
 683                         if (!(status & (ST0_EXL | ST0_ERL)) &&
 684                             (status & ST0_KSU))
 685                                 return true;
 686                         /*
 687                          * EVA access instructions in kernel
 688                          * mode access user address space.
 689                          */
 690                         opc = (u32 *)vcpu->arch.pc;
 691                         if (vcpu->arch.host_cp0_cause & CAUSEF_BD)
 692                                 opc += 1;
 693                         err = kvm_get_badinstr(opc, vcpu, &inst.word);
 694                         if (!err && is_eva_access(inst))
 695                                 return true;
 696                 }
 697         }
 698
 699         return false;
 700 }
 701
 702 /**
 703  * kvm_vz_gva_to_gpa() - Convert valid GVA to GPA.
 704  * @vcpu:       KVM VCPU state.
 705  * @gva:        Guest virtual address to convert.
 706  * @gpa:        Output guest physical address.
 707  *
 708  * Convert a guest virtual address (GVA) which is valid according to the guest
 709  * context, to a guest physical address (GPA).
 710  *
 711  * Returns:     0 on success.
 712  *              -errno on failure.
 713  */
 714 static int kvm_vz_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
 715                              unsigned long *gpa)
 716 {
 717         u32 gva32 = gva;
 718         unsigned long segctl;
 719
 720         if ((long)gva == (s32)gva32) {
 721                 /* Handle canonical 32-bit virtual address */
 722                 if (cpu_guest_has_segments) {
 723                         unsigned long mask, pa;
 724
 725                         switch (gva32 >> 29) {
 726                         case 0:
 727                         case 1: /* CFG5 (1GB) */
 728                                 segctl = read_gc0_segctl2() >> 16;
 729                                 mask = (unsigned long)0xfc0000000ull;
 730                                 break;
 731                         case 2:
 732                         case 3: /* CFG4 (1GB) */
 733                                 segctl = read_gc0_segctl2();
 734                                 mask = (unsigned long)0xfc0000000ull;
 735                                 break;
 736                         case 4: /* CFG3 (512MB) */
 737                                 segctl = read_gc0_segctl1() >> 16;
 738                                 mask = (unsigned long)0xfe0000000ull;
 739                                 break;
 740                         case 5: /* CFG2 (512MB) */
 741                                 segctl = read_gc0_segctl1();
 742                                 mask = (unsigned long)0xfe0000000ull;
 743                                 break;
 744                         case 6: /* CFG1 (512MB) */
 745                                 segctl = read_gc0_segctl0() >> 16;
 746                                 mask = (unsigned long)0xfe0000000ull;
 747                                 break;
 748                         case 7: /* CFG0 (512MB) */
 749                                 segctl = read_gc0_segctl0();
 750                                 mask = (unsigned long)0xfe0000000ull;
 751                                 break;
 752                         default:
 753                                 /*
 754                                  * GCC 4.9 isn't smart enough to figure out that
 755                                  * segctl and mask are always initialised.
 756                                  */
 757                                 unreachable();
 758                         }
 759
 760                         if (is_eva_am_mapped(vcpu, (segctl >> 4) & 0x7,
 761                                              segctl & 0x0008))
 762                                 goto tlb_mapped;
 763
 764                         /* Unmapped, find guest physical address */
 765                         pa = (segctl << 20) & mask;
 766                         pa |= gva32 & ~mask;
 767                         *gpa = pa;
 768                         return 0;
 769                 } else if ((s32)gva32 < (s32)0xc0000000) {
 770                         /* legacy unmapped KSeg0 or KSeg1 */
 771                         *gpa = gva32 & 0x1fffffff;
 772                         return 0;
 773                 }
 774 #ifdef CONFIG_64BIT
 775         } else if ((gva & 0xc000000000000000) == 0x8000000000000000) {
 776                 /* XKPHYS */
 777                 if (cpu_guest_has_segments) {
 778                         /*
 779                          * Each of the 8 regions can be overridden by SegCtl2.XR
 780                          * to use SegCtl1.XAM.
 781                          */
 782                         segctl = read_gc0_segctl2();
 783                         if (segctl & (1ull << (56 + ((gva >> 59) & 0x7)))) {
 784                                 segctl = read_gc0_segctl1();
 785                                 if (is_eva_am_mapped(vcpu, (segctl >> 59) & 0x7,
 786                                                      0))
 787                                         goto tlb_mapped;
 788                         }
 789
 790                 }
 791                 /*
 792                  * Traditionally fully unmapped.
 793                  * Bits 61:59 specify the CCA, which we can just mask off here.
 794                  * Bits 58:PABITS should be zero, but we shouldn't have got here
 795                  * if it wasn't.
 796                  */
 797                 *gpa = gva & 0x07ffffffffffffff;
 798                 return 0;
 799 #endif
 800         }
 801
 802 tlb_mapped:
 803         return kvm_vz_guest_tlb_lookup(vcpu, gva, gpa);
 804 }
 805
 806 /**
 807  * kvm_vz_badvaddr_to_gpa() - Convert GVA BadVAddr from root exception to GPA.
 808  * @vcpu:       KVM VCPU state.
 809  * @badvaddr:   Root BadVAddr.
 810  * @gpa:        Output guest physical address.
 811  *
 812  * VZ implementations are permitted to report guest virtual addresses (GVA) in
 813  * BadVAddr on a root exception during guest execution, instead of the more
 814  * convenient guest physical addresses (GPA). When we get a GVA, this function
 815  * converts it to a GPA, taking into account guest segmentation and guest TLB
 816  * state.
 817  *
 818  * Returns:     0 on success.
 819  *              -errno on failure.
 820  */
 821 static int kvm_vz_badvaddr_to_gpa(struct kvm_vcpu *vcpu, unsigned long badvaddr,
 822                                   unsigned long *gpa)
 823 {
 824         unsigned int gexccode = (vcpu->arch.host_cp0_guestctl0 &
 825                                  MIPS_GCTL0_GEXC) >> MIPS_GCTL0_GEXC_SHIFT;
 826
 827         /* If BadVAddr is GPA, then all is well in the world */
 828         if (likely(gexccode == MIPS_GCTL0_GEXC_GPA)) {
 829                 *gpa = badvaddr;
 830                 return 0;
 831         }
 832
 833         /* Otherwise we'd expect it to be GVA ... */
 834         if (WARN(gexccode != MIPS_GCTL0_GEXC_GVA,
 835                  "Unexpected gexccode %#x\n", gexccode))
 836                 return -EINVAL;
 837
 838         /* ... and we need to perform the GVA->GPA translation in software */
 839         return kvm_vz_gva_to_gpa(vcpu, badvaddr, gpa);
 840 }
 841
 842 static int kvm_trap_vz_no_handler(struct kvm_vcpu *vcpu)
 843 {
 844         u32 *opc = (u32 *) vcpu->arch.pc;
 845         u32 cause = vcpu->arch.host_cp0_cause;
 846         u32 exccode = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
 847         unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;
 848         u32 inst = 0;
 849
 850         /*
 851          *  Fetch the instruction.
 852          */
 853         if (cause & CAUSEF_BD)
 854                 opc += 1;
 855         kvm_get_badinstr(opc, vcpu, &inst);
 856
 857         kvm_err("Exception Code: %d not handled @ PC: %p, inst: 0x%08x BadVaddr: %#lx Status: %#x\n",
 858                 exccode, opc, inst, badvaddr,
 859                 read_gc0_status());
 860         kvm_arch_vcpu_dump_regs(vcpu);
 861         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
 862         return RESUME_HOST;
 863 }
 864
 865 static unsigned long mips_process_maar(unsigned int op, unsigned long val)
 866 {
 867         /* Mask off unused bits */
 868         unsigned long mask = 0xfffff000 | MIPS_MAAR_S | MIPS_MAAR_VL;
 869
 870         if (read_gc0_pagegrain() & PG_ELPA)
 871                 mask |= 0x00ffffff00000000ull;
 872         if (cpu_guest_has_mvh)
 873                 mask |= MIPS_MAAR_VH;
 874
 875         /* Set or clear VH */
 876         if (op == mtc_op) {
 877                 /* clear VH */
 878                 val &= ~MIPS_MAAR_VH;
 879         } else if (op == dmtc_op) {
 880                 /* set VH to match VL */
 881                 val &= ~MIPS_MAAR_VH;
 882                 if (val & MIPS_MAAR_VL)
 883                         val |= MIPS_MAAR_VH;
 884         }
 885
 886         return val & mask;
 887 }
 888
 889 static void kvm_write_maari(struct kvm_vcpu *vcpu, unsigned long val)
 890 {
 891         struct mips_coproc *cop0 = vcpu->arch.cop0;
 892
 893         val &= MIPS_MAARI_INDEX;
 894         if (val == MIPS_MAARI_INDEX)
 895                 kvm_write_sw_gc0_maari(cop0, ARRAY_SIZE(vcpu->arch.maar) - 1);
 896         else if (val < ARRAY_SIZE(vcpu->arch.maar))
 897                 kvm_write_sw_gc0_maari(cop0, val);
 898 }
 899
 900 static enum emulation_result kvm_vz_gpsi_cop0(union mips_instruction inst,
 901                                               u32 *opc, u32 cause,
 902                                               struct kvm_run *run,
 903                                               struct kvm_vcpu *vcpu)
 904 {
 905         struct mips_coproc *cop0 = vcpu->arch.cop0;
 906         enum emulation_result er = EMULATE_DONE;
 907         u32 rt, rd, sel;
 908         unsigned long curr_pc;
 909         unsigned long val;
 910
 911         /*
 912          * Update PC and hold onto current PC in case there is
 913          * an error and we want to rollback the PC
 914          */
 915         curr_pc = vcpu->arch.pc;
 916         er = update_pc(vcpu, cause);
 917         if (er == EMULATE_FAIL)
 918                 return er;
 919
 920         if (inst.co_format.co) {
 921                 switch (inst.co_format.func) {
 922                 case wait_op:
 923                         er = kvm_mips_emul_wait(vcpu);
 924                         break;
 925                 default:
 926                         er = EMULATE_FAIL;
 927                 }
 928         } else {
 929                 rt = inst.c0r_format.rt;
 930                 rd = inst.c0r_format.rd;
 931                 sel = inst.c0r_format.sel;
 932
 933                 switch (inst.c0r_format.rs) {
 934                 case dmfc_op:
 935                 case mfc_op:
 936 #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
 937                         cop0->stat[rd][sel]++;
 938 #endif
 939                         if (rd == MIPS_CP0_COUNT &&
 940                             sel == 0) {                 /* Count */
 941                                 val = kvm_mips_read_count(vcpu);
 942                         } else if (rd == MIPS_CP0_COMPARE &&
 943                                    sel == 0) {          /* Compare */
 944                                 val = read_gc0_compare();
 945                         } else if (rd == MIPS_CP0_LLADDR &&
 946                                    sel == 0) {          /* LLAddr */
 947                                 if (cpu_guest_has_rw_llb)
 948                                         val = read_gc0_lladdr() &
 949                                                 MIPS_LLADDR_LLB;
 950                                 else
 951                                         val = 0;
 952                         } else if (rd == MIPS_CP0_LLADDR &&
 953                                    sel == 1 &&          /* MAAR */
 954                                    cpu_guest_has_maar &&
 955                                    !cpu_guest_has_dyn_maar) {
 956                                 /* MAARI must be in range */
 957                                 BUG_ON(kvm_read_sw_gc0_maari(cop0) >=
 958                                                 ARRAY_SIZE(vcpu->arch.maar));
 959                                 val = vcpu->arch.maar[
 960                                         kvm_read_sw_gc0_maari(cop0)];
 961                         } else if ((rd == MIPS_CP0_PRID &&
 962                                     (sel == 0 ||        /* PRid */
 963                                      sel == 2 ||        /* CDMMBase */
 964                                      sel == 3)) ||      /* CMGCRBase */
 965                                    (rd == MIPS_CP0_STATUS &&
 966                                     (sel == 2 ||        /* SRSCtl */
 967                                      sel == 3)) ||      /* SRSMap */
 968                                    (rd == MIPS_CP0_CONFIG &&
 969                                     (sel == 7)) ||      /* Config7 */
 970                                    (rd == MIPS_CP0_LLADDR &&
 971                                     (sel == 2) &&       /* MAARI */
 972                                     cpu_guest_has_maar &&
 973                                     !cpu_guest_has_dyn_maar) ||
 974                                    (rd == MIPS_CP0_ERRCTL &&
 975                                     (sel == 0))) {      /* ErrCtl */
 976                                 val = cop0->reg[rd][sel];
 977                         } else {
 978                                 val = 0;
 979                                 er = EMULATE_FAIL;
 980                         }
 981
 982                         if (er != EMULATE_FAIL) {
 983                                 /* Sign extend */
 984                                 if (inst.c0r_format.rs == mfc_op)
 985                                         val = (int)val;
 986                                 vcpu->arch.gprs[rt] = val;
 987                         }
 988
 989                         trace_kvm_hwr(vcpu, (inst.c0r_format.rs == mfc_op) ?
 990                                         KVM_TRACE_MFC0 : KVM_TRACE_DMFC0,
 991                                       KVM_TRACE_COP0(rd, sel), val);
 992                         break;
 993
 994                 case dmtc_op:
 995                 case mtc_op:
 996 #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
 997                         cop0->stat[rd][sel]++;
 998 #endif
 999                         val = vcpu->arch.gprs[rt];
1000                         trace_kvm_hwr(vcpu, (inst.c0r_format.rs == mtc_op) ?
1001                                         KVM_TRACE_MTC0 : KVM_TRACE_DMTC0,
1002                                       KVM_TRACE_COP0(rd, sel), val);
1003
1004                         if (rd == MIPS_CP0_COUNT &&
1005                             sel == 0) {                 /* Count */
1006                                 kvm_vz_lose_htimer(vcpu);
1007                                 kvm_mips_write_count(vcpu, vcpu->arch.gprs[rt]);
1008                         } else if (rd == MIPS_CP0_COMPARE &&
1009                                    sel == 0) {          /* Compare */
1010                                 kvm_mips_write_compare(vcpu,
1011                                                        vcpu->arch.gprs[rt],
1012                                                        true);
1013                         } else if (rd == MIPS_CP0_LLADDR &&
1014                                    sel == 0) {          /* LLAddr */
1015                                 /*
1016                                  * P5600 generates GPSI on guest MTC0 LLAddr.
1017                                  * Only allow the guest to clear LLB.
1018                                  */
1019                                 if (cpu_guest_has_rw_llb &&
1020                                     !(val & MIPS_LLADDR_LLB))
1021                                         write_gc0_lladdr(0);
1022                         } else if (rd == MIPS_CP0_LLADDR &&
1023                                    sel == 1 &&          /* MAAR */
1024                                    cpu_guest_has_maar &&
1025                                    !cpu_guest_has_dyn_maar) {
1026                                 val = mips_process_maar(inst.c0r_format.rs,
1027                                                         val);
1028
1029                                 /* MAARI must be in range */
1030                                 BUG_ON(kvm_read_sw_gc0_maari(cop0) >=
1031                                                 ARRAY_SIZE(vcpu->arch.maar));
1032                                 vcpu->arch.maar[kvm_read_sw_gc0_maari(cop0)] =
1033                                                                         val;
1034                         } else if (rd == MIPS_CP0_LLADDR &&
1035                                    (sel == 2) &&        /* MAARI */
1036                                    cpu_guest_has_maar &&
1037                                    !cpu_guest_has_dyn_maar) {
1038                                 kvm_write_maari(vcpu, val);
1039                         } else if (rd == MIPS_CP0_ERRCTL &&
1040                                    (sel == 0)) {        /* ErrCtl */
1041                                 /* ignore the written value */
1042                         } else {
1043                                 er = EMULATE_FAIL;
1044                         }
1045                         break;
1046
1047                 default:
1048                         er = EMULATE_FAIL;
1049                         break;
1050                 }
1051         }
1052         /* Rollback PC only if emulation was unsuccessful */
1053         if (er == EMULATE_FAIL) {
1054                 kvm_err("[%#lx]%s: unsupported cop0 instruction 0x%08x\n",
1055                         curr_pc, __func__, inst.word);
1056
1057                 vcpu->arch.pc = curr_pc;
1058         }
1059
1060         return er;
1061 }
1062
1063 static enum emulation_result kvm_vz_gpsi_cache(union mips_instruction inst,
1064                                                u32 *opc, u32 cause,
1065                                                struct kvm_run *run,
1066                                                struct kvm_vcpu *vcpu)
1067 {
1068         enum emulation_result er = EMULATE_DONE;
1069         u32 cache, op_inst, op, base;
1070         s16 offset;
1071         struct kvm_vcpu_arch *arch = &vcpu->arch;
1072         unsigned long va, curr_pc;
1073
1074         /*
1075          * Update PC and hold onto current PC in case there is
1076          * an error and we want to rollback the PC
1077          */
1078         curr_pc = vcpu->arch.pc;
1079         er = update_pc(vcpu, cause);
1080         if (er == EMULATE_FAIL)
1081                 return er;
1082
1083         base = inst.i_format.rs;
1084         op_inst = inst.i_format.rt;
1085         if (cpu_has_mips_r6)
1086                 offset = inst.spec3_format.simmediate;
1087         else
1088                 offset = inst.i_format.simmediate;
1089         cache = op_inst & CacheOp_Cache;
1090         op = op_inst & CacheOp_Op;
1091
1092         va = arch->gprs[base] + offset;
1093
1094         kvm_debug("CACHE (cache: %#x, op: %#x, base[%d]: %#lx, offset: %#x\n",
1095                   cache, op, base, arch->gprs[base], offset);
1096
1097         /* Secondary or tirtiary cache ops ignored */
1098         if (cache != Cache_I && cache != Cache_D)
1099                 return EMULATE_DONE;
1100
1101         switch (op_inst) {
1102         case Index_Invalidate_I:
1103                 flush_icache_line_indexed(va);
1104                 return EMULATE_DONE;
1105         case Index_Writeback_Inv_D:
1106                 flush_dcache_line_indexed(va);
1107                 return EMULATE_DONE;
1108         default:
1109                 break;
1110         };
1111
1112         kvm_err("@ %#lx/%#lx CACHE (cache: %#x, op: %#x, base[%d]: %#lx, offset: %#x\n",
1113                 curr_pc, vcpu->arch.gprs[31], cache, op, base, arch->gprs[base],
1114                 offset);
1115         /* Rollback PC */
1116         vcpu->arch.pc = curr_pc;
1117
1118         return EMULATE_FAIL;
1119 }
1120
1121 static enum emulation_result kvm_trap_vz_handle_gpsi(u32 cause, u32 *opc,
1122                                                      struct kvm_vcpu *vcpu)
1123 {
1124         enum emulation_result er = EMULATE_DONE;
1125         struct kvm_vcpu_arch *arch = &vcpu->arch;
1126         struct kvm_run *run = vcpu->run;
1127         union mips_instruction inst;
1128         int rd, rt, sel;
1129         int err;
1130
1131         /*
1132          *  Fetch the instruction.
1133          */
1134         if (cause & CAUSEF_BD)
1135                 opc += 1;
1136         err = kvm_get_badinstr(opc, vcpu, &inst.word);
1137         if (err)
1138                 return EMULATE_FAIL;
1139
1140         switch (inst.r_format.opcode) {
1141         case cop0_op:
1142                 er = kvm_vz_gpsi_cop0(inst, opc, cause, run, vcpu);
1143                 break;
1144 #ifndef CONFIG_CPU_MIPSR6
1145         case cache_op:
1146                 trace_kvm_exit(vcpu, KVM_TRACE_EXIT_CACHE);
1147                 er = kvm_vz_gpsi_cache(inst, opc, cause, run, vcpu);
1148                 break;
1149 #endif
1150         case spec3_op:
1151                 switch (inst.spec3_format.func) {
1152 #ifdef CONFIG_CPU_MIPSR6
1153                 case cache6_op:
1154                         trace_kvm_exit(vcpu, KVM_TRACE_EXIT_CACHE);
1155                         er = kvm_vz_gpsi_cache(inst, opc, cause, run, vcpu);
1156                         break;
1157 #endif
1158                 case rdhwr_op:
1159                         if (inst.r_format.rs || (inst.r_format.re >> 3))
1160                                 goto unknown;
1161
1162                         rd = inst.r_format.rd;
1163                         rt = inst.r_format.rt;
1164                         sel = inst.r_format.re & 0x7;
1165
1166                         switch (rd) {
1167                         case MIPS_HWR_CC:       /* Read count register */
1168                                 arch->gprs[rt] =
1169                                         (long)(int)kvm_mips_read_count(vcpu);
1170                                 break;
1171                         default:
1172                                 trace_kvm_hwr(vcpu, KVM_TRACE_RDHWR,
1173                                               KVM_TRACE_HWR(rd, sel), 0);
1174                                 goto unknown;
1175                         };
1176
1177                         trace_kvm_hwr(vcpu, KVM_TRACE_RDHWR,
1178                                       KVM_TRACE_HWR(rd, sel), arch->gprs[rt]);
1179
1180                         er = update_pc(vcpu, cause);
1181                         break;
1182                 default:
1183                         goto unknown;
1184                 };
1185                 break;
1186 unknown:
1187
1188         default:
1189                 kvm_err("GPSI exception not supported (%p/%#x)\n",
1190                                 opc, inst.word);
1191                 kvm_arch_vcpu_dump_regs(vcpu);
1192                 er = EMULATE_FAIL;
1193                 break;
1194         }
1195
1196         return er;
1197 }
1198
1199 static enum emulation_result kvm_trap_vz_handle_gsfc(u32 cause, u32 *opc,
1200                                                      struct kvm_vcpu *vcpu)
1201 {
1202         enum emulation_result er = EMULATE_DONE;
1203         struct kvm_vcpu_arch *arch = &vcpu->arch;
1204         union mips_instruction inst;
1205         int err;
1206
1207         /*
1208          *  Fetch the instruction.
1209          */
1210         if (cause & CAUSEF_BD)
1211                 opc += 1;
1212         err = kvm_get_badinstr(opc, vcpu, &inst.word);
1213         if (err)
1214                 return EMULATE_FAIL;
1215
1216         /* complete MTC0 on behalf of guest and advance EPC */
1217         if (inst.c0r_format.opcode == cop0_op &&
1218             inst.c0r_format.rs == mtc_op &&
1219             inst.c0r_format.z == 0) {
1220                 int rt = inst.c0r_format.rt;
1221                 int rd = inst.c0r_format.rd;
1222                 int sel = inst.c0r_format.sel;
1223                 unsigned int val = arch->gprs[rt];
1224                 unsigned int old_val, change;
1225
1226                 trace_kvm_hwr(vcpu, KVM_TRACE_MTC0, KVM_TRACE_COP0(rd, sel),
1227                               val);
1228
1229                 if ((rd == MIPS_CP0_STATUS) && (sel == 0)) {
1230                         /* FR bit should read as zero if no FPU */
1231                         if (!kvm_mips_guest_has_fpu(&vcpu->arch))
1232                                 val &= ~(ST0_CU1 | ST0_FR);
1233
1234                         /*
1235                          * Also don't allow FR to be set if host doesn't support
1236                          * it.
1237                          */
1238                         if (!(boot_cpu_data.fpu_id & MIPS_FPIR_F64))
1239                                 val &= ~ST0_FR;
1240
1241                         old_val = read_gc0_status();
1242                         change = val ^ old_val;
1243
1244                         if (change & ST0_FR) {
1245                                 /*
1246                                  * FPU and Vector register state is made
1247                                  * UNPREDICTABLE by a change of FR, so don't
1248                                  * even bother saving it.
1249                                  */
1250                                 kvm_drop_fpu(vcpu);
1251                         }
1252
1253                         /*
1254                          * If MSA state is already live, it is undefined how it
1255                          * interacts with FR=0 FPU state, and we don't want to
1256                          * hit reserved instruction exceptions trying to save
1257                          * the MSA state later when CU=1 && FR=1, so play it
1258                          * safe and save it first.
1259                          */
1260                         if (change & ST0_CU1 && !(val & ST0_FR) &&
1261                             vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA)
1262                                 kvm_lose_fpu(vcpu);
1263
1264                         write_gc0_status(val);
1265                 } else if ((rd == MIPS_CP0_CAUSE) && (sel == 0)) {
1266                         u32 old_cause = read_gc0_cause();
1267                         u32 change = old_cause ^ val;
1268
1269                         /* DC bit enabling/disabling timer? */
1270                         if (change & CAUSEF_DC) {
1271                                 if (val & CAUSEF_DC) {
1272                                         kvm_vz_lose_htimer(vcpu);
1273                                         kvm_mips_count_disable_cause(vcpu);
1274                                 } else {
1275                                         kvm_mips_count_enable_cause(vcpu);
1276                                 }
1277                         }
1278
1279                         /* Only certain bits are RW to the guest */
1280                         change &= (CAUSEF_DC | CAUSEF_IV | CAUSEF_WP |
1281                                    CAUSEF_IP0 | CAUSEF_IP1);
1282
1283                         /* WP can only be cleared */
1284                         change &= ~CAUSEF_WP | old_cause;
1285
1286                         write_gc0_cause(old_cause ^ change);
1287                 } else if ((rd == MIPS_CP0_STATUS) && (sel == 1)) { /* IntCtl */
1288                         write_gc0_intctl(val);
1289                 } else if ((rd == MIPS_CP0_CONFIG) && (sel == 5)) {
1290                         old_val = read_gc0_config5();
1291                         change = val ^ old_val;
1292                         /* Handle changes in FPU/MSA modes */
1293                         preempt_disable();
1294
1295                         /*
1296                          * Propagate FRE changes immediately if the FPU
1297                          * context is already loaded.
1298                          */
1299                         if (change & MIPS_CONF5_FRE &&
1300                             vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU)
1301                                 change_c0_config5(MIPS_CONF5_FRE, val);
1302
1303                         preempt_enable();
1304
1305                         val = old_val ^
1306                                 (change & kvm_vz_config5_guest_wrmask(vcpu));
1307                         write_gc0_config5(val);
1308                 } else {
1309                         kvm_err("Handle GSFC, unsupported field change @ %p: %#x\n",
1310                             opc, inst.word);
1311                         er = EMULATE_FAIL;
1312                 }
1313
1314                 if (er != EMULATE_FAIL)
1315                         er = update_pc(vcpu, cause);
1316         } else {
1317                 kvm_err("Handle GSFC, unrecognized instruction @ %p: %#x\n",
1318                         opc, inst.word);
1319                 er = EMULATE_FAIL;
1320         }
1321
1322         return er;
1323 }
1324
1325 static enum emulation_result kvm_trap_vz_handle_ghfc(u32 cause, u32 *opc,
1326                                                      struct kvm_vcpu *vcpu)
1327 {
1328         /*
1329          * Presumably this is due to MC (guest mode change), so lets trace some
1330          * relevant info.
1331          */
1332         trace_kvm_guest_mode_change(vcpu);
1333
1334         return EMULATE_DONE;
1335 }
1336
1337 static enum emulation_result kvm_trap_vz_handle_hc(u32 cause, u32 *opc,
1338                                                    struct kvm_vcpu *vcpu)
1339 {
1340         enum emulation_result er;
1341         union mips_instruction inst;
1342         unsigned long curr_pc;
1343         int err;
1344
1345         if (cause & CAUSEF_BD)
1346                 opc += 1;
1347         err = kvm_get_badinstr(opc, vcpu, &inst.word);
1348         if (err)
1349                 return EMULATE_FAIL;
1350
1351         /*
1352          * Update PC and hold onto current PC in case there is
1353          * an error and we want to rollback the PC
1354          */
1355         curr_pc = vcpu->arch.pc;
1356         er = update_pc(vcpu, cause);
1357         if (er == EMULATE_FAIL)
1358                 return er;
1359
1360         er = kvm_mips_emul_hypcall(vcpu, inst);
1361         if (er == EMULATE_FAIL)
1362                 vcpu->arch.pc = curr_pc;
1363
1364         return er;
1365 }
1366
1367 static enum emulation_result kvm_trap_vz_no_handler_guest_exit(u32 gexccode,
1368                                                         u32 cause,
1369                                                         u32 *opc,
1370                                                         struct kvm_vcpu *vcpu)
1371 {
1372         u32 inst;
1373
1374         /*
1375          *  Fetch the instruction.
1376          */
1377         if (cause & CAUSEF_BD)
1378                 opc += 1;
1379         kvm_get_badinstr(opc, vcpu, &inst);
1380
1381         kvm_err("Guest Exception Code: %d not yet handled @ PC: %p, inst: 0x%08x  Status: %#x\n",
1382                 gexccode, opc, inst, read_gc0_status());
1383
1384         return EMULATE_FAIL;
1385 }
1386
1387 static int kvm_trap_vz_handle_guest_exit(struct kvm_vcpu *vcpu)
1388 {
1389         u32 *opc = (u32 *) vcpu->arch.pc;
1390         u32 cause = vcpu->arch.host_cp0_cause;
1391         enum emulation_result er = EMULATE_DONE;
1392         u32 gexccode = (vcpu->arch.host_cp0_guestctl0 &
1393                         MIPS_GCTL0_GEXC) >> MIPS_GCTL0_GEXC_SHIFT;
1394         int ret = RESUME_GUEST;
1395
1396         trace_kvm_exit(vcpu, KVM_TRACE_EXIT_GEXCCODE_BASE + gexccode);
1397         switch (gexccode) {
1398         case MIPS_GCTL0_GEXC_GPSI:
1399                 ++vcpu->stat.vz_gpsi_exits;
1400                 er = kvm_trap_vz_handle_gpsi(cause, opc, vcpu);
1401                 break;
1402         case MIPS_GCTL0_GEXC_GSFC:
1403                 ++vcpu->stat.vz_gsfc_exits;
1404                 er = kvm_trap_vz_handle_gsfc(cause, opc, vcpu);
1405                 break;
1406         case MIPS_GCTL0_GEXC_HC:
1407                 ++vcpu->stat.vz_hc_exits;
1408                 er = kvm_trap_vz_handle_hc(cause, opc, vcpu);
1409                 break;
1410         case MIPS_GCTL0_GEXC_GRR:
1411                 ++vcpu->stat.vz_grr_exits;
1412                 er = kvm_trap_vz_no_handler_guest_exit(gexccode, cause, opc,
1413                                                        vcpu);
1414                 break;
1415         case MIPS_GCTL0_GEXC_GVA:
1416                 ++vcpu->stat.vz_gva_exits;
1417                 er = kvm_trap_vz_no_handler_guest_exit(gexccode, cause, opc,
1418                                                        vcpu);
1419                 break;
1420         case MIPS_GCTL0_GEXC_GHFC:
1421                 ++vcpu->stat.vz_ghfc_exits;
1422                 er = kvm_trap_vz_handle_ghfc(cause, opc, vcpu);
1423                 break;
1424         case MIPS_GCTL0_GEXC_GPA:
1425                 ++vcpu->stat.vz_gpa_exits;
1426                 er = kvm_trap_vz_no_handler_guest_exit(gexccode, cause, opc,
1427                                                        vcpu);
1428                 break;
1429         default:
1430                 ++vcpu->stat.vz_resvd_exits;
1431                 er = kvm_trap_vz_no_handler_guest_exit(gexccode, cause, opc,
1432                                                        vcpu);
1433                 break;
1434
1435         }
1436
1437         if (er == EMULATE_DONE) {
1438                 ret = RESUME_GUEST;
1439         } else if (er == EMULATE_HYPERCALL) {
1440                 ret = kvm_mips_handle_hypcall(vcpu);
1441         } else {
1442                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1443                 ret = RESUME_HOST;
1444         }
1445         return ret;
1446 }
1447
1448 /**
1449  * kvm_trap_vz_handle_cop_unusuable() - Guest used unusable coprocessor.
1450  * @vcpu:       Virtual CPU context.
1451  *
1452  * Handle when the guest attempts to use a coprocessor which hasn't been allowed
1453  * by the root context.
1454  */
1455 static int kvm_trap_vz_handle_cop_unusable(struct kvm_vcpu *vcpu)
1456 {
1457         struct kvm_run *run = vcpu->run;
1458         u32 cause = vcpu->arch.host_cp0_cause;
1459         enum emulation_result er = EMULATE_FAIL;
1460         int ret = RESUME_GUEST;
1461
1462         if (((cause & CAUSEF_CE) >> CAUSEB_CE) == 1) {
1463                 /*
1464                  * If guest FPU not present, the FPU operation should have been
1465                  * treated as a reserved instruction!
1466                  * If FPU already in use, we shouldn't get this at all.
1467                  */
1468                 if (WARN_ON(!kvm_mips_guest_has_fpu(&vcpu->arch) ||
1469                             vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU)) {
1470                         preempt_enable();
1471                         return EMULATE_FAIL;
1472                 }
1473
1474                 kvm_own_fpu(vcpu);
1475                 er = EMULATE_DONE;
1476         }
1477         /* other coprocessors not handled */
1478
1479         switch (er) {
1480         case EMULATE_DONE:
1481                 ret = RESUME_GUEST;
1482                 break;
1483
1484         case EMULATE_FAIL:
1485                 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1486                 ret = RESUME_HOST;
1487                 break;
1488
1489         default:
1490                 BUG();
1491         }
1492         return ret;
1493 }
1494
1495 /**
1496  * kvm_trap_vz_handle_msa_disabled() - Guest used MSA while disabled in root.
1497  * @vcpu:       Virtual CPU context.
1498  *
1499  * Handle when the guest attempts to use MSA when it is disabled in the root
1500  * context.
1501  */
1502 static int kvm_trap_vz_handle_msa_disabled(struct kvm_vcpu *vcpu)
1503 {
1504         struct kvm_run *run = vcpu->run;
1505
1506         /*
1507          * If MSA not present or not exposed to guest or FR=0, the MSA operation
1508          * should have been treated as a reserved instruction!
1509          * Same if CU1=1, FR=0.
1510          * If MSA already in use, we shouldn't get this at all.
1511          */
1512         if (!kvm_mips_guest_has_msa(&vcpu->arch) ||
1513             (read_gc0_status() & (ST0_CU1 | ST0_FR)) == ST0_CU1 ||
1514             !(read_gc0_config5() & MIPS_CONF5_MSAEN) ||
1515             vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
1516                 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1517                 return RESUME_HOST;
1518         }
1519
1520         kvm_own_msa(vcpu);
1521
1522         return RESUME_GUEST;
1523 }
1524
1525 static int kvm_trap_vz_handle_tlb_ld_miss(struct kvm_vcpu *vcpu)
1526 {
1527         struct kvm_run *run = vcpu->run;
1528         u32 *opc = (u32 *) vcpu->arch.pc;
1529         u32 cause = vcpu->arch.host_cp0_cause;
1530         ulong badvaddr = vcpu->arch.host_cp0_badvaddr;
1531         union mips_instruction inst;
1532         enum emulation_result er = EMULATE_DONE;
1533         int err, ret = RESUME_GUEST;
1534
1535         if (kvm_mips_handle_vz_root_tlb_fault(badvaddr, vcpu, false)) {
1536                 /* A code fetch fault doesn't count as an MMIO */
1537                 if (kvm_is_ifetch_fault(&vcpu->arch)) {
1538                         run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1539                         return RESUME_HOST;
1540                 }
1541
1542                 /* Fetch the instruction */
1543                 if (cause & CAUSEF_BD)
1544                         opc += 1;
1545                 err = kvm_get_badinstr(opc, vcpu, &inst.word);
1546                 if (err) {
1547                         run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1548                         return RESUME_HOST;
1549                 }
1550
1551                 /* Treat as MMIO */
1552                 er = kvm_mips_emulate_load(inst, cause, run, vcpu);
1553                 if (er == EMULATE_FAIL) {
1554                         kvm_err("Guest Emulate Load from MMIO space failed: PC: %p, BadVaddr: %#lx\n",
1555                                 opc, badvaddr);
1556                         run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1557                 }
1558         }
1559
1560         if (er == EMULATE_DONE) {
1561                 ret = RESUME_GUEST;
1562         } else if (er == EMULATE_DO_MMIO) {
1563                 run->exit_reason = KVM_EXIT_MMIO;
1564                 ret = RESUME_HOST;
1565         } else {
1566                 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1567                 ret = RESUME_HOST;
1568         }
1569         return ret;
1570 }
1571
1572 static int kvm_trap_vz_handle_tlb_st_miss(struct kvm_vcpu *vcpu)
1573 {
1574         struct kvm_run *run = vcpu->run;
1575         u32 *opc = (u32 *) vcpu->arch.pc;
1576         u32 cause = vcpu->arch.host_cp0_cause;
1577         ulong badvaddr = vcpu->arch.host_cp0_badvaddr;
1578         union mips_instruction inst;
1579         enum emulation_result er = EMULATE_DONE;
1580         int err;
1581         int ret = RESUME_GUEST;
1582
1583         /* Just try the access again if we couldn't do the translation */
1584         if (kvm_vz_badvaddr_to_gpa(vcpu, badvaddr, &badvaddr))
1585                 return RESUME_GUEST;
1586         vcpu->arch.host_cp0_badvaddr = badvaddr;
1587
1588         if (kvm_mips_handle_vz_root_tlb_fault(badvaddr, vcpu, true)) {
1589                 /* Fetch the instruction */
1590                 if (cause & CAUSEF_BD)
1591                         opc += 1;
1592                 err = kvm_get_badinstr(opc, vcpu, &inst.word);
1593                 if (err) {
1594                         run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1595                         return RESUME_HOST;
1596                 }
1597
1598                 /* Treat as MMIO */
1599                 er = kvm_mips_emulate_store(inst, cause, run, vcpu);
1600                 if (er == EMULATE_FAIL) {
1601                         kvm_err("Guest Emulate Store to MMIO space failed: PC: %p, BadVaddr: %#lx\n",
1602                                 opc, badvaddr);
1603                         run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1604                 }
1605         }
1606
1607         if (er == EMULATE_DONE) {
1608                 ret = RESUME_GUEST;
1609         } else if (er == EMULATE_DO_MMIO) {
1610                 run->exit_reason = KVM_EXIT_MMIO;
1611                 ret = RESUME_HOST;
1612         } else {
1613                 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1614                 ret = RESUME_HOST;
1615         }
1616         return ret;
1617 }
1618
1619 static u64 kvm_vz_get_one_regs[] = {
1620         KVM_REG_MIPS_CP0_INDEX,
1621         KVM_REG_MIPS_CP0_ENTRYLO0,
1622         KVM_REG_MIPS_CP0_ENTRYLO1,
1623         KVM_REG_MIPS_CP0_CONTEXT,
1624         KVM_REG_MIPS_CP0_PAGEMASK,
1625         KVM_REG_MIPS_CP0_PAGEGRAIN,
1626         KVM_REG_MIPS_CP0_WIRED,
1627         KVM_REG_MIPS_CP0_HWRENA,
1628         KVM_REG_MIPS_CP0_BADVADDR,
1629         KVM_REG_MIPS_CP0_COUNT,
1630         KVM_REG_MIPS_CP0_ENTRYHI,
1631         KVM_REG_MIPS_CP0_COMPARE,
1632         KVM_REG_MIPS_CP0_STATUS,
1633         KVM_REG_MIPS_CP0_INTCTL,
1634         KVM_REG_MIPS_CP0_CAUSE,
1635         KVM_REG_MIPS_CP0_EPC,
1636         KVM_REG_MIPS_CP0_PRID,
1637         KVM_REG_MIPS_CP0_EBASE,
1638         KVM_REG_MIPS_CP0_CONFIG,
1639         KVM_REG_MIPS_CP0_CONFIG1,
1640         KVM_REG_MIPS_CP0_CONFIG2,
1641         KVM_REG_MIPS_CP0_CONFIG3,
1642         KVM_REG_MIPS_CP0_CONFIG4,
1643         KVM_REG_MIPS_CP0_CONFIG5,
1644 #ifdef CONFIG_64BIT
1645         KVM_REG_MIPS_CP0_XCONTEXT,
1646 #endif
1647         KVM_REG_MIPS_CP0_ERROREPC,
1648
1649         KVM_REG_MIPS_COUNT_CTL,
1650         KVM_REG_MIPS_COUNT_RESUME,
1651         KVM_REG_MIPS_COUNT_HZ,
1652 };
1653
1654 static u64 kvm_vz_get_one_regs_contextconfig[] = {
1655         KVM_REG_MIPS_CP0_CONTEXTCONFIG,
1656 #ifdef CONFIG_64BIT
1657         KVM_REG_MIPS_CP0_XCONTEXTCONFIG,
1658 #endif
1659 };
1660
1661 static u64 kvm_vz_get_one_regs_segments[] = {
1662         KVM_REG_MIPS_CP0_SEGCTL0,
1663         KVM_REG_MIPS_CP0_SEGCTL1,
1664         KVM_REG_MIPS_CP0_SEGCTL2,
1665 };
1666
1667 static u64 kvm_vz_get_one_regs_htw[] = {
1668         KVM_REG_MIPS_CP0_PWBASE,
1669         KVM_REG_MIPS_CP0_PWFIELD,
1670         KVM_REG_MIPS_CP0_PWSIZE,
1671         KVM_REG_MIPS_CP0_PWCTL,
1672 };
1673
1674 static u64 kvm_vz_get_one_regs_kscratch[] = {
1675         KVM_REG_MIPS_CP0_KSCRATCH1,
1676         KVM_REG_MIPS_CP0_KSCRATCH2,
1677         KVM_REG_MIPS_CP0_KSCRATCH3,
1678         KVM_REG_MIPS_CP0_KSCRATCH4,
1679         KVM_REG_MIPS_CP0_KSCRATCH5,
1680         KVM_REG_MIPS_CP0_KSCRATCH6,
1681 };
1682
1683 static unsigned long kvm_vz_num_regs(struct kvm_vcpu *vcpu)
1684 {
1685         unsigned long ret;
1686
1687         ret = ARRAY_SIZE(kvm_vz_get_one_regs);
1688         if (cpu_guest_has_userlocal)
1689                 ++ret;
1690         if (cpu_guest_has_badinstr)
1691                 ++ret;
1692         if (cpu_guest_has_badinstrp)
1693                 ++ret;
1694         if (cpu_guest_has_contextconfig)
1695                 ret += ARRAY_SIZE(kvm_vz_get_one_regs_contextconfig);
1696         if (cpu_guest_has_segments)
1697                 ret += ARRAY_SIZE(kvm_vz_get_one_regs_segments);
1698         if (cpu_guest_has_htw)
1699                 ret += ARRAY_SIZE(kvm_vz_get_one_regs_htw);
1700         if (cpu_guest_has_maar && !cpu_guest_has_dyn_maar)
1701                 ret += 1 + ARRAY_SIZE(vcpu->arch.maar);
1702         ret += __arch_hweight8(cpu_data[0].guest.kscratch_mask);
1703
1704         return ret;
1705 }
1706
1707 static int kvm_vz_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices)
1708 {
1709         u64 index;
1710         unsigned int i;
1711
1712         if (copy_to_user(indices, kvm_vz_get_one_regs,
1713                          sizeof(kvm_vz_get_one_regs)))
1714                 return -EFAULT;
1715         indices += ARRAY_SIZE(kvm_vz_get_one_regs);
1716
1717         if (cpu_guest_has_userlocal) {
1718                 index = KVM_REG_MIPS_CP0_USERLOCAL;
1719                 if (copy_to_user(indices, &index, sizeof(index)))
1720                         return -EFAULT;
1721                 ++indices;
1722         }
1723         if (cpu_guest_has_badinstr) {
1724                 index = KVM_REG_MIPS_CP0_BADINSTR;
1725                 if (copy_to_user(indices, &index, sizeof(index)))
1726                         return -EFAULT;
1727                 ++indices;
1728         }
1729         if (cpu_guest_has_badinstrp) {
1730                 index = KVM_REG_MIPS_CP0_BADINSTRP;
1731                 if (copy_to_user(indices, &index, sizeof(index)))
1732                         return -EFAULT;
1733                 ++indices;
1734         }
1735         if (cpu_guest_has_contextconfig) {
1736                 if (copy_to_user(indices, kvm_vz_get_one_regs_contextconfig,
1737                                  sizeof(kvm_vz_get_one_regs_contextconfig)))
1738                         return -EFAULT;
1739                 indices += ARRAY_SIZE(kvm_vz_get_one_regs_contextconfig);
1740         }
1741         if (cpu_guest_has_segments) {
1742                 if (copy_to_user(indices, kvm_vz_get_one_regs_segments,
1743                                  sizeof(kvm_vz_get_one_regs_segments)))
1744                         return -EFAULT;
1745                 indices += ARRAY_SIZE(kvm_vz_get_one_regs_segments);
1746         }
1747         if (cpu_guest_has_htw) {
1748                 if (copy_to_user(indices, kvm_vz_get_one_regs_htw,
1749                                  sizeof(kvm_vz_get_one_regs_htw)))
1750                         return -EFAULT;
1751                 indices += ARRAY_SIZE(kvm_vz_get_one_regs_htw);
1752         }
1753         if (cpu_guest_has_maar && !cpu_guest_has_dyn_maar) {
1754                 for (i = 0; i < ARRAY_SIZE(vcpu->arch.maar); ++i) {
1755                         index = KVM_REG_MIPS_CP0_MAAR(i);
1756                         if (copy_to_user(indices, &index, sizeof(index)))
1757                                 return -EFAULT;
1758                         ++indices;
1759                 }
1760
1761                 index = KVM_REG_MIPS_CP0_MAARI;
1762                 if (copy_to_user(indices, &index, sizeof(index)))
1763                         return -EFAULT;
1764                 ++indices;
1765         }
1766         for (i = 0; i < 6; ++i) {
1767                 if (!cpu_guest_has_kscr(i + 2))
1768                         continue;
1769
1770                 if (copy_to_user(indices, &kvm_vz_get_one_regs_kscratch[i],
1771                                  sizeof(kvm_vz_get_one_regs_kscratch[i])))
1772                         return -EFAULT;
1773                 ++indices;
1774         }
1775
1776         return 0;
1777 }
1778
1779 static inline s64 entrylo_kvm_to_user(unsigned long v)
1780 {
1781         s64 mask, ret = v;
1782
1783         if (BITS_PER_LONG == 32) {
1784                 /*
1785                  * KVM API exposes 64-bit version of the register, so move the
1786                  * RI/XI bits up into place.
1787                  */
1788                 mask = MIPS_ENTRYLO_RI | MIPS_ENTRYLO_XI;
1789                 ret &= ~mask;
1790                 ret |= ((s64)v & mask) << 32;
1791         }
1792         return ret;
1793 }
1794
1795 static inline unsigned long entrylo_user_to_kvm(s64 v)
1796 {
1797         unsigned long mask, ret = v;
1798
1799         if (BITS_PER_LONG == 32) {
1800                 /*
1801                  * KVM API exposes 64-bit versiono of the register, so move the
1802                  * RI/XI bits down into place.
1803                  */
1804                 mask = MIPS_ENTRYLO_RI | MIPS_ENTRYLO_XI;
1805                 ret &= ~mask;
1806                 ret |= (v >> 32) & mask;
1807         }
1808         return ret;
1809 }
1810
1811 static int kvm_vz_get_one_reg(struct kvm_vcpu *vcpu,
1812                               const struct kvm_one_reg *reg,
1813                               s64 *v)
1814 {
1815         struct mips_coproc *cop0 = vcpu->arch.cop0;
1816         unsigned int idx;
1817
1818         switch (reg->id) {
1819         case KVM_REG_MIPS_CP0_INDEX:
1820                 *v = (long)read_gc0_index();
1821                 break;
1822         case KVM_REG_MIPS_CP0_ENTRYLO0:
1823                 *v = entrylo_kvm_to_user(read_gc0_entrylo0());
1824                 break;
1825         case KVM_REG_MIPS_CP0_ENTRYLO1:
1826                 *v = entrylo_kvm_to_user(read_gc0_entrylo1());
1827                 break;
1828         case KVM_REG_MIPS_CP0_CONTEXT:
1829                 *v = (long)read_gc0_context();
1830                 break;
1831         case KVM_REG_MIPS_CP0_CONTEXTCONFIG:
1832                 if (!cpu_guest_has_contextconfig)
1833                         return -EINVAL;
1834                 *v = read_gc0_contextconfig();
1835                 break;
1836         case KVM_REG_MIPS_CP0_USERLOCAL:
1837                 if (!cpu_guest_has_userlocal)
1838                         return -EINVAL;
1839                 *v = read_gc0_userlocal();
1840                 break;
1841 #ifdef CONFIG_64BIT
1842         case KVM_REG_MIPS_CP0_XCONTEXTCONFIG:
1843                 if (!cpu_guest_has_contextconfig)
1844                         return -EINVAL;
1845                 *v = read_gc0_xcontextconfig();
1846                 break;
1847 #endif
1848         case KVM_REG_MIPS_CP0_PAGEMASK:
1849                 *v = (long)read_gc0_pagemask();
1850                 break;
1851         case KVM_REG_MIPS_CP0_PAGEGRAIN:
1852                 *v = (long)read_gc0_pagegrain();
1853                 break;
1854         case KVM_REG_MIPS_CP0_SEGCTL0:
1855                 if (!cpu_guest_has_segments)
1856                         return -EINVAL;
1857                 *v = read_gc0_segctl0();
1858                 break;
1859         case KVM_REG_MIPS_CP0_SEGCTL1:
1860                 if (!cpu_guest_has_segments)
1861                         return -EINVAL;
1862                 *v = read_gc0_segctl1();
1863                 break;
1864         case KVM_REG_MIPS_CP0_SEGCTL2:
1865                 if (!cpu_guest_has_segments)
1866                         return -EINVAL;
1867                 *v = read_gc0_segctl2();
1868                 break;
1869         case KVM_REG_MIPS_CP0_PWBASE:
1870                 if (!cpu_guest_has_htw)
1871                         return -EINVAL;
1872                 *v = read_gc0_pwbase();
1873                 break;
1874         case KVM_REG_MIPS_CP0_PWFIELD:
1875                 if (!cpu_guest_has_htw)
1876                         return -EINVAL;
1877                 *v = read_gc0_pwfield();
1878                 break;
1879         case KVM_REG_MIPS_CP0_PWSIZE:
1880                 if (!cpu_guest_has_htw)
1881                         return -EINVAL;
1882                 *v = read_gc0_pwsize();
1883                 break;
1884         case KVM_REG_MIPS_CP0_WIRED:
1885                 *v = (long)read_gc0_wired();
1886                 break;
1887         case KVM_REG_MIPS_CP0_PWCTL:
1888                 if (!cpu_guest_has_htw)
1889                         return -EINVAL;
1890                 *v = read_gc0_pwctl();
1891                 break;
1892         case KVM_REG_MIPS_CP0_HWRENA:
1893                 *v = (long)read_gc0_hwrena();
1894                 break;
1895         case KVM_REG_MIPS_CP0_BADVADDR:
1896                 *v = (long)read_gc0_badvaddr();
1897                 break;
1898         case KVM_REG_MIPS_CP0_BADINSTR:
1899                 if (!cpu_guest_has_badinstr)
1900                         return -EINVAL;
1901                 *v = read_gc0_badinstr();
1902                 break;
1903         case KVM_REG_MIPS_CP0_BADINSTRP:
1904                 if (!cpu_guest_has_badinstrp)
1905                         return -EINVAL;
1906                 *v = read_gc0_badinstrp();
1907                 break;
1908         case KVM_REG_MIPS_CP0_COUNT:
1909                 *v = kvm_mips_read_count(vcpu);
1910                 break;
1911         case KVM_REG_MIPS_CP0_ENTRYHI:
1912                 *v = (long)read_gc0_entryhi();
1913                 break;
1914         case KVM_REG_MIPS_CP0_COMPARE:
1915                 *v = (long)read_gc0_compare();
1916                 break;
1917         case KVM_REG_MIPS_CP0_STATUS:
1918                 *v = (long)read_gc0_status();
1919                 break;
1920         case KVM_REG_MIPS_CP0_INTCTL:
1921                 *v = read_gc0_intctl();
1922                 break;
1923         case KVM_REG_MIPS_CP0_CAUSE:
1924                 *v = (long)read_gc0_cause();
1925                 break;
1926         case KVM_REG_MIPS_CP0_EPC:
1927                 *v = (long)read_gc0_epc();
1928                 break;
1929         case KVM_REG_MIPS_CP0_PRID:
1930                 *v = (long)kvm_read_c0_guest_prid(cop0);
1931                 break;
1932         case KVM_REG_MIPS_CP0_EBASE:
1933                 *v = kvm_vz_read_gc0_ebase();
1934                 break;
1935         case KVM_REG_MIPS_CP0_CONFIG:
1936                 *v = read_gc0_config();
1937                 break;
1938         case KVM_REG_MIPS_CP0_CONFIG1:
1939                 if (!cpu_guest_has_conf1)
1940                         return -EINVAL;
1941                 *v = read_gc0_config1();
1942                 break;
1943         case KVM_REG_MIPS_CP0_CONFIG2:
1944                 if (!cpu_guest_has_conf2)
1945                         return -EINVAL;
1946                 *v = read_gc0_config2();
1947                 break;
1948         case KVM_REG_MIPS_CP0_CONFIG3:
1949                 if (!cpu_guest_has_conf3)
1950                         return -EINVAL;
1951                 *v = read_gc0_config3();
1952                 break;
1953         case KVM_REG_MIPS_CP0_CONFIG4:
1954                 if (!cpu_guest_has_conf4)
1955                         return -EINVAL;
1956                 *v = read_gc0_config4();
1957                 break;
1958         case KVM_REG_MIPS_CP0_CONFIG5:
1959                 if (!cpu_guest_has_conf5)
1960                         return -EINVAL;
1961                 *v = read_gc0_config5();
1962                 break;
1963         case KVM_REG_MIPS_CP0_MAAR(0) ... KVM_REG_MIPS_CP0_MAAR(0x3f):
1964                 if (!cpu_guest_has_maar || cpu_guest_has_dyn_maar)
1965                         return -EINVAL;
1966                 idx = reg->id - KVM_REG_MIPS_CP0_MAAR(0);
1967                 if (idx >= ARRAY_SIZE(vcpu->arch.maar))
1968                         return -EINVAL;
1969                 *v = vcpu->arch.maar[idx];
1970                 break;
1971         case KVM_REG_MIPS_CP0_MAARI:
1972                 if (!cpu_guest_has_maar || cpu_guest_has_dyn_maar)
1973                         return -EINVAL;
1974                 *v = kvm_read_sw_gc0_maari(vcpu->arch.cop0);
1975                 break;
1976 #ifdef CONFIG_64BIT
1977         case KVM_REG_MIPS_CP0_XCONTEXT:
1978                 *v = read_gc0_xcontext();
1979                 break;
1980 #endif
1981         case KVM_REG_MIPS_CP0_ERROREPC:
1982                 *v = (long)read_gc0_errorepc();
1983                 break;
1984         case KVM_REG_MIPS_CP0_KSCRATCH1 ... KVM_REG_MIPS_CP0_KSCRATCH6:
1985                 idx = reg->id - KVM_REG_MIPS_CP0_KSCRATCH1 + 2;
1986                 if (!cpu_guest_has_kscr(idx))
1987                         return -EINVAL;
1988                 switch (idx) {
1989                 case 2:
1990                         *v = (long)read_gc0_kscratch1();
1991                         break;
1992                 case 3:
1993                         *v = (long)read_gc0_kscratch2();
1994                         break;
1995                 case 4:
1996                         *v = (long)read_gc0_kscratch3();
1997                         break;
1998                 case 5:
1999                         *v = (long)read_gc0_kscratch4();
2000                         break;
2001                 case 6:
2002                         *v = (long)read_gc0_kscratch5();
2003                         break;
2004                 case 7:
2005                         *v = (long)read_gc0_kscratch6();
2006                         break;
2007                 }
2008                 break;
2009         case KVM_REG_MIPS_COUNT_CTL:
2010                 *v = vcpu->arch.count_ctl;
2011                 break;
2012         case KVM_REG_MIPS_COUNT_RESUME:
2013                 *v = ktime_to_ns(vcpu->arch.count_resume);
2014                 break;
2015         case KVM_REG_MIPS_COUNT_HZ:
2016                 *v = vcpu->arch.count_hz;
2017                 break;
2018         default:
2019                 return -EINVAL;
2020         }
2021         return 0;
2022 }
2023
2024 static int kvm_vz_set_one_reg(struct kvm_vcpu *vcpu,
2025                               const struct kvm_one_reg *reg,
2026                               s64 v)
2027 {
2028         struct mips_coproc *cop0 = vcpu->arch.cop0;
2029         unsigned int idx;
2030         int ret = 0;
2031         unsigned int cur, change;
2032
2033         switch (reg->id) {
2034         case KVM_REG_MIPS_CP0_INDEX:
2035                 write_gc0_index(v);
2036                 break;
2037         case KVM_REG_MIPS_CP0_ENTRYLO0:
2038                 write_gc0_entrylo0(entrylo_user_to_kvm(v));
2039                 break;
2040         case KVM_REG_MIPS_CP0_ENTRYLO1:
2041                 write_gc0_entrylo1(entrylo_user_to_kvm(v));
2042                 break;
2043         case KVM_REG_MIPS_CP0_CONTEXT:
2044                 write_gc0_context(v);
2045                 break;
2046         case KVM_REG_MIPS_CP0_CONTEXTCONFIG:
2047                 if (!cpu_guest_has_contextconfig)
2048                         return -EINVAL;
2049                 write_gc0_contextconfig(v);
2050                 break;
2051         case KVM_REG_MIPS_CP0_USERLOCAL:
2052                 if (!cpu_guest_has_userlocal)
2053                         return -EINVAL;
2054                 write_gc0_userlocal(v);
2055                 break;
2056 #ifdef CONFIG_64BIT
2057         case KVM_REG_MIPS_CP0_XCONTEXTCONFIG:
2058                 if (!cpu_guest_has_contextconfig)
2059                         return -EINVAL;
2060                 write_gc0_xcontextconfig(v);
2061                 break;
2062 #endif
2063         case KVM_REG_MIPS_CP0_PAGEMASK:
2064                 write_gc0_pagemask(v);
2065                 break;
2066         case KVM_REG_MIPS_CP0_PAGEGRAIN:
2067                 write_gc0_pagegrain(v);
2068                 break;
2069         case KVM_REG_MIPS_CP0_SEGCTL0:
2070                 if (!cpu_guest_has_segments)
2071                         return -EINVAL;
2072                 write_gc0_segctl0(v);
2073                 break;
2074         case KVM_REG_MIPS_CP0_SEGCTL1:
2075                 if (!cpu_guest_has_segments)
2076                         return -EINVAL;
2077                 write_gc0_segctl1(v);
2078                 break;
2079         case KVM_REG_MIPS_CP0_SEGCTL2:
2080                 if (!cpu_guest_has_segments)
2081                         return -EINVAL;
2082                 write_gc0_segctl2(v);
2083                 break;
2084         case KVM_REG_MIPS_CP0_PWBASE:
2085                 if (!cpu_guest_has_htw)
2086                         return -EINVAL;
2087                 write_gc0_pwbase(v);
2088                 break;
2089         case KVM_REG_MIPS_CP0_PWFIELD:
2090                 if (!cpu_guest_has_htw)
2091                         return -EINVAL;
2092                 write_gc0_pwfield(v);
2093                 break;
2094         case KVM_REG_MIPS_CP0_PWSIZE:
2095                 if (!cpu_guest_has_htw)
2096                         return -EINVAL;
2097                 write_gc0_pwsize(v);
2098                 break;
2099         case KVM_REG_MIPS_CP0_WIRED:
2100                 change_gc0_wired(MIPSR6_WIRED_WIRED, v);
2101                 break;
2102         case KVM_REG_MIPS_CP0_PWCTL:
2103                 if (!cpu_guest_has_htw)
2104                         return -EINVAL;
2105                 write_gc0_pwctl(v);
2106                 break;
2107         case KVM_REG_MIPS_CP0_HWRENA:
2108                 write_gc0_hwrena(v);
2109                 break;
2110         case KVM_REG_MIPS_CP0_BADVADDR:
2111                 write_gc0_badvaddr(v);
2112                 break;
2113         case KVM_REG_MIPS_CP0_BADINSTR:
2114                 if (!cpu_guest_has_badinstr)
2115                         return -EINVAL;
2116                 write_gc0_badinstr(v);
2117                 break;
2118         case KVM_REG_MIPS_CP0_BADINSTRP:
2119                 if (!cpu_guest_has_badinstrp)
2120                         return -EINVAL;
2121                 write_gc0_badinstrp(v);
2122                 break;
2123         case KVM_REG_MIPS_CP0_COUNT:
2124                 kvm_mips_write_count(vcpu, v);
2125                 break;
2126         case KVM_REG_MIPS_CP0_ENTRYHI:
2127                 write_gc0_entryhi(v);
2128                 break;
2129         case KVM_REG_MIPS_CP0_COMPARE:
2130                 kvm_mips_write_compare(vcpu, v, false);
2131                 break;
2132         case KVM_REG_MIPS_CP0_STATUS:
2133                 write_gc0_status(v);
2134                 break;
2135         case KVM_REG_MIPS_CP0_INTCTL:
2136                 write_gc0_intctl(v);
2137                 break;
2138         case KVM_REG_MIPS_CP0_CAUSE:
2139                 /*
2140                  * If the timer is stopped or started (DC bit) it must look
2141                  * atomic with changes to the timer interrupt pending bit (TI).
2142                  * A timer interrupt should not happen in between.
2143                  */
2144                 if ((read_gc0_cause() ^ v) & CAUSEF_DC) {
2145                         if (v & CAUSEF_DC) {
2146                                 /* disable timer first */
2147                                 kvm_mips_count_disable_cause(vcpu);
2148                                 change_gc0_cause((u32)~CAUSEF_DC, v);
2149                         } else {
2150                                 /* enable timer last */
2151                                 change_gc0_cause((u32)~CAUSEF_DC, v);
2152                                 kvm_mips_count_enable_cause(vcpu);
2153                         }
2154                 } else {
2155                         write_gc0_cause(v);
2156                 }
2157                 break;
2158         case KVM_REG_MIPS_CP0_EPC:
2159                 write_gc0_epc(v);
2160                 break;
2161         case KVM_REG_MIPS_CP0_PRID:
2162                 kvm_write_c0_guest_prid(cop0, v);
2163                 break;
2164         case KVM_REG_MIPS_CP0_EBASE:
2165                 kvm_vz_write_gc0_ebase(v);
2166                 break;
2167         case KVM_REG_MIPS_CP0_CONFIG:
2168                 cur = read_gc0_config();
2169                 change = (cur ^ v) & kvm_vz_config_user_wrmask(vcpu);
2170                 if (change) {
2171                         v = cur ^ change;
2172                         write_gc0_config(v);
2173                 }
2174                 break;
2175         case KVM_REG_MIPS_CP0_CONFIG1:
2176                 if (!cpu_guest_has_conf1)
2177                         break;
2178                 cur = read_gc0_config1();
2179                 change = (cur ^ v) & kvm_vz_config1_user_wrmask(vcpu);
2180                 if (change) {
2181                         v = cur ^ change;
2182                         write_gc0_config1(v);
2183                 }
2184                 break;
2185         case KVM_REG_MIPS_CP0_CONFIG2:
2186                 if (!cpu_guest_has_conf2)
2187                         break;
2188                 cur = read_gc0_config2();
2189                 change = (cur ^ v) & kvm_vz_config2_user_wrmask(vcpu);
2190                 if (change) {
2191                         v = cur ^ change;
2192                         write_gc0_config2(v);
2193                 }
2194                 break;
2195         case KVM_REG_MIPS_CP0_CONFIG3:
2196                 if (!cpu_guest_has_conf3)
2197                         break;
2198                 cur = read_gc0_config3();
2199                 change = (cur ^ v) & kvm_vz_config3_user_wrmask(vcpu);
2200                 if (change) {
2201                         v = cur ^ change;
2202                         write_gc0_config3(v);
2203                 }
2204                 break;
2205         case KVM_REG_MIPS_CP0_CONFIG4:
2206                 if (!cpu_guest_has_conf4)
2207                         break;
2208                 cur = read_gc0_config4();
2209                 change = (cur ^ v) & kvm_vz_config4_user_wrmask(vcpu);
2210                 if (change) {
2211                         v = cur ^ change;
2212                         write_gc0_config4(v);
2213                 }
2214                 break;
2215         case KVM_REG_MIPS_CP0_CONFIG5:
2216                 if (!cpu_guest_has_conf5)
2217                         break;
2218                 cur = read_gc0_config5();
2219                 change = (cur ^ v) & kvm_vz_config5_user_wrmask(vcpu);
2220                 if (change) {
2221                         v = cur ^ change;
2222                         write_gc0_config5(v);
2223                 }
2224                 break;
2225         case KVM_REG_MIPS_CP0_MAAR(0) ... KVM_REG_MIPS_CP0_MAAR(0x3f):
2226                 if (!cpu_guest_has_maar || cpu_guest_has_dyn_maar)
2227                         return -EINVAL;
2228                 idx = reg->id - KVM_REG_MIPS_CP0_MAAR(0);
2229                 if (idx >= ARRAY_SIZE(vcpu->arch.maar))
2230                         return -EINVAL;
2231                 vcpu->arch.maar[idx] = mips_process_maar(dmtc_op, v);
2232                 break;
2233         case KVM_REG_MIPS_CP0_MAARI:
2234                 if (!cpu_guest_has_maar || cpu_guest_has_dyn_maar)
2235                         return -EINVAL;
2236                 kvm_write_maari(vcpu, v);
2237                 break;
2238 #ifdef CONFIG_64BIT
2239         case KVM_REG_MIPS_CP0_XCONTEXT:
2240                 write_gc0_xcontext(v);
2241                 break;
2242 #endif
2243         case KVM_REG_MIPS_CP0_ERROREPC:
2244                 write_gc0_errorepc(v);
2245                 break;
2246         case KVM_REG_MIPS_CP0_KSCRATCH1 ... KVM_REG_MIPS_CP0_KSCRATCH6:
2247                 idx = reg->id - KVM_REG_MIPS_CP0_KSCRATCH1 + 2;
2248                 if (!cpu_guest_has_kscr(idx))
2249                         return -EINVAL;
2250                 switch (idx) {
2251                 case 2:
2252                         write_gc0_kscratch1(v);
2253                         break;
2254                 case 3:
2255                         write_gc0_kscratch2(v);
2256                         break;
2257                 case 4:
2258                         write_gc0_kscratch3(v);
2259                         break;
2260                 case 5:
2261                         write_gc0_kscratch4(v);
2262                         break;
2263                 case 6:
2264                         write_gc0_kscratch5(v);
2265                         break;
2266                 case 7:
2267                         write_gc0_kscratch6(v);
2268                         break;
2269                 }
2270                 break;
2271         case KVM_REG_MIPS_COUNT_CTL:
2272                 ret = kvm_mips_set_count_ctl(vcpu, v);
2273                 break;
2274         case KVM_REG_MIPS_COUNT_RESUME:
2275                 ret = kvm_mips_set_count_resume(vcpu, v);
2276                 break;
2277         case KVM_REG_MIPS_COUNT_HZ:
2278                 ret = kvm_mips_set_count_hz(vcpu, v);
2279                 break;
2280         default:
2281                 return -EINVAL;
2282         }
2283         return ret;
2284 }
2285
2286 #define guestid_cache(cpu)      (cpu_data[cpu].guestid_cache)
2287 static void kvm_vz_get_new_guestid(unsigned long cpu, struct kvm_vcpu *vcpu)
2288 {
2289         unsigned long guestid = guestid_cache(cpu);
2290
2291         if (!(++guestid & GUESTID_MASK)) {
2292                 if (cpu_has_vtag_icache)
2293                         flush_icache_all();
2294
2295                 if (!guestid)           /* fix version if needed */
2296                         guestid = GUESTID_FIRST_VERSION;
2297
2298                 ++guestid;              /* guestid 0 reserved for root */
2299
2300                 /* start new guestid cycle */
2301                 kvm_vz_local_flush_roottlb_all_guests();
2302                 kvm_vz_local_flush_guesttlb_all();
2303         }
2304
2305         guestid_cache(cpu) = guestid;
2306 }
2307
2308 /* Returns 1 if the guest TLB may be clobbered */
2309 static int kvm_vz_check_requests(struct kvm_vcpu *vcpu, int cpu)
2310 {
2311         int ret = 0;
2312         int i;
2313
2314         if (!vcpu->requests)
2315                 return 0;
2316
2317         if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) {
2318                 if (cpu_has_guestid) {
2319                         /* Drop all GuestIDs for this VCPU */
2320                         for_each_possible_cpu(i)
2321                                 vcpu->arch.vzguestid[i] = 0;
2322                         /* This will clobber guest TLB contents too */
2323                         ret = 1;
2324                 }
2325                 /*
2326                  * For Root ASID Dealias (RAD) we don't do anything here, but we
2327                  * still need the request to ensure we recheck asid_flush_mask.
2328                  * We can still return 0 as only the root TLB will be affected
2329                  * by a root ASID flush.
2330                  */
2331         }
2332
2333         return ret;
2334 }
2335
2336 static void kvm_vz_vcpu_save_wired(struct kvm_vcpu *vcpu)
2337 {
2338         unsigned int wired = read_gc0_wired();
2339         struct kvm_mips_tlb *tlbs;
2340         int i;
2341
2342         /* Expand the wired TLB array if necessary */
2343         wired &= MIPSR6_WIRED_WIRED;
2344         if (wired > vcpu->arch.wired_tlb_limit) {
2345                 tlbs = krealloc(vcpu->arch.wired_tlb, wired *
2346                                 sizeof(*vcpu->arch.wired_tlb), GFP_ATOMIC);
2347                 if (WARN_ON(!tlbs)) {
2348                         /* Save whatever we can */
2349                         wired = vcpu->arch.wired_tlb_limit;
2350                 } else {
2351                         vcpu->arch.wired_tlb = tlbs;
2352                         vcpu->arch.wired_tlb_limit = wired;
2353                 }
2354         }
2355
2356         if (wired)
2357                 /* Save wired entries from the guest TLB */
2358                 kvm_vz_save_guesttlb(vcpu->arch.wired_tlb, 0, wired);
2359         /* Invalidate any dropped entries since last time */
2360         for (i = wired; i < vcpu->arch.wired_tlb_used; ++i) {
2361                 vcpu->arch.wired_tlb[i].tlb_hi = UNIQUE_GUEST_ENTRYHI(i);
2362                 vcpu->arch.wired_tlb[i].tlb_lo[0] = 0;
2363                 vcpu->arch.wired_tlb[i].tlb_lo[1] = 0;
2364                 vcpu->arch.wired_tlb[i].tlb_mask = 0;
2365         }
2366         vcpu->arch.wired_tlb_used = wired;
2367 }
2368
2369 static void kvm_vz_vcpu_load_wired(struct kvm_vcpu *vcpu)
2370 {
2371         /* Load wired entries into the guest TLB */
2372         if (vcpu->arch.wired_tlb)
2373                 kvm_vz_load_guesttlb(vcpu->arch.wired_tlb, 0,
2374                                      vcpu->arch.wired_tlb_used);
2375 }
2376
2377 static void kvm_vz_vcpu_load_tlb(struct kvm_vcpu *vcpu, int cpu)
2378 {
2379         struct kvm *kvm = vcpu->kvm;
2380         struct mm_struct *gpa_mm = &kvm->arch.gpa_mm;
2381         bool migrated;
2382
2383         /*
2384          * Are we entering guest context on a different CPU to last time?
2385          * If so, the VCPU's guest TLB state on this CPU may be stale.
2386          */
2387         migrated = (vcpu->arch.last_exec_cpu != cpu);
2388         vcpu->arch.last_exec_cpu = cpu;
2389
2390         /*
2391          * A vcpu's GuestID is set in GuestCtl1.ID when the vcpu is loaded and
2392          * remains set until another vcpu is loaded in.  As a rule GuestRID
2393          * remains zeroed when in root context unless the kernel is busy
2394          * manipulating guest tlb entries.
2395          */
2396         if (cpu_has_guestid) {
2397                 /*
2398                  * Check if our GuestID is of an older version and thus invalid.
2399                  *
2400                  * We also discard the stored GuestID if we've executed on
2401                  * another CPU, as the guest mappings may have changed without
2402                  * hypervisor knowledge.
2403                  */
2404                 if (migrated ||
2405                     (vcpu->arch.vzguestid[cpu] ^ guestid_cache(cpu)) &
2406                                         GUESTID_VERSION_MASK) {
2407                         kvm_vz_get_new_guestid(cpu, vcpu);
2408                         vcpu->arch.vzguestid[cpu] = guestid_cache(cpu);
2409                         trace_kvm_guestid_change(vcpu,
2410                                                  vcpu->arch.vzguestid[cpu]);
2411                 }
2412
2413                 /* Restore GuestID */
2414                 change_c0_guestctl1(GUESTID_MASK, vcpu->arch.vzguestid[cpu]);
2415         } else {
2416                 /*
2417                  * The Guest TLB only stores a single guest's TLB state, so
2418                  * flush it if another VCPU has executed on this CPU.
2419                  *
2420                  * We also flush if we've executed on another CPU, as the guest
2421                  * mappings may have changed without hypervisor knowledge.
2422                  */
2423                 if (migrated || last_exec_vcpu[cpu] != vcpu)
2424                         kvm_vz_local_flush_guesttlb_all();
2425                 last_exec_vcpu[cpu] = vcpu;
2426
2427                 /*
2428                  * Root ASID dealiases guest GPA mappings in the root TLB.
2429                  * Allocate new root ASID if needed.
2430                  */
2431                 if (cpumask_test_and_clear_cpu(cpu, &kvm->arch.asid_flush_mask)
2432                     || (cpu_context(cpu, gpa_mm) ^ asid_cache(cpu)) &
2433                                                 asid_version_mask(cpu))
2434                         get_new_mmu_context(gpa_mm, cpu);
2435         }
2436 }
2437
2438 static int kvm_vz_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2439 {
2440         struct mips_coproc *cop0 = vcpu->arch.cop0;
2441         bool migrated, all;
2442
2443         /*
2444          * Have we migrated to a different CPU?
2445          * If so, any old guest TLB state may be stale.
2446          */
2447         migrated = (vcpu->arch.last_sched_cpu != cpu);
2448
2449         /*
2450          * Was this the last VCPU to run on this CPU?
2451          * If not, any old guest state from this VCPU will have been clobbered.
2452          */
2453         all = migrated || (last_vcpu[cpu] != vcpu);
2454         last_vcpu[cpu] = vcpu;
2455
2456         /*
2457          * Restore CP0_Wired unconditionally as we clear it after use, and
2458          * restore wired guest TLB entries (while in guest context).
2459          */
2460         kvm_restore_gc0_wired(cop0);
2461         if (current->flags & PF_VCPU) {
2462                 tlbw_use_hazard();
2463                 kvm_vz_vcpu_load_tlb(vcpu, cpu);
2464                 kvm_vz_vcpu_load_wired(vcpu);
2465         }
2466
2467         /*
2468          * Restore timer state regardless, as e.g. Cause.TI can change over time
2469          * if left unmaintained.
2470          */
2471         kvm_vz_restore_timer(vcpu);
2472
2473         /* Set MC bit if we want to trace guest mode changes */
2474         if (kvm_trace_guest_mode_change)
2475                 set_c0_guestctl0(MIPS_GCTL0_MC);
2476         else
2477                 clear_c0_guestctl0(MIPS_GCTL0_MC);
2478
2479         /* Don't bother restoring registers multiple times unless necessary */
2480         if (!all)
2481                 return 0;
2482
2483         /*
2484          * Restore config registers first, as some implementations restrict
2485          * writes to other registers when the corresponding feature bits aren't
2486          * set. For example Status.CU1 cannot be set unless Config1.FP is set.
2487          */
2488         kvm_restore_gc0_config(cop0);
2489         if (cpu_guest_has_conf1)
2490                 kvm_restore_gc0_config1(cop0);
2491         if (cpu_guest_has_conf2)
2492                 kvm_restore_gc0_config2(cop0);
2493         if (cpu_guest_has_conf3)
2494                 kvm_restore_gc0_config3(cop0);
2495         if (cpu_guest_has_conf4)
2496                 kvm_restore_gc0_config4(cop0);
2497         if (cpu_guest_has_conf5)
2498                 kvm_restore_gc0_config5(cop0);
2499         if (cpu_guest_has_conf6)
2500                 kvm_restore_gc0_config6(cop0);
2501         if (cpu_guest_has_conf7)
2502                 kvm_restore_gc0_config7(cop0);
2503
2504         kvm_restore_gc0_index(cop0);
2505         kvm_restore_gc0_entrylo0(cop0);
2506         kvm_restore_gc0_entrylo1(cop0);
2507         kvm_restore_gc0_context(cop0);
2508         if (cpu_guest_has_contextconfig)
2509                 kvm_restore_gc0_contextconfig(cop0);
2510 #ifdef CONFIG_64BIT
2511         kvm_restore_gc0_xcontext(cop0);
2512         if (cpu_guest_has_contextconfig)
2513                 kvm_restore_gc0_xcontextconfig(cop0);
2514 #endif
2515         kvm_restore_gc0_pagemask(cop0);
2516         kvm_restore_gc0_pagegrain(cop0);
2517         kvm_restore_gc0_hwrena(cop0);
2518         kvm_restore_gc0_badvaddr(cop0);
2519         kvm_restore_gc0_entryhi(cop0);
2520         kvm_restore_gc0_status(cop0);
2521         kvm_restore_gc0_intctl(cop0);
2522         kvm_restore_gc0_epc(cop0);
2523         kvm_vz_write_gc0_ebase(kvm_read_sw_gc0_ebase(cop0));
2524         if (cpu_guest_has_userlocal)
2525                 kvm_restore_gc0_userlocal(cop0);
2526
2527         kvm_restore_gc0_errorepc(cop0);
2528
2529         /* restore KScratch registers if enabled in guest */
2530         if (cpu_guest_has_conf4) {
2531                 if (cpu_guest_has_kscr(2))
2532                         kvm_restore_gc0_kscratch1(cop0);
2533                 if (cpu_guest_has_kscr(3))
2534                         kvm_restore_gc0_kscratch2(cop0);
2535                 if (cpu_guest_has_kscr(4))
2536                         kvm_restore_gc0_kscratch3(cop0);
2537                 if (cpu_guest_has_kscr(5))
2538                         kvm_restore_gc0_kscratch4(cop0);
2539                 if (cpu_guest_has_kscr(6))
2540                         kvm_restore_gc0_kscratch5(cop0);
2541                 if (cpu_guest_has_kscr(7))
2542                         kvm_restore_gc0_kscratch6(cop0);
2543         }
2544
2545         if (cpu_guest_has_badinstr)
2546                 kvm_restore_gc0_badinstr(cop0);
2547         if (cpu_guest_has_badinstrp)
2548                 kvm_restore_gc0_badinstrp(cop0);
2549
2550         if (cpu_guest_has_segments) {
2551                 kvm_restore_gc0_segctl0(cop0);
2552                 kvm_restore_gc0_segctl1(cop0);
2553                 kvm_restore_gc0_segctl2(cop0);
2554         }
2555
2556         /* restore HTW registers */
2557         if (cpu_guest_has_htw) {
2558                 kvm_restore_gc0_pwbase(cop0);
2559                 kvm_restore_gc0_pwfield(cop0);
2560                 kvm_restore_gc0_pwsize(cop0);
2561                 kvm_restore_gc0_pwctl(cop0);
2562         }
2563
2564         /* restore Root.GuestCtl2 from unused Guest guestctl2 register */
2565         if (cpu_has_guestctl2)
2566                 write_c0_guestctl2(
2567                         cop0->reg[MIPS_CP0_GUESTCTL2][MIPS_CP0_GUESTCTL2_SEL]);
2568
2569         /*
2570          * We should clear linked load bit to break interrupted atomics. This
2571          * prevents a SC on the next VCPU from succeeding by matching a LL on
2572          * the previous VCPU.
2573          */
2574         if (cpu_guest_has_rw_llb)
2575                 write_gc0_lladdr(0);
2576
2577         return 0;
2578 }
2579
2580 static int kvm_vz_vcpu_put(struct kvm_vcpu *vcpu, int cpu)
2581 {
2582         struct mips_coproc *cop0 = vcpu->arch.cop0;
2583
2584         if (current->flags & PF_VCPU)
2585                 kvm_vz_vcpu_save_wired(vcpu);
2586
2587         kvm_lose_fpu(vcpu);
2588
2589         kvm_save_gc0_index(cop0);
2590         kvm_save_gc0_entrylo0(cop0);
2591         kvm_save_gc0_entrylo1(cop0);
2592         kvm_save_gc0_context(cop0);
2593         if (cpu_guest_has_contextconfig)
2594                 kvm_save_gc0_contextconfig(cop0);
2595 #ifdef CONFIG_64BIT
2596         kvm_save_gc0_xcontext(cop0);
2597         if (cpu_guest_has_contextconfig)
2598                 kvm_save_gc0_xcontextconfig(cop0);
2599 #endif
2600         kvm_save_gc0_pagemask(cop0);
2601         kvm_save_gc0_pagegrain(cop0);
2602         kvm_save_gc0_wired(cop0);
2603         /* allow wired TLB entries to be overwritten */
2604         clear_gc0_wired(MIPSR6_WIRED_WIRED);
2605         kvm_save_gc0_hwrena(cop0);
2606         kvm_save_gc0_badvaddr(cop0);
2607         kvm_save_gc0_entryhi(cop0);
2608         kvm_save_gc0_status(cop0);
2609         kvm_save_gc0_intctl(cop0);
2610         kvm_save_gc0_epc(cop0);
2611         kvm_write_sw_gc0_ebase(cop0, kvm_vz_read_gc0_ebase());
2612         if (cpu_guest_has_userlocal)
2613                 kvm_save_gc0_userlocal(cop0);
2614
2615         /* only save implemented config registers */
2616         kvm_save_gc0_config(cop0);
2617         if (cpu_guest_has_conf1)
2618                 kvm_save_gc0_config1(cop0);
2619         if (cpu_guest_has_conf2)
2620                 kvm_save_gc0_config2(cop0);
2621         if (cpu_guest_has_conf3)
2622                 kvm_save_gc0_config3(cop0);
2623         if (cpu_guest_has_conf4)
2624                 kvm_save_gc0_config4(cop0);
2625         if (cpu_guest_has_conf5)
2626                 kvm_save_gc0_config5(cop0);
2627         if (cpu_guest_has_conf6)
2628                 kvm_save_gc0_config6(cop0);
2629         if (cpu_guest_has_conf7)
2630                 kvm_save_gc0_config7(cop0);
2631
2632         kvm_save_gc0_errorepc(cop0);
2633
2634         /* save KScratch registers if enabled in guest */
2635         if (cpu_guest_has_conf4) {
2636                 if (cpu_guest_has_kscr(2))
2637                         kvm_save_gc0_kscratch1(cop0);
2638                 if (cpu_guest_has_kscr(3))
2639                         kvm_save_gc0_kscratch2(cop0);
2640                 if (cpu_guest_has_kscr(4))
2641                         kvm_save_gc0_kscratch3(cop0);
2642                 if (cpu_guest_has_kscr(5))
2643                         kvm_save_gc0_kscratch4(cop0);
2644                 if (cpu_guest_has_kscr(6))
2645                         kvm_save_gc0_kscratch5(cop0);
2646                 if (cpu_guest_has_kscr(7))
2647                         kvm_save_gc0_kscratch6(cop0);
2648         }
2649
2650         if (cpu_guest_has_badinstr)
2651                 kvm_save_gc0_badinstr(cop0);
2652         if (cpu_guest_has_badinstrp)
2653                 kvm_save_gc0_badinstrp(cop0);
2654
2655         if (cpu_guest_has_segments) {
2656                 kvm_save_gc0_segctl0(cop0);
2657                 kvm_save_gc0_segctl1(cop0);
2658                 kvm_save_gc0_segctl2(cop0);
2659         }
2660
2661         /* save HTW registers if enabled in guest */
2662         if (cpu_guest_has_htw &&
2663             kvm_read_sw_gc0_config3(cop0) & MIPS_CONF3_PW) {
2664                 kvm_save_gc0_pwbase(cop0);
2665                 kvm_save_gc0_pwfield(cop0);
2666                 kvm_save_gc0_pwsize(cop0);
2667                 kvm_save_gc0_pwctl(cop0);
2668         }
2669
2670         kvm_vz_save_timer(vcpu);
2671
2672         /* save Root.GuestCtl2 in unused Guest guestctl2 register */
2673         if (cpu_has_guestctl2)
2674                 cop0->reg[MIPS_CP0_GUESTCTL2][MIPS_CP0_GUESTCTL2_SEL] =
2675                         read_c0_guestctl2();
2676
2677         return 0;
2678 }
2679
2680 /**
2681  * kvm_vz_resize_guest_vtlb() - Attempt to resize guest VTLB.
2682  * @size:       Number of guest VTLB entries (0 < @size <= root VTLB entries).
2683  *
2684  * Attempt to resize the guest VTLB by writing guest Config registers. This is
2685  * necessary for cores with a shared root/guest TLB to avoid overlap with wired
2686  * entries in the root VTLB.
2687  *
2688  * Returns:     The resulting guest VTLB size.
2689  */
2690 static unsigned int kvm_vz_resize_guest_vtlb(unsigned int size)
2691 {
2692         unsigned int config4 = 0, ret = 0, limit;
2693
2694         /* Write MMUSize - 1 into guest Config registers */
2695         if (cpu_guest_has_conf1)
2696                 change_gc0_config1(MIPS_CONF1_TLBS,
2697                                    (size - 1) << MIPS_CONF1_TLBS_SHIFT);
2698         if (cpu_guest_has_conf4) {
2699                 config4 = read_gc0_config4();
2700                 if (cpu_has_mips_r6 || (config4 & MIPS_CONF4_MMUEXTDEF) ==
2701                     MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT) {
2702                         config4 &= ~MIPS_CONF4_VTLBSIZEEXT;
2703                         config4 |= ((size - 1) >> MIPS_CONF1_TLBS_SIZE) <<
2704                                 MIPS_CONF4_VTLBSIZEEXT_SHIFT;
2705                 } else if ((config4 & MIPS_CONF4_MMUEXTDEF) ==
2706                            MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT) {
2707                         config4 &= ~MIPS_CONF4_MMUSIZEEXT;
2708                         config4 |= ((size - 1) >> MIPS_CONF1_TLBS_SIZE) <<
2709                                 MIPS_CONF4_MMUSIZEEXT_SHIFT;
2710                 }
2711                 write_gc0_config4(config4);
2712         }
2713
2714         /*
2715          * Set Guest.Wired.Limit = 0 (no limit up to Guest.MMUSize-1), unless it
2716          * would exceed Root.Wired.Limit (clearing Guest.Wired.Wired so write
2717          * not dropped)
2718          */
2719         if (cpu_has_mips_r6) {
2720                 limit = (read_c0_wired() & MIPSR6_WIRED_LIMIT) >>
2721                                                 MIPSR6_WIRED_LIMIT_SHIFT;
2722                 if (size - 1 <= limit)
2723                         limit = 0;
2724                 write_gc0_wired(limit << MIPSR6_WIRED_LIMIT_SHIFT);
2725         }
2726
2727         /* Read back MMUSize - 1 */
2728         back_to_back_c0_hazard();
2729         if (cpu_guest_has_conf1)
2730                 ret = (read_gc0_config1() & MIPS_CONF1_TLBS) >>
2731                                                 MIPS_CONF1_TLBS_SHIFT;
2732         if (config4) {
2733                 if (cpu_has_mips_r6 || (config4 & MIPS_CONF4_MMUEXTDEF) ==
2734                     MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT)
2735                         ret |= ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
2736                                 MIPS_CONF4_VTLBSIZEEXT_SHIFT) <<
2737                                 MIPS_CONF1_TLBS_SIZE;
2738                 else if ((config4 & MIPS_CONF4_MMUEXTDEF) ==
2739                          MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT)
2740                         ret |= ((config4 & MIPS_CONF4_MMUSIZEEXT) >>
2741                                 MIPS_CONF4_MMUSIZEEXT_SHIFT) <<
2742                                 MIPS_CONF1_TLBS_SIZE;
2743         }
2744         return ret + 1;
2745 }
2746
2747 static int kvm_vz_hardware_enable(void)
2748 {
2749         unsigned int mmu_size, guest_mmu_size, ftlb_size;
2750         u64 guest_cvmctl, cvmvmconfig;
2751
2752         switch (current_cpu_type()) {
2753         case CPU_CAVIUM_OCTEON3:
2754                 /* Set up guest timer/perfcount IRQ lines */
2755                 guest_cvmctl = read_gc0_cvmctl();
2756                 guest_cvmctl &= ~CVMCTL_IPTI;
2757                 guest_cvmctl |= 7ull << CVMCTL_IPTI_SHIFT;
2758                 guest_cvmctl &= ~CVMCTL_IPPCI;
2759                 guest_cvmctl |= 6ull << CVMCTL_IPPCI_SHIFT;
2760                 write_gc0_cvmctl(guest_cvmctl);
2761
2762                 cvmvmconfig = read_c0_cvmvmconfig();
2763                 /* No I/O hole translation. */
2764                 cvmvmconfig |= CVMVMCONF_DGHT;
2765                 /* Halve the root MMU size */
2766                 mmu_size = ((cvmvmconfig & CVMVMCONF_MMUSIZEM1)
2767                             >> CVMVMCONF_MMUSIZEM1_S) + 1;
2768                 guest_mmu_size = mmu_size / 2;
2769                 mmu_size -= guest_mmu_size;
2770                 cvmvmconfig &= ~CVMVMCONF_RMMUSIZEM1;
2771                 cvmvmconfig |= mmu_size - 1;
2772                 write_c0_cvmvmconfig(cvmvmconfig);
2773
2774                 /* Update our records */
2775                 current_cpu_data.tlbsize = mmu_size;
2776                 current_cpu_data.tlbsizevtlb = mmu_size;
2777                 current_cpu_data.guest.tlbsize = guest_mmu_size;
2778
2779                 /* Flush moved entries in new (guest) context */
2780                 kvm_vz_local_flush_guesttlb_all();
2781                 break;
2782         default:
2783                 /*
2784                  * ImgTec cores tend to use a shared root/guest TLB. To avoid
2785                  * overlap of root wired and guest entries, the guest TLB may
2786                  * need resizing.
2787                  */
2788                 mmu_size = current_cpu_data.tlbsizevtlb;
2789                 ftlb_size = current_cpu_data.tlbsize - mmu_size;
2790
2791                 /* Try switching to maximum guest VTLB size for flush */
2792                 guest_mmu_size = kvm_vz_resize_guest_vtlb(mmu_size);
2793                 current_cpu_data.guest.tlbsize = guest_mmu_size + ftlb_size;
2794                 kvm_vz_local_flush_guesttlb_all();
2795
2796                 /*
2797                  * Reduce to make space for root wired entries and at least 2
2798                  * root non-wired entries. This does assume that long-term wired
2799                  * entries won't be added later.
2800                  */
2801                 guest_mmu_size = mmu_size - num_wired_entries() - 2;
2802                 guest_mmu_size = kvm_vz_resize_guest_vtlb(guest_mmu_size);
2803                 current_cpu_data.guest.tlbsize = guest_mmu_size + ftlb_size;
2804
2805                 /*
2806                  * Write the VTLB size, but if another CPU has already written,
2807                  * check it matches or we won't provide a consistent view to the
2808                  * guest. If this ever happens it suggests an asymmetric number
2809                  * of wired entries.
2810                  */
2811                 if (cmpxchg(&kvm_vz_guest_vtlb_size, 0, guest_mmu_size) &&
2812                     WARN(guest_mmu_size != kvm_vz_guest_vtlb_size,
2813                          "Available guest VTLB size mismatch"))
2814                         return -EINVAL;
2815                 break;
2816         }
2817
2818         /*
2819          * Enable virtualization features granting guest direct control of
2820          * certain features:
2821          * CP0=1:       Guest coprocessor 0 context.
2822          * AT=Guest:    Guest MMU.
2823          * CG=1:        Hit (virtual address) CACHE operations (optional).
2824          * CF=1:        Guest Config registers.
2825          * CGI=1:       Indexed flush CACHE operations (optional).
2826          */
2827         write_c0_guestctl0(MIPS_GCTL0_CP0 |
2828                            (MIPS_GCTL0_AT_GUEST << MIPS_GCTL0_AT_SHIFT) |
2829                            MIPS_GCTL0_CG | MIPS_GCTL0_CF);
2830         if (cpu_has_guestctl0ext)
2831                 set_c0_guestctl0ext(MIPS_GCTL0EXT_CGI);
2832
2833         if (cpu_has_guestid) {
2834                 write_c0_guestctl1(0);
2835                 kvm_vz_local_flush_roottlb_all_guests();
2836
2837                 GUESTID_MASK = current_cpu_data.guestid_mask;
2838                 GUESTID_FIRST_VERSION = GUESTID_MASK + 1;
2839                 GUESTID_VERSION_MASK = ~GUESTID_MASK;
2840
2841                 current_cpu_data.guestid_cache = GUESTID_FIRST_VERSION;
2842         }
2843
2844         /* clear any pending injected virtual guest interrupts */
2845         if (cpu_has_guestctl2)
2846                 clear_c0_guestctl2(0x3f << 10);
2847
2848         return 0;
2849 }
2850
2851 static void kvm_vz_hardware_disable(void)
2852 {
2853         u64 cvmvmconfig;
2854         unsigned int mmu_size;
2855
2856         /* Flush any remaining guest TLB entries */
2857         kvm_vz_local_flush_guesttlb_all();
2858
2859         switch (current_cpu_type()) {
2860         case CPU_CAVIUM_OCTEON3:
2861                 /*
2862                  * Allocate whole TLB for root. Existing guest TLB entries will
2863                  * change ownership to the root TLB. We should be safe though as
2864                  * they've already been flushed above while in guest TLB.
2865                  */
2866                 cvmvmconfig = read_c0_cvmvmconfig();
2867                 mmu_size = ((cvmvmconfig & CVMVMCONF_MMUSIZEM1)
2868                             >> CVMVMCONF_MMUSIZEM1_S) + 1;
2869                 cvmvmconfig &= ~CVMVMCONF_RMMUSIZEM1;
2870                 cvmvmconfig |= mmu_size - 1;
2871                 write_c0_cvmvmconfig(cvmvmconfig);
2872
2873                 /* Update our records */
2874                 current_cpu_data.tlbsize = mmu_size;
2875                 current_cpu_data.tlbsizevtlb = mmu_size;
2876                 current_cpu_data.guest.tlbsize = 0;
2877
2878                 /* Flush moved entries in new (root) context */
2879                 local_flush_tlb_all();
2880                 break;
2881         }
2882
2883         if (cpu_has_guestid) {
2884                 write_c0_guestctl1(0);
2885                 kvm_vz_local_flush_roottlb_all_guests();
2886         }
2887 }
2888
2889 static int kvm_vz_check_extension(struct kvm *kvm, long ext)
2890 {
2891         int r;
2892
2893         switch (ext) {
2894         case KVM_CAP_MIPS_VZ:
2895                 /* we wouldn't be here unless cpu_has_vz */
2896                 r = 1;
2897                 break;
2898 #ifdef CONFIG_64BIT
2899         case KVM_CAP_MIPS_64BIT:
2900                 /* We support 64-bit registers/operations and addresses */
2901                 r = 2;
2902                 break;
2903 #endif
2904         default:
2905                 r = 0;
2906                 break;
2907         }
2908
2909         return r;
2910 }
2911
2912 static int kvm_vz_vcpu_init(struct kvm_vcpu *vcpu)
2913 {
2914         int i;
2915
2916         for_each_possible_cpu(i)
2917                 vcpu->arch.vzguestid[i] = 0;
2918
2919         return 0;
2920 }
2921
2922 static void kvm_vz_vcpu_uninit(struct kvm_vcpu *vcpu)
2923 {
2924         int cpu;
2925
2926         /*
2927          * If the VCPU is freed and reused as another VCPU, we don't want the
2928          * matching pointer wrongly hanging around in last_vcpu[] or
2929          * last_exec_vcpu[].
2930          */
2931         for_each_possible_cpu(cpu) {
2932                 if (last_vcpu[cpu] == vcpu)
2933                         last_vcpu[cpu] = NULL;
2934                 if (last_exec_vcpu[cpu] == vcpu)
2935                         last_exec_vcpu[cpu] = NULL;
2936         }
2937 }
2938
2939 static int kvm_vz_vcpu_setup(struct kvm_vcpu *vcpu)
2940 {
2941         struct mips_coproc *cop0 = vcpu->arch.cop0;
2942         unsigned long count_hz = 100*1000*1000; /* default to 100 MHz */
2943
2944         /*
2945          * Start off the timer at the same frequency as the host timer, but the
2946          * soft timer doesn't handle frequencies greater than 1GHz yet.
2947          */
2948         if (mips_hpt_frequency && mips_hpt_frequency <= NSEC_PER_SEC)
2949                 count_hz = mips_hpt_frequency;
2950         kvm_mips_init_count(vcpu, count_hz);
2951
2952         /*
2953          * Initialize guest register state to valid architectural reset state.
2954          */
2955
2956         /* PageGrain */
2957         if (cpu_has_mips_r6)
2958                 kvm_write_sw_gc0_pagegrain(cop0, PG_RIE | PG_XIE | PG_IEC);
2959         /* Wired */
2960         if (cpu_has_mips_r6)
2961                 kvm_write_sw_gc0_wired(cop0,
2962                                        read_gc0_wired() & MIPSR6_WIRED_LIMIT);
2963         /* Status */
2964         kvm_write_sw_gc0_status(cop0, ST0_BEV | ST0_ERL);
2965         if (cpu_has_mips_r6)
2966                 kvm_change_sw_gc0_status(cop0, ST0_FR, read_gc0_status());
2967         /* IntCtl */
2968         kvm_write_sw_gc0_intctl(cop0, read_gc0_intctl() &
2969                                 (INTCTLF_IPFDC | INTCTLF_IPPCI | INTCTLF_IPTI));
2970         /* PRId */
2971         kvm_write_sw_gc0_prid(cop0, boot_cpu_data.processor_id);
2972         /* EBase */
2973         kvm_write_sw_gc0_ebase(cop0, (s32)0x80000000 | vcpu->vcpu_id);
2974         /* Config */
2975         kvm_save_gc0_config(cop0);
2976         /* architecturally writable (e.g. from guest) */
2977         kvm_change_sw_gc0_config(cop0, CONF_CM_CMASK,
2978                                  _page_cachable_default >> _CACHE_SHIFT);
2979         /* architecturally read only, but maybe writable from root */
2980         kvm_change_sw_gc0_config(cop0, MIPS_CONF_MT, read_c0_config());
2981         if (cpu_guest_has_conf1) {
2982                 kvm_set_sw_gc0_config(cop0, MIPS_CONF_M);
2983                 /* Config1 */
2984                 kvm_save_gc0_config1(cop0);
2985                 /* architecturally read only, but maybe writable from root */
2986                 kvm_clear_sw_gc0_config1(cop0, MIPS_CONF1_C2    |
2987                                                MIPS_CONF1_MD    |
2988                                                MIPS_CONF1_PC    |
2989                                                MIPS_CONF1_WR    |
2990                                                MIPS_CONF1_CA    |
2991                                                MIPS_CONF1_FP);
2992         }
2993         if (cpu_guest_has_conf2) {
2994                 kvm_set_sw_gc0_config1(cop0, MIPS_CONF_M);
2995                 /* Config2 */
2996                 kvm_save_gc0_config2(cop0);
2997         }
2998         if (cpu_guest_has_conf3) {
2999                 kvm_set_sw_gc0_config2(cop0, MIPS_CONF_M);
3000                 /* Config3 */
3001                 kvm_save_gc0_config3(cop0);
3002                 /* architecturally writable (e.g. from guest) */
3003                 kvm_clear_sw_gc0_config3(cop0, MIPS_CONF3_ISA_OE);
3004                 /* architecturally read only, but maybe writable from root */
3005                 kvm_clear_sw_gc0_config3(cop0, MIPS_CONF3_MSA   |
3006                                                MIPS_CONF3_BPG   |
3007                                                MIPS_CONF3_ULRI  |
3008                                                MIPS_CONF3_DSP   |
3009                                                MIPS_CONF3_CTXTC |
3010                                                MIPS_CONF3_ITL   |
3011                                                MIPS_CONF3_LPA   |
3012                                                MIPS_CONF3_VEIC  |
3013                                                MIPS_CONF3_VINT  |
3014                                                MIPS_CONF3_SP    |
3015                                                MIPS_CONF3_CDMM  |
3016                                                MIPS_CONF3_MT    |
3017                                                MIPS_CONF3_SM    |
3018                                                MIPS_CONF3_TL);
3019         }
3020         if (cpu_guest_has_conf4) {
3021                 kvm_set_sw_gc0_config3(cop0, MIPS_CONF_M);
3022                 /* Config4 */
3023                 kvm_save_gc0_config4(cop0);
3024         }
3025         if (cpu_guest_has_conf5) {
3026                 kvm_set_sw_gc0_config4(cop0, MIPS_CONF_M);
3027                 /* Config5 */
3028                 kvm_save_gc0_config5(cop0);
3029                 /* architecturally writable (e.g. from guest) */
3030                 kvm_clear_sw_gc0_config5(cop0, MIPS_CONF5_K     |
3031                                                MIPS_CONF5_CV    |
3032                                                MIPS_CONF5_MSAEN |
3033                                                MIPS_CONF5_UFE   |
3034                                                MIPS_CONF5_FRE   |
3035                                                MIPS_CONF5_SBRI  |
3036                                                MIPS_CONF5_UFR);
3037                 /* architecturally read only, but maybe writable from root */
3038                 kvm_clear_sw_gc0_config5(cop0, MIPS_CONF5_MRP);
3039         }
3040
3041         if (cpu_guest_has_contextconfig) {
3042                 /* ContextConfig */
3043                 kvm_write_sw_gc0_contextconfig(cop0, 0x007ffff0);
3044 #ifdef CONFIG_64BIT
3045                 /* XContextConfig */
3046                 /* bits SEGBITS-13+3:4 set */
3047                 kvm_write_sw_gc0_xcontextconfig(cop0,
3048                                         ((1ull << (cpu_vmbits - 13)) - 1) << 4);
3049 #endif
3050         }
3051
3052         /* Implementation dependent, use the legacy layout */
3053         if (cpu_guest_has_segments) {
3054                 /* SegCtl0, SegCtl1, SegCtl2 */
3055                 kvm_write_sw_gc0_segctl0(cop0, 0x00200010);
3056                 kvm_write_sw_gc0_segctl1(cop0, 0x00000002 |
3057                                 (_page_cachable_default >> _CACHE_SHIFT) <<
3058                                                 (16 + MIPS_SEGCFG_C_SHIFT));
3059                 kvm_write_sw_gc0_segctl2(cop0, 0x00380438);
3060         }
3061
3062         /* reset HTW registers */
3063         if (cpu_guest_has_htw && cpu_has_mips_r6) {
3064                 /* PWField */
3065                 kvm_write_sw_gc0_pwfield(cop0, 0x0c30c302);
3066                 /* PWSize */
3067                 kvm_write_sw_gc0_pwsize(cop0, 1 << MIPS_PWSIZE_PTW_SHIFT);
3068         }
3069
3070         /* start with no pending virtual guest interrupts */
3071         if (cpu_has_guestctl2)
3072                 cop0->reg[MIPS_CP0_GUESTCTL2][MIPS_CP0_GUESTCTL2_SEL] = 0;
3073
3074         /* Put PC at reset vector */
3075         vcpu->arch.pc = CKSEG1ADDR(0x1fc00000);
3076
3077         return 0;
3078 }
3079
3080 static void kvm_vz_flush_shadow_all(struct kvm *kvm)
3081 {
3082         if (cpu_has_guestid) {
3083                 /* Flush GuestID for each VCPU individually */
3084                 kvm_flush_remote_tlbs(kvm);
3085         } else {
3086                 /*
3087                  * For each CPU there is a single GPA ASID used by all VCPUs in
3088                  * the VM, so it doesn't make sense for the VCPUs to handle
3089                  * invalidation of these ASIDs individually.
3090                  *
3091                  * Instead mark all CPUs as needing ASID invalidation in
3092                  * asid_flush_mask, and just use kvm_flush_remote_tlbs(kvm) to
3093                  * kick any running VCPUs so they check asid_flush_mask.
3094                  */
3095                 cpumask_setall(&kvm->arch.asid_flush_mask);
3096                 kvm_flush_remote_tlbs(kvm);
3097         }
3098 }
3099
3100 static void kvm_vz_flush_shadow_memslot(struct kvm *kvm,
3101                                         const struct kvm_memory_slot *slot)
3102 {
3103         kvm_vz_flush_shadow_all(kvm);
3104 }
3105
3106 static void kvm_vz_vcpu_reenter(struct kvm_run *run, struct kvm_vcpu *vcpu)
3107 {
3108         int cpu = smp_processor_id();
3109         int preserve_guest_tlb;
3110
3111         preserve_guest_tlb = kvm_vz_check_requests(vcpu, cpu);
3112
3113         if (preserve_guest_tlb)
3114                 kvm_vz_vcpu_save_wired(vcpu);
3115
3116         kvm_vz_vcpu_load_tlb(vcpu, cpu);
3117
3118         if (preserve_guest_tlb)
3119                 kvm_vz_vcpu_load_wired(vcpu);
3120 }
3121
3122 static int kvm_vz_vcpu_run(struct kvm_run *run, struct kvm_vcpu *vcpu)
3123 {
3124         int cpu = smp_processor_id();
3125         int r;
3126
3127         kvm_vz_acquire_htimer(vcpu);
3128         /* Check if we have any exceptions/interrupts pending */
3129         kvm_mips_deliver_interrupts(vcpu, read_gc0_cause());
3130
3131         kvm_vz_check_requests(vcpu, cpu);
3132         kvm_vz_vcpu_load_tlb(vcpu, cpu);
3133         kvm_vz_vcpu_load_wired(vcpu);
3134
3135         r = vcpu->arch.vcpu_run(run, vcpu);
3136
3137         kvm_vz_vcpu_save_wired(vcpu);
3138
3139         return r;
3140 }
3141
3142 static struct kvm_mips_callbacks kvm_vz_callbacks = {
3143         .handle_cop_unusable = kvm_trap_vz_handle_cop_unusable,
3144         .handle_tlb_mod = kvm_trap_vz_handle_tlb_st_miss,
3145         .handle_tlb_ld_miss = kvm_trap_vz_handle_tlb_ld_miss,
3146         .handle_tlb_st_miss = kvm_trap_vz_handle_tlb_st_miss,
3147         .handle_addr_err_st = kvm_trap_vz_no_handler,
3148         .handle_addr_err_ld = kvm_trap_vz_no_handler,
3149         .handle_syscall = kvm_trap_vz_no_handler,
3150         .handle_res_inst = kvm_trap_vz_no_handler,
3151         .handle_break = kvm_trap_vz_no_handler,
3152         .handle_msa_disabled = kvm_trap_vz_handle_msa_disabled,
3153         .handle_guest_exit = kvm_trap_vz_handle_guest_exit,
3154
3155         .hardware_enable = kvm_vz_hardware_enable,
3156         .hardware_disable = kvm_vz_hardware_disable,
3157         .check_extension = kvm_vz_check_extension,
3158         .vcpu_init = kvm_vz_vcpu_init,
3159         .vcpu_uninit = kvm_vz_vcpu_uninit,
3160         .vcpu_setup = kvm_vz_vcpu_setup,
3161         .flush_shadow_all = kvm_vz_flush_shadow_all,
3162         .flush_shadow_memslot = kvm_vz_flush_shadow_memslot,
3163         .gva_to_gpa = kvm_vz_gva_to_gpa_cb,
3164         .queue_timer_int = kvm_vz_queue_timer_int_cb,
3165         .dequeue_timer_int = kvm_vz_dequeue_timer_int_cb,
3166         .queue_io_int = kvm_vz_queue_io_int_cb,
3167         .dequeue_io_int = kvm_vz_dequeue_io_int_cb,
3168         .irq_deliver = kvm_vz_irq_deliver_cb,
3169         .irq_clear = kvm_vz_irq_clear_cb,
3170         .num_regs = kvm_vz_num_regs,
3171         .copy_reg_indices = kvm_vz_copy_reg_indices,
3172         .get_one_reg = kvm_vz_get_one_reg,
3173         .set_one_reg = kvm_vz_set_one_reg,
3174         .vcpu_load = kvm_vz_vcpu_load,
3175         .vcpu_put = kvm_vz_vcpu_put,
3176         .vcpu_run = kvm_vz_vcpu_run,
3177         .vcpu_reenter = kvm_vz_vcpu_reenter,
3178 };
3179
3180 int kvm_mips_emulation_init(struct kvm_mips_callbacks **install_callbacks)
3181 {
3182         if (!cpu_has_vz)
3183                 return -ENODEV;
3184
3185         /*
3186          * VZ requires at least 2 KScratch registers, so it should have been
3187          * possible to allocate pgd_reg.
3188          */
3189         if (WARN(pgd_reg == -1,
3190                  "pgd_reg not allocated even though cpu_has_vz\n"))
3191                 return -ENODEV;
3192
3193         pr_info("Starting KVM with MIPS VZ extensions\n");
3194
3195         *install_callbacks = &kvm_vz_callbacks;
3196         return 0;
3197 }