arch/mips/kvm/mips.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * KVM/MIPS: MIPS specific KVM APIs
   7  *
   8  * Copyright (C) 2012  MIPS Technologies, Inc.  All rights reserved.
   9  * Authors: Sanjay Lal <sanjayl@kymasys.com>
  10  */
  11
  12 #include <linux/bitops.h>
  13 #include <linux/errno.h>
  14 #include <linux/err.h>
  15 #include <linux/kdebug.h>
  16 #include <linux/module.h>
  17 #include <linux/uaccess.h>
  18 #include <linux/vmalloc.h>
  19 #include <linux/sched/signal.h>
  20 #include <linux/fs.h>
  21 #include <linux/bootmem.h>
  22
  23 #include <asm/fpu.h>
  24 #include <asm/page.h>
  25 #include <asm/cacheflush.h>
  26 #include <asm/mmu_context.h>
  27 #include <asm/pgalloc.h>
  28 #include <asm/pgtable.h>
  29
  30 #include <linux/kvm_host.h>
  31
  32 #include "interrupt.h"
  33 #include "commpage.h"
  34
  35 #define CREATE_TRACE_POINTS
  36 #include "trace.h"
  37
  38 #ifndef VECTORSPACING
  39 #define VECTORSPACING 0x100     /* for EI/VI mode */
  40 #endif
  41
  42 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x)
  43 struct kvm_stats_debugfs_item debugfs_entries[] = {
  44         { "wait",         VCPU_STAT(wait_exits),         KVM_STAT_VCPU },
  45         { "cache",        VCPU_STAT(cache_exits),        KVM_STAT_VCPU },
  46         { "signal",       VCPU_STAT(signal_exits),       KVM_STAT_VCPU },
  47         { "interrupt",    VCPU_STAT(int_exits),          KVM_STAT_VCPU },
  48         { "cop_unsuable", VCPU_STAT(cop_unusable_exits), KVM_STAT_VCPU },
  49         { "tlbmod",       VCPU_STAT(tlbmod_exits),       KVM_STAT_VCPU },
  50         { "tlbmiss_ld",   VCPU_STAT(tlbmiss_ld_exits),   KVM_STAT_VCPU },
  51         { "tlbmiss_st",   VCPU_STAT(tlbmiss_st_exits),   KVM_STAT_VCPU },
  52         { "addrerr_st",   VCPU_STAT(addrerr_st_exits),   KVM_STAT_VCPU },
  53         { "addrerr_ld",   VCPU_STAT(addrerr_ld_exits),   KVM_STAT_VCPU },
  54         { "syscall",      VCPU_STAT(syscall_exits),      KVM_STAT_VCPU },
  55         { "resvd_inst",   VCPU_STAT(resvd_inst_exits),   KVM_STAT_VCPU },
  56         { "break_inst",   VCPU_STAT(break_inst_exits),   KVM_STAT_VCPU },
  57         { "trap_inst",    VCPU_STAT(trap_inst_exits),    KVM_STAT_VCPU },
  58         { "msa_fpe",      VCPU_STAT(msa_fpe_exits),      KVM_STAT_VCPU },
  59         { "fpe",          VCPU_STAT(fpe_exits),          KVM_STAT_VCPU },
  60         { "msa_disabled", VCPU_STAT(msa_disabled_exits), KVM_STAT_VCPU },
  61         { "flush_dcache", VCPU_STAT(flush_dcache_exits), KVM_STAT_VCPU },
  62 #ifdef CONFIG_KVM_MIPS_VZ
  63         { "vz_gpsi",      VCPU_STAT(vz_gpsi_exits),      KVM_STAT_VCPU },
  64         { "vz_gsfc",      VCPU_STAT(vz_gsfc_exits),      KVM_STAT_VCPU },
  65         { "vz_hc",        VCPU_STAT(vz_hc_exits),        KVM_STAT_VCPU },
  66         { "vz_grr",       VCPU_STAT(vz_grr_exits),       KVM_STAT_VCPU },
  67         { "vz_gva",       VCPU_STAT(vz_gva_exits),       KVM_STAT_VCPU },
  68         { "vz_ghfc",      VCPU_STAT(vz_ghfc_exits),      KVM_STAT_VCPU },
  69         { "vz_gpa",       VCPU_STAT(vz_gpa_exits),       KVM_STAT_VCPU },
  70         { "vz_resvd",     VCPU_STAT(vz_resvd_exits),     KVM_STAT_VCPU },
  71 #endif
  72         { "halt_successful_poll", VCPU_STAT(halt_successful_poll), KVM_STAT_VCPU },
  73         { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll), KVM_STAT_VCPU },
  74         { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid), KVM_STAT_VCPU },
  75         { "halt_wakeup",  VCPU_STAT(halt_wakeup),        KVM_STAT_VCPU },
  76         {NULL}
  77 };
  78
  79 /*
  80  * XXXKYMA: We are simulatoring a processor that has the WII bit set in
  81  * Config7, so we are "runnable" if interrupts are pending
  82  */
  83 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
  84 {
  85         return !!(vcpu->arch.pending_exceptions);
  86 }
  87
  88 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
  89 {
  90         return 1;
  91 }
  92
  93 int kvm_arch_hardware_enable(void)
  94 {
  95         return kvm_mips_callbacks->hardware_enable();
  96 }
  97
  98 void kvm_arch_hardware_disable(void)
  99 {
 100         kvm_mips_callbacks->hardware_disable();
 101 }
 102
 103 int kvm_arch_hardware_setup(void)
 104 {
 105         return 0;
 106 }
 107
 108 void kvm_arch_check_processor_compat(void *rtn)
 109 {
 110         *(int *)rtn = 0;
 111 }
 112
 113 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
 114 {
 115         switch (type) {
 116 #ifdef CONFIG_KVM_MIPS_VZ
 117         case KVM_VM_MIPS_VZ:
 118 #else
 119         case KVM_VM_MIPS_TE:
 120 #endif
 121                 break;
 122         default:
 123                 /* Unsupported KVM type */
 124                 return -EINVAL;
 125         };
 126
 127         /* Allocate page table to map GPA -> RPA */
 128         kvm->arch.gpa_mm.pgd = kvm_pgd_alloc();
 129         if (!kvm->arch.gpa_mm.pgd)
 130                 return -ENOMEM;
 131
 132         return 0;
 133 }
 134
 135 bool kvm_arch_has_vcpu_debugfs(void)
 136 {
 137         return false;
 138 }
 139
 140 int kvm_arch_create_vcpu_debugfs(struct kvm_vcpu *vcpu)
 141 {
 142         return 0;
 143 }
 144
 145 void kvm_mips_free_vcpus(struct kvm *kvm)
 146 {
 147         unsigned int i;
 148         struct kvm_vcpu *vcpu;
 149
 150         kvm_for_each_vcpu(i, vcpu, kvm) {
 151                 kvm_arch_vcpu_free(vcpu);
 152         }
 153
 154         mutex_lock(&kvm->lock);
 155
 156         for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
 157                 kvm->vcpus[i] = NULL;
 158
 159         atomic_set(&kvm->online_vcpus, 0);
 160
 161         mutex_unlock(&kvm->lock);
 162 }
 163
 164 static void kvm_mips_free_gpa_pt(struct kvm *kvm)
 165 {
 166         /* It should always be safe to remove after flushing the whole range */
 167         WARN_ON(!kvm_mips_flush_gpa_pt(kvm, 0, ~0));
 168         pgd_free(NULL, kvm->arch.gpa_mm.pgd);
 169 }
 170
 171 void kvm_arch_destroy_vm(struct kvm *kvm)
 172 {
 173         kvm_mips_free_vcpus(kvm);
 174         kvm_mips_free_gpa_pt(kvm);
 175 }
 176
 177 long kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl,
 178                         unsigned long arg)
 179 {
 180         return -ENOIOCTLCMD;
 181 }
 182
 183 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
 184                             unsigned long npages)
 185 {
 186         return 0;
 187 }
 188
 189 void kvm_arch_flush_shadow_all(struct kvm *kvm)
 190 {
 191         /* Flush whole GPA */
 192         kvm_mips_flush_gpa_pt(kvm, 0, ~0);
 193
 194         /* Let implementation do the rest */
 195         kvm_mips_callbacks->flush_shadow_all(kvm);
 196 }
 197
 198 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
 199                                    struct kvm_memory_slot *slot)
 200 {
 201         /*
 202          * The slot has been made invalid (ready for moving or deletion), so we
 203          * need to ensure that it can no longer be accessed by any guest VCPUs.
 204          */
 205
 206         spin_lock(&kvm->mmu_lock);
 207         /* Flush slot from GPA */
 208         kvm_mips_flush_gpa_pt(kvm, slot->base_gfn,
 209                               slot->base_gfn + slot->npages - 1);
 210         /* Let implementation do the rest */
 211         kvm_mips_callbacks->flush_shadow_memslot(kvm, slot);
 212         spin_unlock(&kvm->mmu_lock);
 213 }
 214
 215 int kvm_arch_prepare_memory_region(struct kvm *kvm,
 216                                    struct kvm_memory_slot *memslot,
 217                                    const struct kvm_userspace_memory_region *mem,
 218                                    enum kvm_mr_change change)
 219 {
 220         return 0;
 221 }
 222
 223 void kvm_arch_commit_memory_region(struct kvm *kvm,
 224                                    const struct kvm_userspace_memory_region *mem,
 225                                    const struct kvm_memory_slot *old,
 226                                    const struct kvm_memory_slot *new,
 227                                    enum kvm_mr_change change)
 228 {
 229         int needs_flush;
 230
 231         kvm_debug("%s: kvm: %p slot: %d, GPA: %llx, size: %llx, QVA: %llx\n",
 232                   __func__, kvm, mem->slot, mem->guest_phys_addr,
 233                   mem->memory_size, mem->userspace_addr);
 234
 235         /*
 236          * If dirty page logging is enabled, write protect all pages in the slot
 237          * ready for dirty logging.
 238          *
 239          * There is no need to do this in any of the following cases:
 240          * CREATE:      No dirty mappings will already exist.
 241          * MOVE/DELETE: The old mappings will already have been cleaned up by
 242          *              kvm_arch_flush_shadow_memslot()
 243          */
 244         if (change == KVM_MR_FLAGS_ONLY &&
 245             (!(old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
 246              new->flags & KVM_MEM_LOG_DIRTY_PAGES)) {
 247                 spin_lock(&kvm->mmu_lock);
 248                 /* Write protect GPA page table entries */
 249                 needs_flush = kvm_mips_mkclean_gpa_pt(kvm, new->base_gfn,
 250                                         new->base_gfn + new->npages - 1);
 251                 /* Let implementation do the rest */
 252                 if (needs_flush)
 253                         kvm_mips_callbacks->flush_shadow_memslot(kvm, new);
 254                 spin_unlock(&kvm->mmu_lock);
 255         }
 256 }
 257
 258 static inline void dump_handler(const char *symbol, void *start, void *end)
 259 {
 260         u32 *p;
 261
 262         pr_debug("LEAF(%s)\n", symbol);
 263
 264         pr_debug("\t.set push\n");
 265         pr_debug("\t.set noreorder\n");
 266
 267         for (p = start; p < (u32 *)end; ++p)
 268                 pr_debug("\t.word\t0x%08x\t\t# %p\n", *p, p);
 269
 270         pr_debug("\t.set\tpop\n");
 271
 272         pr_debug("\tEND(%s)\n", symbol);
 273 }
 274
 275 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, unsigned int id)
 276 {
 277         int err, size;
 278         void *gebase, *p, *handler, *refill_start, *refill_end;
 279         int i;
 280
 281         struct kvm_vcpu *vcpu = kzalloc(sizeof(struct kvm_vcpu), GFP_KERNEL);
 282
 283         if (!vcpu) {
 284                 err = -ENOMEM;
 285                 goto out;
 286         }
 287
 288         err = kvm_vcpu_init(vcpu, kvm, id);
 289
 290         if (err)
 291                 goto out_free_cpu;
 292
 293         kvm_debug("kvm @ %p: create cpu %d at %p\n", kvm, id, vcpu);
 294
 295         /*
 296          * Allocate space for host mode exception handlers that handle
 297          * guest mode exits
 298          */
 299         if (cpu_has_veic || cpu_has_vint)
 300                 size = 0x200 + VECTORSPACING * 64;
 301         else
 302                 size = 0x4000;
 303
 304         gebase = kzalloc(ALIGN(size, PAGE_SIZE), GFP_KERNEL);
 305
 306         if (!gebase) {
 307                 err = -ENOMEM;
 308                 goto out_uninit_cpu;
 309         }
 310         kvm_debug("Allocated %d bytes for KVM Exception Handlers @ %p\n",
 311                   ALIGN(size, PAGE_SIZE), gebase);
 312
 313         /*
 314          * Check new ebase actually fits in CP0_EBase. The lack of a write gate
 315          * limits us to the low 512MB of physical address space. If the memory
 316          * we allocate is out of range, just give up now.
 317          */
 318         if (!cpu_has_ebase_wg && virt_to_phys(gebase) >= 0x20000000) {
 319                 kvm_err("CP0_EBase.WG required for guest exception base %pK\n",
 320                         gebase);
 321                 err = -ENOMEM;
 322                 goto out_free_gebase;
 323         }
 324
 325         /* Save new ebase */
 326         vcpu->arch.guest_ebase = gebase;
 327
 328         /* Build guest exception vectors dynamically in unmapped memory */
 329         handler = gebase + 0x2000;
 330
 331         /* TLB refill (or XTLB refill on 64-bit VZ where KX=1) */
 332         refill_start = gebase;
 333         if (IS_ENABLED(CONFIG_KVM_MIPS_VZ) && IS_ENABLED(CONFIG_64BIT))
 334                 refill_start += 0x080;
 335         refill_end = kvm_mips_build_tlb_refill_exception(refill_start, handler);
 336
 337         /* General Exception Entry point */
 338         kvm_mips_build_exception(gebase + 0x180, handler);
 339
 340         /* For vectored interrupts poke the exception code @ all offsets 0-7 */
 341         for (i = 0; i < 8; i++) {
 342                 kvm_debug("L1 Vectored handler @ %p\n",
 343                           gebase + 0x200 + (i * VECTORSPACING));
 344                 kvm_mips_build_exception(gebase + 0x200 + i * VECTORSPACING,
 345                                          handler);
 346         }
 347
 348         /* General exit handler */
 349         p = handler;
 350         p = kvm_mips_build_exit(p);
 351
 352         /* Guest entry routine */
 353         vcpu->arch.vcpu_run = p;
 354         p = kvm_mips_build_vcpu_run(p);
 355
 356         /* Dump the generated code */
 357         pr_debug("#include <asm/asm.h>\n");
 358         pr_debug("#include <asm/regdef.h>\n");
 359         pr_debug("\n");
 360         dump_handler("kvm_vcpu_run", vcpu->arch.vcpu_run, p);
 361         dump_handler("kvm_tlb_refill", refill_start, refill_end);
 362         dump_handler("kvm_gen_exc", gebase + 0x180, gebase + 0x200);
 363         dump_handler("kvm_exit", gebase + 0x2000, vcpu->arch.vcpu_run);
 364
 365         /* Invalidate the icache for these ranges */
 366         flush_icache_range((unsigned long)gebase,
 367                            (unsigned long)gebase + ALIGN(size, PAGE_SIZE));
 368
 369         /*
 370          * Allocate comm page for guest kernel, a TLB will be reserved for
 371          * mapping GVA @ 0xFFFF8000 to this page
 372          */
 373         vcpu->arch.kseg0_commpage = kzalloc(PAGE_SIZE << 1, GFP_KERNEL);
 374
 375         if (!vcpu->arch.kseg0_commpage) {
 376                 err = -ENOMEM;
 377                 goto out_free_gebase;
 378         }
 379
 380         kvm_debug("Allocated COMM page @ %p\n", vcpu->arch.kseg0_commpage);
 381         kvm_mips_commpage_init(vcpu);
 382
 383         /* Init */
 384         vcpu->arch.last_sched_cpu = -1;
 385         vcpu->arch.last_exec_cpu = -1;
 386
 387         return vcpu;
 388
 389 out_free_gebase:
 390         kfree(gebase);
 391
 392 out_uninit_cpu:
 393         kvm_vcpu_uninit(vcpu);
 394
 395 out_free_cpu:
 396         kfree(vcpu);
 397
 398 out:
 399         return ERR_PTR(err);
 400 }
 401
 402 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
 403 {
 404         hrtimer_cancel(&vcpu->arch.comparecount_timer);
 405
 406         kvm_vcpu_uninit(vcpu);
 407
 408         kvm_mips_dump_stats(vcpu);
 409
 410         kvm_mmu_free_memory_caches(vcpu);
 411         kfree(vcpu->arch.guest_ebase);
 412         kfree(vcpu->arch.kseg0_commpage);
 413         kfree(vcpu);
 414 }
 415
 416 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
 417 {
 418         kvm_arch_vcpu_free(vcpu);
 419 }
 420
 421 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
 422                                         struct kvm_guest_debug *dbg)
 423 {
 424         return -ENOIOCTLCMD;
 425 }
 426
 427 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
 428 {
 429         int r = -EINTR;
 430         sigset_t sigsaved;
 431
 432         if (vcpu->sigset_active)
 433                 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
 434
 435         if (vcpu->mmio_needed) {
 436                 if (!vcpu->mmio_is_write)
 437                         kvm_mips_complete_mmio_load(vcpu, run);
 438                 vcpu->mmio_needed = 0;
 439         }
 440
 441         if (run->immediate_exit)
 442                 goto out;
 443
 444         lose_fpu(1);
 445
 446         local_irq_disable();
 447         guest_enter_irqoff();
 448         trace_kvm_enter(vcpu);
 449
 450         /*
 451          * Make sure the read of VCPU requests in vcpu_run() callback is not
 452          * reordered ahead of the write to vcpu->mode, or we could miss a TLB
 453          * flush request while the requester sees the VCPU as outside of guest
 454          * mode and not needing an IPI.
 455          */
 456         smp_store_mb(vcpu->mode, IN_GUEST_MODE);
 457
 458         r = kvm_mips_callbacks->vcpu_run(run, vcpu);
 459
 460         trace_kvm_out(vcpu);
 461         guest_exit_irqoff();
 462         local_irq_enable();
 463
 464 out:
 465         if (vcpu->sigset_active)
 466                 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
 467
 468         return r;
 469 }
 470
 471 int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
 472                              struct kvm_mips_interrupt *irq)
 473 {
 474         int intr = (int)irq->irq;
 475         struct kvm_vcpu *dvcpu = NULL;
 476
 477         if (intr == 3 || intr == -3 || intr == 4 || intr == -4)
 478                 kvm_debug("%s: CPU: %d, INTR: %d\n", __func__, irq->cpu,
 479                           (int)intr);
 480
 481         if (irq->cpu == -1)
 482                 dvcpu = vcpu;
 483         else
 484                 dvcpu = vcpu->kvm->vcpus[irq->cpu];
 485
 486         if (intr == 2 || intr == 3 || intr == 4) {
 487                 kvm_mips_callbacks->queue_io_int(dvcpu, irq);
 488
 489         } else if (intr == -2 || intr == -3 || intr == -4) {
 490                 kvm_mips_callbacks->dequeue_io_int(dvcpu, irq);
 491         } else {
 492                 kvm_err("%s: invalid interrupt ioctl (%d:%d)\n", __func__,
 493                         irq->cpu, irq->irq);
 494                 return -EINVAL;
 495         }
 496
 497         dvcpu->arch.wait = 0;
 498
 499         if (swait_active(&dvcpu->wq))
 500                 swake_up(&dvcpu->wq);
 501
 502         return 0;
 503 }
 504
 505 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
 506                                     struct kvm_mp_state *mp_state)
 507 {
 508         return -ENOIOCTLCMD;
 509 }
 510
 511 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
 512                                     struct kvm_mp_state *mp_state)
 513 {
 514         return -ENOIOCTLCMD;
 515 }
 516
 517 static u64 kvm_mips_get_one_regs[] = {
 518         KVM_REG_MIPS_R0,
 519         KVM_REG_MIPS_R1,
 520         KVM_REG_MIPS_R2,
 521         KVM_REG_MIPS_R3,
 522         KVM_REG_MIPS_R4,
 523         KVM_REG_MIPS_R5,
 524         KVM_REG_MIPS_R6,
 525         KVM_REG_MIPS_R7,
 526         KVM_REG_MIPS_R8,
 527         KVM_REG_MIPS_R9,
 528         KVM_REG_MIPS_R10,
 529         KVM_REG_MIPS_R11,
 530         KVM_REG_MIPS_R12,
 531         KVM_REG_MIPS_R13,
 532         KVM_REG_MIPS_R14,
 533         KVM_REG_MIPS_R15,
 534         KVM_REG_MIPS_R16,
 535         KVM_REG_MIPS_R17,
 536         KVM_REG_MIPS_R18,
 537         KVM_REG_MIPS_R19,
 538         KVM_REG_MIPS_R20,
 539         KVM_REG_MIPS_R21,
 540         KVM_REG_MIPS_R22,
 541         KVM_REG_MIPS_R23,
 542         KVM_REG_MIPS_R24,
 543         KVM_REG_MIPS_R25,
 544         KVM_REG_MIPS_R26,
 545         KVM_REG_MIPS_R27,
 546         KVM_REG_MIPS_R28,
 547         KVM_REG_MIPS_R29,
 548         KVM_REG_MIPS_R30,
 549         KVM_REG_MIPS_R31,
 550
 551 #ifndef CONFIG_CPU_MIPSR6
 552         KVM_REG_MIPS_HI,
 553         KVM_REG_MIPS_LO,
 554 #endif
 555         KVM_REG_MIPS_PC,
 556 };
 557
 558 static u64 kvm_mips_get_one_regs_fpu[] = {
 559         KVM_REG_MIPS_FCR_IR,
 560         KVM_REG_MIPS_FCR_CSR,
 561 };
 562
 563 static u64 kvm_mips_get_one_regs_msa[] = {
 564         KVM_REG_MIPS_MSA_IR,
 565         KVM_REG_MIPS_MSA_CSR,
 566 };
 567
 568 static unsigned long kvm_mips_num_regs(struct kvm_vcpu *vcpu)
 569 {
 570         unsigned long ret;
 571
 572         ret = ARRAY_SIZE(kvm_mips_get_one_regs);
 573         if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) {
 574                 ret += ARRAY_SIZE(kvm_mips_get_one_regs_fpu) + 48;
 575                 /* odd doubles */
 576                 if (boot_cpu_data.fpu_id & MIPS_FPIR_F64)
 577                         ret += 16;
 578         }
 579         if (kvm_mips_guest_can_have_msa(&vcpu->arch))
 580                 ret += ARRAY_SIZE(kvm_mips_get_one_regs_msa) + 32;
 581         ret += kvm_mips_callbacks->num_regs(vcpu);
 582
 583         return ret;
 584 }
 585
 586 static int kvm_mips_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices)
 587 {
 588         u64 index;
 589         unsigned int i;
 590
 591         if (copy_to_user(indices, kvm_mips_get_one_regs,
 592                          sizeof(kvm_mips_get_one_regs)))
 593                 return -EFAULT;
 594         indices += ARRAY_SIZE(kvm_mips_get_one_regs);
 595
 596         if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) {
 597                 if (copy_to_user(indices, kvm_mips_get_one_regs_fpu,
 598                                  sizeof(kvm_mips_get_one_regs_fpu)))
 599                         return -EFAULT;
 600                 indices += ARRAY_SIZE(kvm_mips_get_one_regs_fpu);
 601
 602                 for (i = 0; i < 32; ++i) {
 603                         index = KVM_REG_MIPS_FPR_32(i);
 604                         if (copy_to_user(indices, &index, sizeof(index)))
 605                                 return -EFAULT;
 606                         ++indices;
 607
 608                         /* skip odd doubles if no F64 */
 609                         if (i & 1 && !(boot_cpu_data.fpu_id & MIPS_FPIR_F64))
 610                                 continue;
 611
 612                         index = KVM_REG_MIPS_FPR_64(i);
 613                         if (copy_to_user(indices, &index, sizeof(index)))
 614                                 return -EFAULT;
 615                         ++indices;
 616                 }
 617         }
 618
 619         if (kvm_mips_guest_can_have_msa(&vcpu->arch)) {
 620                 if (copy_to_user(indices, kvm_mips_get_one_regs_msa,
 621                                  sizeof(kvm_mips_get_one_regs_msa)))
 622                         return -EFAULT;
 623                 indices += ARRAY_SIZE(kvm_mips_get_one_regs_msa);
 624
 625                 for (i = 0; i < 32; ++i) {
 626                         index = KVM_REG_MIPS_VEC_128(i);
 627                         if (copy_to_user(indices, &index, sizeof(index)))
 628                                 return -EFAULT;
 629                         ++indices;
 630                 }
 631         }
 632
 633         return kvm_mips_callbacks->copy_reg_indices(vcpu, indices);
 634 }
 635
 636 static int kvm_mips_get_reg(struct kvm_vcpu *vcpu,
 637                             const struct kvm_one_reg *reg)
 638 {
 639         struct mips_coproc *cop0 = vcpu->arch.cop0;
 640         struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
 641         int ret;
 642         s64 v;
 643         s64 vs[2];
 644         unsigned int idx;
 645
 646         switch (reg->id) {
 647         /* General purpose registers */
 648         case KVM_REG_MIPS_R0 ... KVM_REG_MIPS_R31:
 649                 v = (long)vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0];
 650                 break;
 651 #ifndef CONFIG_CPU_MIPSR6
 652         case KVM_REG_MIPS_HI:
 653                 v = (long)vcpu->arch.hi;
 654                 break;
 655         case KVM_REG_MIPS_LO:
 656                 v = (long)vcpu->arch.lo;
 657                 break;
 658 #endif
 659         case KVM_REG_MIPS_PC:
 660                 v = (long)vcpu->arch.pc;
 661                 break;
 662
 663         /* Floating point registers */
 664         case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
 665                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 666                         return -EINVAL;
 667                 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
 668                 /* Odd singles in top of even double when FR=0 */
 669                 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
 670                         v = get_fpr32(&fpu->fpr[idx], 0);
 671                 else
 672                         v = get_fpr32(&fpu->fpr[idx & ~1], idx & 1);
 673                 break;
 674         case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
 675                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 676                         return -EINVAL;
 677                 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
 678                 /* Can't access odd doubles in FR=0 mode */
 679                 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
 680                         return -EINVAL;
 681                 v = get_fpr64(&fpu->fpr[idx], 0);
 682                 break;
 683         case KVM_REG_MIPS_FCR_IR:
 684                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 685                         return -EINVAL;
 686                 v = boot_cpu_data.fpu_id;
 687                 break;
 688         case KVM_REG_MIPS_FCR_CSR:
 689                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 690                         return -EINVAL;
 691                 v = fpu->fcr31;
 692                 break;
 693
 694         /* MIPS SIMD Architecture (MSA) registers */
 695         case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
 696                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 697                         return -EINVAL;
 698                 /* Can't access MSA registers in FR=0 mode */
 699                 if (!(kvm_read_c0_guest_status(cop0) & ST0_FR))
 700                         return -EINVAL;
 701                 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
 702 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 703                 /* least significant byte first */
 704                 vs[0] = get_fpr64(&fpu->fpr[idx], 0);
 705                 vs[1] = get_fpr64(&fpu->fpr[idx], 1);
 706 #else
 707                 /* most significant byte first */
 708                 vs[0] = get_fpr64(&fpu->fpr[idx], 1);
 709                 vs[1] = get_fpr64(&fpu->fpr[idx], 0);
 710 #endif
 711                 break;
 712         case KVM_REG_MIPS_MSA_IR:
 713                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 714                         return -EINVAL;
 715                 v = boot_cpu_data.msa_id;
 716                 break;
 717         case KVM_REG_MIPS_MSA_CSR:
 718                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 719                         return -EINVAL;
 720                 v = fpu->msacsr;
 721                 break;
 722
 723         /* registers to be handled specially */
 724         default:
 725                 ret = kvm_mips_callbacks->get_one_reg(vcpu, reg, &v);
 726                 if (ret)
 727                         return ret;
 728                 break;
 729         }
 730         if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
 731                 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
 732
 733                 return put_user(v, uaddr64);
 734         } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
 735                 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
 736                 u32 v32 = (u32)v;
 737
 738                 return put_user(v32, uaddr32);
 739         } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
 740                 void __user *uaddr = (void __user *)(long)reg->addr;
 741
 742                 return copy_to_user(uaddr, vs, 16) ? -EFAULT : 0;
 743         } else {
 744                 return -EINVAL;
 745         }
 746 }
 747
 748 static int kvm_mips_set_reg(struct kvm_vcpu *vcpu,
 749                             const struct kvm_one_reg *reg)
 750 {
 751         struct mips_coproc *cop0 = vcpu->arch.cop0;
 752         struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
 753         s64 v;
 754         s64 vs[2];
 755         unsigned int idx;
 756
 757         if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
 758                 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
 759
 760                 if (get_user(v, uaddr64) != 0)
 761                         return -EFAULT;
 762         } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
 763                 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
 764                 s32 v32;
 765
 766                 if (get_user(v32, uaddr32) != 0)
 767                         return -EFAULT;
 768                 v = (s64)v32;
 769         } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
 770                 void __user *uaddr = (void __user *)(long)reg->addr;
 771
 772                 return copy_from_user(vs, uaddr, 16) ? -EFAULT : 0;
 773         } else {
 774                 return -EINVAL;
 775         }
 776
 777         switch (reg->id) {
 778         /* General purpose registers */
 779         case KVM_REG_MIPS_R0:
 780                 /* Silently ignore requests to set $0 */
 781                 break;
 782         case KVM_REG_MIPS_R1 ... KVM_REG_MIPS_R31:
 783                 vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0] = v;
 784                 break;
 785 #ifndef CONFIG_CPU_MIPSR6
 786         case KVM_REG_MIPS_HI:
 787                 vcpu->arch.hi = v;
 788                 break;
 789         case KVM_REG_MIPS_LO:
 790                 vcpu->arch.lo = v;
 791                 break;
 792 #endif
 793         case KVM_REG_MIPS_PC:
 794                 vcpu->arch.pc = v;
 795                 break;
 796
 797         /* Floating point registers */
 798         case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
 799                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 800                         return -EINVAL;
 801                 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
 802                 /* Odd singles in top of even double when FR=0 */
 803                 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
 804                         set_fpr32(&fpu->fpr[idx], 0, v);
 805                 else
 806                         set_fpr32(&fpu->fpr[idx & ~1], idx & 1, v);
 807                 break;
 808         case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
 809                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 810                         return -EINVAL;
 811                 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
 812                 /* Can't access odd doubles in FR=0 mode */
 813                 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
 814                         return -EINVAL;
 815                 set_fpr64(&fpu->fpr[idx], 0, v);
 816                 break;
 817         case KVM_REG_MIPS_FCR_IR:
 818                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 819                         return -EINVAL;
 820                 /* Read-only */
 821                 break;
 822         case KVM_REG_MIPS_FCR_CSR:
 823                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 824                         return -EINVAL;
 825                 fpu->fcr31 = v;
 826                 break;
 827
 828         /* MIPS SIMD Architecture (MSA) registers */
 829         case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
 830                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 831                         return -EINVAL;
 832                 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
 833 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 834                 /* least significant byte first */
 835                 set_fpr64(&fpu->fpr[idx], 0, vs[0]);
 836                 set_fpr64(&fpu->fpr[idx], 1, vs[1]);
 837 #else
 838                 /* most significant byte first */
 839                 set_fpr64(&fpu->fpr[idx], 1, vs[0]);
 840                 set_fpr64(&fpu->fpr[idx], 0, vs[1]);
 841 #endif
 842                 break;
 843         case KVM_REG_MIPS_MSA_IR:
 844                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 845                         return -EINVAL;
 846                 /* Read-only */
 847                 break;
 848         case KVM_REG_MIPS_MSA_CSR:
 849                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 850                         return -EINVAL;
 851                 fpu->msacsr = v;
 852                 break;
 853
 854         /* registers to be handled specially */
 855         default:
 856                 return kvm_mips_callbacks->set_one_reg(vcpu, reg, v);
 857         }
 858         return 0;
 859 }
 860
 861 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
 862                                      struct kvm_enable_cap *cap)
 863 {
 864         int r = 0;
 865
 866         if (!kvm_vm_ioctl_check_extension(vcpu->kvm, cap->cap))
 867                 return -EINVAL;
 868         if (cap->flags)
 869                 return -EINVAL;
 870         if (cap->args[0])
 871                 return -EINVAL;
 872
 873         switch (cap->cap) {
 874         case KVM_CAP_MIPS_FPU:
 875                 vcpu->arch.fpu_enabled = true;
 876                 break;
 877         case KVM_CAP_MIPS_MSA:
 878                 vcpu->arch.msa_enabled = true;
 879                 break;
 880         default:
 881                 r = -EINVAL;
 882                 break;
 883         }
 884
 885         return r;
 886 }
 887
 888 long kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl,
 889                          unsigned long arg)
 890 {
 891         struct kvm_vcpu *vcpu = filp->private_data;
 892         void __user *argp = (void __user *)arg;
 893         long r;
 894
 895         switch (ioctl) {
 896         case KVM_SET_ONE_REG:
 897         case KVM_GET_ONE_REG: {
 898                 struct kvm_one_reg reg;
 899
 900                 if (copy_from_user(&reg, argp, sizeof(reg)))
 901                         return -EFAULT;
 902                 if (ioctl == KVM_SET_ONE_REG)
 903                         return kvm_mips_set_reg(vcpu, &reg);
 904                 else
 905                         return kvm_mips_get_reg(vcpu, &reg);
 906         }
 907         case KVM_GET_REG_LIST: {
 908                 struct kvm_reg_list __user *user_list = argp;
 909                 struct kvm_reg_list reg_list;
 910                 unsigned n;
 911
 912                 if (copy_from_user(&reg_list, user_list, sizeof(reg_list)))
 913                         return -EFAULT;
 914                 n = reg_list.n;
 915                 reg_list.n = kvm_mips_num_regs(vcpu);
 916                 if (copy_to_user(user_list, &reg_list, sizeof(reg_list)))
 917                         return -EFAULT;
 918                 if (n < reg_list.n)
 919                         return -E2BIG;
 920                 return kvm_mips_copy_reg_indices(vcpu, user_list->reg);
 921         }
 922         case KVM_INTERRUPT:
 923                 {
 924                         struct kvm_mips_interrupt irq;
 925
 926                         if (copy_from_user(&irq, argp, sizeof(irq)))
 927                                 return -EFAULT;
 928                         kvm_debug("[%d] %s: irq: %d\n", vcpu->vcpu_id, __func__,
 929                                   irq.irq);
 930
 931                         r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
 932                         break;
 933                 }
 934         case KVM_ENABLE_CAP: {
 935                 struct kvm_enable_cap cap;
 936
 937                 if (copy_from_user(&cap, argp, sizeof(cap)))
 938                         return -EFAULT;
 939                 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
 940                 break;
 941         }
 942         default:
 943                 r = -ENOIOCTLCMD;
 944         }
 945         return r;
 946 }
 947
 948 /**
 949  * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
 950  * @kvm: kvm instance
 951  * @log: slot id and address to which we copy the log
 952  *
 953  * Steps 1-4 below provide general overview of dirty page logging. See
 954  * kvm_get_dirty_log_protect() function description for additional details.
 955  *
 956  * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
 957  * always flush the TLB (step 4) even if previous step failed  and the dirty
 958  * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
 959  * does not preclude user space subsequent dirty log read. Flushing TLB ensures
 960  * writes will be marked dirty for next log read.
 961  *
 962  *   1. Take a snapshot of the bit and clear it if needed.
 963  *   2. Write protect the corresponding page.
 964  *   3. Copy the snapshot to the userspace.
 965  *   4. Flush TLB's if needed.
 966  */
 967 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
 968 {
 969         struct kvm_memslots *slots;
 970         struct kvm_memory_slot *memslot;
 971         bool is_dirty = false;
 972         int r;
 973
 974         mutex_lock(&kvm->slots_lock);
 975
 976         r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
 977
 978         if (is_dirty) {
 979                 slots = kvm_memslots(kvm);
 980                 memslot = id_to_memslot(slots, log->slot);
 981
 982                 /* Let implementation handle TLB/GVA invalidation */
 983                 kvm_mips_callbacks->flush_shadow_memslot(kvm, memslot);
 984         }
 985
 986         mutex_unlock(&kvm->slots_lock);
 987         return r;
 988 }
 989
 990 long kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
 991 {
 992         long r;
 993
 994         switch (ioctl) {
 995         default:
 996                 r = -ENOIOCTLCMD;
 997         }
 998
 999         return r;
1000 }
1001
1002 int kvm_arch_init(void *opaque)
1003 {
1004         if (kvm_mips_callbacks) {
1005                 kvm_err("kvm: module already exists\n");
1006                 return -EEXIST;
1007         }
1008
1009         return kvm_mips_emulation_init(&kvm_mips_callbacks);
1010 }
1011
1012 void kvm_arch_exit(void)
1013 {
1014         kvm_mips_callbacks = NULL;
1015 }
1016
1017 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
1018                                   struct kvm_sregs *sregs)
1019 {
1020         return -ENOIOCTLCMD;
1021 }
1022
1023 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
1024                                   struct kvm_sregs *sregs)
1025 {
1026         return -ENOIOCTLCMD;
1027 }
1028
1029 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
1030 {
1031 }
1032
1033 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1034 {
1035         return -ENOIOCTLCMD;
1036 }
1037
1038 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1039 {
1040         return -ENOIOCTLCMD;
1041 }
1042
1043 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
1044 {
1045         return VM_FAULT_SIGBUS;
1046 }
1047
1048 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
1049 {
1050         int r;
1051
1052         switch (ext) {
1053         case KVM_CAP_ONE_REG:
1054         case KVM_CAP_ENABLE_CAP:
1055         case KVM_CAP_READONLY_MEM:
1056         case KVM_CAP_SYNC_MMU:
1057         case KVM_CAP_IMMEDIATE_EXIT:
1058                 r = 1;
1059                 break;
1060         case KVM_CAP_COALESCED_MMIO:
1061                 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1062                 break;
1063         case KVM_CAP_NR_VCPUS:
1064                 r = num_online_cpus();
1065                 break;
1066         case KVM_CAP_MAX_VCPUS:
1067                 r = KVM_MAX_VCPUS;
1068                 break;
1069         case KVM_CAP_MIPS_FPU:
1070                 /* We don't handle systems with inconsistent cpu_has_fpu */
1071                 r = !!raw_cpu_has_fpu;
1072                 break;
1073         case KVM_CAP_MIPS_MSA:
1074                 /*
1075                  * We don't support MSA vector partitioning yet:
1076                  * 1) It would require explicit support which can't be tested
1077                  *    yet due to lack of support in current hardware.
1078                  * 2) It extends the state that would need to be saved/restored
1079                  *    by e.g. QEMU for migration.
1080                  *
1081                  * When vector partitioning hardware becomes available, support
1082                  * could be added by requiring a flag when enabling
1083                  * KVM_CAP_MIPS_MSA capability to indicate that userland knows
1084                  * to save/restore the appropriate extra state.
1085                  */
1086                 r = cpu_has_msa && !(boot_cpu_data.msa_id & MSA_IR_WRPF);
1087                 break;
1088         default:
1089                 r = kvm_mips_callbacks->check_extension(kvm, ext);
1090                 break;
1091         }
1092         return r;
1093 }
1094
1095 int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
1096 {
1097         return kvm_mips_pending_timer(vcpu) ||
1098                 kvm_read_c0_guest_cause(vcpu->arch.cop0) & C_TI;
1099 }
1100
1101 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu)
1102 {
1103         int i;
1104         struct mips_coproc *cop0;
1105
1106         if (!vcpu)
1107                 return -1;
1108
1109         kvm_debug("VCPU Register Dump:\n");
1110         kvm_debug("\tpc = 0x%08lx\n", vcpu->arch.pc);
1111         kvm_debug("\texceptions: %08lx\n", vcpu->arch.pending_exceptions);
1112
1113         for (i = 0; i < 32; i += 4) {
1114                 kvm_debug("\tgpr%02d: %08lx %08lx %08lx %08lx\n", i,
1115                        vcpu->arch.gprs[i],
1116                        vcpu->arch.gprs[i + 1],
1117                        vcpu->arch.gprs[i + 2], vcpu->arch.gprs[i + 3]);
1118         }
1119         kvm_debug("\thi: 0x%08lx\n", vcpu->arch.hi);
1120         kvm_debug("\tlo: 0x%08lx\n", vcpu->arch.lo);
1121
1122         cop0 = vcpu->arch.cop0;
1123         kvm_debug("\tStatus: 0x%08x, Cause: 0x%08x\n",
1124                   kvm_read_c0_guest_status(cop0),
1125                   kvm_read_c0_guest_cause(cop0));
1126
1127         kvm_debug("\tEPC: 0x%08lx\n", kvm_read_c0_guest_epc(cop0));
1128
1129         return 0;
1130 }
1131
1132 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1133 {
1134         int i;
1135
1136         for (i = 1; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1137                 vcpu->arch.gprs[i] = regs->gpr[i];
1138         vcpu->arch.gprs[0] = 0; /* zero is special, and cannot be set. */
1139         vcpu->arch.hi = regs->hi;
1140         vcpu->arch.lo = regs->lo;
1141         vcpu->arch.pc = regs->pc;
1142
1143         return 0;
1144 }
1145
1146 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1147 {
1148         int i;
1149
1150         for (i = 0; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1151                 regs->gpr[i] = vcpu->arch.gprs[i];
1152
1153         regs->hi = vcpu->arch.hi;
1154         regs->lo = vcpu->arch.lo;
1155         regs->pc = vcpu->arch.pc;
1156
1157         return 0;
1158 }
1159
1160 static void kvm_mips_comparecount_func(unsigned long data)
1161 {
1162         struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data;
1163
1164         kvm_mips_callbacks->queue_timer_int(vcpu);
1165
1166         vcpu->arch.wait = 0;
1167         if (swait_active(&vcpu->wq))
1168                 swake_up(&vcpu->wq);
1169 }
1170
1171 /* low level hrtimer wake routine */
1172 static enum hrtimer_restart kvm_mips_comparecount_wakeup(struct hrtimer *timer)
1173 {
1174         struct kvm_vcpu *vcpu;
1175
1176         vcpu = container_of(timer, struct kvm_vcpu, arch.comparecount_timer);
1177         kvm_mips_comparecount_func((unsigned long) vcpu);
1178         return kvm_mips_count_timeout(vcpu);
1179 }
1180
1181 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
1182 {
1183         int err;
1184
1185         err = kvm_mips_callbacks->vcpu_init(vcpu);
1186         if (err)
1187                 return err;
1188
1189         hrtimer_init(&vcpu->arch.comparecount_timer, CLOCK_MONOTONIC,
1190                      HRTIMER_MODE_REL);
1191         vcpu->arch.comparecount_timer.function = kvm_mips_comparecount_wakeup;
1192         return 0;
1193 }
1194
1195 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
1196 {
1197         kvm_mips_callbacks->vcpu_uninit(vcpu);
1198 }
1199
1200 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
1201                                   struct kvm_translation *tr)
1202 {
1203         return 0;
1204 }
1205
1206 /* Initial guest state */
1207 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
1208 {
1209         return kvm_mips_callbacks->vcpu_setup(vcpu);
1210 }
1211
1212 static void kvm_mips_set_c0_status(void)
1213 {
1214         u32 status = read_c0_status();
1215
1216         if (cpu_has_dsp)
1217                 status |= (ST0_MX);
1218
1219         write_c0_status(status);
1220         ehb();
1221 }
1222
1223 /*
1224  * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV)
1225  */
1226 int kvm_mips_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu)
1227 {
1228         u32 cause = vcpu->arch.host_cp0_cause;
1229         u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
1230         u32 __user *opc = (u32 __user *) vcpu->arch.pc;
1231         unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;
1232         enum emulation_result er = EMULATE_DONE;
1233         u32 inst;
1234         int ret = RESUME_GUEST;
1235
1236         vcpu->mode = OUTSIDE_GUEST_MODE;
1237
1238         /* re-enable HTW before enabling interrupts */
1239         if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ))
1240                 htw_start();
1241
1242         /* Set a default exit reason */
1243         run->exit_reason = KVM_EXIT_UNKNOWN;
1244         run->ready_for_interrupt_injection = 1;
1245
1246         /*
1247          * Set the appropriate status bits based on host CPU features,
1248          * before we hit the scheduler
1249          */
1250         kvm_mips_set_c0_status();
1251
1252         local_irq_enable();
1253
1254         kvm_debug("kvm_mips_handle_exit: cause: %#x, PC: %p, kvm_run: %p, kvm_vcpu: %p\n",
1255                         cause, opc, run, vcpu);
1256         trace_kvm_exit(vcpu, exccode);
1257
1258         if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) {
1259                 /*
1260                  * Do a privilege check, if in UM most of these exit conditions
1261                  * end up causing an exception to be delivered to the Guest
1262                  * Kernel
1263                  */
1264                 er = kvm_mips_check_privilege(cause, opc, run, vcpu);
1265                 if (er == EMULATE_PRIV_FAIL) {
1266                         goto skip_emul;
1267                 } else if (er == EMULATE_FAIL) {
1268                         run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1269                         ret = RESUME_HOST;
1270                         goto skip_emul;
1271                 }
1272         }
1273
1274         switch (exccode) {
1275         case EXCCODE_INT:
1276                 kvm_debug("[%d]EXCCODE_INT @ %p\n", vcpu->vcpu_id, opc);
1277
1278                 ++vcpu->stat.int_exits;
1279
1280                 if (need_resched())
1281                         cond_resched();
1282
1283                 ret = RESUME_GUEST;
1284                 break;
1285
1286         case EXCCODE_CPU:
1287                 kvm_debug("EXCCODE_CPU: @ PC: %p\n", opc);
1288
1289                 ++vcpu->stat.cop_unusable_exits;
1290                 ret = kvm_mips_callbacks->handle_cop_unusable(vcpu);
1291                 /* XXXKYMA: Might need to return to user space */
1292                 if (run->exit_reason == KVM_EXIT_IRQ_WINDOW_OPEN)
1293                         ret = RESUME_HOST;
1294                 break;
1295
1296         case EXCCODE_MOD:
1297                 ++vcpu->stat.tlbmod_exits;
1298                 ret = kvm_mips_callbacks->handle_tlb_mod(vcpu);
1299                 break;
1300
1301         case EXCCODE_TLBS:
1302                 kvm_debug("TLB ST fault:  cause %#x, status %#x, PC: %p, BadVaddr: %#lx\n",
1303                           cause, kvm_read_c0_guest_status(vcpu->arch.cop0), opc,
1304                           badvaddr);
1305
1306                 ++vcpu->stat.tlbmiss_st_exits;
1307                 ret = kvm_mips_callbacks->handle_tlb_st_miss(vcpu);
1308                 break;
1309
1310         case EXCCODE_TLBL:
1311                 kvm_debug("TLB LD fault: cause %#x, PC: %p, BadVaddr: %#lx\n",
1312                           cause, opc, badvaddr);
1313
1314                 ++vcpu->stat.tlbmiss_ld_exits;
1315                 ret = kvm_mips_callbacks->handle_tlb_ld_miss(vcpu);
1316                 break;
1317
1318         case EXCCODE_ADES:
1319                 ++vcpu->stat.addrerr_st_exits;
1320                 ret = kvm_mips_callbacks->handle_addr_err_st(vcpu);
1321                 break;
1322
1323         case EXCCODE_ADEL:
1324                 ++vcpu->stat.addrerr_ld_exits;
1325                 ret = kvm_mips_callbacks->handle_addr_err_ld(vcpu);
1326                 break;
1327
1328         case EXCCODE_SYS:
1329                 ++vcpu->stat.syscall_exits;
1330                 ret = kvm_mips_callbacks->handle_syscall(vcpu);
1331                 break;
1332
1333         case EXCCODE_RI:
1334                 ++vcpu->stat.resvd_inst_exits;
1335                 ret = kvm_mips_callbacks->handle_res_inst(vcpu);
1336                 break;
1337
1338         case EXCCODE_BP:
1339                 ++vcpu->stat.break_inst_exits;
1340                 ret = kvm_mips_callbacks->handle_break(vcpu);
1341                 break;
1342
1343         case EXCCODE_TR:
1344                 ++vcpu->stat.trap_inst_exits;
1345                 ret = kvm_mips_callbacks->handle_trap(vcpu);
1346                 break;
1347
1348         case EXCCODE_MSAFPE:
1349                 ++vcpu->stat.msa_fpe_exits;
1350                 ret = kvm_mips_callbacks->handle_msa_fpe(vcpu);
1351                 break;
1352
1353         case EXCCODE_FPE:
1354                 ++vcpu->stat.fpe_exits;
1355                 ret = kvm_mips_callbacks->handle_fpe(vcpu);
1356                 break;
1357
1358         case EXCCODE_MSADIS:
1359                 ++vcpu->stat.msa_disabled_exits;
1360                 ret = kvm_mips_callbacks->handle_msa_disabled(vcpu);
1361                 break;
1362
1363         case EXCCODE_GE:
1364                 /* defer exit accounting to handler */
1365                 ret = kvm_mips_callbacks->handle_guest_exit(vcpu);
1366                 break;
1367
1368         default:
1369                 if (cause & CAUSEF_BD)
1370                         opc += 1;
1371                 inst = 0;
1372                 kvm_get_badinstr(opc, vcpu, &inst);
1373                 kvm_err("Exception Code: %d, not yet handled, @ PC: %p, inst: 0x%08x  BadVaddr: %#lx Status: %#x\n",
1374                         exccode, opc, inst, badvaddr,
1375                         kvm_read_c0_guest_status(vcpu->arch.cop0));
1376                 kvm_arch_vcpu_dump_regs(vcpu);
1377                 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1378                 ret = RESUME_HOST;
1379                 break;
1380
1381         }
1382
1383 skip_emul:
1384         local_irq_disable();
1385
1386         if (ret == RESUME_GUEST)
1387                 kvm_vz_acquire_htimer(vcpu);
1388
1389         if (er == EMULATE_DONE && !(ret & RESUME_HOST))
1390                 kvm_mips_deliver_interrupts(vcpu, cause);
1391
1392         if (!(ret & RESUME_HOST)) {
1393                 /* Only check for signals if not already exiting to userspace */
1394                 if (signal_pending(current)) {
1395                         run->exit_reason = KVM_EXIT_INTR;
1396                         ret = (-EINTR << 2) | RESUME_HOST;
1397                         ++vcpu->stat.signal_exits;
1398                         trace_kvm_exit(vcpu, KVM_TRACE_EXIT_SIGNAL);
1399                 }
1400         }
1401
1402         if (ret == RESUME_GUEST) {
1403                 trace_kvm_reenter(vcpu);
1404
1405                 /*
1406                  * Make sure the read of VCPU requests in vcpu_reenter()
1407                  * callback is not reordered ahead of the write to vcpu->mode,
1408                  * or we could miss a TLB flush request while the requester sees
1409                  * the VCPU as outside of guest mode and not needing an IPI.
1410                  */
1411                 smp_store_mb(vcpu->mode, IN_GUEST_MODE);
1412
1413                 kvm_mips_callbacks->vcpu_reenter(run, vcpu);
1414
1415                 /*
1416                  * If FPU / MSA are enabled (i.e. the guest's FPU / MSA context
1417                  * is live), restore FCR31 / MSACSR.
1418                  *
1419                  * This should be before returning to the guest exception
1420                  * vector, as it may well cause an [MSA] FP exception if there
1421                  * are pending exception bits unmasked. (see
1422                  * kvm_mips_csr_die_notifier() for how that is handled).
1423                  */
1424                 if (kvm_mips_guest_has_fpu(&vcpu->arch) &&
1425                     read_c0_status() & ST0_CU1)
1426                         __kvm_restore_fcsr(&vcpu->arch);
1427
1428                 if (kvm_mips_guest_has_msa(&vcpu->arch) &&
1429                     read_c0_config5() & MIPS_CONF5_MSAEN)
1430                         __kvm_restore_msacsr(&vcpu->arch);
1431         }
1432
1433         /* Disable HTW before returning to guest or host */
1434         if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ))
1435                 htw_stop();
1436
1437         return ret;
1438 }
1439
1440 /* Enable FPU for guest and restore context */
1441 void kvm_own_fpu(struct kvm_vcpu *vcpu)
1442 {
1443         struct mips_coproc *cop0 = vcpu->arch.cop0;
1444         unsigned int sr, cfg5;
1445
1446         preempt_disable();
1447
1448         sr = kvm_read_c0_guest_status(cop0);
1449
1450         /*
1451          * If MSA state is already live, it is undefined how it interacts with
1452          * FR=0 FPU state, and we don't want to hit reserved instruction
1453          * exceptions trying to save the MSA state later when CU=1 && FR=1, so
1454          * play it safe and save it first.
1455          *
1456          * In theory we shouldn't ever hit this case since kvm_lose_fpu() should
1457          * get called when guest CU1 is set, however we can't trust the guest
1458          * not to clobber the status register directly via the commpage.
1459          */
1460         if (cpu_has_msa && sr & ST0_CU1 && !(sr & ST0_FR) &&
1461             vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA)
1462                 kvm_lose_fpu(vcpu);
1463
1464         /*
1465          * Enable FPU for guest
1466          * We set FR and FRE according to guest context
1467          */
1468         change_c0_status(ST0_CU1 | ST0_FR, sr);
1469         if (cpu_has_fre) {
1470                 cfg5 = kvm_read_c0_guest_config5(cop0);
1471                 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1472         }
1473         enable_fpu_hazard();
1474
1475         /* If guest FPU state not active, restore it now */
1476         if (!(vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU)) {
1477                 __kvm_restore_fpu(&vcpu->arch);
1478                 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
1479                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_FPU);
1480         } else {
1481                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_FPU);
1482         }
1483
1484         preempt_enable();
1485 }
1486
1487 #ifdef CONFIG_CPU_HAS_MSA
1488 /* Enable MSA for guest and restore context */
1489 void kvm_own_msa(struct kvm_vcpu *vcpu)
1490 {
1491         struct mips_coproc *cop0 = vcpu->arch.cop0;
1492         unsigned int sr, cfg5;
1493
1494         preempt_disable();
1495
1496         /*
1497          * Enable FPU if enabled in guest, since we're restoring FPU context
1498          * anyway. We set FR and FRE according to guest context.
1499          */
1500         if (kvm_mips_guest_has_fpu(&vcpu->arch)) {
1501                 sr = kvm_read_c0_guest_status(cop0);
1502
1503                 /*
1504                  * If FR=0 FPU state is already live, it is undefined how it
1505                  * interacts with MSA state, so play it safe and save it first.
1506                  */
1507                 if (!(sr & ST0_FR) &&
1508                     (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU |
1509                                 KVM_MIPS_AUX_MSA)) == KVM_MIPS_AUX_FPU)
1510                         kvm_lose_fpu(vcpu);
1511
1512                 change_c0_status(ST0_CU1 | ST0_FR, sr);
1513                 if (sr & ST0_CU1 && cpu_has_fre) {
1514                         cfg5 = kvm_read_c0_guest_config5(cop0);
1515                         change_c0_config5(MIPS_CONF5_FRE, cfg5);
1516                 }
1517         }
1518
1519         /* Enable MSA for guest */
1520         set_c0_config5(MIPS_CONF5_MSAEN);
1521         enable_fpu_hazard();
1522
1523         switch (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA)) {
1524         case KVM_MIPS_AUX_FPU:
1525                 /*
1526                  * Guest FPU state already loaded, only restore upper MSA state
1527                  */
1528                 __kvm_restore_msa_upper(&vcpu->arch);
1529                 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
1530                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_MSA);
1531                 break;
1532         case 0:
1533                 /* Neither FPU or MSA already active, restore full MSA state */
1534                 __kvm_restore_msa(&vcpu->arch);
1535                 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
1536                 if (kvm_mips_guest_has_fpu(&vcpu->arch))
1537                         vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
1538                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE,
1539                               KVM_TRACE_AUX_FPU_MSA);
1540                 break;
1541         default:
1542                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_MSA);
1543                 break;
1544         }
1545
1546         preempt_enable();
1547 }
1548 #endif
1549
1550 /* Drop FPU & MSA without saving it */
1551 void kvm_drop_fpu(struct kvm_vcpu *vcpu)
1552 {
1553         preempt_disable();
1554         if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
1555                 disable_msa();
1556                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_MSA);
1557                 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_MSA;
1558         }
1559         if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1560                 clear_c0_status(ST0_CU1 | ST0_FR);
1561                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_FPU);
1562                 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
1563         }
1564         preempt_enable();
1565 }
1566
1567 /* Save and disable FPU & MSA */
1568 void kvm_lose_fpu(struct kvm_vcpu *vcpu)
1569 {
1570         /*
1571          * With T&E, FPU & MSA get disabled in root context (hardware) when it
1572          * is disabled in guest context (software), but the register state in
1573          * the hardware may still be in use.
1574          * This is why we explicitly re-enable the hardware before saving.
1575          */
1576
1577         preempt_disable();
1578         if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
1579                 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) {
1580                         set_c0_config5(MIPS_CONF5_MSAEN);
1581                         enable_fpu_hazard();
1582                 }
1583
1584                 __kvm_save_msa(&vcpu->arch);
1585                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU_MSA);
1586
1587                 /* Disable MSA & FPU */
1588                 disable_msa();
1589                 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1590                         clear_c0_status(ST0_CU1 | ST0_FR);
1591                         disable_fpu_hazard();
1592                 }
1593                 vcpu->arch.aux_inuse &= ~(KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA);
1594         } else if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1595                 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) {
1596                         set_c0_status(ST0_CU1);
1597                         enable_fpu_hazard();
1598                 }
1599
1600                 __kvm_save_fpu(&vcpu->arch);
1601                 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
1602                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU);
1603
1604                 /* Disable FPU */
1605                 clear_c0_status(ST0_CU1 | ST0_FR);
1606                 disable_fpu_hazard();
1607         }
1608         preempt_enable();
1609 }
1610
1611 /*
1612  * Step over a specific ctc1 to FCSR and a specific ctcmsa to MSACSR which are
1613  * used to restore guest FCSR/MSACSR state and may trigger a "harmless" FP/MSAFP
1614  * exception if cause bits are set in the value being written.
1615  */
1616 static int kvm_mips_csr_die_notify(struct notifier_block *self,
1617                                    unsigned long cmd, void *ptr)
1618 {
1619         struct die_args *args = (struct die_args *)ptr;
1620         struct pt_regs *regs = args->regs;
1621         unsigned long pc;
1622
1623         /* Only interested in FPE and MSAFPE */
1624         if (cmd != DIE_FP && cmd != DIE_MSAFP)
1625                 return NOTIFY_DONE;
1626
1627         /* Return immediately if guest context isn't active */
1628         if (!(current->flags & PF_VCPU))
1629                 return NOTIFY_DONE;
1630
1631         /* Should never get here from user mode */
1632         BUG_ON(user_mode(regs));
1633
1634         pc = instruction_pointer(regs);
1635         switch (cmd) {
1636         case DIE_FP:
1637                 /* match 2nd instruction in __kvm_restore_fcsr */
1638                 if (pc != (unsigned long)&__kvm_restore_fcsr + 4)
1639                         return NOTIFY_DONE;
1640                 break;
1641         case DIE_MSAFP:
1642                 /* match 2nd/3rd instruction in __kvm_restore_msacsr */
1643                 if (!cpu_has_msa ||
1644                     pc < (unsigned long)&__kvm_restore_msacsr + 4 ||
1645                     pc > (unsigned long)&__kvm_restore_msacsr + 8)
1646                         return NOTIFY_DONE;
1647                 break;
1648         }
1649
1650         /* Move PC forward a little and continue executing */
1651         instruction_pointer(regs) += 4;
1652
1653         return NOTIFY_STOP;
1654 }
1655
1656 static struct notifier_block kvm_mips_csr_die_notifier = {
1657         .notifier_call = kvm_mips_csr_die_notify,
1658 };
1659
1660 static int __init kvm_mips_init(void)
1661 {
1662         int ret;
1663
1664         ret = kvm_mips_entry_setup();
1665         if (ret)
1666                 return ret;
1667
1668         ret = kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE);
1669
1670         if (ret)
1671                 return ret;
1672
1673         register_die_notifier(&kvm_mips_csr_die_notifier);
1674
1675         return 0;
1676 }
1677
1678 static void __exit kvm_mips_exit(void)
1679 {
1680         kvm_exit();
1681
1682         unregister_die_notifier(&kvm_mips_csr_die_notifier);
1683 }
1684
1685 module_init(kvm_mips_init);
1686 module_exit(kvm_mips_exit);
1687
1688 EXPORT_TRACEPOINT_SYMBOL(kvm_exit);