arch/mips/kernel/cpu-probe.c

   1 /*
   2  * Processor capabilities determination functions.
   3  *
   4  * Copyright (C) xxxx  the Anonymous
   5  * Copyright (C) 2003, 2004  Maciej W. Rozycki
   6  * Copyright (C) 1994 - 2003 Ralf Baechle
   7  * Copyright (C) 2001, 2004  MIPS Inc.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or (at your option) any later version.
  13  */
  14 #include <linux/config.h>
  15 #include <linux/init.h>
  16 #include <linux/kernel.h>
  17 #include <linux/ptrace.h>
  18 #include <linux/stddef.h>
  19
  20 #include <asm/cpu.h>
  21 #include <asm/fpu.h>
  22 #include <asm/mipsregs.h>
  23 #include <asm/system.h>
  24
  25 /*
  26  * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
  27  * the implementation of the "wait" feature differs between CPU families. This
  28  * points to the function that implements CPU specific wait.
  29  * The wait instruction stops the pipeline and reduces the power consumption of
  30  * the CPU very much.
  31  */
  32 void (*cpu_wait)(void) = NULL;
  33
  34 static void r3081_wait(void)
  35 {
  36         unsigned long cfg = read_c0_conf();
  37         write_c0_conf(cfg | R30XX_CONF_HALT);
  38 }
  39
  40 static void r39xx_wait(void)
  41 {
  42         unsigned long cfg = read_c0_conf();
  43         write_c0_conf(cfg | TX39_CONF_HALT);
  44 }
  45
  46 static void r4k_wait(void)
  47 {
  48         __asm__(".set\tmips3\n\t"
  49                 "wait\n\t"
  50                 ".set\tmips0");
  51 }
  52
  53 /* The Au1xxx wait is available only if using 32khz counter or
  54  * external timer source, but specifically not CP0 Counter. */
  55 int allow_au1k_wait;
  56
  57 static void au1k_wait(void)
  58 {
  59         /* using the wait instruction makes CP0 counter unusable */
  60         __asm__(".set mips3\n\t"
  61                 "cache 0x14, 0(%0)\n\t"
  62                 "cache 0x14, 32(%0)\n\t"
  63                 "sync\n\t"
  64                 "nop\n\t"
  65                 "wait\n\t"
  66                 "nop\n\t"
  67                 "nop\n\t"
  68                 "nop\n\t"
  69                 "nop\n\t"
  70                 ".set mips0\n\t"
  71                 : : "r" (au1k_wait));
  72 }
  73
  74 static inline void check_wait(void)
  75 {
  76         struct cpuinfo_mips *c = &current_cpu_data;
  77
  78         printk("Checking for 'wait' instruction... ");
  79         switch (c->cputype) {
  80         case CPU_R3081:
  81         case CPU_R3081E:
  82                 cpu_wait = r3081_wait;
  83                 printk(" available.\n");
  84                 break;
  85         case CPU_TX3927:
  86                 cpu_wait = r39xx_wait;
  87                 printk(" available.\n");
  88                 break;
  89         case CPU_R4200:
  90 /*      case CPU_R4300: */
  91         case CPU_R4600:
  92         case CPU_R4640:
  93         case CPU_R4650:
  94         case CPU_R4700:
  95         case CPU_R5000:
  96         case CPU_NEVADA:
  97         case CPU_RM7000:
  98         case CPU_RM9000:
  99         case CPU_TX49XX:
 100         case CPU_4KC:
 101         case CPU_4KEC:
 102         case CPU_4KSC:
 103         case CPU_5KC:
 104 /*      case CPU_20KC:*/
 105         case CPU_24K:
 106         case CPU_25KF:
 107                 cpu_wait = r4k_wait;
 108                 printk(" available.\n");
 109                 break;
 110         case CPU_AU1000:
 111         case CPU_AU1100:
 112         case CPU_AU1500:
 113         case CPU_AU1550:
 114         case CPU_AU1200:
 115                 if (allow_au1k_wait) {
 116                         cpu_wait = au1k_wait;
 117                         printk(" available.\n");
 118                 } else
 119                         printk(" unavailable.\n");
 120                 break;
 121         default:
 122                 printk(" unavailable.\n");
 123                 break;
 124         }
 125 }
 126
 127 void __init check_bugs32(void)
 128 {
 129         check_wait();
 130 }
 131
 132 /*
 133  * Probe whether cpu has config register by trying to play with
 134  * alternate cache bit and see whether it matters.
 135  * It's used by cpu_probe to distinguish between R3000A and R3081.
 136  */
 137 static inline int cpu_has_confreg(void)
 138 {
 139 #ifdef CONFIG_CPU_R3000
 140         extern unsigned long r3k_cache_size(unsigned long);
 141         unsigned long size1, size2;
 142         unsigned long cfg = read_c0_conf();
 143
 144         size1 = r3k_cache_size(ST0_ISC);
 145         write_c0_conf(cfg ^ R30XX_CONF_AC);
 146         size2 = r3k_cache_size(ST0_ISC);
 147         write_c0_conf(cfg);
 148         return size1 != size2;
 149 #else
 150         return 0;
 151 #endif
 152 }
 153
 154 /*
 155  * Get the FPU Implementation/Revision.
 156  */
 157 static inline unsigned long cpu_get_fpu_id(void)
 158 {
 159         unsigned long tmp, fpu_id;
 160
 161         tmp = read_c0_status();
 162         __enable_fpu();
 163         fpu_id = read_32bit_cp1_register(CP1_REVISION);
 164         write_c0_status(tmp);
 165         return fpu_id;
 166 }
 167
 168 /*
 169  * Check the CPU has an FPU the official way.
 170  */
 171 static inline int __cpu_has_fpu(void)
 172 {
 173         return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
 174 }
 175
 176 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4KTLB \
 177                 | MIPS_CPU_COUNTER)
 178
 179 static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
 180 {
 181         switch (c->processor_id & 0xff00) {
 182         case PRID_IMP_R2000:
 183                 c->cputype = CPU_R2000;
 184                 c->isa_level = MIPS_CPU_ISA_I;
 185                 c->options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX;
 186                 if (__cpu_has_fpu())
 187                         c->options |= MIPS_CPU_FPU;
 188                 c->tlbsize = 64;
 189                 break;
 190         case PRID_IMP_R3000:
 191                 if ((c->processor_id & 0xff) == PRID_REV_R3000A)
 192                         if (cpu_has_confreg())
 193                                 c->cputype = CPU_R3081E;
 194                         else
 195                                 c->cputype = CPU_R3000A;
 196                 else
 197                         c->cputype = CPU_R3000;
 198                 c->isa_level = MIPS_CPU_ISA_I;
 199                 c->options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX;
 200                 if (__cpu_has_fpu())
 201                         c->options |= MIPS_CPU_FPU;
 202                 c->tlbsize = 64;
 203                 break;
 204         case PRID_IMP_R4000:
 205                 if (read_c0_config() & CONF_SC) {
 206                         if ((c->processor_id & 0xff) >= PRID_REV_R4400)
 207                                 c->cputype = CPU_R4400PC;
 208                         else
 209                                 c->cputype = CPU_R4000PC;
 210                 } else {
 211                         if ((c->processor_id & 0xff) >= PRID_REV_R4400)
 212                                 c->cputype = CPU_R4400SC;
 213                         else
 214                                 c->cputype = CPU_R4000SC;
 215                 }
 216
 217                 c->isa_level = MIPS_CPU_ISA_III;
 218                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 219                              MIPS_CPU_WATCH | MIPS_CPU_VCE |
 220                              MIPS_CPU_LLSC;
 221                 c->tlbsize = 48;
 222                 break;
 223         case PRID_IMP_VR41XX:
 224                 switch (c->processor_id & 0xf0) {
 225                 case PRID_REV_VR4111:
 226                         c->cputype = CPU_VR4111;
 227                         break;
 228                 case PRID_REV_VR4121:
 229                         c->cputype = CPU_VR4121;
 230                         break;
 231                 case PRID_REV_VR4122:
 232                         if ((c->processor_id & 0xf) < 0x3)
 233                                 c->cputype = CPU_VR4122;
 234                         else
 235                                 c->cputype = CPU_VR4181A;
 236                         break;
 237                 case PRID_REV_VR4130:
 238                         if ((c->processor_id & 0xf) < 0x4)
 239                                 c->cputype = CPU_VR4131;
 240                         else
 241                                 c->cputype = CPU_VR4133;
 242                         break;
 243                 default:
 244                         printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
 245                         c->cputype = CPU_VR41XX;
 246                         break;
 247                 }
 248                 c->isa_level = MIPS_CPU_ISA_III;
 249                 c->options = R4K_OPTS;
 250                 c->tlbsize = 32;
 251                 break;
 252         case PRID_IMP_R4300:
 253                 c->cputype = CPU_R4300;
 254                 c->isa_level = MIPS_CPU_ISA_III;
 255                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 256                              MIPS_CPU_LLSC;
 257                 c->tlbsize = 32;
 258                 break;
 259         case PRID_IMP_R4600:
 260                 c->cputype = CPU_R4600;
 261                 c->isa_level = MIPS_CPU_ISA_III;
 262                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
 263                 c->tlbsize = 48;
 264                 break;
 265         #if 0
 266         case PRID_IMP_R4650:
 267                 /*
 268                  * This processor doesn't have an MMU, so it's not
 269                  * "real easy" to run Linux on it. It is left purely
 270                  * for documentation.  Commented out because it shares
 271                  * it's c0_prid id number with the TX3900.
 272                  */
 273                 c->cputype = CPU_R4650;
 274                 c->isa_level = MIPS_CPU_ISA_III;
 275                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
 276                 c->tlbsize = 48;
 277                 break;
 278         #endif
 279         case PRID_IMP_TX39:
 280                 c->isa_level = MIPS_CPU_ISA_I;
 281                 c->options = MIPS_CPU_TLB;
 282
 283                 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
 284                         c->cputype = CPU_TX3927;
 285                         c->tlbsize = 64;
 286                 } else {
 287                         switch (c->processor_id & 0xff) {
 288                         case PRID_REV_TX3912:
 289                                 c->cputype = CPU_TX3912;
 290                                 c->tlbsize = 32;
 291                                 break;
 292                         case PRID_REV_TX3922:
 293                                 c->cputype = CPU_TX3922;
 294                                 c->tlbsize = 64;
 295                                 break;
 296                         default:
 297                                 c->cputype = CPU_UNKNOWN;
 298                                 break;
 299                         }
 300                 }
 301                 break;
 302         case PRID_IMP_R4700:
 303                 c->cputype = CPU_R4700;
 304                 c->isa_level = MIPS_CPU_ISA_III;
 305                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 306                              MIPS_CPU_LLSC;
 307                 c->tlbsize = 48;
 308                 break;
 309         case PRID_IMP_TX49:
 310                 c->cputype = CPU_TX49XX;
 311                 c->isa_level = MIPS_CPU_ISA_III;
 312                 c->options = R4K_OPTS | MIPS_CPU_LLSC;
 313                 if (!(c->processor_id & 0x08))
 314                         c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
 315                 c->tlbsize = 48;
 316                 break;
 317         case PRID_IMP_R5000:
 318                 c->cputype = CPU_R5000;
 319                 c->isa_level = MIPS_CPU_ISA_IV;
 320                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 321                              MIPS_CPU_LLSC;
 322                 c->tlbsize = 48;
 323                 break;
 324         case PRID_IMP_R5432:
 325                 c->cputype = CPU_R5432;
 326                 c->isa_level = MIPS_CPU_ISA_IV;
 327                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 328                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 329                 c->tlbsize = 48;
 330                 break;
 331         case PRID_IMP_R5500:
 332                 c->cputype = CPU_R5500;
 333                 c->isa_level = MIPS_CPU_ISA_IV;
 334                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 335                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 336                 c->tlbsize = 48;
 337                 break;
 338         case PRID_IMP_NEVADA:
 339                 c->cputype = CPU_NEVADA;
 340                 c->isa_level = MIPS_CPU_ISA_IV;
 341                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 342                              MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
 343                 c->tlbsize = 48;
 344                 break;
 345         case PRID_IMP_R6000:
 346                 c->cputype = CPU_R6000;
 347                 c->isa_level = MIPS_CPU_ISA_II;
 348                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 349                              MIPS_CPU_LLSC;
 350                 c->tlbsize = 32;
 351                 break;
 352         case PRID_IMP_R6000A:
 353                 c->cputype = CPU_R6000A;
 354                 c->isa_level = MIPS_CPU_ISA_II;
 355                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 356                              MIPS_CPU_LLSC;
 357                 c->tlbsize = 32;
 358                 break;
 359         case PRID_IMP_RM7000:
 360                 c->cputype = CPU_RM7000;
 361                 c->isa_level = MIPS_CPU_ISA_IV;
 362                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 363                              MIPS_CPU_LLSC;
 364                 /*
 365                  * Undocumented RM7000:  Bit 29 in the info register of
 366                  * the RM7000 v2.0 indicates if the TLB has 48 or 64
 367                  * entries.
 368                  *
 369                  * 29      1 =>    64 entry JTLB
 370                  *         0 =>    48 entry JTLB
 371                  */
 372                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
 373                 break;
 374         case PRID_IMP_RM9000:
 375                 c->cputype = CPU_RM9000;
 376                 c->isa_level = MIPS_CPU_ISA_IV;
 377                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 378                              MIPS_CPU_LLSC;
 379                 /*
 380                  * Bit 29 in the info register of the RM9000
 381                  * indicates if the TLB has 48 or 64 entries.
 382                  *
 383                  * 29      1 =>    64 entry JTLB
 384                  *         0 =>    48 entry JTLB
 385                  */
 386                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
 387                 break;
 388         case PRID_IMP_R8000:
 389                 c->cputype = CPU_R8000;
 390                 c->isa_level = MIPS_CPU_ISA_IV;
 391                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
 392                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 393                              MIPS_CPU_LLSC;
 394                 c->tlbsize = 384;      /* has weird TLB: 3-way x 128 */
 395                 break;
 396         case PRID_IMP_R10000:
 397                 c->cputype = CPU_R10000;
 398                 c->isa_level = MIPS_CPU_ISA_IV;
 399                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
 400                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 401                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 402                              MIPS_CPU_LLSC;
 403                 c->tlbsize = 64;
 404                 break;
 405         case PRID_IMP_R12000:
 406                 c->cputype = CPU_R12000;
 407                 c->isa_level = MIPS_CPU_ISA_IV;
 408                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
 409                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 410                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 411                              MIPS_CPU_LLSC;
 412                 c->tlbsize = 64;
 413                 break;
 414         }
 415 }
 416
 417 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
 418 {
 419         unsigned int config0;
 420         int isa;
 421
 422         config0 = read_c0_config();
 423
 424         if (((config0 & MIPS_CONF_MT) >> 7) == 1)
 425                 c->options |= MIPS_CPU_TLB;
 426         isa = (config0 & MIPS_CONF_AT) >> 13;
 427         switch (isa) {
 428         case 0:
 429                 c->isa_level = MIPS_CPU_ISA_M32;
 430                 break;
 431         case 2:
 432                 c->isa_level = MIPS_CPU_ISA_M64;
 433                 break;
 434         default:
 435                 panic("Unsupported ISA type, cp0.config0.at: %d.", isa);
 436         }
 437
 438         return config0 & MIPS_CONF_M;
 439 }
 440
 441 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
 442 {
 443         unsigned int config1;
 444
 445         config1 = read_c0_config1();
 446
 447         if (config1 & MIPS_CONF1_MD)
 448                 c->ases |= MIPS_ASE_MDMX;
 449         if (config1 & MIPS_CONF1_WR)
 450                 c->options |= MIPS_CPU_WATCH;
 451         if (config1 & MIPS_CONF1_CA)
 452                 c->ases |= MIPS_ASE_MIPS16;
 453         if (config1 & MIPS_CONF1_EP)
 454                 c->options |= MIPS_CPU_EJTAG;
 455         if (config1 & MIPS_CONF1_FP) {
 456                 c->options |= MIPS_CPU_FPU;
 457                 c->options |= MIPS_CPU_32FPR;
 458         }
 459         if (cpu_has_tlb)
 460                 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
 461
 462         return config1 & MIPS_CONF_M;
 463 }
 464
 465 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
 466 {
 467         unsigned int config2;
 468
 469         config2 = read_c0_config2();
 470
 471         if (config2 & MIPS_CONF2_SL)
 472                 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
 473
 474         return config2 & MIPS_CONF_M;
 475 }
 476
 477 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
 478 {
 479         unsigned int config3;
 480
 481         config3 = read_c0_config3();
 482
 483         if (config3 & MIPS_CONF3_SM)
 484                 c->ases |= MIPS_ASE_SMARTMIPS;
 485         if (config3 & MIPS_CONF3_DSP)
 486                 c->ases |= MIPS_ASE_DSP;
 487
 488         return config3 & MIPS_CONF_M;
 489 }
 490
 491 static inline void decode_configs(struct cpuinfo_mips *c)
 492 {
 493         /* MIPS32 or MIPS64 compliant CPU.  */
 494         c->options = MIPS_CPU_4KEX | MIPS_CPU_COUNTER | MIPS_CPU_DIVEC |
 495                      MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
 496
 497         c->scache.flags = MIPS_CACHE_NOT_PRESENT;
 498
 499         /* Read Config registers.  */
 500         if (!decode_config0(c))
 501                 return;                 /* actually worth a panic() */
 502         if (!decode_config1(c))
 503                 return;
 504         if (!decode_config2(c))
 505                 return;
 506         if (!decode_config3(c))
 507                 return;
 508 }
 509
 510 static inline void cpu_probe_mips(struct cpuinfo_mips *c)
 511 {
 512         decode_configs(c);
 513         c->options |= MIPS_CPU_4KTLB;
 514         switch (c->processor_id & 0xff00) {
 515         case PRID_IMP_4KC:
 516                 c->cputype = CPU_4KC;
 517                 break;
 518         case PRID_IMP_4KEC:
 519                 c->cputype = CPU_4KEC;
 520                 break;
 521         case PRID_IMP_4KECR2:
 522                 c->cputype = CPU_4KEC;
 523                 break;
 524         case PRID_IMP_4KSC:
 525                 c->cputype = CPU_4KSC;
 526                 break;
 527         case PRID_IMP_5KC:
 528                 c->cputype = CPU_5KC;
 529                 break;
 530         case PRID_IMP_20KC:
 531                 c->cputype = CPU_20KC;
 532                 break;
 533         case PRID_IMP_24K:
 534         case PRID_IMP_24KE:
 535                 c->cputype = CPU_24K;
 536                 break;
 537         case PRID_IMP_25KF:
 538                 c->cputype = CPU_25KF;
 539                 /* Probe for L2 cache */
 540                 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
 541                 break;
 542         }
 543 }
 544
 545 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
 546 {
 547         decode_configs(c);
 548         c->options |= MIPS_CPU_4KTLB;
 549         switch (c->processor_id & 0xff00) {
 550         case PRID_IMP_AU1_REV1:
 551         case PRID_IMP_AU1_REV2:
 552                 switch ((c->processor_id >> 24) & 0xff) {
 553                 case 0:
 554                         c->cputype = CPU_AU1000;
 555                         break;
 556                 case 1:
 557                         c->cputype = CPU_AU1500;
 558                         break;
 559                 case 2:
 560                         c->cputype = CPU_AU1100;
 561                         break;
 562                 case 3:
 563                         c->cputype = CPU_AU1550;
 564                         break;
 565                 case 4:
 566                         c->cputype = CPU_AU1200;
 567                         break;
 568                 default:
 569                         panic("Unknown Au Core!");
 570                         break;
 571                 }
 572                 break;
 573         }
 574 }
 575
 576 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
 577 {
 578         decode_configs(c);
 579         c->options |= MIPS_CPU_4KTLB;
 580         switch (c->processor_id & 0xff00) {
 581         case PRID_IMP_SB1:
 582                 c->cputype = CPU_SB1;
 583 #ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
 584                 /* FPU in pass1 is known to have issues. */
 585                 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
 586 #endif
 587                 break;
 588         }
 589 }
 590
 591 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
 592 {
 593         decode_configs(c);
 594         c->options |= MIPS_CPU_4KTLB;
 595         switch (c->processor_id & 0xff00) {
 596         case PRID_IMP_SR71000:
 597                 c->cputype = CPU_SR71000;
 598                 c->scache.ways = 8;
 599                 c->tlbsize = 64;
 600                 break;
 601         }
 602 }
 603
 604 __init void cpu_probe(void)
 605 {
 606         struct cpuinfo_mips *c = &current_cpu_data;
 607
 608         c->processor_id = PRID_IMP_UNKNOWN;
 609         c->fpu_id       = FPIR_IMP_NONE;
 610         c->cputype      = CPU_UNKNOWN;
 611
 612         c->processor_id = read_c0_prid();
 613         switch (c->processor_id & 0xff0000) {
 614         case PRID_COMP_LEGACY:
 615                 cpu_probe_legacy(c);
 616                 break;
 617         case PRID_COMP_MIPS:
 618                 cpu_probe_mips(c);
 619                 break;
 620         case PRID_COMP_ALCHEMY:
 621                 cpu_probe_alchemy(c);
 622                 break;
 623         case PRID_COMP_SIBYTE:
 624                 cpu_probe_sibyte(c);
 625                 break;
 626         case PRID_COMP_SANDCRAFT:
 627                 cpu_probe_sandcraft(c);
 628                 break;
 629         default:
 630                 c->cputype = CPU_UNKNOWN;
 631         }
 632         if (c->options & MIPS_CPU_FPU) {
 633                 c->fpu_id = cpu_get_fpu_id();
 634
 635                 if (c->isa_level == MIPS_CPU_ISA_M32 ||
 636                     c->isa_level == MIPS_CPU_ISA_M64) {
 637                         if (c->fpu_id & MIPS_FPIR_3D)
 638                                 c->ases |= MIPS_ASE_MIPS3D;
 639                 }
 640         }
 641 }
 642
 643 __init void cpu_report(void)
 644 {
 645         struct cpuinfo_mips *c = &current_cpu_data;
 646
 647         printk("CPU revision is: %08x\n", c->processor_id);
 648         if (c->options & MIPS_CPU_FPU)
 649                 printk("FPU revision is: %08x\n", c->fpu_id);
 650 }