arch/mips/kernel/branch.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1996, 97, 2000, 2001 by Ralf Baechle
   7  * Copyright (C) 2001 MIPS Technologies, Inc.
   8  */
   9 #include <linux/kernel.h>
  10 #include <linux/sched.h>
  11 #include <linux/signal.h>
  12 #include <linux/module.h>
  13 #include <asm/branch.h>
  14 #include <asm/cpu.h>
  15 #include <asm/cpu-features.h>
  16 #include <asm/fpu.h>
  17 #include <asm/fpu_emulator.h>
  18 #include <asm/inst.h>
  19 #include <asm/ptrace.h>
  20 #include <asm/uaccess.h>
  21
  22 /*
  23  * Calculate and return exception PC in case of branch delay slot
  24  * for microMIPS and MIPS16e. It does not clear the ISA mode bit.
  25  */
  26 int __isa_exception_epc(struct pt_regs *regs)
  27 {
  28         unsigned short inst;
  29         long epc = regs->cp0_epc;
  30
  31         /* Calculate exception PC in branch delay slot. */
  32         if (__get_user(inst, (u16 __user *) msk_isa16_mode(epc))) {
  33                 /* This should never happen because delay slot was checked. */
  34                 force_sig(SIGSEGV, current);
  35                 return epc;
  36         }
  37         if (cpu_has_mips16) {
  38                 if (((union mips16e_instruction)inst).ri.opcode
  39                                 == MIPS16e_jal_op)
  40                         epc += 4;
  41                 else
  42                         epc += 2;
  43         } else if (mm_insn_16bit(inst))
  44                 epc += 2;
  45         else
  46                 epc += 4;
  47
  48         return epc;
  49 }
  50
  51 /* (microMIPS) Convert 16-bit register encoding to 32-bit register encoding. */
  52 static const unsigned int reg16to32map[8] = {16, 17, 2, 3, 4, 5, 6, 7};
  53
  54 int __mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
  55                        unsigned long *contpc)
  56 {
  57         union mips_instruction insn = (union mips_instruction)dec_insn.insn;
  58         int bc_false = 0;
  59         unsigned int fcr31;
  60         unsigned int bit;
  61
  62         if (!cpu_has_mmips)
  63                 return 0;
  64
  65         switch (insn.mm_i_format.opcode) {
  66         case mm_pool32a_op:
  67                 if ((insn.mm_i_format.simmediate & MM_POOL32A_MINOR_MASK) ==
  68                     mm_pool32axf_op) {
  69                         switch (insn.mm_i_format.simmediate >>
  70                                 MM_POOL32A_MINOR_SHIFT) {
  71                         case mm_jalr_op:
  72                         case mm_jalrhb_op:
  73                         case mm_jalrs_op:
  74                         case mm_jalrshb_op:
  75                                 if (insn.mm_i_format.rt != 0)   /* Not mm_jr */
  76                                         regs->regs[insn.mm_i_format.rt] =
  77                                                 regs->cp0_epc +
  78                                                 dec_insn.pc_inc +
  79                                                 dec_insn.next_pc_inc;
  80                                 *contpc = regs->regs[insn.mm_i_format.rs];
  81                                 return 1;
  82                         }
  83                 }
  84                 break;
  85         case mm_pool32i_op:
  86                 switch (insn.mm_i_format.rt) {
  87                 case mm_bltzals_op:
  88                 case mm_bltzal_op:
  89                         regs->regs[31] = regs->cp0_epc +
  90                                 dec_insn.pc_inc +
  91                                 dec_insn.next_pc_inc;
  92                         /* Fall through */
  93                 case mm_bltz_op:
  94                         if ((long)regs->regs[insn.mm_i_format.rs] < 0)
  95                                 *contpc = regs->cp0_epc +
  96                                         dec_insn.pc_inc +
  97                                         (insn.mm_i_format.simmediate << 1);
  98                         else
  99                                 *contpc = regs->cp0_epc +
 100                                         dec_insn.pc_inc +
 101                                         dec_insn.next_pc_inc;
 102                         return 1;
 103                 case mm_bgezals_op:
 104                 case mm_bgezal_op:
 105                         regs->regs[31] = regs->cp0_epc +
 106                                         dec_insn.pc_inc +
 107                                         dec_insn.next_pc_inc;
 108                         /* Fall through */
 109                 case mm_bgez_op:
 110                         if ((long)regs->regs[insn.mm_i_format.rs] >= 0)
 111                                 *contpc = regs->cp0_epc +
 112                                         dec_insn.pc_inc +
 113                                         (insn.mm_i_format.simmediate << 1);
 114                         else
 115                                 *contpc = regs->cp0_epc +
 116                                         dec_insn.pc_inc +
 117                                         dec_insn.next_pc_inc;
 118                         return 1;
 119                 case mm_blez_op:
 120                         if ((long)regs->regs[insn.mm_i_format.rs] <= 0)
 121                                 *contpc = regs->cp0_epc +
 122                                         dec_insn.pc_inc +
 123                                         (insn.mm_i_format.simmediate << 1);
 124                         else
 125                                 *contpc = regs->cp0_epc +
 126                                         dec_insn.pc_inc +
 127                                         dec_insn.next_pc_inc;
 128                         return 1;
 129                 case mm_bgtz_op:
 130                         if ((long)regs->regs[insn.mm_i_format.rs] <= 0)
 131                                 *contpc = regs->cp0_epc +
 132                                         dec_insn.pc_inc +
 133                                         (insn.mm_i_format.simmediate << 1);
 134                         else
 135                                 *contpc = regs->cp0_epc +
 136                                         dec_insn.pc_inc +
 137                                         dec_insn.next_pc_inc;
 138                         return 1;
 139                 case mm_bc2f_op:
 140                 case mm_bc1f_op:
 141                         bc_false = 1;
 142                         /* Fall through */
 143                 case mm_bc2t_op:
 144                 case mm_bc1t_op:
 145                         preempt_disable();
 146                         if (is_fpu_owner())
 147                                 fcr31 = read_32bit_cp1_register(CP1_STATUS);
 148                         else
 149                                 fcr31 = current->thread.fpu.fcr31;
 150                         preempt_enable();
 151
 152                         if (bc_false)
 153                                 fcr31 = ~fcr31;
 154
 155                         bit = (insn.mm_i_format.rs >> 2);
 156                         bit += (bit != 0);
 157                         bit += 23;
 158                         if (fcr31 & (1 << bit))
 159                                 *contpc = regs->cp0_epc +
 160                                         dec_insn.pc_inc +
 161                                         (insn.mm_i_format.simmediate << 1);
 162                         else
 163                                 *contpc = regs->cp0_epc +
 164                                         dec_insn.pc_inc + dec_insn.next_pc_inc;
 165                         return 1;
 166                 }
 167                 break;
 168         case mm_pool16c_op:
 169                 switch (insn.mm_i_format.rt) {
 170                 case mm_jalr16_op:
 171                 case mm_jalrs16_op:
 172                         regs->regs[31] = regs->cp0_epc +
 173                                 dec_insn.pc_inc + dec_insn.next_pc_inc;
 174                         /* Fall through */
 175                 case mm_jr16_op:
 176                         *contpc = regs->regs[insn.mm_i_format.rs];
 177                         return 1;
 178                 }
 179                 break;
 180         case mm_beqz16_op:
 181                 if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] == 0)
 182                         *contpc = regs->cp0_epc +
 183                                 dec_insn.pc_inc +
 184                                 (insn.mm_b1_format.simmediate << 1);
 185                 else
 186                         *contpc = regs->cp0_epc +
 187                                 dec_insn.pc_inc + dec_insn.next_pc_inc;
 188                 return 1;
 189         case mm_bnez16_op:
 190                 if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] != 0)
 191                         *contpc = regs->cp0_epc +
 192                                 dec_insn.pc_inc +
 193                                 (insn.mm_b1_format.simmediate << 1);
 194                 else
 195                         *contpc = regs->cp0_epc +
 196                                 dec_insn.pc_inc + dec_insn.next_pc_inc;
 197                 return 1;
 198         case mm_b16_op:
 199                 *contpc = regs->cp0_epc + dec_insn.pc_inc +
 200                          (insn.mm_b0_format.simmediate << 1);
 201                 return 1;
 202         case mm_beq32_op:
 203                 if (regs->regs[insn.mm_i_format.rs] ==
 204                     regs->regs[insn.mm_i_format.rt])
 205                         *contpc = regs->cp0_epc +
 206                                 dec_insn.pc_inc +
 207                                 (insn.mm_i_format.simmediate << 1);
 208                 else
 209                         *contpc = regs->cp0_epc +
 210                                 dec_insn.pc_inc +
 211                                 dec_insn.next_pc_inc;
 212                 return 1;
 213         case mm_bne32_op:
 214                 if (regs->regs[insn.mm_i_format.rs] !=
 215                     regs->regs[insn.mm_i_format.rt])
 216                         *contpc = regs->cp0_epc +
 217                                 dec_insn.pc_inc +
 218                                 (insn.mm_i_format.simmediate << 1);
 219                 else
 220                         *contpc = regs->cp0_epc +
 221                                 dec_insn.pc_inc + dec_insn.next_pc_inc;
 222                 return 1;
 223         case mm_jalx32_op:
 224                 regs->regs[31] = regs->cp0_epc +
 225                         dec_insn.pc_inc + dec_insn.next_pc_inc;
 226                 *contpc = regs->cp0_epc + dec_insn.pc_inc;
 227                 *contpc >>= 28;
 228                 *contpc <<= 28;
 229                 *contpc |= (insn.j_format.target << 2);
 230                 return 1;
 231         case mm_jals32_op:
 232         case mm_jal32_op:
 233                 regs->regs[31] = regs->cp0_epc +
 234                         dec_insn.pc_inc + dec_insn.next_pc_inc;
 235                 /* Fall through */
 236         case mm_j32_op:
 237                 *contpc = regs->cp0_epc + dec_insn.pc_inc;
 238                 *contpc >>= 27;
 239                 *contpc <<= 27;
 240                 *contpc |= (insn.j_format.target << 1);
 241                 set_isa16_mode(*contpc);
 242                 return 1;
 243         }
 244         return 0;
 245 }
 246
 247 /*
 248  * Compute return address and emulate branch in microMIPS mode after an
 249  * exception only. It does not handle compact branches/jumps and cannot
 250  * be used in interrupt context. (Compact branches/jumps do not cause
 251  * exceptions.)
 252  */
 253 int __microMIPS_compute_return_epc(struct pt_regs *regs)
 254 {
 255         u16 __user *pc16;
 256         u16 halfword;
 257         unsigned int word;
 258         unsigned long contpc;
 259         struct mm_decoded_insn mminsn = { 0 };
 260
 261         mminsn.micro_mips_mode = 1;
 262
 263         /* This load never faults. */
 264         pc16 = (unsigned short __user *)msk_isa16_mode(regs->cp0_epc);
 265         __get_user(halfword, pc16);
 266         pc16++;
 267         contpc = regs->cp0_epc + 2;
 268         word = ((unsigned int)halfword << 16);
 269         mminsn.pc_inc = 2;
 270
 271         if (!mm_insn_16bit(halfword)) {
 272                 __get_user(halfword, pc16);
 273                 pc16++;
 274                 contpc = regs->cp0_epc + 4;
 275                 mminsn.pc_inc = 4;
 276                 word |= halfword;
 277         }
 278         mminsn.insn = word;
 279
 280         if (get_user(halfword, pc16))
 281                 goto sigsegv;
 282         mminsn.next_pc_inc = 2;
 283         word = ((unsigned int)halfword << 16);
 284
 285         if (!mm_insn_16bit(halfword)) {
 286                 pc16++;
 287                 if (get_user(halfword, pc16))
 288                         goto sigsegv;
 289                 mminsn.next_pc_inc = 4;
 290                 word |= halfword;
 291         }
 292         mminsn.next_insn = word;
 293
 294         mm_isBranchInstr(regs, mminsn, &contpc);
 295
 296         regs->cp0_epc = contpc;
 297
 298         return 0;
 299
 300 sigsegv:
 301         force_sig(SIGSEGV, current);
 302         return -EFAULT;
 303 }
 304
 305 /*
 306  * Compute return address and emulate branch in MIPS16e mode after an
 307  * exception only. It does not handle compact branches/jumps and cannot
 308  * be used in interrupt context. (Compact branches/jumps do not cause
 309  * exceptions.)
 310  */
 311 int __MIPS16e_compute_return_epc(struct pt_regs *regs)
 312 {
 313         u16 __user *addr;
 314         union mips16e_instruction inst;
 315         u16 inst2;
 316         u32 fullinst;
 317         long epc;
 318
 319         epc = regs->cp0_epc;
 320
 321         /* Read the instruction. */
 322         addr = (u16 __user *)msk_isa16_mode(epc);
 323         if (__get_user(inst.full, addr)) {
 324                 force_sig(SIGSEGV, current);
 325                 return -EFAULT;
 326         }
 327
 328         switch (inst.ri.opcode) {
 329         case MIPS16e_extend_op:
 330                 regs->cp0_epc += 4;
 331                 return 0;
 332
 333                 /*
 334                  *  JAL and JALX in MIPS16e mode
 335                  */
 336         case MIPS16e_jal_op:
 337                 addr += 1;
 338                 if (__get_user(inst2, addr)) {
 339                         force_sig(SIGSEGV, current);
 340                         return -EFAULT;
 341                 }
 342                 fullinst = ((unsigned)inst.full << 16) | inst2;
 343                 regs->regs[31] = epc + 6;
 344                 epc += 4;
 345                 epc >>= 28;
 346                 epc <<= 28;
 347                 /*
 348                  * JAL:5 X:1 TARGET[20-16]:5 TARGET[25:21]:5 TARGET[15:0]:16
 349                  *
 350                  * ......TARGET[15:0].................TARGET[20:16]...........
 351                  * ......TARGET[25:21]
 352                  */
 353                 epc |=
 354                     ((fullinst & 0xffff) << 2) | ((fullinst & 0x3e00000) >> 3) |
 355                     ((fullinst & 0x1f0000) << 7);
 356                 if (!inst.jal.x)
 357                         set_isa16_mode(epc);    /* Set ISA mode bit. */
 358                 regs->cp0_epc = epc;
 359                 return 0;
 360
 361                 /*
 362                  *  J(AL)R(C)
 363                  */
 364         case MIPS16e_rr_op:
 365                 if (inst.rr.func == MIPS16e_jr_func) {
 366
 367                         if (inst.rr.ra)
 368                                 regs->cp0_epc = regs->regs[31];
 369                         else
 370                                 regs->cp0_epc =
 371                                     regs->regs[reg16to32[inst.rr.rx]];
 372
 373                         if (inst.rr.l) {
 374                                 if (inst.rr.nd)
 375                                         regs->regs[31] = epc + 2;
 376                                 else
 377                                         regs->regs[31] = epc + 4;
 378                         }
 379                         return 0;
 380                 }
 381                 break;
 382         }
 383
 384         /*
 385          * All other cases have no branch delay slot and are 16-bits.
 386          * Branches do not cause an exception.
 387          */
 388         regs->cp0_epc += 2;
 389
 390         return 0;
 391 }
 392
 393 /**
 394  * __compute_return_epc_for_insn - Computes the return address and do emulate
 395  *                                  branch simulation, if required.
 396  *
 397  * @regs:       Pointer to pt_regs
 398  * @insn:       branch instruction to decode
 399  * @returns:    -EFAULT on error and forces SIGBUS, and on success
 400  *              returns 0 or BRANCH_LIKELY_TAKEN as appropriate after
 401  *              evaluating the branch.
 402  */
 403 int __compute_return_epc_for_insn(struct pt_regs *regs,
 404                                    union mips_instruction insn)
 405 {
 406         unsigned int bit, fcr31, dspcontrol, reg;
 407         long epc = regs->cp0_epc;
 408         int ret = 0;
 409
 410         switch (insn.i_format.opcode) {
 411         /*
 412          * jr and jalr are in r_format format.
 413          */
 414         case spec_op:
 415                 switch (insn.r_format.func) {
 416                 case jalr_op:
 417                         regs->regs[insn.r_format.rd] = epc + 8;
 418                         /* Fall through */
 419                 case jr_op:
 420                         if (NO_R6EMU && insn.r_format.func == jr_op)
 421                                 goto sigill_r6;
 422                         regs->cp0_epc = regs->regs[insn.r_format.rs];
 423                         break;
 424                 }
 425                 break;
 426
 427         /*
 428          * This group contains:
 429          * bltz_op, bgez_op, bltzl_op, bgezl_op,
 430          * bltzal_op, bgezal_op, bltzall_op, bgezall_op.
 431          */
 432         case bcond_op:
 433                 switch (insn.i_format.rt) {
 434                 case bltzl_op:
 435                         if (NO_R6EMU)
 436                                 goto sigill_r6;
 437                 case bltz_op:
 438                         if ((long)regs->regs[insn.i_format.rs] < 0) {
 439                                 epc = epc + 4 + (insn.i_format.simmediate << 2);
 440                                 if (insn.i_format.rt == bltzl_op)
 441                                         ret = BRANCH_LIKELY_TAKEN;
 442                         } else
 443                                 epc += 8;
 444                         regs->cp0_epc = epc;
 445                         break;
 446
 447                 case bgezl_op:
 448                         if (NO_R6EMU)
 449                                 goto sigill_r6;
 450                 case bgez_op:
 451                         if ((long)regs->regs[insn.i_format.rs] >= 0) {
 452                                 epc = epc + 4 + (insn.i_format.simmediate << 2);
 453                                 if (insn.i_format.rt == bgezl_op)
 454                                         ret = BRANCH_LIKELY_TAKEN;
 455                         } else
 456                                 epc += 8;
 457                         regs->cp0_epc = epc;
 458                         break;
 459
 460                 case bltzal_op:
 461                 case bltzall_op:
 462                         if (NO_R6EMU && (insn.i_format.rs ||
 463                             insn.i_format.rt == bltzall_op)) {
 464                                 ret = -SIGILL;
 465                                 break;
 466                         }
 467                         regs->regs[31] = epc + 8;
 468                         /*
 469                          * OK we are here either because we hit a NAL
 470                          * instruction or because we are emulating an
 471                          * old bltzal{,l} one. Lets figure out what the
 472                          * case really is.
 473                          */
 474                         if (!insn.i_format.rs) {
 475                                 /*
 476                                  * NAL or BLTZAL with rs == 0
 477                                  * Doesn't matter if we are R6 or not. The
 478                                  * result is the same
 479                                  */
 480                                 regs->cp0_epc += 4 +
 481                                         (insn.i_format.simmediate << 2);
 482                                 break;
 483                         }
 484                         /* Now do the real thing for non-R6 BLTZAL{,L} */
 485                         if ((long)regs->regs[insn.i_format.rs] < 0) {
 486                                 epc = epc + 4 + (insn.i_format.simmediate << 2);
 487                                 if (insn.i_format.rt == bltzall_op)
 488                                         ret = BRANCH_LIKELY_TAKEN;
 489                         } else
 490                                 epc += 8;
 491                         regs->cp0_epc = epc;
 492                         break;
 493
 494                 case bgezal_op:
 495                 case bgezall_op:
 496                         if (NO_R6EMU && (insn.i_format.rs ||
 497                             insn.i_format.rt == bgezall_op)) {
 498                                 ret = -SIGILL;
 499                                 break;
 500                         }
 501                         regs->regs[31] = epc + 8;
 502                         /*
 503                          * OK we are here either because we hit a BAL
 504                          * instruction or because we are emulating an
 505                          * old bgezal{,l} one. Lets figure out what the
 506                          * case really is.
 507                          */
 508                         if (!insn.i_format.rs) {
 509                                 /*
 510                                  * BAL or BGEZAL with rs == 0
 511                                  * Doesn't matter if we are R6 or not. The
 512                                  * result is the same
 513                                  */
 514                                 regs->cp0_epc += 4 +
 515                                         (insn.i_format.simmediate << 2);
 516                                 break;
 517                         }
 518                         /* Now do the real thing for non-R6 BGEZAL{,L} */
 519                         if ((long)regs->regs[insn.i_format.rs] >= 0) {
 520                                 epc = epc + 4 + (insn.i_format.simmediate << 2);
 521                                 if (insn.i_format.rt == bgezall_op)
 522                                         ret = BRANCH_LIKELY_TAKEN;
 523                         } else
 524                                 epc += 8;
 525                         regs->cp0_epc = epc;
 526                         break;
 527
 528                 case bposge32_op:
 529                         if (!cpu_has_dsp)
 530                                 goto sigill_dsp;
 531
 532                         dspcontrol = rddsp(0x01);
 533
 534                         if (dspcontrol >= 32) {
 535                                 epc = epc + 4 + (insn.i_format.simmediate << 2);
 536                         } else
 537                                 epc += 8;
 538                         regs->cp0_epc = epc;
 539                         break;
 540                 }
 541                 break;
 542
 543         /*
 544          * These are unconditional and in j_format.
 545          */
 546         case jal_op:
 547                 regs->regs[31] = regs->cp0_epc + 8;
 548         case j_op:
 549                 epc += 4;
 550                 epc >>= 28;
 551                 epc <<= 28;
 552                 epc |= (insn.j_format.target << 2);
 553                 regs->cp0_epc = epc;
 554                 if (insn.i_format.opcode == jalx_op)
 555                         set_isa16_mode(regs->cp0_epc);
 556                 break;
 557
 558         /*
 559          * These are conditional and in i_format.
 560          */
 561         case beql_op:
 562                 if (NO_R6EMU)
 563                         goto sigill_r6;
 564         case beq_op:
 565                 if (regs->regs[insn.i_format.rs] ==
 566                     regs->regs[insn.i_format.rt]) {
 567                         epc = epc + 4 + (insn.i_format.simmediate << 2);
 568                         if (insn.i_format.opcode == beql_op)
 569                                 ret = BRANCH_LIKELY_TAKEN;
 570                 } else
 571                         epc += 8;
 572                 regs->cp0_epc = epc;
 573                 break;
 574
 575         case bnel_op:
 576                 if (NO_R6EMU)
 577                         goto sigill_r6;
 578         case bne_op:
 579                 if (regs->regs[insn.i_format.rs] !=
 580                     regs->regs[insn.i_format.rt]) {
 581                         epc = epc + 4 + (insn.i_format.simmediate << 2);
 582                         if (insn.i_format.opcode == bnel_op)
 583                                 ret = BRANCH_LIKELY_TAKEN;
 584                 } else
 585                         epc += 8;
 586                 regs->cp0_epc = epc;
 587                 break;
 588
 589         case blezl_op: /* not really i_format */
 590                 if (NO_R6EMU)
 591                         goto sigill_r6;
 592         case blez_op:
 593                 /* rt field assumed to be zero */
 594                 if ((long)regs->regs[insn.i_format.rs] <= 0) {
 595                         epc = epc + 4 + (insn.i_format.simmediate << 2);
 596                         if (insn.i_format.opcode == blezl_op)
 597                                 ret = BRANCH_LIKELY_TAKEN;
 598                 } else
 599                         epc += 8;
 600                 regs->cp0_epc = epc;
 601                 break;
 602
 603         case bgtzl_op:
 604                 if (NO_R6EMU)
 605                         goto sigill_r6;
 606         case bgtz_op:
 607                 /* rt field assumed to be zero */
 608                 if ((long)regs->regs[insn.i_format.rs] > 0) {
 609                         epc = epc + 4 + (insn.i_format.simmediate << 2);
 610                         if (insn.i_format.opcode == bgtzl_op)
 611                                 ret = BRANCH_LIKELY_TAKEN;
 612                 } else
 613                         epc += 8;
 614                 regs->cp0_epc = epc;
 615                 break;
 616
 617         /*
 618          * And now the FPA/cp1 branch instructions.
 619          */
 620         case cop1_op:
 621                 if (cpu_has_mips_r6 &&
 622                     ((insn.i_format.rs == bc1eqz_op) ||
 623                      (insn.i_format.rs == bc1nez_op))) {
 624                         if (!used_math()) { /* First time FPU user */
 625                                 ret = init_fpu();
 626                                 if (ret && NO_R6EMU) {
 627                                         ret = -ret;
 628                                         break;
 629                                 }
 630                                 ret = 0;
 631                                 set_used_math();
 632                         }
 633                         lose_fpu(1);    /* Save FPU state for the emulator. */
 634                         reg = insn.i_format.rt;
 635                         bit = 0;
 636                         switch (insn.i_format.rs) {
 637                         case bc1eqz_op:
 638                                 /* Test bit 0 */
 639                                 if (get_fpr32(&current->thread.fpu.fpr[reg], 0)
 640                                     & 0x1)
 641                                         bit = 1;
 642                                 break;
 643                         case bc1nez_op:
 644                                 /* Test bit 0 */
 645                                 if (!(get_fpr32(&current->thread.fpu.fpr[reg], 0)
 646                                       & 0x1))
 647                                         bit = 1;
 648                                 break;
 649                         }
 650                         own_fpu(1);
 651                         if (bit)
 652                                 epc = epc + 4 +
 653                                         (insn.i_format.simmediate << 2);
 654                         else
 655                                 epc += 8;
 656                         regs->cp0_epc = epc;
 657
 658                         break;
 659                 } else {
 660
 661                         preempt_disable();
 662                         if (is_fpu_owner())
 663                                 fcr31 = read_32bit_cp1_register(CP1_STATUS);
 664                         else
 665                                 fcr31 = current->thread.fpu.fcr31;
 666                         preempt_enable();
 667
 668                         bit = (insn.i_format.rt >> 2);
 669                         bit += (bit != 0);
 670                         bit += 23;
 671                         switch (insn.i_format.rt & 3) {
 672                         case 0: /* bc1f */
 673                         case 2: /* bc1fl */
 674                                 if (~fcr31 & (1 << bit)) {
 675                                         epc = epc + 4 +
 676                                                 (insn.i_format.simmediate << 2);
 677                                         if (insn.i_format.rt == 2)
 678                                                 ret = BRANCH_LIKELY_TAKEN;
 679                                 } else
 680                                         epc += 8;
 681                                 regs->cp0_epc = epc;
 682                                 break;
 683
 684                         case 1: /* bc1t */
 685                         case 3: /* bc1tl */
 686                                 if (fcr31 & (1 << bit)) {
 687                                         epc = epc + 4 +
 688                                                 (insn.i_format.simmediate << 2);
 689                                         if (insn.i_format.rt == 3)
 690                                                 ret = BRANCH_LIKELY_TAKEN;
 691                                 } else
 692                                         epc += 8;
 693                                 regs->cp0_epc = epc;
 694                                 break;
 695                         }
 696                         break;
 697                 }
 698 #ifdef CONFIG_CPU_CAVIUM_OCTEON
 699         case lwc2_op: /* This is bbit0 on Octeon */
 700                 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
 701                      == 0)
 702                         epc = epc + 4 + (insn.i_format.simmediate << 2);
 703                 else
 704                         epc += 8;
 705                 regs->cp0_epc = epc;
 706                 break;
 707         case ldc2_op: /* This is bbit032 on Octeon */
 708                 if ((regs->regs[insn.i_format.rs] &
 709                     (1ull<<(insn.i_format.rt+32))) == 0)
 710                         epc = epc + 4 + (insn.i_format.simmediate << 2);
 711                 else
 712                         epc += 8;
 713                 regs->cp0_epc = epc;
 714                 break;
 715         case swc2_op: /* This is bbit1 on Octeon */
 716                 if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
 717                         epc = epc + 4 + (insn.i_format.simmediate << 2);
 718                 else
 719                         epc += 8;
 720                 regs->cp0_epc = epc;
 721                 break;
 722         case sdc2_op: /* This is bbit132 on Octeon */
 723                 if (regs->regs[insn.i_format.rs] &
 724                     (1ull<<(insn.i_format.rt+32)))
 725                         epc = epc + 4 + (insn.i_format.simmediate << 2);
 726                 else
 727                         epc += 8;
 728                 regs->cp0_epc = epc;
 729                 break;
 730 #endif
 731         }
 732
 733         return ret;
 734
 735 sigill_dsp:
 736         printk("%s: DSP branch but not DSP ASE - sending SIGBUS.\n", current->comm);
 737         force_sig(SIGBUS, current);
 738         return -EFAULT;
 739 sigill_r6:
 740         pr_info("%s: R2 branch but r2-to-r6 emulator is not preset - sending SIGILL.\n",
 741                 current->comm);
 742         force_sig(SIGILL, current);
 743         return -EFAULT;
 744 }
 745 EXPORT_SYMBOL_GPL(__compute_return_epc_for_insn);
 746
 747 int __compute_return_epc(struct pt_regs *regs)
 748 {
 749         unsigned int __user *addr;
 750         long epc;
 751         union mips_instruction insn;
 752
 753         epc = regs->cp0_epc;
 754         if (epc & 3)
 755                 goto unaligned;
 756
 757         /*
 758          * Read the instruction
 759          */
 760         addr = (unsigned int __user *) epc;
 761         if (__get_user(insn.word, addr)) {
 762                 force_sig(SIGSEGV, current);
 763                 return -EFAULT;
 764         }
 765
 766         return __compute_return_epc_for_insn(regs, insn);
 767
 768 unaligned:
 769         printk("%s: unaligned epc - sending SIGBUS.\n", current->comm);
 770         force_sig(SIGBUS, current);
 771         return -EFAULT;
 772 }