2 * BPF JIT compiler for ARM64
4 * Copyright (C) 2014-2015 Zi Shen Lim <zlim.lnx@gmail.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #define pr_fmt(fmt) "bpf_jit: " fmt
21 #include <linux/filter.h>
22 #include <linux/printk.h>
23 #include <linux/skbuff.h>
24 #include <linux/slab.h>
26 #include <asm/byteorder.h>
27 #include <asm/cacheflush.h>
28 #include <asm/debug-monitors.h>
32 int bpf_jit_enable __read_mostly;
34 #define TMP_REG_1 (MAX_BPF_REG + 0)
35 #define TMP_REG_2 (MAX_BPF_REG + 1)
37 /* Map BPF registers to A64 registers */
38 static const int bpf2a64[] = {
39 /* return value from in-kernel function, and exit value from eBPF */
40 [BPF_REG_0] = A64_R(7),
41 /* arguments from eBPF program to in-kernel function */
42 [BPF_REG_1] = A64_R(0),
43 [BPF_REG_2] = A64_R(1),
44 [BPF_REG_3] = A64_R(2),
45 [BPF_REG_4] = A64_R(3),
46 [BPF_REG_5] = A64_R(4),
47 /* callee saved registers that in-kernel function will preserve */
48 [BPF_REG_6] = A64_R(19),
49 [BPF_REG_7] = A64_R(20),
50 [BPF_REG_8] = A64_R(21),
51 [BPF_REG_9] = A64_R(22),
52 /* read-only frame pointer to access stack */
53 [BPF_REG_FP] = A64_FP,
54 /* temporary register for internal BPF JIT */
55 [TMP_REG_1] = A64_R(23),
56 [TMP_REG_2] = A64_R(24),
60 const struct bpf_prog *prog;
68 static inline void emit(const u32 insn, struct jit_ctx *ctx)
70 if (ctx->image != NULL)
71 ctx->image[ctx->idx] = cpu_to_le32(insn);
76 static inline void emit_a64_mov_i64(const int reg, const u64 val,
82 emit(A64_MOVZ(1, reg, tmp & 0xffff, shift), ctx);
87 emit(A64_MOVK(1, reg, tmp & 0xffff, shift), ctx);
93 static inline void emit_a64_mov_i(const int is64, const int reg,
94 const s32 val, struct jit_ctx *ctx)
97 u16 lo = val & 0xffff;
101 emit(A64_MOVN(is64, reg, (u16)~lo, 0), ctx);
103 emit(A64_MOVN(is64, reg, (u16)~hi, 16), ctx);
104 emit(A64_MOVK(is64, reg, lo, 0), ctx);
107 emit(A64_MOVZ(is64, reg, lo, 0), ctx);
109 emit(A64_MOVK(is64, reg, hi, 16), ctx);
113 static inline int bpf2a64_offset(int bpf_to, int bpf_from,
114 const struct jit_ctx *ctx)
116 int to = ctx->offset[bpf_to];
117 /* -1 to account for the Branch instruction */
118 int from = ctx->offset[bpf_from] - 1;
123 static void jit_fill_hole(void *area, unsigned int size)
126 /* We are guaranteed to have aligned memory. */
127 for (ptr = area; size >= sizeof(u32); size -= sizeof(u32))
128 *ptr++ = cpu_to_le32(AARCH64_BREAK_FAULT);
131 static inline int epilogue_offset(const struct jit_ctx *ctx)
133 int to = ctx->epilogue_offset;
139 /* Stack must be multiples of 16B */
140 #define STACK_ALIGN(sz) (((sz) + 15) & ~15)
142 static void build_prologue(struct jit_ctx *ctx)
144 const u8 r6 = bpf2a64[BPF_REG_6];
145 const u8 r7 = bpf2a64[BPF_REG_7];
146 const u8 r8 = bpf2a64[BPF_REG_8];
147 const u8 r9 = bpf2a64[BPF_REG_9];
148 const u8 fp = bpf2a64[BPF_REG_FP];
149 const u8 ra = bpf2a64[BPF_REG_A];
150 const u8 rx = bpf2a64[BPF_REG_X];
151 const u8 tmp1 = bpf2a64[TMP_REG_1];
152 const u8 tmp2 = bpf2a64[TMP_REG_2];
153 int stack_size = MAX_BPF_STACK;
155 stack_size += 4; /* extra for skb_copy_bits buffer */
156 stack_size = STACK_ALIGN(stack_size);
158 /* Save callee-saved register */
159 emit(A64_PUSH(r6, r7, A64_SP), ctx);
160 emit(A64_PUSH(r8, r9, A64_SP), ctx);
162 emit(A64_PUSH(tmp1, tmp2, A64_SP), ctx);
164 /* Set up BPF stack */
165 emit(A64_SUB_I(1, A64_SP, A64_SP, stack_size), ctx);
167 /* Set up frame pointer */
168 emit(A64_MOV(1, fp, A64_SP), ctx);
170 /* Clear registers A and X */
171 emit_a64_mov_i64(ra, 0, ctx);
172 emit_a64_mov_i64(rx, 0, ctx);
175 static void build_epilogue(struct jit_ctx *ctx)
177 const u8 r0 = bpf2a64[BPF_REG_0];
178 const u8 r6 = bpf2a64[BPF_REG_6];
179 const u8 r7 = bpf2a64[BPF_REG_7];
180 const u8 r8 = bpf2a64[BPF_REG_8];
181 const u8 r9 = bpf2a64[BPF_REG_9];
182 const u8 fp = bpf2a64[BPF_REG_FP];
183 const u8 tmp1 = bpf2a64[TMP_REG_1];
184 const u8 tmp2 = bpf2a64[TMP_REG_2];
185 int stack_size = MAX_BPF_STACK;
187 stack_size += 4; /* extra for skb_copy_bits buffer */
188 stack_size = STACK_ALIGN(stack_size);
190 /* We're done with BPF stack */
191 emit(A64_ADD_I(1, A64_SP, A64_SP, stack_size), ctx);
193 /* Restore callee-saved register */
195 emit(A64_POP(tmp1, tmp2, A64_SP), ctx);
196 emit(A64_POP(r8, r9, A64_SP), ctx);
197 emit(A64_POP(r6, r7, A64_SP), ctx);
199 /* Restore frame pointer */
200 emit(A64_MOV(1, fp, A64_SP), ctx);
202 /* Set return value */
203 emit(A64_MOV(1, A64_R(0), r0), ctx);
205 emit(A64_RET(A64_LR), ctx);
208 /* JITs an eBPF instruction.
210 * 0 - successfully JITed an 8-byte eBPF instruction.
211 * >0 - successfully JITed a 16-byte eBPF instruction.
212 * <0 - failed to JIT.
214 static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx)
216 const u8 code = insn->code;
217 const u8 dst = bpf2a64[insn->dst_reg];
218 const u8 src = bpf2a64[insn->src_reg];
219 const u8 tmp = bpf2a64[TMP_REG_1];
220 const u8 tmp2 = bpf2a64[TMP_REG_2];
221 const s16 off = insn->off;
222 const s32 imm = insn->imm;
223 const int i = insn - ctx->prog->insnsi;
224 const bool is64 = BPF_CLASS(code) == BPF_ALU64;
228 #define check_imm(bits, imm) do { \
229 if ((((imm) > 0) && ((imm) >> (bits))) || \
230 (((imm) < 0) && (~(imm) >> (bits)))) { \
231 pr_info("[%2d] imm=%d(0x%x) out of range\n", \
236 #define check_imm19(imm) check_imm(19, imm)
237 #define check_imm26(imm) check_imm(26, imm)
241 case BPF_ALU | BPF_MOV | BPF_X:
242 case BPF_ALU64 | BPF_MOV | BPF_X:
243 emit(A64_MOV(is64, dst, src), ctx);
245 /* dst = dst OP src */
246 case BPF_ALU | BPF_ADD | BPF_X:
247 case BPF_ALU64 | BPF_ADD | BPF_X:
248 emit(A64_ADD(is64, dst, dst, src), ctx);
250 case BPF_ALU | BPF_SUB | BPF_X:
251 case BPF_ALU64 | BPF_SUB | BPF_X:
252 emit(A64_SUB(is64, dst, dst, src), ctx);
254 case BPF_ALU | BPF_AND | BPF_X:
255 case BPF_ALU64 | BPF_AND | BPF_X:
256 emit(A64_AND(is64, dst, dst, src), ctx);
258 case BPF_ALU | BPF_OR | BPF_X:
259 case BPF_ALU64 | BPF_OR | BPF_X:
260 emit(A64_ORR(is64, dst, dst, src), ctx);
262 case BPF_ALU | BPF_XOR | BPF_X:
263 case BPF_ALU64 | BPF_XOR | BPF_X:
264 emit(A64_EOR(is64, dst, dst, src), ctx);
266 case BPF_ALU | BPF_MUL | BPF_X:
267 case BPF_ALU64 | BPF_MUL | BPF_X:
268 emit(A64_MUL(is64, dst, dst, src), ctx);
270 case BPF_ALU | BPF_DIV | BPF_X:
271 case BPF_ALU64 | BPF_DIV | BPF_X:
273 const u8 r0 = bpf2a64[BPF_REG_0];
275 /* if (src == 0) return 0 */
276 jmp_offset = 3; /* skip ahead to else path */
277 check_imm19(jmp_offset);
278 emit(A64_CBNZ(is64, src, jmp_offset), ctx);
279 emit(A64_MOVZ(1, r0, 0, 0), ctx);
280 jmp_offset = epilogue_offset(ctx);
281 check_imm26(jmp_offset);
282 emit(A64_B(jmp_offset), ctx);
284 emit(A64_UDIV(is64, dst, dst, src), ctx);
287 case BPF_ALU | BPF_MOD | BPF_X:
288 case BPF_ALU64 | BPF_MOD | BPF_X:
290 emit(A64_UDIV(is64, tmp, dst, src), ctx);
291 emit(A64_MUL(is64, tmp, tmp, src), ctx);
292 emit(A64_SUB(is64, dst, dst, tmp), ctx);
294 case BPF_ALU | BPF_LSH | BPF_X:
295 case BPF_ALU64 | BPF_LSH | BPF_X:
296 emit(A64_LSLV(is64, dst, dst, src), ctx);
298 case BPF_ALU | BPF_RSH | BPF_X:
299 case BPF_ALU64 | BPF_RSH | BPF_X:
300 emit(A64_LSRV(is64, dst, dst, src), ctx);
302 case BPF_ALU | BPF_ARSH | BPF_X:
303 case BPF_ALU64 | BPF_ARSH | BPF_X:
304 emit(A64_ASRV(is64, dst, dst, src), ctx);
307 case BPF_ALU | BPF_NEG:
308 case BPF_ALU64 | BPF_NEG:
309 emit(A64_NEG(is64, dst, dst), ctx);
311 /* dst = BSWAP##imm(dst) */
312 case BPF_ALU | BPF_END | BPF_FROM_LE:
313 case BPF_ALU | BPF_END | BPF_FROM_BE:
314 #ifdef CONFIG_CPU_BIG_ENDIAN
315 if (BPF_SRC(code) == BPF_FROM_BE)
317 #else /* !CONFIG_CPU_BIG_ENDIAN */
318 if (BPF_SRC(code) == BPF_FROM_LE)
323 emit(A64_REV16(is64, dst, dst), ctx);
324 /* zero-extend 16 bits into 64 bits */
325 emit(A64_UXTH(is64, dst, dst), ctx);
328 emit(A64_REV32(is64, dst, dst), ctx);
329 /* upper 32 bits already cleared */
332 emit(A64_REV64(dst, dst), ctx);
339 /* zero-extend 16 bits into 64 bits */
340 emit(A64_UXTH(is64, dst, dst), ctx);
343 /* zero-extend 32 bits into 64 bits */
344 emit(A64_UXTW(is64, dst, dst), ctx);
352 case BPF_ALU | BPF_MOV | BPF_K:
353 case BPF_ALU64 | BPF_MOV | BPF_K:
354 emit_a64_mov_i(is64, dst, imm, ctx);
356 /* dst = dst OP imm */
357 case BPF_ALU | BPF_ADD | BPF_K:
358 case BPF_ALU64 | BPF_ADD | BPF_K:
360 emit_a64_mov_i(is64, tmp, imm, ctx);
361 emit(A64_ADD(is64, dst, dst, tmp), ctx);
363 case BPF_ALU | BPF_SUB | BPF_K:
364 case BPF_ALU64 | BPF_SUB | BPF_K:
366 emit_a64_mov_i(is64, tmp, imm, ctx);
367 emit(A64_SUB(is64, dst, dst, tmp), ctx);
369 case BPF_ALU | BPF_AND | BPF_K:
370 case BPF_ALU64 | BPF_AND | BPF_K:
372 emit_a64_mov_i(is64, tmp, imm, ctx);
373 emit(A64_AND(is64, dst, dst, tmp), ctx);
375 case BPF_ALU | BPF_OR | BPF_K:
376 case BPF_ALU64 | BPF_OR | BPF_K:
378 emit_a64_mov_i(is64, tmp, imm, ctx);
379 emit(A64_ORR(is64, dst, dst, tmp), ctx);
381 case BPF_ALU | BPF_XOR | BPF_K:
382 case BPF_ALU64 | BPF_XOR | BPF_K:
384 emit_a64_mov_i(is64, tmp, imm, ctx);
385 emit(A64_EOR(is64, dst, dst, tmp), ctx);
387 case BPF_ALU | BPF_MUL | BPF_K:
388 case BPF_ALU64 | BPF_MUL | BPF_K:
390 emit_a64_mov_i(is64, tmp, imm, ctx);
391 emit(A64_MUL(is64, dst, dst, tmp), ctx);
393 case BPF_ALU | BPF_DIV | BPF_K:
394 case BPF_ALU64 | BPF_DIV | BPF_K:
396 emit_a64_mov_i(is64, tmp, imm, ctx);
397 emit(A64_UDIV(is64, dst, dst, tmp), ctx);
399 case BPF_ALU | BPF_MOD | BPF_K:
400 case BPF_ALU64 | BPF_MOD | BPF_K:
402 emit_a64_mov_i(is64, tmp2, imm, ctx);
403 emit(A64_UDIV(is64, tmp, dst, tmp2), ctx);
404 emit(A64_MUL(is64, tmp, tmp, tmp2), ctx);
405 emit(A64_SUB(is64, dst, dst, tmp), ctx);
407 case BPF_ALU | BPF_LSH | BPF_K:
408 case BPF_ALU64 | BPF_LSH | BPF_K:
409 emit(A64_LSL(is64, dst, dst, imm), ctx);
411 case BPF_ALU | BPF_RSH | BPF_K:
412 case BPF_ALU64 | BPF_RSH | BPF_K:
413 emit(A64_LSR(is64, dst, dst, imm), ctx);
415 case BPF_ALU | BPF_ARSH | BPF_K:
416 case BPF_ALU64 | BPF_ARSH | BPF_K:
417 emit(A64_ASR(is64, dst, dst, imm), ctx);
421 case BPF_JMP | BPF_JA:
422 jmp_offset = bpf2a64_offset(i + off, i, ctx);
423 check_imm26(jmp_offset);
424 emit(A64_B(jmp_offset), ctx);
426 /* IF (dst COND src) JUMP off */
427 case BPF_JMP | BPF_JEQ | BPF_X:
428 case BPF_JMP | BPF_JGT | BPF_X:
429 case BPF_JMP | BPF_JGE | BPF_X:
430 case BPF_JMP | BPF_JNE | BPF_X:
431 case BPF_JMP | BPF_JSGT | BPF_X:
432 case BPF_JMP | BPF_JSGE | BPF_X:
433 emit(A64_CMP(1, dst, src), ctx);
435 jmp_offset = bpf2a64_offset(i + off, i, ctx);
436 check_imm19(jmp_offset);
437 switch (BPF_OP(code)) {
439 jmp_cond = A64_COND_EQ;
442 jmp_cond = A64_COND_HI;
445 jmp_cond = A64_COND_CS;
448 jmp_cond = A64_COND_NE;
451 jmp_cond = A64_COND_GT;
454 jmp_cond = A64_COND_GE;
459 emit(A64_B_(jmp_cond, jmp_offset), ctx);
461 case BPF_JMP | BPF_JSET | BPF_X:
462 emit(A64_TST(1, dst, src), ctx);
464 /* IF (dst COND imm) JUMP off */
465 case BPF_JMP | BPF_JEQ | BPF_K:
466 case BPF_JMP | BPF_JGT | BPF_K:
467 case BPF_JMP | BPF_JGE | BPF_K:
468 case BPF_JMP | BPF_JNE | BPF_K:
469 case BPF_JMP | BPF_JSGT | BPF_K:
470 case BPF_JMP | BPF_JSGE | BPF_K:
472 emit_a64_mov_i(1, tmp, imm, ctx);
473 emit(A64_CMP(1, dst, tmp), ctx);
475 case BPF_JMP | BPF_JSET | BPF_K:
477 emit_a64_mov_i(1, tmp, imm, ctx);
478 emit(A64_TST(1, dst, tmp), ctx);
481 case BPF_JMP | BPF_CALL:
483 const u8 r0 = bpf2a64[BPF_REG_0];
484 const u64 func = (u64)__bpf_call_base + imm;
487 emit_a64_mov_i64(tmp, func, ctx);
488 emit(A64_PUSH(A64_FP, A64_LR, A64_SP), ctx);
489 emit(A64_MOV(1, A64_FP, A64_SP), ctx);
490 emit(A64_BLR(tmp), ctx);
491 emit(A64_MOV(1, r0, A64_R(0)), ctx);
492 emit(A64_POP(A64_FP, A64_LR, A64_SP), ctx);
495 /* function return */
496 case BPF_JMP | BPF_EXIT:
497 /* Optimization: when last instruction is EXIT,
498 simply fallthrough to epilogue. */
499 if (i == ctx->prog->len - 1)
501 jmp_offset = epilogue_offset(ctx);
502 check_imm26(jmp_offset);
503 emit(A64_B(jmp_offset), ctx);
507 case BPF_LD | BPF_IMM | BPF_DW:
509 const struct bpf_insn insn1 = insn[1];
512 if (insn1.code != 0 || insn1.src_reg != 0 ||
513 insn1.dst_reg != 0 || insn1.off != 0) {
514 /* Note: verifier in BPF core must catch invalid
517 pr_err_once("Invalid BPF_LD_IMM64 instruction\n");
521 imm64 = (u64)insn1.imm << 32 | (u32)imm;
522 emit_a64_mov_i64(dst, imm64, ctx);
527 /* LDX: dst = *(size *)(src + off) */
528 case BPF_LDX | BPF_MEM | BPF_W:
529 case BPF_LDX | BPF_MEM | BPF_H:
530 case BPF_LDX | BPF_MEM | BPF_B:
531 case BPF_LDX | BPF_MEM | BPF_DW:
533 emit_a64_mov_i(1, tmp, off, ctx);
534 switch (BPF_SIZE(code)) {
536 emit(A64_LDR32(dst, src, tmp), ctx);
539 emit(A64_LDRH(dst, src, tmp), ctx);
542 emit(A64_LDRB(dst, src, tmp), ctx);
545 emit(A64_LDR64(dst, src, tmp), ctx);
550 /* ST: *(size *)(dst + off) = imm */
551 case BPF_ST | BPF_MEM | BPF_W:
552 case BPF_ST | BPF_MEM | BPF_H:
553 case BPF_ST | BPF_MEM | BPF_B:
554 case BPF_ST | BPF_MEM | BPF_DW:
557 /* STX: *(size *)(dst + off) = src */
558 case BPF_STX | BPF_MEM | BPF_W:
559 case BPF_STX | BPF_MEM | BPF_H:
560 case BPF_STX | BPF_MEM | BPF_B:
561 case BPF_STX | BPF_MEM | BPF_DW:
563 emit_a64_mov_i(1, tmp, off, ctx);
564 switch (BPF_SIZE(code)) {
566 emit(A64_STR32(src, dst, tmp), ctx);
569 emit(A64_STRH(src, dst, tmp), ctx);
572 emit(A64_STRB(src, dst, tmp), ctx);
575 emit(A64_STR64(src, dst, tmp), ctx);
579 /* STX XADD: lock *(u32 *)(dst + off) += src */
580 case BPF_STX | BPF_XADD | BPF_W:
581 /* STX XADD: lock *(u64 *)(dst + off) += src */
582 case BPF_STX | BPF_XADD | BPF_DW:
585 /* R0 = ntohx(*(size *)(((struct sk_buff *)R6)->data + imm)) */
586 case BPF_LD | BPF_ABS | BPF_W:
587 case BPF_LD | BPF_ABS | BPF_H:
588 case BPF_LD | BPF_ABS | BPF_B:
589 /* R0 = ntohx(*(size *)(((struct sk_buff *)R6)->data + src + imm)) */
590 case BPF_LD | BPF_IND | BPF_W:
591 case BPF_LD | BPF_IND | BPF_H:
592 case BPF_LD | BPF_IND | BPF_B:
594 const u8 r0 = bpf2a64[BPF_REG_0]; /* r0 = return value */
595 const u8 r6 = bpf2a64[BPF_REG_6]; /* r6 = pointer to sk_buff */
596 const u8 fp = bpf2a64[BPF_REG_FP];
597 const u8 r1 = bpf2a64[BPF_REG_1]; /* r1: struct sk_buff *skb */
598 const u8 r2 = bpf2a64[BPF_REG_2]; /* r2: int k */
599 const u8 r3 = bpf2a64[BPF_REG_3]; /* r3: unsigned int size */
600 const u8 r4 = bpf2a64[BPF_REG_4]; /* r4: void *buffer */
601 const u8 r5 = bpf2a64[BPF_REG_5]; /* r5: void *(*func)(...) */
604 emit(A64_MOV(1, r1, r6), ctx);
605 emit_a64_mov_i(0, r2, imm, ctx);
606 if (BPF_MODE(code) == BPF_IND)
607 emit(A64_ADD(0, r2, r2, src), ctx);
608 switch (BPF_SIZE(code)) {
621 emit_a64_mov_i64(r3, size, ctx);
622 emit(A64_ADD_I(1, r4, fp, MAX_BPF_STACK), ctx);
623 emit_a64_mov_i64(r5, (unsigned long)bpf_load_pointer, ctx);
624 emit(A64_PUSH(A64_FP, A64_LR, A64_SP), ctx);
625 emit(A64_MOV(1, A64_FP, A64_SP), ctx);
626 emit(A64_BLR(r5), ctx);
627 emit(A64_MOV(1, r0, A64_R(0)), ctx);
628 emit(A64_POP(A64_FP, A64_LR, A64_SP), ctx);
630 jmp_offset = epilogue_offset(ctx);
631 check_imm19(jmp_offset);
632 emit(A64_CBZ(1, r0, jmp_offset), ctx);
633 emit(A64_MOV(1, r5, r0), ctx);
634 switch (BPF_SIZE(code)) {
636 emit(A64_LDR32(r0, r5, A64_ZR), ctx);
637 #ifndef CONFIG_CPU_BIG_ENDIAN
638 emit(A64_REV32(0, r0, r0), ctx);
642 emit(A64_LDRH(r0, r5, A64_ZR), ctx);
643 #ifndef CONFIG_CPU_BIG_ENDIAN
644 emit(A64_REV16(0, r0, r0), ctx);
648 emit(A64_LDRB(r0, r5, A64_ZR), ctx);
654 pr_info_once("*** NOT YET: opcode %02x ***\n", code);
658 pr_err_once("unknown opcode %02x\n", code);
665 static int build_body(struct jit_ctx *ctx)
667 const struct bpf_prog *prog = ctx->prog;
670 for (i = 0; i < prog->len; i++) {
671 const struct bpf_insn *insn = &prog->insnsi[i];
674 ret = build_insn(insn, ctx);
676 if (ctx->image == NULL)
677 ctx->offset[i] = ctx->idx;
690 static inline void bpf_flush_icache(void *start, void *end)
692 flush_icache_range((unsigned long)start, (unsigned long)end);
695 void bpf_jit_compile(struct bpf_prog *prog)
697 /* Nothing to do here. We support Internal BPF. */
700 void bpf_int_jit_compile(struct bpf_prog *prog)
702 struct bpf_binary_header *header;
710 if (!prog || !prog->len)
713 memset(&ctx, 0, sizeof(ctx));
716 ctx.offset = kcalloc(prog->len, sizeof(int), GFP_KERNEL);
717 if (ctx.offset == NULL)
720 /* 1. Initial fake pass to compute ctx->idx. */
722 /* Fake pass to fill in ctx->offset and ctx->tmp_used. */
723 if (build_body(&ctx))
726 build_prologue(&ctx);
728 ctx.epilogue_offset = ctx.idx;
729 build_epilogue(&ctx);
731 /* Now we know the actual image size. */
732 image_size = sizeof(u32) * ctx.idx;
733 header = bpf_jit_binary_alloc(image_size, &image_ptr,
734 sizeof(u32), jit_fill_hole);
738 /* 2. Now, the actual pass. */
740 ctx.image = (u32 *)image_ptr;
743 build_prologue(&ctx);
745 if (build_body(&ctx)) {
746 bpf_jit_binary_free(header);
750 build_epilogue(&ctx);
752 /* And we're done. */
753 if (bpf_jit_enable > 1)
754 bpf_jit_dump(prog->len, image_size, 2, ctx.image);
756 bpf_flush_icache(ctx.image, ctx.image + ctx.idx);
758 set_memory_ro((unsigned long)header, header->pages);
759 prog->bpf_func = (void *)ctx.image;
765 void bpf_jit_free(struct bpf_prog *prog)
767 unsigned long addr = (unsigned long)prog->bpf_func & PAGE_MASK;
768 struct bpf_binary_header *header = (void *)addr;
773 set_memory_rw(addr, header->pages);
774 bpf_jit_binary_free(header);
777 bpf_prog_unlock_free(prog);