arch/arm64/kernel/perf_event.c

   1 /*
   2  * PMU support
   3  *
   4  * Copyright (C) 2012 ARM Limited
   5  * Author: Will Deacon <will.deacon@arm.com>
   6  *
   7  * This code is based heavily on the ARMv7 perf event code.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include <asm/irq_regs.h>
  23 #include <asm/perf_event.h>
  24 #include <asm/sysreg.h>
  25 #include <asm/virt.h>
  26
  27 #include <linux/of.h>
  28 #include <linux/perf/arm_pmu.h>
  29 #include <linux/platform_device.h>
  30
  31 /*
  32  * ARMv8 PMUv3 Performance Events handling code.
  33  * Common event types.
  34  */
  35
  36 /* Required events. */
  37 #define ARMV8_PMUV3_PERFCTR_SW_INCR                             0x00
  38 #define ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL                    0x03
  39 #define ARMV8_PMUV3_PERFCTR_L1D_CACHE                           0x04
  40 #define ARMV8_PMUV3_PERFCTR_BR_MIS_PRED                         0x10
  41 #define ARMV8_PMUV3_PERFCTR_CPU_CYCLES                          0x11
  42 #define ARMV8_PMUV3_PERFCTR_BR_PRED                             0x12
  43
  44 /* At least one of the following is required. */
  45 #define ARMV8_PMUV3_PERFCTR_INST_RETIRED                        0x08
  46 #define ARMV8_PMUV3_PERFCTR_INST_SPEC                           0x1B
  47
  48 /* Common architectural events. */
  49 #define ARMV8_PMUV3_PERFCTR_LD_RETIRED                          0x06
  50 #define ARMV8_PMUV3_PERFCTR_ST_RETIRED                          0x07
  51 #define ARMV8_PMUV3_PERFCTR_EXC_TAKEN                           0x09
  52 #define ARMV8_PMUV3_PERFCTR_EXC_RETURN                          0x0A
  53 #define ARMV8_PMUV3_PERFCTR_CID_WRITE_RETIRED                   0x0B
  54 #define ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED                    0x0C
  55 #define ARMV8_PMUV3_PERFCTR_BR_IMMED_RETIRED                    0x0D
  56 #define ARMV8_PMUV3_PERFCTR_BR_RETURN_RETIRED                   0x0E
  57 #define ARMV8_PMUV3_PERFCTR_UNALIGNED_LDST_RETIRED              0x0F
  58 #define ARMV8_PMUV3_PERFCTR_TTBR_WRITE_RETIRED                  0x1C
  59 #define ARMV8_PMUV3_PERFCTR_CHAIN                               0x1E
  60 #define ARMV8_PMUV3_PERFCTR_BR_RETIRED                          0x21
  61
  62 /* Common microarchitectural events. */
  63 #define ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL                    0x01
  64 #define ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL                      0x02
  65 #define ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL                      0x05
  66 #define ARMV8_PMUV3_PERFCTR_MEM_ACCESS                          0x13
  67 #define ARMV8_PMUV3_PERFCTR_L1I_CACHE                           0x14
  68 #define ARMV8_PMUV3_PERFCTR_L1D_CACHE_WB                        0x15
  69 #define ARMV8_PMUV3_PERFCTR_L2D_CACHE                           0x16
  70 #define ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL                    0x17
  71 #define ARMV8_PMUV3_PERFCTR_L2D_CACHE_WB                        0x18
  72 #define ARMV8_PMUV3_PERFCTR_BUS_ACCESS                          0x19
  73 #define ARMV8_PMUV3_PERFCTR_MEMORY_ERROR                        0x1A
  74 #define ARMV8_PMUV3_PERFCTR_BUS_CYCLES                          0x1D
  75 #define ARMV8_PMUV3_PERFCTR_L1D_CACHE_ALLOCATE                  0x1F
  76 #define ARMV8_PMUV3_PERFCTR_L2D_CACHE_ALLOCATE                  0x20
  77 #define ARMV8_PMUV3_PERFCTR_BR_MIS_PRED_RETIRED                 0x22
  78 #define ARMV8_PMUV3_PERFCTR_STALL_FRONTEND                      0x23
  79 #define ARMV8_PMUV3_PERFCTR_STALL_BACKEND                       0x24
  80 #define ARMV8_PMUV3_PERFCTR_L1D_TLB                             0x25
  81 #define ARMV8_PMUV3_PERFCTR_L1I_TLB                             0x26
  82 #define ARMV8_PMUV3_PERFCTR_L2I_CACHE                           0x27
  83 #define ARMV8_PMUV3_PERFCTR_L2I_CACHE_REFILL                    0x28
  84 #define ARMV8_PMUV3_PERFCTR_L3D_CACHE_ALLOCATE                  0x29
  85 #define ARMV8_PMUV3_PERFCTR_L3D_CACHE_REFILL                    0x2A
  86 #define ARMV8_PMUV3_PERFCTR_L3D_CACHE                           0x2B
  87 #define ARMV8_PMUV3_PERFCTR_L3D_CACHE_WB                        0x2C
  88 #define ARMV8_PMUV3_PERFCTR_L2D_TLB_REFILL                      0x2D
  89 #define ARMV8_PMUV3_PERFCTR_L2I_TLB_REFILL                      0x2E
  90 #define ARMV8_PMUV3_PERFCTR_L2D_TLB                             0x2F
  91 #define ARMV8_PMUV3_PERFCTR_L2I_TLB                             0x30
  92
  93 /* ARMv8 recommended implementation defined event types */
  94 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD                       0x40
  95 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR                       0x41
  96 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD                0x42
  97 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR                0x43
  98 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_INNER             0x44
  99 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_OUTER             0x45
 100 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WB_VICTIM                0x46
 101 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WB_CLEAN                 0x47
 102 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_INVAL                    0x48
 103
 104 #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD                  0x4C
 105 #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR                  0x4D
 106 #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD                         0x4E
 107 #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR                         0x4F
 108 #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_RD                       0x50
 109 #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WR                       0x51
 110 #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_REFILL_RD                0x52
 111 #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_REFILL_WR                0x53
 112
 113 #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WB_VICTIM                0x56
 114 #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WB_CLEAN                 0x57
 115 #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_INVAL                    0x58
 116
 117 #define ARMV8_IMPDEF_PERFCTR_L2D_TLB_REFILL_RD                  0x5C
 118 #define ARMV8_IMPDEF_PERFCTR_L2D_TLB_REFILL_WR                  0x5D
 119 #define ARMV8_IMPDEF_PERFCTR_L2D_TLB_RD                         0x5E
 120 #define ARMV8_IMPDEF_PERFCTR_L2D_TLB_WR                         0x5F
 121
 122 #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD                      0x60
 123 #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR                      0x61
 124 #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_SHARED                  0x62
 125 #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_NOT_SHARED              0x63
 126 #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_NORMAL                  0x64
 127 #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_PERIPH                  0x65
 128
 129 #define ARMV8_IMPDEF_PERFCTR_MEM_ACCESS_RD                      0x66
 130 #define ARMV8_IMPDEF_PERFCTR_MEM_ACCESS_WR                      0x67
 131 #define ARMV8_IMPDEF_PERFCTR_UNALIGNED_LD_SPEC                  0x68
 132 #define ARMV8_IMPDEF_PERFCTR_UNALIGNED_ST_SPEC                  0x69
 133 #define ARMV8_IMPDEF_PERFCTR_UNALIGNED_LDST_SPEC                0x6A
 134
 135 #define ARMV8_IMPDEF_PERFCTR_LDREX_SPEC                         0x6C
 136 #define ARMV8_IMPDEF_PERFCTR_STREX_PASS_SPEC                    0x6D
 137 #define ARMV8_IMPDEF_PERFCTR_STREX_FAIL_SPEC                    0x6E
 138 #define ARMV8_IMPDEF_PERFCTR_STREX_SPEC                         0x6F
 139 #define ARMV8_IMPDEF_PERFCTR_LD_SPEC                            0x70
 140 #define ARMV8_IMPDEF_PERFCTR_ST_SPEC                            0x71
 141 #define ARMV8_IMPDEF_PERFCTR_LDST_SPEC                          0x72
 142 #define ARMV8_IMPDEF_PERFCTR_DP_SPEC                            0x73
 143 #define ARMV8_IMPDEF_PERFCTR_ASE_SPEC                           0x74
 144 #define ARMV8_IMPDEF_PERFCTR_VFP_SPEC                           0x75
 145 #define ARMV8_IMPDEF_PERFCTR_PC_WRITE_SPEC                      0x76
 146 #define ARMV8_IMPDEF_PERFCTR_CRYPTO_SPEC                        0x77
 147 #define ARMV8_IMPDEF_PERFCTR_BR_IMMED_SPEC                      0x78
 148 #define ARMV8_IMPDEF_PERFCTR_BR_RETURN_SPEC                     0x79
 149 #define ARMV8_IMPDEF_PERFCTR_BR_INDIRECT_SPEC                   0x7A
 150
 151 #define ARMV8_IMPDEF_PERFCTR_ISB_SPEC                           0x7C
 152 #define ARMV8_IMPDEF_PERFCTR_DSB_SPEC                           0x7D
 153 #define ARMV8_IMPDEF_PERFCTR_DMB_SPEC                           0x7E
 154
 155 #define ARMV8_IMPDEF_PERFCTR_EXC_UNDEF                          0x81
 156 #define ARMV8_IMPDEF_PERFCTR_EXC_SVC                            0x82
 157 #define ARMV8_IMPDEF_PERFCTR_EXC_PABORT                         0x83
 158 #define ARMV8_IMPDEF_PERFCTR_EXC_DABORT                         0x84
 159
 160 #define ARMV8_IMPDEF_PERFCTR_EXC_IRQ                            0x86
 161 #define ARMV8_IMPDEF_PERFCTR_EXC_FIQ                            0x87
 162 #define ARMV8_IMPDEF_PERFCTR_EXC_SMC                            0x88
 163
 164 #define ARMV8_IMPDEF_PERFCTR_EXC_HVC                            0x8A
 165 #define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_PABORT                    0x8B
 166 #define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_DABORT                    0x8C
 167 #define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_OTHER                     0x8D
 168 #define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_IRQ                       0x8E
 169 #define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_FIQ                       0x8F
 170 #define ARMV8_IMPDEF_PERFCTR_RC_LD_SPEC                         0x90
 171 #define ARMV8_IMPDEF_PERFCTR_RC_ST_SPEC                         0x91
 172
 173 #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_RD                       0xA0
 174 #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WR                       0xA1
 175 #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_REFILL_RD                0xA2
 176 #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_REFILL_WR                0xA3
 177
 178 #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WB_VICTIM                0xA6
 179 #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WB_CLEAN                 0xA7
 180 #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_INVAL                    0xA8
 181
 182 /* ARMv8 Cortex-A53 specific event types. */
 183 #define ARMV8_A53_PERFCTR_PREF_LINEFILL                         0xC2
 184
 185 /* ARMv8 Cavium ThunderX specific event types. */
 186 #define ARMV8_THUNDER_PERFCTR_L1D_CACHE_MISS_ST                 0xE9
 187 #define ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_ACCESS             0xEA
 188 #define ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_MISS               0xEB
 189 #define ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_ACCESS             0xEC
 190 #define ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_MISS               0xED
 191
 192 /* PMUv3 HW events mapping. */
 193 static const unsigned armv8_pmuv3_perf_map[PERF_COUNT_HW_MAX] = {
 194         PERF_MAP_ALL_UNSUPPORTED,
 195         [PERF_COUNT_HW_CPU_CYCLES]              = ARMV8_PMUV3_PERFCTR_CPU_CYCLES,
 196         [PERF_COUNT_HW_INSTRUCTIONS]            = ARMV8_PMUV3_PERFCTR_INST_RETIRED,
 197         [PERF_COUNT_HW_CACHE_REFERENCES]        = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
 198         [PERF_COUNT_HW_CACHE_MISSES]            = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
 199         [PERF_COUNT_HW_BRANCH_MISSES]           = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
 200 };
 201
 202 /* ARM Cortex-A53 HW events mapping. */
 203 static const unsigned armv8_a53_perf_map[PERF_COUNT_HW_MAX] = {
 204         PERF_MAP_ALL_UNSUPPORTED,
 205         [PERF_COUNT_HW_CPU_CYCLES]              = ARMV8_PMUV3_PERFCTR_CPU_CYCLES,
 206         [PERF_COUNT_HW_INSTRUCTIONS]            = ARMV8_PMUV3_PERFCTR_INST_RETIRED,
 207         [PERF_COUNT_HW_CACHE_REFERENCES]        = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
 208         [PERF_COUNT_HW_CACHE_MISSES]            = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
 209         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED,
 210         [PERF_COUNT_HW_BRANCH_MISSES]           = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
 211         [PERF_COUNT_HW_BUS_CYCLES]              = ARMV8_PMUV3_PERFCTR_BUS_CYCLES,
 212 };
 213
 214 /* ARM Cortex-A57 and Cortex-A72 events mapping. */
 215 static const unsigned armv8_a57_perf_map[PERF_COUNT_HW_MAX] = {
 216         PERF_MAP_ALL_UNSUPPORTED,
 217         [PERF_COUNT_HW_CPU_CYCLES]              = ARMV8_PMUV3_PERFCTR_CPU_CYCLES,
 218         [PERF_COUNT_HW_INSTRUCTIONS]            = ARMV8_PMUV3_PERFCTR_INST_RETIRED,
 219         [PERF_COUNT_HW_CACHE_REFERENCES]        = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
 220         [PERF_COUNT_HW_CACHE_MISSES]            = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
 221         [PERF_COUNT_HW_BRANCH_MISSES]           = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
 222         [PERF_COUNT_HW_BUS_CYCLES]              = ARMV8_PMUV3_PERFCTR_BUS_CYCLES,
 223 };
 224
 225 static const unsigned armv8_thunder_perf_map[PERF_COUNT_HW_MAX] = {
 226         PERF_MAP_ALL_UNSUPPORTED,
 227         [PERF_COUNT_HW_CPU_CYCLES]              = ARMV8_PMUV3_PERFCTR_CPU_CYCLES,
 228         [PERF_COUNT_HW_INSTRUCTIONS]            = ARMV8_PMUV3_PERFCTR_INST_RETIRED,
 229         [PERF_COUNT_HW_CACHE_REFERENCES]        = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
 230         [PERF_COUNT_HW_CACHE_MISSES]            = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
 231         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED,
 232         [PERF_COUNT_HW_BRANCH_MISSES]           = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
 233         [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV8_PMUV3_PERFCTR_STALL_FRONTEND,
 234         [PERF_COUNT_HW_STALLED_CYCLES_BACKEND]  = ARMV8_PMUV3_PERFCTR_STALL_BACKEND,
 235 };
 236
 237 static const unsigned armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 238                                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 239                                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
 240         PERF_CACHE_MAP_ALL_UNSUPPORTED,
 241
 242         [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
 243         [C(L1D)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
 244         [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
 245         [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
 246
 247         [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_BR_PRED,
 248         [C(BPU)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
 249         [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
 250         [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
 251 };
 252
 253 static const unsigned armv8_a53_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 254                                               [PERF_COUNT_HW_CACHE_OP_MAX]
 255                                               [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
 256         PERF_CACHE_MAP_ALL_UNSUPPORTED,
 257
 258         [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
 259         [C(L1D)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
 260         [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
 261         [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
 262         [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_A53_PERFCTR_PREF_LINEFILL,
 263
 264         [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
 265         [C(L1I)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
 266
 267         [C(ITLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL,
 268
 269         [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_BR_PRED,
 270         [C(BPU)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
 271         [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
 272         [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
 273 };
 274
 275 static const unsigned armv8_a57_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 276                                               [PERF_COUNT_HW_CACHE_OP_MAX]
 277                                               [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
 278         PERF_CACHE_MAP_ALL_UNSUPPORTED,
 279
 280         [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
 281         [C(L1D)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
 282         [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
 283         [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR,
 284
 285         [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
 286         [C(L1I)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
 287
 288         [C(DTLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
 289         [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)]  = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
 290
 291         [C(ITLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL,
 292
 293         [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_BR_PRED,
 294         [C(BPU)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
 295         [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
 296         [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
 297 };
 298
 299 static const unsigned armv8_thunder_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 300                                                    [PERF_COUNT_HW_CACHE_OP_MAX]
 301                                                    [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
 302         PERF_CACHE_MAP_ALL_UNSUPPORTED,
 303
 304         [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
 305         [C(L1D)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
 306         [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
 307         [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_THUNDER_PERFCTR_L1D_CACHE_MISS_ST,
 308         [C(L1D)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_ACCESS,
 309         [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_MISS,
 310
 311         [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
 312         [C(L1I)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
 313         [C(L1I)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_ACCESS,
 314         [C(L1I)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_MISS,
 315
 316         [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD,
 317         [C(DTLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
 318         [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR,
 319         [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)]  = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
 320
 321         [C(ITLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL,
 322
 323         [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_BR_PRED,
 324         [C(BPU)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
 325         [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
 326         [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
 327 };
 328
 329 #define ARMV8_EVENT_ATTR_RESOLVE(m) #m
 330 #define ARMV8_EVENT_ATTR(name, config) \
 331         PMU_EVENT_ATTR_STRING(name, armv8_event_attr_##name, \
 332                               "event=" ARMV8_EVENT_ATTR_RESOLVE(config))
 333
 334 ARMV8_EVENT_ATTR(sw_incr, ARMV8_PMUV3_PERFCTR_SW_INCR);
 335 ARMV8_EVENT_ATTR(l1i_cache_refill, ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL);
 336 ARMV8_EVENT_ATTR(l1i_tlb_refill, ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL);
 337 ARMV8_EVENT_ATTR(l1d_cache_refill, ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL);
 338 ARMV8_EVENT_ATTR(l1d_cache, ARMV8_PMUV3_PERFCTR_L1D_CACHE);
 339 ARMV8_EVENT_ATTR(l1d_tlb_refill, ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL);
 340 ARMV8_EVENT_ATTR(ld_retired, ARMV8_PMUV3_PERFCTR_LD_RETIRED);
 341 ARMV8_EVENT_ATTR(st_retired, ARMV8_PMUV3_PERFCTR_ST_RETIRED);
 342 ARMV8_EVENT_ATTR(inst_retired, ARMV8_PMUV3_PERFCTR_INST_RETIRED);
 343 ARMV8_EVENT_ATTR(exc_taken, ARMV8_PMUV3_PERFCTR_EXC_TAKEN);
 344 ARMV8_EVENT_ATTR(exc_return, ARMV8_PMUV3_PERFCTR_EXC_RETURN);
 345 ARMV8_EVENT_ATTR(cid_write_retired, ARMV8_PMUV3_PERFCTR_CID_WRITE_RETIRED);
 346 ARMV8_EVENT_ATTR(pc_write_retired, ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED);
 347 ARMV8_EVENT_ATTR(br_immed_retired, ARMV8_PMUV3_PERFCTR_BR_IMMED_RETIRED);
 348 ARMV8_EVENT_ATTR(br_return_retired, ARMV8_PMUV3_PERFCTR_BR_RETURN_RETIRED);
 349 ARMV8_EVENT_ATTR(unaligned_ldst_retired, ARMV8_PMUV3_PERFCTR_UNALIGNED_LDST_RETIRED);
 350 ARMV8_EVENT_ATTR(br_mis_pred, ARMV8_PMUV3_PERFCTR_BR_MIS_PRED);
 351 ARMV8_EVENT_ATTR(cpu_cycles, ARMV8_PMUV3_PERFCTR_CPU_CYCLES);
 352 ARMV8_EVENT_ATTR(br_pred, ARMV8_PMUV3_PERFCTR_BR_PRED);
 353 ARMV8_EVENT_ATTR(mem_access, ARMV8_PMUV3_PERFCTR_MEM_ACCESS);
 354 ARMV8_EVENT_ATTR(l1i_cache, ARMV8_PMUV3_PERFCTR_L1I_CACHE);
 355 ARMV8_EVENT_ATTR(l1d_cache_wb, ARMV8_PMUV3_PERFCTR_L1D_CACHE_WB);
 356 ARMV8_EVENT_ATTR(l2d_cache, ARMV8_PMUV3_PERFCTR_L2D_CACHE);
 357 ARMV8_EVENT_ATTR(l2d_cache_refill, ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL);
 358 ARMV8_EVENT_ATTR(l2d_cache_wb, ARMV8_PMUV3_PERFCTR_L2D_CACHE_WB);
 359 ARMV8_EVENT_ATTR(bus_access, ARMV8_PMUV3_PERFCTR_BUS_ACCESS);
 360 ARMV8_EVENT_ATTR(memory_error, ARMV8_PMUV3_PERFCTR_MEMORY_ERROR);
 361 ARMV8_EVENT_ATTR(inst_spec, ARMV8_PMUV3_PERFCTR_INST_SPEC);
 362 ARMV8_EVENT_ATTR(ttbr_write_retired, ARMV8_PMUV3_PERFCTR_TTBR_WRITE_RETIRED);
 363 ARMV8_EVENT_ATTR(bus_cycles, ARMV8_PMUV3_PERFCTR_BUS_CYCLES);
 364 ARMV8_EVENT_ATTR(chain, ARMV8_PMUV3_PERFCTR_CHAIN);
 365 ARMV8_EVENT_ATTR(l1d_cache_allocate, ARMV8_PMUV3_PERFCTR_L1D_CACHE_ALLOCATE);
 366 ARMV8_EVENT_ATTR(l2d_cache_allocate, ARMV8_PMUV3_PERFCTR_L2D_CACHE_ALLOCATE);
 367 ARMV8_EVENT_ATTR(br_retired, ARMV8_PMUV3_PERFCTR_BR_RETIRED);
 368 ARMV8_EVENT_ATTR(br_mis_pred_retired, ARMV8_PMUV3_PERFCTR_BR_MIS_PRED_RETIRED);
 369 ARMV8_EVENT_ATTR(stall_frontend, ARMV8_PMUV3_PERFCTR_STALL_FRONTEND);
 370 ARMV8_EVENT_ATTR(stall_backend, ARMV8_PMUV3_PERFCTR_STALL_BACKEND);
 371 ARMV8_EVENT_ATTR(l1d_tlb, ARMV8_PMUV3_PERFCTR_L1D_TLB);
 372 ARMV8_EVENT_ATTR(l1i_tlb, ARMV8_PMUV3_PERFCTR_L1I_TLB);
 373 ARMV8_EVENT_ATTR(l2i_cache, ARMV8_PMUV3_PERFCTR_L2I_CACHE);
 374 ARMV8_EVENT_ATTR(l2i_cache_refill, ARMV8_PMUV3_PERFCTR_L2I_CACHE_REFILL);
 375 ARMV8_EVENT_ATTR(l3d_cache_allocate, ARMV8_PMUV3_PERFCTR_L3D_CACHE_ALLOCATE);
 376 ARMV8_EVENT_ATTR(l3d_cache_refill, ARMV8_PMUV3_PERFCTR_L3D_CACHE_REFILL);
 377 ARMV8_EVENT_ATTR(l3d_cache, ARMV8_PMUV3_PERFCTR_L3D_CACHE);
 378 ARMV8_EVENT_ATTR(l3d_cache_wb, ARMV8_PMUV3_PERFCTR_L3D_CACHE_WB);
 379 ARMV8_EVENT_ATTR(l2d_tlb_refill, ARMV8_PMUV3_PERFCTR_L2D_TLB_REFILL);
 380 ARMV8_EVENT_ATTR(l2i_tlb_refill, ARMV8_PMUV3_PERFCTR_L2I_TLB_REFILL);
 381 ARMV8_EVENT_ATTR(l2d_tlb, ARMV8_PMUV3_PERFCTR_L2D_TLB);
 382 ARMV8_EVENT_ATTR(l2i_tlb, ARMV8_PMUV3_PERFCTR_L2I_TLB);
 383
 384 static struct attribute *armv8_pmuv3_event_attrs[] = {
 385         &armv8_event_attr_sw_incr.attr.attr,
 386         &armv8_event_attr_l1i_cache_refill.attr.attr,
 387         &armv8_event_attr_l1i_tlb_refill.attr.attr,
 388         &armv8_event_attr_l1d_cache_refill.attr.attr,
 389         &armv8_event_attr_l1d_cache.attr.attr,
 390         &armv8_event_attr_l1d_tlb_refill.attr.attr,
 391         &armv8_event_attr_ld_retired.attr.attr,
 392         &armv8_event_attr_st_retired.attr.attr,
 393         &armv8_event_attr_inst_retired.attr.attr,
 394         &armv8_event_attr_exc_taken.attr.attr,
 395         &armv8_event_attr_exc_return.attr.attr,
 396         &armv8_event_attr_cid_write_retired.attr.attr,
 397         &armv8_event_attr_pc_write_retired.attr.attr,
 398         &armv8_event_attr_br_immed_retired.attr.attr,
 399         &armv8_event_attr_br_return_retired.attr.attr,
 400         &armv8_event_attr_unaligned_ldst_retired.attr.attr,
 401         &armv8_event_attr_br_mis_pred.attr.attr,
 402         &armv8_event_attr_cpu_cycles.attr.attr,
 403         &armv8_event_attr_br_pred.attr.attr,
 404         &armv8_event_attr_mem_access.attr.attr,
 405         &armv8_event_attr_l1i_cache.attr.attr,
 406         &armv8_event_attr_l1d_cache_wb.attr.attr,
 407         &armv8_event_attr_l2d_cache.attr.attr,
 408         &armv8_event_attr_l2d_cache_refill.attr.attr,
 409         &armv8_event_attr_l2d_cache_wb.attr.attr,
 410         &armv8_event_attr_bus_access.attr.attr,
 411         &armv8_event_attr_memory_error.attr.attr,
 412         &armv8_event_attr_inst_spec.attr.attr,
 413         &armv8_event_attr_ttbr_write_retired.attr.attr,
 414         &armv8_event_attr_bus_cycles.attr.attr,
 415         &armv8_event_attr_chain.attr.attr,
 416         &armv8_event_attr_l1d_cache_allocate.attr.attr,
 417         &armv8_event_attr_l2d_cache_allocate.attr.attr,
 418         &armv8_event_attr_br_retired.attr.attr,
 419         &armv8_event_attr_br_mis_pred_retired.attr.attr,
 420         &armv8_event_attr_stall_frontend.attr.attr,
 421         &armv8_event_attr_stall_backend.attr.attr,
 422         &armv8_event_attr_l1d_tlb.attr.attr,
 423         &armv8_event_attr_l1i_tlb.attr.attr,
 424         &armv8_event_attr_l2i_cache.attr.attr,
 425         &armv8_event_attr_l2i_cache_refill.attr.attr,
 426         &armv8_event_attr_l3d_cache_allocate.attr.attr,
 427         &armv8_event_attr_l3d_cache_refill.attr.attr,
 428         &armv8_event_attr_l3d_cache.attr.attr,
 429         &armv8_event_attr_l3d_cache_wb.attr.attr,
 430         &armv8_event_attr_l2d_tlb_refill.attr.attr,
 431         &armv8_event_attr_l2i_tlb_refill.attr.attr,
 432         &armv8_event_attr_l2d_tlb.attr.attr,
 433         &armv8_event_attr_l2i_tlb.attr.attr,
 434         NULL,
 435 };
 436
 437 static struct attribute_group armv8_pmuv3_events_attr_group = {
 438         .name = "events",
 439         .attrs = armv8_pmuv3_event_attrs,
 440 };
 441
 442 PMU_FORMAT_ATTR(event, "config:0-9");
 443
 444 static struct attribute *armv8_pmuv3_format_attrs[] = {
 445         &format_attr_event.attr,
 446         NULL,
 447 };
 448
 449 static struct attribute_group armv8_pmuv3_format_attr_group = {
 450         .name = "format",
 451         .attrs = armv8_pmuv3_format_attrs,
 452 };
 453
 454 static const struct attribute_group *armv8_pmuv3_attr_groups[] = {
 455         &armv8_pmuv3_events_attr_group,
 456         &armv8_pmuv3_format_attr_group,
 457         NULL,
 458 };
 459
 460 /*
 461  * Perf Events' indices
 462  */
 463 #define ARMV8_IDX_CYCLE_COUNTER 0
 464 #define ARMV8_IDX_COUNTER0      1
 465 #define ARMV8_IDX_COUNTER_LAST(cpu_pmu) \
 466         (ARMV8_IDX_CYCLE_COUNTER + cpu_pmu->num_events - 1)
 467
 468 /*
 469  * ARMv8 low level PMU access
 470  */
 471
 472 /*
 473  * Perf Event to low level counters mapping
 474  */
 475 #define ARMV8_IDX_TO_COUNTER(x) \
 476         (((x) - ARMV8_IDX_COUNTER0) & ARMV8_PMU_COUNTER_MASK)
 477
 478 static inline u32 armv8pmu_pmcr_read(void)
 479 {
 480         return read_sysreg(pmcr_el0);
 481 }
 482
 483 static inline void armv8pmu_pmcr_write(u32 val)
 484 {
 485         val &= ARMV8_PMU_PMCR_MASK;
 486         isb();
 487         write_sysreg(val, pmcr_el0);
 488 }
 489
 490 static inline int armv8pmu_has_overflowed(u32 pmovsr)
 491 {
 492         return pmovsr & ARMV8_PMU_OVERFLOWED_MASK;
 493 }
 494
 495 static inline int armv8pmu_counter_valid(struct arm_pmu *cpu_pmu, int idx)
 496 {
 497         return idx >= ARMV8_IDX_CYCLE_COUNTER &&
 498                 idx <= ARMV8_IDX_COUNTER_LAST(cpu_pmu);
 499 }
 500
 501 static inline int armv8pmu_counter_has_overflowed(u32 pmnc, int idx)
 502 {
 503         return pmnc & BIT(ARMV8_IDX_TO_COUNTER(idx));
 504 }
 505
 506 static inline int armv8pmu_select_counter(int idx)
 507 {
 508         u32 counter = ARMV8_IDX_TO_COUNTER(idx);
 509         write_sysreg(counter, pmselr_el0);
 510         isb();
 511
 512         return idx;
 513 }
 514
 515 static inline u32 armv8pmu_read_counter(struct perf_event *event)
 516 {
 517         struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
 518         struct hw_perf_event *hwc = &event->hw;
 519         int idx = hwc->idx;
 520         u32 value = 0;
 521
 522         if (!armv8pmu_counter_valid(cpu_pmu, idx))
 523                 pr_err("CPU%u reading wrong counter %d\n",
 524                         smp_processor_id(), idx);
 525         else if (idx == ARMV8_IDX_CYCLE_COUNTER)
 526                 value = read_sysreg(pmccntr_el0);
 527         else if (armv8pmu_select_counter(idx) == idx)
 528                 value = read_sysreg(pmxevcntr_el0);
 529
 530         return value;
 531 }
 532
 533 static inline void armv8pmu_write_counter(struct perf_event *event, u32 value)
 534 {
 535         struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
 536         struct hw_perf_event *hwc = &event->hw;
 537         int idx = hwc->idx;
 538
 539         if (!armv8pmu_counter_valid(cpu_pmu, idx))
 540                 pr_err("CPU%u writing wrong counter %d\n",
 541                         smp_processor_id(), idx);
 542         else if (idx == ARMV8_IDX_CYCLE_COUNTER) {
 543                 /*
 544                  * Set the upper 32bits as this is a 64bit counter but we only
 545                  * count using the lower 32bits and we want an interrupt when
 546                  * it overflows.
 547                  */
 548                 u64 value64 = 0xffffffff00000000ULL | value;
 549
 550                 write_sysreg(value64, pmccntr_el0);
 551         } else if (armv8pmu_select_counter(idx) == idx)
 552                 write_sysreg(value, pmxevcntr_el0);
 553 }
 554
 555 static inline void armv8pmu_write_evtype(int idx, u32 val)
 556 {
 557         if (armv8pmu_select_counter(idx) == idx) {
 558                 val &= ARMV8_PMU_EVTYPE_MASK;
 559                 write_sysreg(val, pmxevtyper_el0);
 560         }
 561 }
 562
 563 static inline int armv8pmu_enable_counter(int idx)
 564 {
 565         u32 counter = ARMV8_IDX_TO_COUNTER(idx);
 566         write_sysreg(BIT(counter), pmcntenset_el0);
 567         return idx;
 568 }
 569
 570 static inline int armv8pmu_disable_counter(int idx)
 571 {
 572         u32 counter = ARMV8_IDX_TO_COUNTER(idx);
 573         write_sysreg(BIT(counter), pmcntenclr_el0);
 574         return idx;
 575 }
 576
 577 static inline int armv8pmu_enable_intens(int idx)
 578 {
 579         u32 counter = ARMV8_IDX_TO_COUNTER(idx);
 580         write_sysreg(BIT(counter), pmintenset_el1);
 581         return idx;
 582 }
 583
 584 static inline int armv8pmu_disable_intens(int idx)
 585 {
 586         u32 counter = ARMV8_IDX_TO_COUNTER(idx);
 587         write_sysreg(BIT(counter), pmintenclr_el1);
 588         isb();
 589         /* Clear the overflow flag in case an interrupt is pending. */
 590         write_sysreg(BIT(counter), pmovsclr_el0);
 591         isb();
 592
 593         return idx;
 594 }
 595
 596 static inline u32 armv8pmu_getreset_flags(void)
 597 {
 598         u32 value;
 599
 600         /* Read */
 601         value = read_sysreg(pmovsclr_el0);
 602
 603         /* Write to clear flags */
 604         value &= ARMV8_PMU_OVSR_MASK;
 605         write_sysreg(value, pmovsclr_el0);
 606
 607         return value;
 608 }
 609
 610 static void armv8pmu_enable_event(struct perf_event *event)
 611 {
 612         unsigned long flags;
 613         struct hw_perf_event *hwc = &event->hw;
 614         struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
 615         struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
 616         int idx = hwc->idx;
 617
 618         /*
 619          * Enable counter and interrupt, and set the counter to count
 620          * the event that we're interested in.
 621          */
 622         raw_spin_lock_irqsave(&events->pmu_lock, flags);
 623
 624         /*
 625          * Disable counter
 626          */
 627         armv8pmu_disable_counter(idx);
 628
 629         /*
 630          * Set event (if destined for PMNx counters).
 631          */
 632         armv8pmu_write_evtype(idx, hwc->config_base);
 633
 634         /*
 635          * Enable interrupt for this counter
 636          */
 637         armv8pmu_enable_intens(idx);
 638
 639         /*
 640          * Enable counter
 641          */
 642         armv8pmu_enable_counter(idx);
 643
 644         raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
 645 }
 646
 647 static void armv8pmu_disable_event(struct perf_event *event)
 648 {
 649         unsigned long flags;
 650         struct hw_perf_event *hwc = &event->hw;
 651         struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
 652         struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
 653         int idx = hwc->idx;
 654
 655         /*
 656          * Disable counter and interrupt
 657          */
 658         raw_spin_lock_irqsave(&events->pmu_lock, flags);
 659
 660         /*
 661          * Disable counter
 662          */
 663         armv8pmu_disable_counter(idx);
 664
 665         /*
 666          * Disable interrupt for this counter
 667          */
 668         armv8pmu_disable_intens(idx);
 669
 670         raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
 671 }
 672
 673 static irqreturn_t armv8pmu_handle_irq(int irq_num, void *dev)
 674 {
 675         u32 pmovsr;
 676         struct perf_sample_data data;
 677         struct arm_pmu *cpu_pmu = (struct arm_pmu *)dev;
 678         struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events);
 679         struct pt_regs *regs;
 680         int idx;
 681
 682         /*
 683          * Get and reset the IRQ flags
 684          */
 685         pmovsr = armv8pmu_getreset_flags();
 686
 687         /*
 688          * Did an overflow occur?
 689          */
 690         if (!armv8pmu_has_overflowed(pmovsr))
 691                 return IRQ_NONE;
 692
 693         /*
 694          * Handle the counter(s) overflow(s)
 695          */
 696         regs = get_irq_regs();
 697
 698         for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
 699                 struct perf_event *event = cpuc->events[idx];
 700                 struct hw_perf_event *hwc;
 701
 702                 /* Ignore if we don't have an event. */
 703                 if (!event)
 704                         continue;
 705
 706                 /*
 707                  * We have a single interrupt for all counters. Check that
 708                  * each counter has overflowed before we process it.
 709                  */
 710                 if (!armv8pmu_counter_has_overflowed(pmovsr, idx))
 711                         continue;
 712
 713                 hwc = &event->hw;
 714                 armpmu_event_update(event);
 715                 perf_sample_data_init(&data, 0, hwc->last_period);
 716                 if (!armpmu_event_set_period(event))
 717                         continue;
 718
 719                 if (perf_event_overflow(event, &data, regs))
 720                         cpu_pmu->disable(event);
 721         }
 722
 723         /*
 724          * Handle the pending perf events.
 725          *
 726          * Note: this call *must* be run with interrupts disabled. For
 727          * platforms that can have the PMU interrupts raised as an NMI, this
 728          * will not work.
 729          */
 730         irq_work_run();
 731
 732         return IRQ_HANDLED;
 733 }
 734
 735 static void armv8pmu_start(struct arm_pmu *cpu_pmu)
 736 {
 737         unsigned long flags;
 738         struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
 739
 740         raw_spin_lock_irqsave(&events->pmu_lock, flags);
 741         /* Enable all counters */
 742         armv8pmu_pmcr_write(armv8pmu_pmcr_read() | ARMV8_PMU_PMCR_E);
 743         raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
 744 }
 745
 746 static void armv8pmu_stop(struct arm_pmu *cpu_pmu)
 747 {
 748         unsigned long flags;
 749         struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
 750
 751         raw_spin_lock_irqsave(&events->pmu_lock, flags);
 752         /* Disable all counters */
 753         armv8pmu_pmcr_write(armv8pmu_pmcr_read() & ~ARMV8_PMU_PMCR_E);
 754         raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
 755 }
 756
 757 static int armv8pmu_get_event_idx(struct pmu_hw_events *cpuc,
 758                                   struct perf_event *event)
 759 {
 760         int idx;
 761         struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
 762         struct hw_perf_event *hwc = &event->hw;
 763         unsigned long evtype = hwc->config_base & ARMV8_PMU_EVTYPE_EVENT;
 764
 765         /* Always place a cycle counter into the cycle counter. */
 766         if (evtype == ARMV8_PMUV3_PERFCTR_CPU_CYCLES) {
 767                 if (test_and_set_bit(ARMV8_IDX_CYCLE_COUNTER, cpuc->used_mask))
 768                         return -EAGAIN;
 769
 770                 return ARMV8_IDX_CYCLE_COUNTER;
 771         }
 772
 773         /*
 774          * For anything other than a cycle counter, try and use
 775          * the events counters
 776          */
 777         for (idx = ARMV8_IDX_COUNTER0; idx < cpu_pmu->num_events; ++idx) {
 778                 if (!test_and_set_bit(idx, cpuc->used_mask))
 779                         return idx;
 780         }
 781
 782         /* The counters are all in use. */
 783         return -EAGAIN;
 784 }
 785
 786 /*
 787  * Add an event filter to a given event. This will only work for PMUv2 PMUs.
 788  */
 789 static int armv8pmu_set_event_filter(struct hw_perf_event *event,
 790                                      struct perf_event_attr *attr)
 791 {
 792         unsigned long config_base = 0;
 793
 794         if (attr->exclude_idle)
 795                 return -EPERM;
 796         if (is_kernel_in_hyp_mode() &&
 797             attr->exclude_kernel != attr->exclude_hv)
 798                 return -EINVAL;
 799         if (attr->exclude_user)
 800                 config_base |= ARMV8_PMU_EXCLUDE_EL0;
 801         if (!is_kernel_in_hyp_mode() && attr->exclude_kernel)
 802                 config_base |= ARMV8_PMU_EXCLUDE_EL1;
 803         if (!attr->exclude_hv)
 804                 config_base |= ARMV8_PMU_INCLUDE_EL2;
 805
 806         /*
 807          * Install the filter into config_base as this is used to
 808          * construct the event type.
 809          */
 810         event->config_base = config_base;
 811
 812         return 0;
 813 }
 814
 815 static void armv8pmu_reset(void *info)
 816 {
 817         struct arm_pmu *cpu_pmu = (struct arm_pmu *)info;
 818         u32 idx, nb_cnt = cpu_pmu->num_events;
 819
 820         /* The counter and interrupt enable registers are unknown at reset. */
 821         for (idx = ARMV8_IDX_CYCLE_COUNTER; idx < nb_cnt; ++idx) {
 822                 armv8pmu_disable_counter(idx);
 823                 armv8pmu_disable_intens(idx);
 824         }
 825
 826         /*
 827          * Initialize & Reset PMNC. Request overflow interrupt for
 828          * 64 bit cycle counter but cheat in armv8pmu_write_counter().
 829          */
 830         armv8pmu_pmcr_write(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C |
 831                             ARMV8_PMU_PMCR_LC);
 832 }
 833
 834 static int armv8_pmuv3_map_event(struct perf_event *event)
 835 {
 836         return armpmu_map_event(event, &armv8_pmuv3_perf_map,
 837                                 &armv8_pmuv3_perf_cache_map,
 838                                 ARMV8_PMU_EVTYPE_EVENT);
 839 }
 840
 841 static int armv8_a53_map_event(struct perf_event *event)
 842 {
 843         return armpmu_map_event(event, &armv8_a53_perf_map,
 844                                 &armv8_a53_perf_cache_map,
 845                                 ARMV8_PMU_EVTYPE_EVENT);
 846 }
 847
 848 static int armv8_a57_map_event(struct perf_event *event)
 849 {
 850         return armpmu_map_event(event, &armv8_a57_perf_map,
 851                                 &armv8_a57_perf_cache_map,
 852                                 ARMV8_PMU_EVTYPE_EVENT);
 853 }
 854
 855 static int armv8_thunder_map_event(struct perf_event *event)
 856 {
 857         return armpmu_map_event(event, &armv8_thunder_perf_map,
 858                                 &armv8_thunder_perf_cache_map,
 859                                 ARMV8_PMU_EVTYPE_EVENT);
 860 }
 861
 862 static void armv8pmu_read_num_pmnc_events(void *info)
 863 {
 864         int *nb_cnt = info;
 865
 866         /* Read the nb of CNTx counters supported from PMNC */
 867         *nb_cnt = (armv8pmu_pmcr_read() >> ARMV8_PMU_PMCR_N_SHIFT) & ARMV8_PMU_PMCR_N_MASK;
 868
 869         /* Add the CPU cycles counter */
 870         *nb_cnt += 1;
 871 }
 872
 873 static int armv8pmu_probe_num_events(struct arm_pmu *arm_pmu)
 874 {
 875         return smp_call_function_any(&arm_pmu->supported_cpus,
 876                                     armv8pmu_read_num_pmnc_events,
 877                                     &arm_pmu->num_events, 1);
 878 }
 879
 880 static void armv8_pmu_init(struct arm_pmu *cpu_pmu)
 881 {
 882         cpu_pmu->handle_irq             = armv8pmu_handle_irq,
 883         cpu_pmu->enable                 = armv8pmu_enable_event,
 884         cpu_pmu->disable                = armv8pmu_disable_event,
 885         cpu_pmu->read_counter           = armv8pmu_read_counter,
 886         cpu_pmu->write_counter          = armv8pmu_write_counter,
 887         cpu_pmu->get_event_idx          = armv8pmu_get_event_idx,
 888         cpu_pmu->start                  = armv8pmu_start,
 889         cpu_pmu->stop                   = armv8pmu_stop,
 890         cpu_pmu->reset                  = armv8pmu_reset,
 891         cpu_pmu->max_period             = (1LLU << 32) - 1,
 892         cpu_pmu->set_event_filter       = armv8pmu_set_event_filter;
 893 }
 894
 895 static int armv8_pmuv3_init(struct arm_pmu *cpu_pmu)
 896 {
 897         armv8_pmu_init(cpu_pmu);
 898         cpu_pmu->name                   = "armv8_pmuv3";
 899         cpu_pmu->map_event              = armv8_pmuv3_map_event;
 900         return armv8pmu_probe_num_events(cpu_pmu);
 901 }
 902
 903 static int armv8_a53_pmu_init(struct arm_pmu *cpu_pmu)
 904 {
 905         armv8_pmu_init(cpu_pmu);
 906         cpu_pmu->name                   = "armv8_cortex_a53";
 907         cpu_pmu->map_event              = armv8_a53_map_event;
 908         cpu_pmu->pmu.attr_groups        = armv8_pmuv3_attr_groups;
 909         return armv8pmu_probe_num_events(cpu_pmu);
 910 }
 911
 912 static int armv8_a57_pmu_init(struct arm_pmu *cpu_pmu)
 913 {
 914         armv8_pmu_init(cpu_pmu);
 915         cpu_pmu->name                   = "armv8_cortex_a57";
 916         cpu_pmu->map_event              = armv8_a57_map_event;
 917         cpu_pmu->pmu.attr_groups        = armv8_pmuv3_attr_groups;
 918         return armv8pmu_probe_num_events(cpu_pmu);
 919 }
 920
 921 static int armv8_a72_pmu_init(struct arm_pmu *cpu_pmu)
 922 {
 923         armv8_pmu_init(cpu_pmu);
 924         cpu_pmu->name                   = "armv8_cortex_a72";
 925         cpu_pmu->map_event              = armv8_a57_map_event;
 926         cpu_pmu->pmu.attr_groups        = armv8_pmuv3_attr_groups;
 927         return armv8pmu_probe_num_events(cpu_pmu);
 928 }
 929
 930 static int armv8_thunder_pmu_init(struct arm_pmu *cpu_pmu)
 931 {
 932         armv8_pmu_init(cpu_pmu);
 933         cpu_pmu->name                   = "armv8_cavium_thunder";
 934         cpu_pmu->map_event              = armv8_thunder_map_event;
 935         cpu_pmu->pmu.attr_groups        = armv8_pmuv3_attr_groups;
 936         return armv8pmu_probe_num_events(cpu_pmu);
 937 }
 938
 939 static const struct of_device_id armv8_pmu_of_device_ids[] = {
 940         {.compatible = "arm,armv8-pmuv3",       .data = armv8_pmuv3_init},
 941         {.compatible = "arm,cortex-a53-pmu",    .data = armv8_a53_pmu_init},
 942         {.compatible = "arm,cortex-a57-pmu",    .data = armv8_a57_pmu_init},
 943         {.compatible = "arm,cortex-a72-pmu",    .data = armv8_a72_pmu_init},
 944         {.compatible = "cavium,thunder-pmu",    .data = armv8_thunder_pmu_init},
 945         {},
 946 };
 947
 948 static int armv8_pmu_device_probe(struct platform_device *pdev)
 949 {
 950         return arm_pmu_device_probe(pdev, armv8_pmu_of_device_ids, NULL);
 951 }
 952
 953 static struct platform_driver armv8_pmu_driver = {
 954         .driver         = {
 955                 .name   = "armv8-pmu",
 956                 .of_match_table = armv8_pmu_of_device_ids,
 957         },
 958         .probe          = armv8_pmu_device_probe,
 959 };
 960
 961 static int __init register_armv8_pmu_driver(void)
 962 {
 963         return platform_driver_register(&armv8_pmu_driver);
 964 }
 965 device_initcall(register_armv8_pmu_driver);