arch/arm64/kernel/perf_event.c

   1 /*
   2  * PMU support
   3  *
   4  * Copyright (C) 2012 ARM Limited
   5  * Author: Will Deacon <will.deacon@arm.com>
   6  *
   7  * This code is based heavily on the ARMv7 perf event code.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include <asm/irq_regs.h>
  23 #include <asm/perf_event.h>
  24 #include <asm/sysreg.h>
  25 #include <asm/virt.h>
  26
  27 #include <linux/of.h>
  28 #include <linux/perf/arm_pmu.h>
  29 #include <linux/platform_device.h>
  30
  31 /*
  32  * ARMv8 PMUv3 Performance Events handling code.
  33  * Common event types.
  34  */
  35
  36 /* Required events. */
  37 #define ARMV8_PMUV3_PERFCTR_SW_INCR                             0x00
  38 #define ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL                    0x03
  39 #define ARMV8_PMUV3_PERFCTR_L1D_CACHE                           0x04
  40 #define ARMV8_PMUV3_PERFCTR_BR_MIS_PRED                         0x10
  41 #define ARMV8_PMUV3_PERFCTR_CPU_CYCLES                          0x11
  42 #define ARMV8_PMUV3_PERFCTR_BR_PRED                             0x12
  43
  44 /* At least one of the following is required. */
  45 #define ARMV8_PMUV3_PERFCTR_INST_RETIRED                        0x08
  46 #define ARMV8_PMUV3_PERFCTR_INST_SPEC                           0x1B
  47
  48 /* Common architectural events. */
  49 #define ARMV8_PMUV3_PERFCTR_LD_RETIRED                          0x06
  50 #define ARMV8_PMUV3_PERFCTR_ST_RETIRED                          0x07
  51 #define ARMV8_PMUV3_PERFCTR_EXC_TAKEN                           0x09
  52 #define ARMV8_PMUV3_PERFCTR_EXC_RETURN                          0x0A
  53 #define ARMV8_PMUV3_PERFCTR_CID_WRITE_RETIRED                   0x0B
  54 #define ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED                    0x0C
  55 #define ARMV8_PMUV3_PERFCTR_BR_IMMED_RETIRED                    0x0D
  56 #define ARMV8_PMUV3_PERFCTR_BR_RETURN_RETIRED                   0x0E
  57 #define ARMV8_PMUV3_PERFCTR_UNALIGNED_LDST_RETIRED              0x0F
  58 #define ARMV8_PMUV3_PERFCTR_TTBR_WRITE_RETIRED                  0x1C
  59 #define ARMV8_PMUV3_PERFCTR_CHAIN                               0x1E
  60 #define ARMV8_PMUV3_PERFCTR_BR_RETIRED                          0x21
  61
  62 /* Common microarchitectural events. */
  63 #define ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL                    0x01
  64 #define ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL                      0x02
  65 #define ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL                      0x05
  66 #define ARMV8_PMUV3_PERFCTR_MEM_ACCESS                          0x13
  67 #define ARMV8_PMUV3_PERFCTR_L1I_CACHE                           0x14
  68 #define ARMV8_PMUV3_PERFCTR_L1D_CACHE_WB                        0x15
  69 #define ARMV8_PMUV3_PERFCTR_L2D_CACHE                           0x16
  70 #define ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL                    0x17
  71 #define ARMV8_PMUV3_PERFCTR_L2D_CACHE_WB                        0x18
  72 #define ARMV8_PMUV3_PERFCTR_BUS_ACCESS                          0x19
  73 #define ARMV8_PMUV3_PERFCTR_MEMORY_ERROR                        0x1A
  74 #define ARMV8_PMUV3_PERFCTR_BUS_CYCLES                          0x1D
  75 #define ARMV8_PMUV3_PERFCTR_L1D_CACHE_ALLOCATE                  0x1F
  76 #define ARMV8_PMUV3_PERFCTR_L2D_CACHE_ALLOCATE                  0x20
  77 #define ARMV8_PMUV3_PERFCTR_BR_MIS_PRED_RETIRED                 0x22
  78 #define ARMV8_PMUV3_PERFCTR_STALL_FRONTEND                      0x23
  79 #define ARMV8_PMUV3_PERFCTR_STALL_BACKEND                       0x24
  80 #define ARMV8_PMUV3_PERFCTR_L1D_TLB                             0x25
  81 #define ARMV8_PMUV3_PERFCTR_L1I_TLB                             0x26
  82 #define ARMV8_PMUV3_PERFCTR_L2I_CACHE                           0x27
  83 #define ARMV8_PMUV3_PERFCTR_L2I_CACHE_REFILL                    0x28
  84 #define ARMV8_PMUV3_PERFCTR_L3D_CACHE_ALLOCATE                  0x29
  85 #define ARMV8_PMUV3_PERFCTR_L3D_CACHE_REFILL                    0x2A
  86 #define ARMV8_PMUV3_PERFCTR_L3D_CACHE                           0x2B
  87 #define ARMV8_PMUV3_PERFCTR_L3D_CACHE_WB                        0x2C
  88 #define ARMV8_PMUV3_PERFCTR_L2D_TLB_REFILL                      0x2D
  89 #define ARMV8_PMUV3_PERFCTR_L2I_TLB_REFILL                      0x2E
  90 #define ARMV8_PMUV3_PERFCTR_L2D_TLB                             0x2F
  91 #define ARMV8_PMUV3_PERFCTR_L2I_TLB                             0x30
  92
  93 /* ARMv8 recommended implementation defined event types */
  94 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD                       0x40
  95 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR                       0x41
  96 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD                0x42
  97 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR                0x43
  98 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_INNER             0x44
  99 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_OUTER             0x45
 100 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WB_VICTIM                0x46
 101 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WB_CLEAN                 0x47
 102 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_INVAL                    0x48
 103
 104 #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD                  0x4C
 105 #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR                  0x4D
 106 #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD                         0x4E
 107 #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR                         0x4F
 108 #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_RD                       0x50
 109 #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WR                       0x51
 110 #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_REFILL_RD                0x52
 111 #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_REFILL_WR                0x53
 112
 113 #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WB_VICTIM                0x56
 114 #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WB_CLEAN                 0x57
 115 #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_INVAL                    0x58
 116
 117 #define ARMV8_IMPDEF_PERFCTR_L2D_TLB_REFILL_RD                  0x5C
 118 #define ARMV8_IMPDEF_PERFCTR_L2D_TLB_REFILL_WR                  0x5D
 119 #define ARMV8_IMPDEF_PERFCTR_L2D_TLB_RD                         0x5E
 120 #define ARMV8_IMPDEF_PERFCTR_L2D_TLB_WR                         0x5F
 121
 122 #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD                      0x60
 123 #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR                      0x61
 124 #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_SHARED                  0x62
 125 #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_NOT_SHARED              0x63
 126 #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_NORMAL                  0x64
 127 #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_PERIPH                  0x65
 128
 129 #define ARMV8_IMPDEF_PERFCTR_MEM_ACCESS_RD                      0x66
 130 #define ARMV8_IMPDEF_PERFCTR_MEM_ACCESS_WR                      0x67
 131 #define ARMV8_IMPDEF_PERFCTR_UNALIGNED_LD_SPEC                  0x68
 132 #define ARMV8_IMPDEF_PERFCTR_UNALIGNED_ST_SPEC                  0x69
 133 #define ARMV8_IMPDEF_PERFCTR_UNALIGNED_LDST_SPEC                0x6A
 134
 135 #define ARMV8_IMPDEF_PERFCTR_LDREX_SPEC                         0x6C
 136 #define ARMV8_IMPDEF_PERFCTR_STREX_PASS_SPEC                    0x6D
 137 #define ARMV8_IMPDEF_PERFCTR_STREX_FAIL_SPEC                    0x6E
 138 #define ARMV8_IMPDEF_PERFCTR_STREX_SPEC                         0x6F
 139 #define ARMV8_IMPDEF_PERFCTR_LD_SPEC                            0x70
 140 #define ARMV8_IMPDEF_PERFCTR_ST_SPEC                            0x71
 141 #define ARMV8_IMPDEF_PERFCTR_LDST_SPEC                          0x72
 142 #define ARMV8_IMPDEF_PERFCTR_DP_SPEC                            0x73
 143 #define ARMV8_IMPDEF_PERFCTR_ASE_SPEC                           0x74
 144 #define ARMV8_IMPDEF_PERFCTR_VFP_SPEC                           0x75
 145 #define ARMV8_IMPDEF_PERFCTR_PC_WRITE_SPEC                      0x76
 146 #define ARMV8_IMPDEF_PERFCTR_CRYPTO_SPEC                        0x77
 147 #define ARMV8_IMPDEF_PERFCTR_BR_IMMED_SPEC                      0x78
 148 #define ARMV8_IMPDEF_PERFCTR_BR_RETURN_SPEC                     0x79
 149 #define ARMV8_IMPDEF_PERFCTR_BR_INDIRECT_SPEC                   0x7A
 150
 151 #define ARMV8_IMPDEF_PERFCTR_ISB_SPEC                           0x7C
 152 #define ARMV8_IMPDEF_PERFCTR_DSB_SPEC                           0x7D
 153 #define ARMV8_IMPDEF_PERFCTR_DMB_SPEC                           0x7E
 154
 155 #define ARMV8_IMPDEF_PERFCTR_EXC_UNDEF                          0x81
 156 #define ARMV8_IMPDEF_PERFCTR_EXC_SVC                            0x82
 157 #define ARMV8_IMPDEF_PERFCTR_EXC_PABORT                         0x83
 158 #define ARMV8_IMPDEF_PERFCTR_EXC_DABORT                         0x84
 159
 160 #define ARMV8_IMPDEF_PERFCTR_EXC_IRQ                            0x86
 161 #define ARMV8_IMPDEF_PERFCTR_EXC_FIQ                            0x87
 162 #define ARMV8_IMPDEF_PERFCTR_EXC_SMC                            0x88
 163
 164 #define ARMV8_IMPDEF_PERFCTR_EXC_HVC                            0x8A
 165 #define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_PABORT                    0x8B
 166 #define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_DABORT                    0x8C
 167 #define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_OTHER                     0x8D
 168 #define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_IRQ                       0x8E
 169 #define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_FIQ                       0x8F
 170 #define ARMV8_IMPDEF_PERFCTR_RC_LD_SPEC                         0x90
 171 #define ARMV8_IMPDEF_PERFCTR_RC_ST_SPEC                         0x91
 172
 173 #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_RD                       0xA0
 174 #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WR                       0xA1
 175 #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_REFILL_RD                0xA2
 176 #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_REFILL_WR                0xA3
 177
 178 #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WB_VICTIM                0xA6
 179 #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WB_CLEAN                 0xA7
 180 #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_INVAL                    0xA8
 181
 182 /* ARMv8 Cortex-A53 specific event types. */
 183 #define ARMV8_A53_PERFCTR_PREF_LINEFILL                         0xC2
 184
 185 /* ARMv8 Cavium ThunderX specific event types. */
 186 #define ARMV8_THUNDER_PERFCTR_L1D_CACHE_MISS_ST                 0xE9
 187 #define ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_ACCESS             0xEA
 188 #define ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_MISS               0xEB
 189 #define ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_ACCESS             0xEC
 190 #define ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_MISS               0xED
 191
 192 /* PMUv3 HW events mapping. */
 193 static const unsigned armv8_pmuv3_perf_map[PERF_COUNT_HW_MAX] = {
 194         PERF_MAP_ALL_UNSUPPORTED,
 195         [PERF_COUNT_HW_CPU_CYCLES]              = ARMV8_PMUV3_PERFCTR_CPU_CYCLES,
 196         [PERF_COUNT_HW_INSTRUCTIONS]            = ARMV8_PMUV3_PERFCTR_INST_RETIRED,
 197         [PERF_COUNT_HW_CACHE_REFERENCES]        = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
 198         [PERF_COUNT_HW_CACHE_MISSES]            = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
 199         [PERF_COUNT_HW_BRANCH_MISSES]           = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
 200 };
 201
 202 /* ARM Cortex-A53 HW events mapping. */
 203 static const unsigned armv8_a53_perf_map[PERF_COUNT_HW_MAX] = {
 204         PERF_MAP_ALL_UNSUPPORTED,
 205         [PERF_COUNT_HW_CPU_CYCLES]              = ARMV8_PMUV3_PERFCTR_CPU_CYCLES,
 206         [PERF_COUNT_HW_INSTRUCTIONS]            = ARMV8_PMUV3_PERFCTR_INST_RETIRED,
 207         [PERF_COUNT_HW_CACHE_REFERENCES]        = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
 208         [PERF_COUNT_HW_CACHE_MISSES]            = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
 209         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED,
 210         [PERF_COUNT_HW_BRANCH_MISSES]           = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
 211         [PERF_COUNT_HW_BUS_CYCLES]              = ARMV8_PMUV3_PERFCTR_BUS_CYCLES,
 212 };
 213
 214 /* ARM Cortex-A57 and Cortex-A72 events mapping. */
 215 static const unsigned armv8_a57_perf_map[PERF_COUNT_HW_MAX] = {
 216         PERF_MAP_ALL_UNSUPPORTED,
 217         [PERF_COUNT_HW_CPU_CYCLES]              = ARMV8_PMUV3_PERFCTR_CPU_CYCLES,
 218         [PERF_COUNT_HW_INSTRUCTIONS]            = ARMV8_PMUV3_PERFCTR_INST_RETIRED,
 219         [PERF_COUNT_HW_CACHE_REFERENCES]        = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
 220         [PERF_COUNT_HW_CACHE_MISSES]            = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
 221         [PERF_COUNT_HW_BRANCH_MISSES]           = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
 222         [PERF_COUNT_HW_BUS_CYCLES]              = ARMV8_PMUV3_PERFCTR_BUS_CYCLES,
 223 };
 224
 225 static const unsigned armv8_thunder_perf_map[PERF_COUNT_HW_MAX] = {
 226         PERF_MAP_ALL_UNSUPPORTED,
 227         [PERF_COUNT_HW_CPU_CYCLES]              = ARMV8_PMUV3_PERFCTR_CPU_CYCLES,
 228         [PERF_COUNT_HW_INSTRUCTIONS]            = ARMV8_PMUV3_PERFCTR_INST_RETIRED,
 229         [PERF_COUNT_HW_CACHE_REFERENCES]        = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
 230         [PERF_COUNT_HW_CACHE_MISSES]            = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
 231         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED,
 232         [PERF_COUNT_HW_BRANCH_MISSES]           = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
 233         [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV8_PMUV3_PERFCTR_STALL_FRONTEND,
 234         [PERF_COUNT_HW_STALLED_CYCLES_BACKEND]  = ARMV8_PMUV3_PERFCTR_STALL_BACKEND,
 235 };
 236
 237 static const unsigned armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 238                                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 239                                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
 240         PERF_CACHE_MAP_ALL_UNSUPPORTED,
 241
 242         [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
 243         [C(L1D)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
 244         [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
 245         [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
 246
 247         [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_BR_PRED,
 248         [C(BPU)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
 249         [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
 250         [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
 251 };
 252
 253 static const unsigned armv8_a53_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 254                                               [PERF_COUNT_HW_CACHE_OP_MAX]
 255                                               [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
 256         PERF_CACHE_MAP_ALL_UNSUPPORTED,
 257
 258         [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
 259         [C(L1D)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
 260         [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
 261         [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
 262         [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_A53_PERFCTR_PREF_LINEFILL,
 263
 264         [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
 265         [C(L1I)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
 266
 267         [C(ITLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL,
 268
 269         [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_BR_PRED,
 270         [C(BPU)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
 271         [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
 272         [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
 273 };
 274
 275 static const unsigned armv8_a57_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 276                                               [PERF_COUNT_HW_CACHE_OP_MAX]
 277                                               [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
 278         PERF_CACHE_MAP_ALL_UNSUPPORTED,
 279
 280         [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
 281         [C(L1D)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
 282         [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
 283         [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR,
 284
 285         [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
 286         [C(L1I)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
 287
 288         [C(DTLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
 289         [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)]  = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
 290
 291         [C(ITLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL,
 292
 293         [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_BR_PRED,
 294         [C(BPU)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
 295         [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
 296         [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
 297 };
 298
 299 static const unsigned armv8_thunder_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 300                                                    [PERF_COUNT_HW_CACHE_OP_MAX]
 301                                                    [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
 302         PERF_CACHE_MAP_ALL_UNSUPPORTED,
 303
 304         [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
 305         [C(L1D)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
 306         [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
 307         [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_THUNDER_PERFCTR_L1D_CACHE_MISS_ST,
 308         [C(L1D)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_ACCESS,
 309         [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_MISS,
 310
 311         [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
 312         [C(L1I)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
 313         [C(L1I)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_ACCESS,
 314         [C(L1I)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_MISS,
 315
 316         [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD,
 317         [C(DTLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
 318         [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR,
 319         [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)]  = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
 320
 321         [C(ITLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL,
 322
 323         [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_BR_PRED,
 324         [C(BPU)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
 325         [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
 326         [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
 327 };
 328
 329
 330 static ssize_t
 331 armv8pmu_events_sysfs_show(struct device *dev,
 332                            struct device_attribute *attr, char *page)
 333 {
 334         struct perf_pmu_events_attr *pmu_attr;
 335
 336         pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
 337
 338         return sprintf(page, "event=0x%03llx\n", pmu_attr->id);
 339 }
 340
 341 #define ARMV8_EVENT_ATTR_RESOLVE(m) #m
 342 #define ARMV8_EVENT_ATTR(name, config) \
 343         PMU_EVENT_ATTR(name, armv8_event_attr_##name, \
 344                        config, armv8pmu_events_sysfs_show)
 345
 346 ARMV8_EVENT_ATTR(sw_incr, ARMV8_PMUV3_PERFCTR_SW_INCR);
 347 ARMV8_EVENT_ATTR(l1i_cache_refill, ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL);
 348 ARMV8_EVENT_ATTR(l1i_tlb_refill, ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL);
 349 ARMV8_EVENT_ATTR(l1d_cache_refill, ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL);
 350 ARMV8_EVENT_ATTR(l1d_cache, ARMV8_PMUV3_PERFCTR_L1D_CACHE);
 351 ARMV8_EVENT_ATTR(l1d_tlb_refill, ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL);
 352 ARMV8_EVENT_ATTR(ld_retired, ARMV8_PMUV3_PERFCTR_LD_RETIRED);
 353 ARMV8_EVENT_ATTR(st_retired, ARMV8_PMUV3_PERFCTR_ST_RETIRED);
 354 ARMV8_EVENT_ATTR(inst_retired, ARMV8_PMUV3_PERFCTR_INST_RETIRED);
 355 ARMV8_EVENT_ATTR(exc_taken, ARMV8_PMUV3_PERFCTR_EXC_TAKEN);
 356 ARMV8_EVENT_ATTR(exc_return, ARMV8_PMUV3_PERFCTR_EXC_RETURN);
 357 ARMV8_EVENT_ATTR(cid_write_retired, ARMV8_PMUV3_PERFCTR_CID_WRITE_RETIRED);
 358 ARMV8_EVENT_ATTR(pc_write_retired, ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED);
 359 ARMV8_EVENT_ATTR(br_immed_retired, ARMV8_PMUV3_PERFCTR_BR_IMMED_RETIRED);
 360 ARMV8_EVENT_ATTR(br_return_retired, ARMV8_PMUV3_PERFCTR_BR_RETURN_RETIRED);
 361 ARMV8_EVENT_ATTR(unaligned_ldst_retired, ARMV8_PMUV3_PERFCTR_UNALIGNED_LDST_RETIRED);
 362 ARMV8_EVENT_ATTR(br_mis_pred, ARMV8_PMUV3_PERFCTR_BR_MIS_PRED);
 363 ARMV8_EVENT_ATTR(cpu_cycles, ARMV8_PMUV3_PERFCTR_CPU_CYCLES);
 364 ARMV8_EVENT_ATTR(br_pred, ARMV8_PMUV3_PERFCTR_BR_PRED);
 365 ARMV8_EVENT_ATTR(mem_access, ARMV8_PMUV3_PERFCTR_MEM_ACCESS);
 366 ARMV8_EVENT_ATTR(l1i_cache, ARMV8_PMUV3_PERFCTR_L1I_CACHE);
 367 ARMV8_EVENT_ATTR(l1d_cache_wb, ARMV8_PMUV3_PERFCTR_L1D_CACHE_WB);
 368 ARMV8_EVENT_ATTR(l2d_cache, ARMV8_PMUV3_PERFCTR_L2D_CACHE);
 369 ARMV8_EVENT_ATTR(l2d_cache_refill, ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL);
 370 ARMV8_EVENT_ATTR(l2d_cache_wb, ARMV8_PMUV3_PERFCTR_L2D_CACHE_WB);
 371 ARMV8_EVENT_ATTR(bus_access, ARMV8_PMUV3_PERFCTR_BUS_ACCESS);
 372 ARMV8_EVENT_ATTR(memory_error, ARMV8_PMUV3_PERFCTR_MEMORY_ERROR);
 373 ARMV8_EVENT_ATTR(inst_spec, ARMV8_PMUV3_PERFCTR_INST_SPEC);
 374 ARMV8_EVENT_ATTR(ttbr_write_retired, ARMV8_PMUV3_PERFCTR_TTBR_WRITE_RETIRED);
 375 ARMV8_EVENT_ATTR(bus_cycles, ARMV8_PMUV3_PERFCTR_BUS_CYCLES);
 376 ARMV8_EVENT_ATTR(chain, ARMV8_PMUV3_PERFCTR_CHAIN);
 377 ARMV8_EVENT_ATTR(l1d_cache_allocate, ARMV8_PMUV3_PERFCTR_L1D_CACHE_ALLOCATE);
 378 ARMV8_EVENT_ATTR(l2d_cache_allocate, ARMV8_PMUV3_PERFCTR_L2D_CACHE_ALLOCATE);
 379 ARMV8_EVENT_ATTR(br_retired, ARMV8_PMUV3_PERFCTR_BR_RETIRED);
 380 ARMV8_EVENT_ATTR(br_mis_pred_retired, ARMV8_PMUV3_PERFCTR_BR_MIS_PRED_RETIRED);
 381 ARMV8_EVENT_ATTR(stall_frontend, ARMV8_PMUV3_PERFCTR_STALL_FRONTEND);
 382 ARMV8_EVENT_ATTR(stall_backend, ARMV8_PMUV3_PERFCTR_STALL_BACKEND);
 383 ARMV8_EVENT_ATTR(l1d_tlb, ARMV8_PMUV3_PERFCTR_L1D_TLB);
 384 ARMV8_EVENT_ATTR(l1i_tlb, ARMV8_PMUV3_PERFCTR_L1I_TLB);
 385 ARMV8_EVENT_ATTR(l2i_cache, ARMV8_PMUV3_PERFCTR_L2I_CACHE);
 386 ARMV8_EVENT_ATTR(l2i_cache_refill, ARMV8_PMUV3_PERFCTR_L2I_CACHE_REFILL);
 387 ARMV8_EVENT_ATTR(l3d_cache_allocate, ARMV8_PMUV3_PERFCTR_L3D_CACHE_ALLOCATE);
 388 ARMV8_EVENT_ATTR(l3d_cache_refill, ARMV8_PMUV3_PERFCTR_L3D_CACHE_REFILL);
 389 ARMV8_EVENT_ATTR(l3d_cache, ARMV8_PMUV3_PERFCTR_L3D_CACHE);
 390 ARMV8_EVENT_ATTR(l3d_cache_wb, ARMV8_PMUV3_PERFCTR_L3D_CACHE_WB);
 391 ARMV8_EVENT_ATTR(l2d_tlb_refill, ARMV8_PMUV3_PERFCTR_L2D_TLB_REFILL);
 392 ARMV8_EVENT_ATTR(l2i_tlb_refill, ARMV8_PMUV3_PERFCTR_L2I_TLB_REFILL);
 393 ARMV8_EVENT_ATTR(l2d_tlb, ARMV8_PMUV3_PERFCTR_L2D_TLB);
 394 ARMV8_EVENT_ATTR(l2i_tlb, ARMV8_PMUV3_PERFCTR_L2I_TLB);
 395
 396 static struct attribute *armv8_pmuv3_event_attrs[] = {
 397         &armv8_event_attr_sw_incr.attr.attr,
 398         &armv8_event_attr_l1i_cache_refill.attr.attr,
 399         &armv8_event_attr_l1i_tlb_refill.attr.attr,
 400         &armv8_event_attr_l1d_cache_refill.attr.attr,
 401         &armv8_event_attr_l1d_cache.attr.attr,
 402         &armv8_event_attr_l1d_tlb_refill.attr.attr,
 403         &armv8_event_attr_ld_retired.attr.attr,
 404         &armv8_event_attr_st_retired.attr.attr,
 405         &armv8_event_attr_inst_retired.attr.attr,
 406         &armv8_event_attr_exc_taken.attr.attr,
 407         &armv8_event_attr_exc_return.attr.attr,
 408         &armv8_event_attr_cid_write_retired.attr.attr,
 409         &armv8_event_attr_pc_write_retired.attr.attr,
 410         &armv8_event_attr_br_immed_retired.attr.attr,
 411         &armv8_event_attr_br_return_retired.attr.attr,
 412         &armv8_event_attr_unaligned_ldst_retired.attr.attr,
 413         &armv8_event_attr_br_mis_pred.attr.attr,
 414         &armv8_event_attr_cpu_cycles.attr.attr,
 415         &armv8_event_attr_br_pred.attr.attr,
 416         &armv8_event_attr_mem_access.attr.attr,
 417         &armv8_event_attr_l1i_cache.attr.attr,
 418         &armv8_event_attr_l1d_cache_wb.attr.attr,
 419         &armv8_event_attr_l2d_cache.attr.attr,
 420         &armv8_event_attr_l2d_cache_refill.attr.attr,
 421         &armv8_event_attr_l2d_cache_wb.attr.attr,
 422         &armv8_event_attr_bus_access.attr.attr,
 423         &armv8_event_attr_memory_error.attr.attr,
 424         &armv8_event_attr_inst_spec.attr.attr,
 425         &armv8_event_attr_ttbr_write_retired.attr.attr,
 426         &armv8_event_attr_bus_cycles.attr.attr,
 427         &armv8_event_attr_chain.attr.attr,
 428         &armv8_event_attr_l1d_cache_allocate.attr.attr,
 429         &armv8_event_attr_l2d_cache_allocate.attr.attr,
 430         &armv8_event_attr_br_retired.attr.attr,
 431         &armv8_event_attr_br_mis_pred_retired.attr.attr,
 432         &armv8_event_attr_stall_frontend.attr.attr,
 433         &armv8_event_attr_stall_backend.attr.attr,
 434         &armv8_event_attr_l1d_tlb.attr.attr,
 435         &armv8_event_attr_l1i_tlb.attr.attr,
 436         &armv8_event_attr_l2i_cache.attr.attr,
 437         &armv8_event_attr_l2i_cache_refill.attr.attr,
 438         &armv8_event_attr_l3d_cache_allocate.attr.attr,
 439         &armv8_event_attr_l3d_cache_refill.attr.attr,
 440         &armv8_event_attr_l3d_cache.attr.attr,
 441         &armv8_event_attr_l3d_cache_wb.attr.attr,
 442         &armv8_event_attr_l2d_tlb_refill.attr.attr,
 443         &armv8_event_attr_l2i_tlb_refill.attr.attr,
 444         &armv8_event_attr_l2d_tlb.attr.attr,
 445         &armv8_event_attr_l2i_tlb.attr.attr,
 446         NULL,
 447 };
 448
 449 static umode_t
 450 armv8pmu_event_attr_is_visible(struct kobject *kobj,
 451                                struct attribute *attr, int unused)
 452 {
 453         struct device *dev = kobj_to_dev(kobj);
 454         struct pmu *pmu = dev_get_drvdata(dev);
 455         struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu);
 456         struct perf_pmu_events_attr *pmu_attr;
 457
 458         pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr.attr);
 459
 460         if (test_bit(pmu_attr->id, cpu_pmu->pmceid_bitmap))
 461                 return attr->mode;
 462
 463         return 0;
 464 }
 465
 466 static struct attribute_group armv8_pmuv3_events_attr_group = {
 467         .name = "events",
 468         .attrs = armv8_pmuv3_event_attrs,
 469         .is_visible = armv8pmu_event_attr_is_visible,
 470 };
 471
 472 PMU_FORMAT_ATTR(event, "config:0-9");
 473
 474 static struct attribute *armv8_pmuv3_format_attrs[] = {
 475         &format_attr_event.attr,
 476         NULL,
 477 };
 478
 479 static struct attribute_group armv8_pmuv3_format_attr_group = {
 480         .name = "format",
 481         .attrs = armv8_pmuv3_format_attrs,
 482 };
 483
 484 static const struct attribute_group *armv8_pmuv3_attr_groups[] = {
 485         &armv8_pmuv3_events_attr_group,
 486         &armv8_pmuv3_format_attr_group,
 487         NULL,
 488 };
 489
 490 /*
 491  * Perf Events' indices
 492  */
 493 #define ARMV8_IDX_CYCLE_COUNTER 0
 494 #define ARMV8_IDX_COUNTER0      1
 495 #define ARMV8_IDX_COUNTER_LAST(cpu_pmu) \
 496         (ARMV8_IDX_CYCLE_COUNTER + cpu_pmu->num_events - 1)
 497
 498 /*
 499  * ARMv8 low level PMU access
 500  */
 501
 502 /*
 503  * Perf Event to low level counters mapping
 504  */
 505 #define ARMV8_IDX_TO_COUNTER(x) \
 506         (((x) - ARMV8_IDX_COUNTER0) & ARMV8_PMU_COUNTER_MASK)
 507
 508 static inline u32 armv8pmu_pmcr_read(void)
 509 {
 510         return read_sysreg(pmcr_el0);
 511 }
 512
 513 static inline void armv8pmu_pmcr_write(u32 val)
 514 {
 515         val &= ARMV8_PMU_PMCR_MASK;
 516         isb();
 517         write_sysreg(val, pmcr_el0);
 518 }
 519
 520 static inline int armv8pmu_has_overflowed(u32 pmovsr)
 521 {
 522         return pmovsr & ARMV8_PMU_OVERFLOWED_MASK;
 523 }
 524
 525 static inline int armv8pmu_counter_valid(struct arm_pmu *cpu_pmu, int idx)
 526 {
 527         return idx >= ARMV8_IDX_CYCLE_COUNTER &&
 528                 idx <= ARMV8_IDX_COUNTER_LAST(cpu_pmu);
 529 }
 530
 531 static inline int armv8pmu_counter_has_overflowed(u32 pmnc, int idx)
 532 {
 533         return pmnc & BIT(ARMV8_IDX_TO_COUNTER(idx));
 534 }
 535
 536 static inline int armv8pmu_select_counter(int idx)
 537 {
 538         u32 counter = ARMV8_IDX_TO_COUNTER(idx);
 539         write_sysreg(counter, pmselr_el0);
 540         isb();
 541
 542         return idx;
 543 }
 544
 545 static inline u32 armv8pmu_read_counter(struct perf_event *event)
 546 {
 547         struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
 548         struct hw_perf_event *hwc = &event->hw;
 549         int idx = hwc->idx;
 550         u32 value = 0;
 551
 552         if (!armv8pmu_counter_valid(cpu_pmu, idx))
 553                 pr_err("CPU%u reading wrong counter %d\n",
 554                         smp_processor_id(), idx);
 555         else if (idx == ARMV8_IDX_CYCLE_COUNTER)
 556                 value = read_sysreg(pmccntr_el0);
 557         else if (armv8pmu_select_counter(idx) == idx)
 558                 value = read_sysreg(pmxevcntr_el0);
 559
 560         return value;
 561 }
 562
 563 static inline void armv8pmu_write_counter(struct perf_event *event, u32 value)
 564 {
 565         struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
 566         struct hw_perf_event *hwc = &event->hw;
 567         int idx = hwc->idx;
 568
 569         if (!armv8pmu_counter_valid(cpu_pmu, idx))
 570                 pr_err("CPU%u writing wrong counter %d\n",
 571                         smp_processor_id(), idx);
 572         else if (idx == ARMV8_IDX_CYCLE_COUNTER) {
 573                 /*
 574                  * Set the upper 32bits as this is a 64bit counter but we only
 575                  * count using the lower 32bits and we want an interrupt when
 576                  * it overflows.
 577                  */
 578                 u64 value64 = 0xffffffff00000000ULL | value;
 579
 580                 write_sysreg(value64, pmccntr_el0);
 581         } else if (armv8pmu_select_counter(idx) == idx)
 582                 write_sysreg(value, pmxevcntr_el0);
 583 }
 584
 585 static inline void armv8pmu_write_evtype(int idx, u32 val)
 586 {
 587         if (armv8pmu_select_counter(idx) == idx) {
 588                 val &= ARMV8_PMU_EVTYPE_MASK;
 589                 write_sysreg(val, pmxevtyper_el0);
 590         }
 591 }
 592
 593 static inline int armv8pmu_enable_counter(int idx)
 594 {
 595         u32 counter = ARMV8_IDX_TO_COUNTER(idx);
 596         write_sysreg(BIT(counter), pmcntenset_el0);
 597         return idx;
 598 }
 599
 600 static inline int armv8pmu_disable_counter(int idx)
 601 {
 602         u32 counter = ARMV8_IDX_TO_COUNTER(idx);
 603         write_sysreg(BIT(counter), pmcntenclr_el0);
 604         return idx;
 605 }
 606
 607 static inline int armv8pmu_enable_intens(int idx)
 608 {
 609         u32 counter = ARMV8_IDX_TO_COUNTER(idx);
 610         write_sysreg(BIT(counter), pmintenset_el1);
 611         return idx;
 612 }
 613
 614 static inline int armv8pmu_disable_intens(int idx)
 615 {
 616         u32 counter = ARMV8_IDX_TO_COUNTER(idx);
 617         write_sysreg(BIT(counter), pmintenclr_el1);
 618         isb();
 619         /* Clear the overflow flag in case an interrupt is pending. */
 620         write_sysreg(BIT(counter), pmovsclr_el0);
 621         isb();
 622
 623         return idx;
 624 }
 625
 626 static inline u32 armv8pmu_getreset_flags(void)
 627 {
 628         u32 value;
 629
 630         /* Read */
 631         value = read_sysreg(pmovsclr_el0);
 632
 633         /* Write to clear flags */
 634         value &= ARMV8_PMU_OVSR_MASK;
 635         write_sysreg(value, pmovsclr_el0);
 636
 637         return value;
 638 }
 639
 640 static void armv8pmu_enable_event(struct perf_event *event)
 641 {
 642         unsigned long flags;
 643         struct hw_perf_event *hwc = &event->hw;
 644         struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
 645         struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
 646         int idx = hwc->idx;
 647
 648         /*
 649          * Enable counter and interrupt, and set the counter to count
 650          * the event that we're interested in.
 651          */
 652         raw_spin_lock_irqsave(&events->pmu_lock, flags);
 653
 654         /*
 655          * Disable counter
 656          */
 657         armv8pmu_disable_counter(idx);
 658
 659         /*
 660          * Set event (if destined for PMNx counters).
 661          */
 662         armv8pmu_write_evtype(idx, hwc->config_base);
 663
 664         /*
 665          * Enable interrupt for this counter
 666          */
 667         armv8pmu_enable_intens(idx);
 668
 669         /*
 670          * Enable counter
 671          */
 672         armv8pmu_enable_counter(idx);
 673
 674         raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
 675 }
 676
 677 static void armv8pmu_disable_event(struct perf_event *event)
 678 {
 679         unsigned long flags;
 680         struct hw_perf_event *hwc = &event->hw;
 681         struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
 682         struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
 683         int idx = hwc->idx;
 684
 685         /*
 686          * Disable counter and interrupt
 687          */
 688         raw_spin_lock_irqsave(&events->pmu_lock, flags);
 689
 690         /*
 691          * Disable counter
 692          */
 693         armv8pmu_disable_counter(idx);
 694
 695         /*
 696          * Disable interrupt for this counter
 697          */
 698         armv8pmu_disable_intens(idx);
 699
 700         raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
 701 }
 702
 703 static irqreturn_t armv8pmu_handle_irq(int irq_num, void *dev)
 704 {
 705         u32 pmovsr;
 706         struct perf_sample_data data;
 707         struct arm_pmu *cpu_pmu = (struct arm_pmu *)dev;
 708         struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events);
 709         struct pt_regs *regs;
 710         int idx;
 711
 712         /*
 713          * Get and reset the IRQ flags
 714          */
 715         pmovsr = armv8pmu_getreset_flags();
 716
 717         /*
 718          * Did an overflow occur?
 719          */
 720         if (!armv8pmu_has_overflowed(pmovsr))
 721                 return IRQ_NONE;
 722
 723         /*
 724          * Handle the counter(s) overflow(s)
 725          */
 726         regs = get_irq_regs();
 727
 728         for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
 729                 struct perf_event *event = cpuc->events[idx];
 730                 struct hw_perf_event *hwc;
 731
 732                 /* Ignore if we don't have an event. */
 733                 if (!event)
 734                         continue;
 735
 736                 /*
 737                  * We have a single interrupt for all counters. Check that
 738                  * each counter has overflowed before we process it.
 739                  */
 740                 if (!armv8pmu_counter_has_overflowed(pmovsr, idx))
 741                         continue;
 742
 743                 hwc = &event->hw;
 744                 armpmu_event_update(event);
 745                 perf_sample_data_init(&data, 0, hwc->last_period);
 746                 if (!armpmu_event_set_period(event))
 747                         continue;
 748
 749                 if (perf_event_overflow(event, &data, regs))
 750                         cpu_pmu->disable(event);
 751         }
 752
 753         /*
 754          * Handle the pending perf events.
 755          *
 756          * Note: this call *must* be run with interrupts disabled. For
 757          * platforms that can have the PMU interrupts raised as an NMI, this
 758          * will not work.
 759          */
 760         irq_work_run();
 761
 762         return IRQ_HANDLED;
 763 }
 764
 765 static void armv8pmu_start(struct arm_pmu *cpu_pmu)
 766 {
 767         unsigned long flags;
 768         struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
 769
 770         raw_spin_lock_irqsave(&events->pmu_lock, flags);
 771         /* Enable all counters */
 772         armv8pmu_pmcr_write(armv8pmu_pmcr_read() | ARMV8_PMU_PMCR_E);
 773         raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
 774 }
 775
 776 static void armv8pmu_stop(struct arm_pmu *cpu_pmu)
 777 {
 778         unsigned long flags;
 779         struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
 780
 781         raw_spin_lock_irqsave(&events->pmu_lock, flags);
 782         /* Disable all counters */
 783         armv8pmu_pmcr_write(armv8pmu_pmcr_read() & ~ARMV8_PMU_PMCR_E);
 784         raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
 785 }
 786
 787 static int armv8pmu_get_event_idx(struct pmu_hw_events *cpuc,
 788                                   struct perf_event *event)
 789 {
 790         int idx;
 791         struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
 792         struct hw_perf_event *hwc = &event->hw;
 793         unsigned long evtype = hwc->config_base & ARMV8_PMU_EVTYPE_EVENT;
 794
 795         /* Always place a cycle counter into the cycle counter. */
 796         if (evtype == ARMV8_PMUV3_PERFCTR_CPU_CYCLES) {
 797                 if (test_and_set_bit(ARMV8_IDX_CYCLE_COUNTER, cpuc->used_mask))
 798                         return -EAGAIN;
 799
 800                 return ARMV8_IDX_CYCLE_COUNTER;
 801         }
 802
 803         /*
 804          * For anything other than a cycle counter, try and use
 805          * the events counters
 806          */
 807         for (idx = ARMV8_IDX_COUNTER0; idx < cpu_pmu->num_events; ++idx) {
 808                 if (!test_and_set_bit(idx, cpuc->used_mask))
 809                         return idx;
 810         }
 811
 812         /* The counters are all in use. */
 813         return -EAGAIN;
 814 }
 815
 816 /*
 817  * Add an event filter to a given event. This will only work for PMUv2 PMUs.
 818  */
 819 static int armv8pmu_set_event_filter(struct hw_perf_event *event,
 820                                      struct perf_event_attr *attr)
 821 {
 822         unsigned long config_base = 0;
 823
 824         if (attr->exclude_idle)
 825                 return -EPERM;
 826         if (is_kernel_in_hyp_mode() &&
 827             attr->exclude_kernel != attr->exclude_hv)
 828                 return -EINVAL;
 829         if (attr->exclude_user)
 830                 config_base |= ARMV8_PMU_EXCLUDE_EL0;
 831         if (!is_kernel_in_hyp_mode() && attr->exclude_kernel)
 832                 config_base |= ARMV8_PMU_EXCLUDE_EL1;
 833         if (!attr->exclude_hv)
 834                 config_base |= ARMV8_PMU_INCLUDE_EL2;
 835
 836         /*
 837          * Install the filter into config_base as this is used to
 838          * construct the event type.
 839          */
 840         event->config_base = config_base;
 841
 842         return 0;
 843 }
 844
 845 static void armv8pmu_reset(void *info)
 846 {
 847         struct arm_pmu *cpu_pmu = (struct arm_pmu *)info;
 848         u32 idx, nb_cnt = cpu_pmu->num_events;
 849
 850         /* The counter and interrupt enable registers are unknown at reset. */
 851         for (idx = ARMV8_IDX_CYCLE_COUNTER; idx < nb_cnt; ++idx) {
 852                 armv8pmu_disable_counter(idx);
 853                 armv8pmu_disable_intens(idx);
 854         }
 855
 856         /*
 857          * Initialize & Reset PMNC. Request overflow interrupt for
 858          * 64 bit cycle counter but cheat in armv8pmu_write_counter().
 859          */
 860         armv8pmu_pmcr_write(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C |
 861                             ARMV8_PMU_PMCR_LC);
 862 }
 863
 864 static int armv8_pmuv3_map_event(struct perf_event *event)
 865 {
 866         return armpmu_map_event(event, &armv8_pmuv3_perf_map,
 867                                 &armv8_pmuv3_perf_cache_map,
 868                                 ARMV8_PMU_EVTYPE_EVENT);
 869 }
 870
 871 static int armv8_a53_map_event(struct perf_event *event)
 872 {
 873         return armpmu_map_event(event, &armv8_a53_perf_map,
 874                                 &armv8_a53_perf_cache_map,
 875                                 ARMV8_PMU_EVTYPE_EVENT);
 876 }
 877
 878 static int armv8_a57_map_event(struct perf_event *event)
 879 {
 880         return armpmu_map_event(event, &armv8_a57_perf_map,
 881                                 &armv8_a57_perf_cache_map,
 882                                 ARMV8_PMU_EVTYPE_EVENT);
 883 }
 884
 885 static int armv8_thunder_map_event(struct perf_event *event)
 886 {
 887         return armpmu_map_event(event, &armv8_thunder_perf_map,
 888                                 &armv8_thunder_perf_cache_map,
 889                                 ARMV8_PMU_EVTYPE_EVENT);
 890 }
 891
 892 static void __armv8pmu_probe_pmu(void *info)
 893 {
 894         struct arm_pmu *cpu_pmu = info;
 895         u32 pmceid[2];
 896
 897         /* Read the nb of CNTx counters supported from PMNC */
 898         cpu_pmu->num_events = (armv8pmu_pmcr_read() >> ARMV8_PMU_PMCR_N_SHIFT)
 899                 & ARMV8_PMU_PMCR_N_MASK;
 900
 901         /* Add the CPU cycles counter */
 902         cpu_pmu->num_events += 1;
 903
 904         pmceid[0] = read_sysreg(pmceid0_el0);
 905         pmceid[1] = read_sysreg(pmceid1_el0);
 906
 907         bitmap_from_u32array(cpu_pmu->pmceid_bitmap,
 908                              ARMV8_PMUV3_MAX_COMMON_EVENTS, pmceid,
 909                              ARRAY_SIZE(pmceid));
 910 }
 911
 912 static int armv8pmu_probe_pmu(struct arm_pmu *cpu_pmu)
 913 {
 914         return smp_call_function_any(&cpu_pmu->supported_cpus,
 915                                     __armv8pmu_probe_pmu,
 916                                     cpu_pmu, 1);
 917 }
 918
 919 static void armv8_pmu_init(struct arm_pmu *cpu_pmu)
 920 {
 921         cpu_pmu->handle_irq             = armv8pmu_handle_irq,
 922         cpu_pmu->enable                 = armv8pmu_enable_event,
 923         cpu_pmu->disable                = armv8pmu_disable_event,
 924         cpu_pmu->read_counter           = armv8pmu_read_counter,
 925         cpu_pmu->write_counter          = armv8pmu_write_counter,
 926         cpu_pmu->get_event_idx          = armv8pmu_get_event_idx,
 927         cpu_pmu->start                  = armv8pmu_start,
 928         cpu_pmu->stop                   = armv8pmu_stop,
 929         cpu_pmu->reset                  = armv8pmu_reset,
 930         cpu_pmu->max_period             = (1LLU << 32) - 1,
 931         cpu_pmu->set_event_filter       = armv8pmu_set_event_filter;
 932 }
 933
 934 static int armv8_pmuv3_init(struct arm_pmu *cpu_pmu)
 935 {
 936         armv8_pmu_init(cpu_pmu);
 937         cpu_pmu->name                   = "armv8_pmuv3";
 938         cpu_pmu->map_event              = armv8_pmuv3_map_event;
 939         cpu_pmu->pmu.attr_groups        = armv8_pmuv3_attr_groups;
 940         return armv8pmu_probe_pmu(cpu_pmu);
 941 }
 942
 943 static int armv8_a53_pmu_init(struct arm_pmu *cpu_pmu)
 944 {
 945         armv8_pmu_init(cpu_pmu);
 946         cpu_pmu->name                   = "armv8_cortex_a53";
 947         cpu_pmu->map_event              = armv8_a53_map_event;
 948         cpu_pmu->pmu.attr_groups        = armv8_pmuv3_attr_groups;
 949         return armv8pmu_probe_pmu(cpu_pmu);
 950 }
 951
 952 static int armv8_a57_pmu_init(struct arm_pmu *cpu_pmu)
 953 {
 954         armv8_pmu_init(cpu_pmu);
 955         cpu_pmu->name                   = "armv8_cortex_a57";
 956         cpu_pmu->map_event              = armv8_a57_map_event;
 957         cpu_pmu->pmu.attr_groups        = armv8_pmuv3_attr_groups;
 958         return armv8pmu_probe_pmu(cpu_pmu);
 959 }
 960
 961 static int armv8_a72_pmu_init(struct arm_pmu *cpu_pmu)
 962 {
 963         armv8_pmu_init(cpu_pmu);
 964         cpu_pmu->name                   = "armv8_cortex_a72";
 965         cpu_pmu->map_event              = armv8_a57_map_event;
 966         cpu_pmu->pmu.attr_groups        = armv8_pmuv3_attr_groups;
 967         return armv8pmu_probe_pmu(cpu_pmu);
 968 }
 969
 970 static int armv8_thunder_pmu_init(struct arm_pmu *cpu_pmu)
 971 {
 972         armv8_pmu_init(cpu_pmu);
 973         cpu_pmu->name                   = "armv8_cavium_thunder";
 974         cpu_pmu->map_event              = armv8_thunder_map_event;
 975         cpu_pmu->pmu.attr_groups        = armv8_pmuv3_attr_groups;
 976         return armv8pmu_probe_pmu(cpu_pmu);
 977 }
 978
 979 static const struct of_device_id armv8_pmu_of_device_ids[] = {
 980         {.compatible = "arm,armv8-pmuv3",       .data = armv8_pmuv3_init},
 981         {.compatible = "arm,cortex-a53-pmu",    .data = armv8_a53_pmu_init},
 982         {.compatible = "arm,cortex-a57-pmu",    .data = armv8_a57_pmu_init},
 983         {.compatible = "arm,cortex-a72-pmu",    .data = armv8_a72_pmu_init},
 984         {.compatible = "cavium,thunder-pmu",    .data = armv8_thunder_pmu_init},
 985         {},
 986 };
 987
 988 static int armv8_pmu_device_probe(struct platform_device *pdev)
 989 {
 990         return arm_pmu_device_probe(pdev, armv8_pmu_of_device_ids, NULL);
 991 }
 992
 993 static struct platform_driver armv8_pmu_driver = {
 994         .driver         = {
 995                 .name   = "armv8-pmu",
 996                 .of_match_table = armv8_pmu_of_device_ids,
 997         },
 998         .probe          = armv8_pmu_device_probe,
 999 };
1000
1001 static int __init register_armv8_pmu_driver(void)
1002 {
1003         return platform_driver_register(&armv8_pmu_driver);
1004 }
1005 device_initcall(register_armv8_pmu_driver);