arch/arm64/kernel/hw_breakpoint.c

   1 /*
   2  * HW_breakpoint: a unified kernel/user-space hardware breakpoint facility,
   3  * using the CPU's debug registers.
   4  *
   5  * Copyright (C) 2012 ARM Limited
   6  * Author: Will Deacon <will.deacon@arm.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #define pr_fmt(fmt) "hw-breakpoint: " fmt
  22
  23 #include <linux/compat.h>
  24 #include <linux/cpu_pm.h>
  25 #include <linux/errno.h>
  26 #include <linux/hw_breakpoint.h>
  27 #include <linux/kprobes.h>
  28 #include <linux/perf_event.h>
  29 #include <linux/ptrace.h>
  30 #include <linux/smp.h>
  31 #include <linux/uaccess.h>
  32
  33 #include <asm/current.h>
  34 #include <asm/debug-monitors.h>
  35 #include <asm/hw_breakpoint.h>
  36 #include <asm/traps.h>
  37 #include <asm/cputype.h>
  38 #include <asm/system_misc.h>
  39
  40 /* Breakpoint currently in use for each BRP. */
  41 static DEFINE_PER_CPU(struct perf_event *, bp_on_reg[ARM_MAX_BRP]);
  42
  43 /* Watchpoint currently in use for each WRP. */
  44 static DEFINE_PER_CPU(struct perf_event *, wp_on_reg[ARM_MAX_WRP]);
  45
  46 /* Currently stepping a per-CPU kernel breakpoint. */
  47 static DEFINE_PER_CPU(int, stepping_kernel_bp);
  48
  49 /* Number of BRP/WRP registers on this CPU. */
  50 static int core_num_brps;
  51 static int core_num_wrps;
  52
  53 int hw_breakpoint_slots(int type)
  54 {
  55         /*
  56          * We can be called early, so don't rely on
  57          * our static variables being initialised.
  58          */
  59         switch (type) {
  60         case TYPE_INST:
  61                 return get_num_brps();
  62         case TYPE_DATA:
  63                 return get_num_wrps();
  64         default:
  65                 pr_warning("unknown slot type: %d\n", type);
  66                 return 0;
  67         }
  68 }
  69
  70 #define READ_WB_REG_CASE(OFF, N, REG, VAL)      \
  71         case (OFF + N):                         \
  72                 AARCH64_DBG_READ(N, REG, VAL);  \
  73                 break
  74
  75 #define WRITE_WB_REG_CASE(OFF, N, REG, VAL)     \
  76         case (OFF + N):                         \
  77                 AARCH64_DBG_WRITE(N, REG, VAL); \
  78                 break
  79
  80 #define GEN_READ_WB_REG_CASES(OFF, REG, VAL)    \
  81         READ_WB_REG_CASE(OFF,  0, REG, VAL);    \
  82         READ_WB_REG_CASE(OFF,  1, REG, VAL);    \
  83         READ_WB_REG_CASE(OFF,  2, REG, VAL);    \
  84         READ_WB_REG_CASE(OFF,  3, REG, VAL);    \
  85         READ_WB_REG_CASE(OFF,  4, REG, VAL);    \
  86         READ_WB_REG_CASE(OFF,  5, REG, VAL);    \
  87         READ_WB_REG_CASE(OFF,  6, REG, VAL);    \
  88         READ_WB_REG_CASE(OFF,  7, REG, VAL);    \
  89         READ_WB_REG_CASE(OFF,  8, REG, VAL);    \
  90         READ_WB_REG_CASE(OFF,  9, REG, VAL);    \
  91         READ_WB_REG_CASE(OFF, 10, REG, VAL);    \
  92         READ_WB_REG_CASE(OFF, 11, REG, VAL);    \
  93         READ_WB_REG_CASE(OFF, 12, REG, VAL);    \
  94         READ_WB_REG_CASE(OFF, 13, REG, VAL);    \
  95         READ_WB_REG_CASE(OFF, 14, REG, VAL);    \
  96         READ_WB_REG_CASE(OFF, 15, REG, VAL)
  97
  98 #define GEN_WRITE_WB_REG_CASES(OFF, REG, VAL)   \
  99         WRITE_WB_REG_CASE(OFF,  0, REG, VAL);   \
 100         WRITE_WB_REG_CASE(OFF,  1, REG, VAL);   \
 101         WRITE_WB_REG_CASE(OFF,  2, REG, VAL);   \
 102         WRITE_WB_REG_CASE(OFF,  3, REG, VAL);   \
 103         WRITE_WB_REG_CASE(OFF,  4, REG, VAL);   \
 104         WRITE_WB_REG_CASE(OFF,  5, REG, VAL);   \
 105         WRITE_WB_REG_CASE(OFF,  6, REG, VAL);   \
 106         WRITE_WB_REG_CASE(OFF,  7, REG, VAL);   \
 107         WRITE_WB_REG_CASE(OFF,  8, REG, VAL);   \
 108         WRITE_WB_REG_CASE(OFF,  9, REG, VAL);   \
 109         WRITE_WB_REG_CASE(OFF, 10, REG, VAL);   \
 110         WRITE_WB_REG_CASE(OFF, 11, REG, VAL);   \
 111         WRITE_WB_REG_CASE(OFF, 12, REG, VAL);   \
 112         WRITE_WB_REG_CASE(OFF, 13, REG, VAL);   \
 113         WRITE_WB_REG_CASE(OFF, 14, REG, VAL);   \
 114         WRITE_WB_REG_CASE(OFF, 15, REG, VAL)
 115
 116 static u64 read_wb_reg(int reg, int n)
 117 {
 118         u64 val = 0;
 119
 120         switch (reg + n) {
 121         GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_BVR, AARCH64_DBG_REG_NAME_BVR, val);
 122         GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_BCR, AARCH64_DBG_REG_NAME_BCR, val);
 123         GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_WVR, AARCH64_DBG_REG_NAME_WVR, val);
 124         GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_WCR, AARCH64_DBG_REG_NAME_WCR, val);
 125         default:
 126                 pr_warning("attempt to read from unknown breakpoint register %d\n", n);
 127         }
 128
 129         return val;
 130 }
 131 NOKPROBE_SYMBOL(read_wb_reg);
 132
 133 static void write_wb_reg(int reg, int n, u64 val)
 134 {
 135         switch (reg + n) {
 136         GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_BVR, AARCH64_DBG_REG_NAME_BVR, val);
 137         GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_BCR, AARCH64_DBG_REG_NAME_BCR, val);
 138         GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_WVR, AARCH64_DBG_REG_NAME_WVR, val);
 139         GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_WCR, AARCH64_DBG_REG_NAME_WCR, val);
 140         default:
 141                 pr_warning("attempt to write to unknown breakpoint register %d\n", n);
 142         }
 143         isb();
 144 }
 145 NOKPROBE_SYMBOL(write_wb_reg);
 146
 147 /*
 148  * Convert a breakpoint privilege level to the corresponding exception
 149  * level.
 150  */
 151 static enum dbg_active_el debug_exception_level(int privilege)
 152 {
 153         switch (privilege) {
 154         case AARCH64_BREAKPOINT_EL0:
 155                 return DBG_ACTIVE_EL0;
 156         case AARCH64_BREAKPOINT_EL1:
 157                 return DBG_ACTIVE_EL1;
 158         default:
 159                 pr_warning("invalid breakpoint privilege level %d\n", privilege);
 160                 return -EINVAL;
 161         }
 162 }
 163 NOKPROBE_SYMBOL(debug_exception_level);
 164
 165 enum hw_breakpoint_ops {
 166         HW_BREAKPOINT_INSTALL,
 167         HW_BREAKPOINT_UNINSTALL,
 168         HW_BREAKPOINT_RESTORE
 169 };
 170
 171 static int is_compat_bp(struct perf_event *bp)
 172 {
 173         struct task_struct *tsk = bp->hw.target;
 174
 175         /*
 176          * tsk can be NULL for per-cpu (non-ptrace) breakpoints.
 177          * In this case, use the native interface, since we don't have
 178          * the notion of a "compat CPU" and could end up relying on
 179          * deprecated behaviour if we use unaligned watchpoints in
 180          * AArch64 state.
 181          */
 182         return tsk && is_compat_thread(task_thread_info(tsk));
 183 }
 184
 185 /**
 186  * hw_breakpoint_slot_setup - Find and setup a perf slot according to
 187  *                            operations
 188  *
 189  * @slots: pointer to array of slots
 190  * @max_slots: max number of slots
 191  * @bp: perf_event to setup
 192  * @ops: operation to be carried out on the slot
 193  *
 194  * Return:
 195  *      slot index on success
 196  *      -ENOSPC if no slot is available/matches
 197  *      -EINVAL on wrong operations parameter
 198  */
 199 static int hw_breakpoint_slot_setup(struct perf_event **slots, int max_slots,
 200                                     struct perf_event *bp,
 201                                     enum hw_breakpoint_ops ops)
 202 {
 203         int i;
 204         struct perf_event **slot;
 205
 206         for (i = 0; i < max_slots; ++i) {
 207                 slot = &slots[i];
 208                 switch (ops) {
 209                 case HW_BREAKPOINT_INSTALL:
 210                         if (!*slot) {
 211                                 *slot = bp;
 212                                 return i;
 213                         }
 214                         break;
 215                 case HW_BREAKPOINT_UNINSTALL:
 216                         if (*slot == bp) {
 217                                 *slot = NULL;
 218                                 return i;
 219                         }
 220                         break;
 221                 case HW_BREAKPOINT_RESTORE:
 222                         if (*slot == bp)
 223                                 return i;
 224                         break;
 225                 default:
 226                         pr_warn_once("Unhandled hw breakpoint ops %d\n", ops);
 227                         return -EINVAL;
 228                 }
 229         }
 230         return -ENOSPC;
 231 }
 232
 233 static int hw_breakpoint_control(struct perf_event *bp,
 234                                  enum hw_breakpoint_ops ops)
 235 {
 236         struct arch_hw_breakpoint *info = counter_arch_bp(bp);
 237         struct perf_event **slots;
 238         struct debug_info *debug_info = &current->thread.debug;
 239         int i, max_slots, ctrl_reg, val_reg, reg_enable;
 240         enum dbg_active_el dbg_el = debug_exception_level(info->ctrl.privilege);
 241         u32 ctrl;
 242
 243         if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) {
 244                 /* Breakpoint */
 245                 ctrl_reg = AARCH64_DBG_REG_BCR;
 246                 val_reg = AARCH64_DBG_REG_BVR;
 247                 slots = this_cpu_ptr(bp_on_reg);
 248                 max_slots = core_num_brps;
 249                 reg_enable = !debug_info->bps_disabled;
 250         } else {
 251                 /* Watchpoint */
 252                 ctrl_reg = AARCH64_DBG_REG_WCR;
 253                 val_reg = AARCH64_DBG_REG_WVR;
 254                 slots = this_cpu_ptr(wp_on_reg);
 255                 max_slots = core_num_wrps;
 256                 reg_enable = !debug_info->wps_disabled;
 257         }
 258
 259         i = hw_breakpoint_slot_setup(slots, max_slots, bp, ops);
 260
 261         if (WARN_ONCE(i < 0, "Can't find any breakpoint slot"))
 262                 return i;
 263
 264         switch (ops) {
 265         case HW_BREAKPOINT_INSTALL:
 266                 /*
 267                  * Ensure debug monitors are enabled at the correct exception
 268                  * level.
 269                  */
 270                 enable_debug_monitors(dbg_el);
 271                 /* Fall through */
 272         case HW_BREAKPOINT_RESTORE:
 273                 /* Setup the address register. */
 274                 write_wb_reg(val_reg, i, info->address);
 275
 276                 /* Setup the control register. */
 277                 ctrl = encode_ctrl_reg(info->ctrl);
 278                 write_wb_reg(ctrl_reg, i,
 279                              reg_enable ? ctrl | 0x1 : ctrl & ~0x1);
 280                 break;
 281         case HW_BREAKPOINT_UNINSTALL:
 282                 /* Reset the control register. */
 283                 write_wb_reg(ctrl_reg, i, 0);
 284
 285                 /*
 286                  * Release the debug monitors for the correct exception
 287                  * level.
 288                  */
 289                 disable_debug_monitors(dbg_el);
 290                 break;
 291         }
 292
 293         return 0;
 294 }
 295
 296 /*
 297  * Install a perf counter breakpoint.
 298  */
 299 int arch_install_hw_breakpoint(struct perf_event *bp)
 300 {
 301         return hw_breakpoint_control(bp, HW_BREAKPOINT_INSTALL);
 302 }
 303
 304 void arch_uninstall_hw_breakpoint(struct perf_event *bp)
 305 {
 306         hw_breakpoint_control(bp, HW_BREAKPOINT_UNINSTALL);
 307 }
 308
 309 static int get_hbp_len(u8 hbp_len)
 310 {
 311         unsigned int len_in_bytes = 0;
 312
 313         switch (hbp_len) {
 314         case ARM_BREAKPOINT_LEN_1:
 315                 len_in_bytes = 1;
 316                 break;
 317         case ARM_BREAKPOINT_LEN_2:
 318                 len_in_bytes = 2;
 319                 break;
 320         case ARM_BREAKPOINT_LEN_3:
 321                 len_in_bytes = 3;
 322                 break;
 323         case ARM_BREAKPOINT_LEN_4:
 324                 len_in_bytes = 4;
 325                 break;
 326         case ARM_BREAKPOINT_LEN_5:
 327                 len_in_bytes = 5;
 328                 break;
 329         case ARM_BREAKPOINT_LEN_6:
 330                 len_in_bytes = 6;
 331                 break;
 332         case ARM_BREAKPOINT_LEN_7:
 333                 len_in_bytes = 7;
 334                 break;
 335         case ARM_BREAKPOINT_LEN_8:
 336                 len_in_bytes = 8;
 337                 break;
 338         }
 339
 340         return len_in_bytes;
 341 }
 342
 343 /*
 344  * Check whether bp virtual address is in kernel space.
 345  */
 346 int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint *hw)
 347 {
 348         unsigned int len;
 349         unsigned long va;
 350
 351         va = hw->address;
 352         len = get_hbp_len(hw->ctrl.len);
 353
 354         return (va >= TASK_SIZE) && ((va + len - 1) >= TASK_SIZE);
 355 }
 356
 357 /*
 358  * Extract generic type and length encodings from an arch_hw_breakpoint_ctrl.
 359  * Hopefully this will disappear when ptrace can bypass the conversion
 360  * to generic breakpoint descriptions.
 361  */
 362 int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl,
 363                            int *gen_len, int *gen_type, int *offset)
 364 {
 365         /* Type */
 366         switch (ctrl.type) {
 367         case ARM_BREAKPOINT_EXECUTE:
 368                 *gen_type = HW_BREAKPOINT_X;
 369                 break;
 370         case ARM_BREAKPOINT_LOAD:
 371                 *gen_type = HW_BREAKPOINT_R;
 372                 break;
 373         case ARM_BREAKPOINT_STORE:
 374                 *gen_type = HW_BREAKPOINT_W;
 375                 break;
 376         case ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE:
 377                 *gen_type = HW_BREAKPOINT_RW;
 378                 break;
 379         default:
 380                 return -EINVAL;
 381         }
 382
 383         if (!ctrl.len)
 384                 return -EINVAL;
 385         *offset = __ffs(ctrl.len);
 386
 387         /* Len */
 388         switch (ctrl.len >> *offset) {
 389         case ARM_BREAKPOINT_LEN_1:
 390                 *gen_len = HW_BREAKPOINT_LEN_1;
 391                 break;
 392         case ARM_BREAKPOINT_LEN_2:
 393                 *gen_len = HW_BREAKPOINT_LEN_2;
 394                 break;
 395         case ARM_BREAKPOINT_LEN_3:
 396                 *gen_len = HW_BREAKPOINT_LEN_3;
 397                 break;
 398         case ARM_BREAKPOINT_LEN_4:
 399                 *gen_len = HW_BREAKPOINT_LEN_4;
 400                 break;
 401         case ARM_BREAKPOINT_LEN_5:
 402                 *gen_len = HW_BREAKPOINT_LEN_5;
 403                 break;
 404         case ARM_BREAKPOINT_LEN_6:
 405                 *gen_len = HW_BREAKPOINT_LEN_6;
 406                 break;
 407         case ARM_BREAKPOINT_LEN_7:
 408                 *gen_len = HW_BREAKPOINT_LEN_7;
 409                 break;
 410         case ARM_BREAKPOINT_LEN_8:
 411                 *gen_len = HW_BREAKPOINT_LEN_8;
 412                 break;
 413         default:
 414                 return -EINVAL;
 415         }
 416
 417         return 0;
 418 }
 419
 420 /*
 421  * Construct an arch_hw_breakpoint from a perf_event.
 422  */
 423 static int arch_build_bp_info(struct perf_event *bp)
 424 {
 425         struct arch_hw_breakpoint *info = counter_arch_bp(bp);
 426
 427         /* Type */
 428         switch (bp->attr.bp_type) {
 429         case HW_BREAKPOINT_X:
 430                 info->ctrl.type = ARM_BREAKPOINT_EXECUTE;
 431                 break;
 432         case HW_BREAKPOINT_R:
 433                 info->ctrl.type = ARM_BREAKPOINT_LOAD;
 434                 break;
 435         case HW_BREAKPOINT_W:
 436                 info->ctrl.type = ARM_BREAKPOINT_STORE;
 437                 break;
 438         case HW_BREAKPOINT_RW:
 439                 info->ctrl.type = ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE;
 440                 break;
 441         default:
 442                 return -EINVAL;
 443         }
 444
 445         /* Len */
 446         switch (bp->attr.bp_len) {
 447         case HW_BREAKPOINT_LEN_1:
 448                 info->ctrl.len = ARM_BREAKPOINT_LEN_1;
 449                 break;
 450         case HW_BREAKPOINT_LEN_2:
 451                 info->ctrl.len = ARM_BREAKPOINT_LEN_2;
 452                 break;
 453         case HW_BREAKPOINT_LEN_3:
 454                 info->ctrl.len = ARM_BREAKPOINT_LEN_3;
 455                 break;
 456         case HW_BREAKPOINT_LEN_4:
 457                 info->ctrl.len = ARM_BREAKPOINT_LEN_4;
 458                 break;
 459         case HW_BREAKPOINT_LEN_5:
 460                 info->ctrl.len = ARM_BREAKPOINT_LEN_5;
 461                 break;
 462         case HW_BREAKPOINT_LEN_6:
 463                 info->ctrl.len = ARM_BREAKPOINT_LEN_6;
 464                 break;
 465         case HW_BREAKPOINT_LEN_7:
 466                 info->ctrl.len = ARM_BREAKPOINT_LEN_7;
 467                 break;
 468         case HW_BREAKPOINT_LEN_8:
 469                 info->ctrl.len = ARM_BREAKPOINT_LEN_8;
 470                 break;
 471         default:
 472                 return -EINVAL;
 473         }
 474
 475         /*
 476          * On AArch64, we only permit breakpoints of length 4, whereas
 477          * AArch32 also requires breakpoints of length 2 for Thumb.
 478          * Watchpoints can be of length 1, 2, 4 or 8 bytes.
 479          */
 480         if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) {
 481                 if (is_compat_bp(bp)) {
 482                         if (info->ctrl.len != ARM_BREAKPOINT_LEN_2 &&
 483                             info->ctrl.len != ARM_BREAKPOINT_LEN_4)
 484                                 return -EINVAL;
 485                 } else if (info->ctrl.len != ARM_BREAKPOINT_LEN_4) {
 486                         /*
 487                          * FIXME: Some tools (I'm looking at you perf) assume
 488                          *        that breakpoints should be sizeof(long). This
 489                          *        is nonsense. For now, we fix up the parameter
 490                          *        but we should probably return -EINVAL instead.
 491                          */
 492                         info->ctrl.len = ARM_BREAKPOINT_LEN_4;
 493                 }
 494         }
 495
 496         /* Address */
 497         info->address = bp->attr.bp_addr;
 498
 499         /*
 500          * Privilege
 501          * Note that we disallow combined EL0/EL1 breakpoints because
 502          * that would complicate the stepping code.
 503          */
 504         if (arch_check_bp_in_kernelspace(info))
 505                 info->ctrl.privilege = AARCH64_BREAKPOINT_EL1;
 506         else
 507                 info->ctrl.privilege = AARCH64_BREAKPOINT_EL0;
 508
 509         /* Enabled? */
 510         info->ctrl.enabled = !bp->attr.disabled;
 511
 512         return 0;
 513 }
 514
 515 /*
 516  * Validate the arch-specific HW Breakpoint register settings.
 517  */
 518 int arch_validate_hwbkpt_settings(struct perf_event *bp)
 519 {
 520         struct arch_hw_breakpoint *info = counter_arch_bp(bp);
 521         int ret;
 522         u64 alignment_mask, offset;
 523
 524         /* Build the arch_hw_breakpoint. */
 525         ret = arch_build_bp_info(bp);
 526         if (ret)
 527                 return ret;
 528
 529         /*
 530          * Check address alignment.
 531          * We don't do any clever alignment correction for watchpoints
 532          * because using 64-bit unaligned addresses is deprecated for
 533          * AArch64.
 534          *
 535          * AArch32 tasks expect some simple alignment fixups, so emulate
 536          * that here.
 537          */
 538         if (is_compat_bp(bp)) {
 539                 if (info->ctrl.len == ARM_BREAKPOINT_LEN_8)
 540                         alignment_mask = 0x7;
 541                 else
 542                         alignment_mask = 0x3;
 543                 offset = info->address & alignment_mask;
 544                 switch (offset) {
 545                 case 0:
 546                         /* Aligned */
 547                         break;
 548                 case 1:
 549                         /* Allow single byte watchpoint. */
 550                         if (info->ctrl.len == ARM_BREAKPOINT_LEN_1)
 551                                 break;
 552                 case 2:
 553                         /* Allow halfword watchpoints and breakpoints. */
 554                         if (info->ctrl.len == ARM_BREAKPOINT_LEN_2)
 555                                 break;
 556                 default:
 557                         return -EINVAL;
 558                 }
 559         } else {
 560                 if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE)
 561                         alignment_mask = 0x3;
 562                 else
 563                         alignment_mask = 0x7;
 564                 offset = info->address & alignment_mask;
 565         }
 566
 567         info->address &= ~alignment_mask;
 568         info->ctrl.len <<= offset;
 569
 570         /*
 571          * Disallow per-task kernel breakpoints since these would
 572          * complicate the stepping code.
 573          */
 574         if (info->ctrl.privilege == AARCH64_BREAKPOINT_EL1 && bp->hw.target)
 575                 return -EINVAL;
 576
 577         return 0;
 578 }
 579
 580 /*
 581  * Enable/disable all of the breakpoints active at the specified
 582  * exception level at the register level.
 583  * This is used when single-stepping after a breakpoint exception.
 584  */
 585 static void toggle_bp_registers(int reg, enum dbg_active_el el, int enable)
 586 {
 587         int i, max_slots, privilege;
 588         u32 ctrl;
 589         struct perf_event **slots;
 590
 591         switch (reg) {
 592         case AARCH64_DBG_REG_BCR:
 593                 slots = this_cpu_ptr(bp_on_reg);
 594                 max_slots = core_num_brps;
 595                 break;
 596         case AARCH64_DBG_REG_WCR:
 597                 slots = this_cpu_ptr(wp_on_reg);
 598                 max_slots = core_num_wrps;
 599                 break;
 600         default:
 601                 return;
 602         }
 603
 604         for (i = 0; i < max_slots; ++i) {
 605                 if (!slots[i])
 606                         continue;
 607
 608                 privilege = counter_arch_bp(slots[i])->ctrl.privilege;
 609                 if (debug_exception_level(privilege) != el)
 610                         continue;
 611
 612                 ctrl = read_wb_reg(reg, i);
 613                 if (enable)
 614                         ctrl |= 0x1;
 615                 else
 616                         ctrl &= ~0x1;
 617                 write_wb_reg(reg, i, ctrl);
 618         }
 619 }
 620 NOKPROBE_SYMBOL(toggle_bp_registers);
 621
 622 /*
 623  * Debug exception handlers.
 624  */
 625 static int breakpoint_handler(unsigned long unused, unsigned int esr,
 626                               struct pt_regs *regs)
 627 {
 628         int i, step = 0, *kernel_step;
 629         u32 ctrl_reg;
 630         u64 addr, val;
 631         struct perf_event *bp, **slots;
 632         struct debug_info *debug_info;
 633         struct arch_hw_breakpoint_ctrl ctrl;
 634
 635         slots = this_cpu_ptr(bp_on_reg);
 636         addr = instruction_pointer(regs);
 637         debug_info = &current->thread.debug;
 638
 639         for (i = 0; i < core_num_brps; ++i) {
 640                 rcu_read_lock();
 641
 642                 bp = slots[i];
 643
 644                 if (bp == NULL)
 645                         goto unlock;
 646
 647                 /* Check if the breakpoint value matches. */
 648                 val = read_wb_reg(AARCH64_DBG_REG_BVR, i);
 649                 if (val != (addr & ~0x3))
 650                         goto unlock;
 651
 652                 /* Possible match, check the byte address select to confirm. */
 653                 ctrl_reg = read_wb_reg(AARCH64_DBG_REG_BCR, i);
 654                 decode_ctrl_reg(ctrl_reg, &ctrl);
 655                 if (!((1 << (addr & 0x3)) & ctrl.len))
 656                         goto unlock;
 657
 658                 counter_arch_bp(bp)->trigger = addr;
 659                 perf_bp_event(bp, regs);
 660
 661                 /* Do we need to handle the stepping? */
 662                 if (is_default_overflow_handler(bp))
 663                         step = 1;
 664 unlock:
 665                 rcu_read_unlock();
 666         }
 667
 668         if (!step)
 669                 return 0;
 670
 671         if (user_mode(regs)) {
 672                 debug_info->bps_disabled = 1;
 673                 toggle_bp_registers(AARCH64_DBG_REG_BCR, DBG_ACTIVE_EL0, 0);
 674
 675                 /* If we're already stepping a watchpoint, just return. */
 676                 if (debug_info->wps_disabled)
 677                         return 0;
 678
 679                 if (test_thread_flag(TIF_SINGLESTEP))
 680                         debug_info->suspended_step = 1;
 681                 else
 682                         user_enable_single_step(current);
 683         } else {
 684                 toggle_bp_registers(AARCH64_DBG_REG_BCR, DBG_ACTIVE_EL1, 0);
 685                 kernel_step = this_cpu_ptr(&stepping_kernel_bp);
 686
 687                 if (*kernel_step != ARM_KERNEL_STEP_NONE)
 688                         return 0;
 689
 690                 if (kernel_active_single_step()) {
 691                         *kernel_step = ARM_KERNEL_STEP_SUSPEND;
 692                 } else {
 693                         *kernel_step = ARM_KERNEL_STEP_ACTIVE;
 694                         kernel_enable_single_step(regs);
 695                 }
 696         }
 697
 698         return 0;
 699 }
 700 NOKPROBE_SYMBOL(breakpoint_handler);
 701
 702 /*
 703  * Arm64 hardware does not always report a watchpoint hit address that matches
 704  * one of the watchpoints set. It can also report an address "near" the
 705  * watchpoint if a single instruction access both watched and unwatched
 706  * addresses. There is no straight-forward way, short of disassembling the
 707  * offending instruction, to map that address back to the watchpoint. This
 708  * function computes the distance of the memory access from the watchpoint as a
 709  * heuristic for the likelyhood that a given access triggered the watchpoint.
 710  *
 711  * See Section D2.10.5 "Determining the memory location that caused a Watchpoint
 712  * exception" of ARMv8 Architecture Reference Manual for details.
 713  *
 714  * The function returns the distance of the address from the bytes watched by
 715  * the watchpoint. In case of an exact match, it returns 0.
 716  */
 717 static u64 get_distance_from_watchpoint(unsigned long addr, u64 val,
 718                                         struct arch_hw_breakpoint_ctrl *ctrl)
 719 {
 720         u64 wp_low, wp_high;
 721         u32 lens, lene;
 722
 723         addr = untagged_addr(addr);
 724
 725         lens = __ffs(ctrl->len);
 726         lene = __fls(ctrl->len);
 727
 728         wp_low = val + lens;
 729         wp_high = val + lene;
 730         if (addr < wp_low)
 731                 return wp_low - addr;
 732         else if (addr > wp_high)
 733                 return addr - wp_high;
 734         else
 735                 return 0;
 736 }
 737
 738 static int watchpoint_handler(unsigned long addr, unsigned int esr,
 739                               struct pt_regs *regs)
 740 {
 741         int i, step = 0, *kernel_step, access, closest_match = 0;
 742         u64 min_dist = -1, dist;
 743         u32 ctrl_reg;
 744         u64 val;
 745         struct perf_event *wp, **slots;
 746         struct debug_info *debug_info;
 747         struct arch_hw_breakpoint *info;
 748         struct arch_hw_breakpoint_ctrl ctrl;
 749
 750         slots = this_cpu_ptr(wp_on_reg);
 751         debug_info = &current->thread.debug;
 752
 753         /*
 754          * Find all watchpoints that match the reported address. If no exact
 755          * match is found. Attribute the hit to the closest watchpoint.
 756          */
 757         rcu_read_lock();
 758         for (i = 0; i < core_num_wrps; ++i) {
 759                 wp = slots[i];
 760                 if (wp == NULL)
 761                         continue;
 762
 763                 /*
 764                  * Check that the access type matches.
 765                  * 0 => load, otherwise => store
 766                  */
 767                 access = (esr & AARCH64_ESR_ACCESS_MASK) ? HW_BREAKPOINT_W :
 768                          HW_BREAKPOINT_R;
 769                 if (!(access & hw_breakpoint_type(wp)))
 770                         continue;
 771
 772                 /* Check if the watchpoint value and byte select match. */
 773                 val = read_wb_reg(AARCH64_DBG_REG_WVR, i);
 774                 ctrl_reg = read_wb_reg(AARCH64_DBG_REG_WCR, i);
 775                 decode_ctrl_reg(ctrl_reg, &ctrl);
 776                 dist = get_distance_from_watchpoint(addr, val, &ctrl);
 777                 if (dist < min_dist) {
 778                         min_dist = dist;
 779                         closest_match = i;
 780                 }
 781                 /* Is this an exact match? */
 782                 if (dist != 0)
 783                         continue;
 784
 785                 info = counter_arch_bp(wp);
 786                 info->trigger = addr;
 787                 perf_bp_event(wp, regs);
 788
 789                 /* Do we need to handle the stepping? */
 790                 if (is_default_overflow_handler(wp))
 791                         step = 1;
 792         }
 793         if (min_dist > 0 && min_dist != -1) {
 794                 /* No exact match found. */
 795                 wp = slots[closest_match];
 796                 info = counter_arch_bp(wp);
 797                 info->trigger = addr;
 798                 perf_bp_event(wp, regs);
 799
 800                 /* Do we need to handle the stepping? */
 801                 if (is_default_overflow_handler(wp))
 802                         step = 1;
 803         }
 804         rcu_read_unlock();
 805
 806         if (!step)
 807                 return 0;
 808
 809         /*
 810          * We always disable EL0 watchpoints because the kernel can
 811          * cause these to fire via an unprivileged access.
 812          */
 813         toggle_bp_registers(AARCH64_DBG_REG_WCR, DBG_ACTIVE_EL0, 0);
 814
 815         if (user_mode(regs)) {
 816                 debug_info->wps_disabled = 1;
 817
 818                 /* If we're already stepping a breakpoint, just return. */
 819                 if (debug_info->bps_disabled)
 820                         return 0;
 821
 822                 if (test_thread_flag(TIF_SINGLESTEP))
 823                         debug_info->suspended_step = 1;
 824                 else
 825                         user_enable_single_step(current);
 826         } else {
 827                 toggle_bp_registers(AARCH64_DBG_REG_WCR, DBG_ACTIVE_EL1, 0);
 828                 kernel_step = this_cpu_ptr(&stepping_kernel_bp);
 829
 830                 if (*kernel_step != ARM_KERNEL_STEP_NONE)
 831                         return 0;
 832
 833                 if (kernel_active_single_step()) {
 834                         *kernel_step = ARM_KERNEL_STEP_SUSPEND;
 835                 } else {
 836                         *kernel_step = ARM_KERNEL_STEP_ACTIVE;
 837                         kernel_enable_single_step(regs);
 838                 }
 839         }
 840
 841         return 0;
 842 }
 843 NOKPROBE_SYMBOL(watchpoint_handler);
 844
 845 /*
 846  * Handle single-step exception.
 847  */
 848 int reinstall_suspended_bps(struct pt_regs *regs)
 849 {
 850         struct debug_info *debug_info = &current->thread.debug;
 851         int handled_exception = 0, *kernel_step;
 852
 853         kernel_step = this_cpu_ptr(&stepping_kernel_bp);
 854
 855         /*
 856          * Called from single-step exception handler.
 857          * Return 0 if execution can resume, 1 if a SIGTRAP should be
 858          * reported.
 859          */
 860         if (user_mode(regs)) {
 861                 if (debug_info->bps_disabled) {
 862                         debug_info->bps_disabled = 0;
 863                         toggle_bp_registers(AARCH64_DBG_REG_BCR, DBG_ACTIVE_EL0, 1);
 864                         handled_exception = 1;
 865                 }
 866
 867                 if (debug_info->wps_disabled) {
 868                         debug_info->wps_disabled = 0;
 869                         toggle_bp_registers(AARCH64_DBG_REG_WCR, DBG_ACTIVE_EL0, 1);
 870                         handled_exception = 1;
 871                 }
 872
 873                 if (handled_exception) {
 874                         if (debug_info->suspended_step) {
 875                                 debug_info->suspended_step = 0;
 876                                 /* Allow exception handling to fall-through. */
 877                                 handled_exception = 0;
 878                         } else {
 879                                 user_disable_single_step(current);
 880                         }
 881                 }
 882         } else if (*kernel_step != ARM_KERNEL_STEP_NONE) {
 883                 toggle_bp_registers(AARCH64_DBG_REG_BCR, DBG_ACTIVE_EL1, 1);
 884                 toggle_bp_registers(AARCH64_DBG_REG_WCR, DBG_ACTIVE_EL1, 1);
 885
 886                 if (!debug_info->wps_disabled)
 887                         toggle_bp_registers(AARCH64_DBG_REG_WCR, DBG_ACTIVE_EL0, 1);
 888
 889                 if (*kernel_step != ARM_KERNEL_STEP_SUSPEND) {
 890                         kernel_disable_single_step();
 891                         handled_exception = 1;
 892                 } else {
 893                         handled_exception = 0;
 894                 }
 895
 896                 *kernel_step = ARM_KERNEL_STEP_NONE;
 897         }
 898
 899         return !handled_exception;
 900 }
 901 NOKPROBE_SYMBOL(reinstall_suspended_bps);
 902
 903 /*
 904  * Context-switcher for restoring suspended breakpoints.
 905  */
 906 void hw_breakpoint_thread_switch(struct task_struct *next)
 907 {
 908         /*
 909          *           current        next
 910          * disabled: 0              0     => The usual case, NOTIFY_DONE
 911          *           0              1     => Disable the registers
 912          *           1              0     => Enable the registers
 913          *           1              1     => NOTIFY_DONE. per-task bps will
 914          *                                   get taken care of by perf.
 915          */
 916
 917         struct debug_info *current_debug_info, *next_debug_info;
 918
 919         current_debug_info = &current->thread.debug;
 920         next_debug_info = &next->thread.debug;
 921
 922         /* Update breakpoints. */
 923         if (current_debug_info->bps_disabled != next_debug_info->bps_disabled)
 924                 toggle_bp_registers(AARCH64_DBG_REG_BCR,
 925                                     DBG_ACTIVE_EL0,
 926                                     !next_debug_info->bps_disabled);
 927
 928         /* Update watchpoints. */
 929         if (current_debug_info->wps_disabled != next_debug_info->wps_disabled)
 930                 toggle_bp_registers(AARCH64_DBG_REG_WCR,
 931                                     DBG_ACTIVE_EL0,
 932                                     !next_debug_info->wps_disabled);
 933 }
 934
 935 /*
 936  * CPU initialisation.
 937  */
 938 static int hw_breakpoint_reset(unsigned int cpu)
 939 {
 940         int i;
 941         struct perf_event **slots;
 942         /*
 943          * When a CPU goes through cold-boot, it does not have any installed
 944          * slot, so it is safe to share the same function for restoring and
 945          * resetting breakpoints; when a CPU is hotplugged in, it goes
 946          * through the slots, which are all empty, hence it just resets control
 947          * and value for debug registers.
 948          * When this function is triggered on warm-boot through a CPU PM
 949          * notifier some slots might be initialized; if so they are
 950          * reprogrammed according to the debug slots content.
 951          */
 952         for (slots = this_cpu_ptr(bp_on_reg), i = 0; i < core_num_brps; ++i) {
 953                 if (slots[i]) {
 954                         hw_breakpoint_control(slots[i], HW_BREAKPOINT_RESTORE);
 955                 } else {
 956                         write_wb_reg(AARCH64_DBG_REG_BCR, i, 0UL);
 957                         write_wb_reg(AARCH64_DBG_REG_BVR, i, 0UL);
 958                 }
 959         }
 960
 961         for (slots = this_cpu_ptr(wp_on_reg), i = 0; i < core_num_wrps; ++i) {
 962                 if (slots[i]) {
 963                         hw_breakpoint_control(slots[i], HW_BREAKPOINT_RESTORE);
 964                 } else {
 965                         write_wb_reg(AARCH64_DBG_REG_WCR, i, 0UL);
 966                         write_wb_reg(AARCH64_DBG_REG_WVR, i, 0UL);
 967                 }
 968         }
 969
 970         return 0;
 971 }
 972
 973 #ifdef CONFIG_CPU_PM
 974 extern void cpu_suspend_set_dbg_restorer(int (*hw_bp_restore)(unsigned int));
 975 #else
 976 static inline void cpu_suspend_set_dbg_restorer(int (*hw_bp_restore)(unsigned int))
 977 {
 978 }
 979 #endif
 980
 981 /*
 982  * One-time initialisation.
 983  */
 984 static int __init arch_hw_breakpoint_init(void)
 985 {
 986         int ret;
 987
 988         core_num_brps = get_num_brps();
 989         core_num_wrps = get_num_wrps();
 990
 991         pr_info("found %d breakpoint and %d watchpoint registers.\n",
 992                 core_num_brps, core_num_wrps);
 993
 994         /* Register debug fault handlers. */
 995         hook_debug_fault_code(DBG_ESR_EVT_HWBP, breakpoint_handler, SIGTRAP,
 996                               TRAP_HWBKPT, "hw-breakpoint handler");
 997         hook_debug_fault_code(DBG_ESR_EVT_HWWP, watchpoint_handler, SIGTRAP,
 998                               TRAP_HWBKPT, "hw-watchpoint handler");
 999
1000         /*
1001          * Reset the breakpoint resources. We assume that a halting
1002          * debugger will leave the world in a nice state for us.
1003          */
1004         ret = cpuhp_setup_state(CPUHP_AP_PERF_ARM_HW_BREAKPOINT_STARTING,
1005                           "perf/arm64/hw_breakpoint:starting",
1006                           hw_breakpoint_reset, NULL);
1007         if (ret)
1008                 pr_err("failed to register CPU hotplug notifier: %d\n", ret);
1009
1010         /* Register cpu_suspend hw breakpoint restore hook */
1011         cpu_suspend_set_dbg_restorer(hw_breakpoint_reset);
1012
1013         return ret;
1014 }
1015 arch_initcall(arch_hw_breakpoint_init);
1016
1017 void hw_breakpoint_pmu_read(struct perf_event *bp)
1018 {
1019 }
1020
1021 /*
1022  * Dummy function to register with die_notifier.
1023  */
1024 int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
1025                                     unsigned long val, void *data)
1026 {
1027         return NOTIFY_DONE;
1028 }