arch/arm64/kernel/cpufeature.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Contains CPU feature definitions
   4  *
   5  * Copyright (C) 2015 ARM Ltd.
   6  */
   7
   8 #define pr_fmt(fmt) "CPU features: " fmt
   9
  10 #include <linux/bsearch.h>
  11 #include <linux/cpumask.h>
  12 #include <linux/crash_dump.h>
  13 #include <linux/sort.h>
  14 #include <linux/stop_machine.h>
  15 #include <linux/types.h>
  16 #include <linux/mm.h>
  17 #include <linux/cpu.h>
  18 #include <asm/cpu.h>
  19 #include <asm/cpufeature.h>
  20 #include <asm/cpu_ops.h>
  21 #include <asm/fpsimd.h>
  22 #include <asm/mmu_context.h>
  23 #include <asm/processor.h>
  24 #include <asm/sysreg.h>
  25 #include <asm/traps.h>
  26 #include <asm/virt.h>
  27
  28 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */
  29 static unsigned long elf_hwcap __read_mostly;
  30
  31 #ifdef CONFIG_COMPAT
  32 #define COMPAT_ELF_HWCAP_DEFAULT        \
  33                                 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
  34                                  COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
  35                                  COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
  36                                  COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
  37                                  COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\
  38                                  COMPAT_HWCAP_LPAE)
  39 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
  40 unsigned int compat_elf_hwcap2 __read_mostly;
  41 #endif
  42
  43 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
  44 EXPORT_SYMBOL(cpu_hwcaps);
  45 static struct arm64_cpu_capabilities const __ro_after_init *cpu_hwcaps_ptrs[ARM64_NCAPS];
  46
  47 /* Need also bit for ARM64_CB_PATCH */
  48 DECLARE_BITMAP(boot_capabilities, ARM64_NPATCHABLE);
  49
  50 /*
  51  * Flag to indicate if we have computed the system wide
  52  * capabilities based on the boot time active CPUs. This
  53  * will be used to determine if a new booting CPU should
  54  * go through the verification process to make sure that it
  55  * supports the system capabilities, without using a hotplug
  56  * notifier.
  57  */
  58 static bool sys_caps_initialised;
  59
  60 static inline void set_sys_caps_initialised(void)
  61 {
  62         sys_caps_initialised = true;
  63 }
  64
  65 static int dump_cpu_hwcaps(struct notifier_block *self, unsigned long v, void *p)
  66 {
  67         /* file-wide pr_fmt adds "CPU features: " prefix */
  68         pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps);
  69         return 0;
  70 }
  71
  72 static struct notifier_block cpu_hwcaps_notifier = {
  73         .notifier_call = dump_cpu_hwcaps
  74 };
  75
  76 static int __init register_cpu_hwcaps_dumper(void)
  77 {
  78         atomic_notifier_chain_register(&panic_notifier_list,
  79                                        &cpu_hwcaps_notifier);
  80         return 0;
  81 }
  82 __initcall(register_cpu_hwcaps_dumper);
  83
  84 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS);
  85 EXPORT_SYMBOL(cpu_hwcap_keys);
  86
  87 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
  88         {                                               \
  89                 .sign = SIGNED,                         \
  90                 .visible = VISIBLE,                     \
  91                 .strict = STRICT,                       \
  92                 .type = TYPE,                           \
  93                 .shift = SHIFT,                         \
  94                 .width = WIDTH,                         \
  95                 .safe_val = SAFE_VAL,                   \
  96         }
  97
  98 /* Define a feature with unsigned values */
  99 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
 100         __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
 101
 102 /* Define a feature with a signed value */
 103 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
 104         __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
 105
 106 #define ARM64_FTR_END                                   \
 107         {                                               \
 108                 .width = 0,                             \
 109         }
 110
 111 /* meta feature for alternatives */
 112 static bool __maybe_unused
 113 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused);
 114
 115 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap);
 116
 117 /*
 118  * NOTE: Any changes to the visibility of features should be kept in
 119  * sync with the documentation of the CPU feature register ABI.
 120  */
 121 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
 122         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0),
 123         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0),
 124         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0),
 125         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0),
 126         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0),
 127         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0),
 128         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
 129         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
 130         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
 131         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
 132         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
 133         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
 134         ARM64_FTR_END,
 135 };
 136
 137 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
 138         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0),
 139         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FRINTTS_SHIFT, 4, 0),
 140         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
 141                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPI_SHIFT, 4, 0),
 142         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
 143                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPA_SHIFT, 4, 0),
 144         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0),
 145         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0),
 146         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),
 147         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
 148                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_API_SHIFT, 4, 0),
 149         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
 150                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_APA_SHIFT, 4, 0),
 151         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0),
 152         ARM64_FTR_END,
 153 };
 154
 155 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
 156         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0),
 157         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
 158         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0),
 159         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 160                                    FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0),
 161         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0),
 162         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0),
 163         S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
 164         S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
 165         /* Linux doesn't care about the EL3 */
 166         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0),
 167         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0),
 168         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
 169         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
 170         ARM64_FTR_END,
 171 };
 172
 173 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {
 174         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI),
 175         ARM64_FTR_END,
 176 };
 177
 178 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = {
 179         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 180                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0),
 181         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 182                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0),
 183         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 184                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0),
 185         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 186                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0),
 187         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 188                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0),
 189         ARM64_FTR_END,
 190 };
 191
 192 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
 193         /*
 194          * We already refuse to boot CPUs that don't support our configured
 195          * page size, so we can only detect mismatches for a page size other
 196          * than the one we're currently using. Unfortunately, SoCs like this
 197          * exist in the wild so, even though we don't like it, we'll have to go
 198          * along with it and treat them as non-strict.
 199          */
 200         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
 201         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
 202         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
 203
 204         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
 205         /* Linux shouldn't care about secure memory */
 206         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
 207         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
 208         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
 209         /*
 210          * Differing PARange is fine as long as all peripherals and memory are mapped
 211          * within the minimum PARange of all CPUs
 212          */
 213         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
 214         ARM64_FTR_END,
 215 };
 216
 217 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
 218         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
 219         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
 220         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
 221         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
 222         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
 223         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
 224         ARM64_FTR_END,
 225 };
 226
 227 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
 228         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0),
 229         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0),
 230         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
 231         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
 232         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
 233         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
 234         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0),
 235         ARM64_FTR_END,
 236 };
 237
 238 static const struct arm64_ftr_bits ftr_ctr[] = {
 239         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */
 240         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1),
 241         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1),
 242         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_CWG_SHIFT, 4, 0),
 243         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_ERG_SHIFT, 4, 0),
 244         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1),
 245         /*
 246          * Linux can handle differing I-cache policies. Userspace JITs will
 247          * make use of *minLine.
 248          * If we have differing I-cache policies, report it as the weakest - VIPT.
 249          */
 250         ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_VIPT),       /* L1Ip */
 251         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0),
 252         ARM64_FTR_END,
 253 };
 254
 255 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
 256         .name           = "SYS_CTR_EL0",
 257         .ftr_bits       = ftr_ctr
 258 };
 259
 260 static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
 261         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0xf),   /* InnerShr */
 262         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),       /* FCSE */
 263         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0),    /* AuxReg */
 264         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),       /* TCM */
 265         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),       /* ShareLvl */
 266         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0xf),    /* OuterShr */
 267         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),        /* PMSA */
 268         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),        /* VMSA */
 269         ARM64_FTR_END,
 270 };
 271
 272 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
 273         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 36, 28, 0),
 274         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0),
 275         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
 276         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
 277         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
 278         /*
 279          * We can instantiate multiple PMU instances with different levels
 280          * of support.
 281          */
 282         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
 283         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
 284         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
 285         ARM64_FTR_END,
 286 };
 287
 288 static const struct arm64_ftr_bits ftr_mvfr2[] = {
 289         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),                /* FPMisc */
 290         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),                /* SIMDMisc */
 291         ARM64_FTR_END,
 292 };
 293
 294 static const struct arm64_ftr_bits ftr_dczid[] = {
 295         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 4, 1, 1),            /* DZP */
 296         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),       /* BS */
 297         ARM64_FTR_END,
 298 };
 299
 300
 301 static const struct arm64_ftr_bits ftr_id_isar5[] = {
 302         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0),
 303         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
 304         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
 305         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
 306         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
 307         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0),
 308         ARM64_FTR_END,
 309 };
 310
 311 static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
 312         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),        /* ac2 */
 313         ARM64_FTR_END,
 314 };
 315
 316 static const struct arm64_ftr_bits ftr_id_pfr0[] = {
 317         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),               /* State3 */
 318         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),                /* State2 */
 319         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),                /* State1 */
 320         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),                /* State0 */
 321         ARM64_FTR_END,
 322 };
 323
 324 static const struct arm64_ftr_bits ftr_id_dfr0[] = {
 325         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
 326         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf),   /* PerfMon */
 327         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
 328         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
 329         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
 330         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
 331         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
 332         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
 333         ARM64_FTR_END,
 334 };
 335
 336 static const struct arm64_ftr_bits ftr_zcr[] = {
 337         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
 338                 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0),        /* LEN */
 339         ARM64_FTR_END,
 340 };
 341
 342 /*
 343  * Common ftr bits for a 32bit register with all hidden, strict
 344  * attributes, with 4bit feature fields and a default safe value of
 345  * 0. Covers the following 32bit registers:
 346  * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
 347  */
 348 static const struct arm64_ftr_bits ftr_generic_32bits[] = {
 349         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
 350         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
 351         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
 352         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
 353         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
 354         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
 355         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
 356         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
 357         ARM64_FTR_END,
 358 };
 359
 360 /* Table for a single 32bit feature value */
 361 static const struct arm64_ftr_bits ftr_single32[] = {
 362         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0),
 363         ARM64_FTR_END,
 364 };
 365
 366 static const struct arm64_ftr_bits ftr_raz[] = {
 367         ARM64_FTR_END,
 368 };
 369
 370 #define ARM64_FTR_REG(id, table) {              \
 371         .sys_id = id,                           \
 372         .reg =  &(struct arm64_ftr_reg){        \
 373                 .name = #id,                    \
 374                 .ftr_bits = &((table)[0]),      \
 375         }}
 376
 377 static const struct __ftr_reg_entry {
 378         u32                     sys_id;
 379         struct arm64_ftr_reg    *reg;
 380 } arm64_ftr_regs[] = {
 381
 382         /* Op1 = 0, CRn = 0, CRm = 1 */
 383         ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
 384         ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),
 385         ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
 386         ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
 387         ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
 388         ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
 389         ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
 390
 391         /* Op1 = 0, CRn = 0, CRm = 2 */
 392         ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
 393         ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
 394         ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
 395         ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
 396         ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),
 397         ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
 398         ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
 399
 400         /* Op1 = 0, CRn = 0, CRm = 3 */
 401         ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
 402         ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
 403         ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
 404
 405         /* Op1 = 0, CRn = 0, CRm = 4 */
 406         ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
 407         ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1),
 408         ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0),
 409
 410         /* Op1 = 0, CRn = 0, CRm = 5 */
 411         ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
 412         ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
 413
 414         /* Op1 = 0, CRn = 0, CRm = 6 */
 415         ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
 416         ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1),
 417
 418         /* Op1 = 0, CRn = 0, CRm = 7 */
 419         ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
 420         ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
 421         ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
 422
 423         /* Op1 = 0, CRn = 1, CRm = 2 */
 424         ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr),
 425
 426         /* Op1 = 3, CRn = 0, CRm = 0 */
 427         { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
 428         ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
 429
 430         /* Op1 = 3, CRn = 14, CRm = 0 */
 431         ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32),
 432 };
 433
 434 static int search_cmp_ftr_reg(const void *id, const void *regp)
 435 {
 436         return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
 437 }
 438
 439 /*
 440  * get_arm64_ftr_reg - Lookup a feature register entry using its
 441  * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
 442  * ascending order of sys_id , we use binary search to find a matching
 443  * entry.
 444  *
 445  * returns - Upon success,  matching ftr_reg entry for id.
 446  *         - NULL on failure. It is upto the caller to decide
 447  *           the impact of a failure.
 448  */
 449 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
 450 {
 451         const struct __ftr_reg_entry *ret;
 452
 453         ret = bsearch((const void *)(unsigned long)sys_id,
 454                         arm64_ftr_regs,
 455                         ARRAY_SIZE(arm64_ftr_regs),
 456                         sizeof(arm64_ftr_regs[0]),
 457                         search_cmp_ftr_reg);
 458         if (ret)
 459                 return ret->reg;
 460         return NULL;
 461 }
 462
 463 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
 464                                s64 ftr_val)
 465 {
 466         u64 mask = arm64_ftr_mask(ftrp);
 467
 468         reg &= ~mask;
 469         reg |= (ftr_val << ftrp->shift) & mask;
 470         return reg;
 471 }
 472
 473 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
 474                                 s64 cur)
 475 {
 476         s64 ret = 0;
 477
 478         switch (ftrp->type) {
 479         case FTR_EXACT:
 480                 ret = ftrp->safe_val;
 481                 break;
 482         case FTR_LOWER_SAFE:
 483                 ret = new < cur ? new : cur;
 484                 break;
 485         case FTR_HIGHER_OR_ZERO_SAFE:
 486                 if (!cur || !new)
 487                         break;
 488                 /* Fallthrough */
 489         case FTR_HIGHER_SAFE:
 490                 ret = new > cur ? new : cur;
 491                 break;
 492         default:
 493                 BUG();
 494         }
 495
 496         return ret;
 497 }
 498
 499 static void __init sort_ftr_regs(void)
 500 {
 501         int i;
 502
 503         /* Check that the array is sorted so that we can do the binary search */
 504         for (i = 1; i < ARRAY_SIZE(arm64_ftr_regs); i++)
 505                 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id);
 506 }
 507
 508 /*
 509  * Initialise the CPU feature register from Boot CPU values.
 510  * Also initiliases the strict_mask for the register.
 511  * Any bits that are not covered by an arm64_ftr_bits entry are considered
 512  * RES0 for the system-wide value, and must strictly match.
 513  */
 514 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
 515 {
 516         u64 val = 0;
 517         u64 strict_mask = ~0x0ULL;
 518         u64 user_mask = 0;
 519         u64 valid_mask = 0;
 520
 521         const struct arm64_ftr_bits *ftrp;
 522         struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
 523
 524         BUG_ON(!reg);
 525
 526         for (ftrp  = reg->ftr_bits; ftrp->width; ftrp++) {
 527                 u64 ftr_mask = arm64_ftr_mask(ftrp);
 528                 s64 ftr_new = arm64_ftr_value(ftrp, new);
 529
 530                 val = arm64_ftr_set_value(ftrp, val, ftr_new);
 531
 532                 valid_mask |= ftr_mask;
 533                 if (!ftrp->strict)
 534                         strict_mask &= ~ftr_mask;
 535                 if (ftrp->visible)
 536                         user_mask |= ftr_mask;
 537                 else
 538                         reg->user_val = arm64_ftr_set_value(ftrp,
 539                                                             reg->user_val,
 540                                                             ftrp->safe_val);
 541         }
 542
 543         val &= valid_mask;
 544
 545         reg->sys_val = val;
 546         reg->strict_mask = strict_mask;
 547         reg->user_mask = user_mask;
 548 }
 549
 550 extern const struct arm64_cpu_capabilities arm64_errata[];
 551 static const struct arm64_cpu_capabilities arm64_features[];
 552
 553 static void __init
 554 init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities *caps)
 555 {
 556         for (; caps->matches; caps++) {
 557                 if (WARN(caps->capability >= ARM64_NCAPS,
 558                         "Invalid capability %d\n", caps->capability))
 559                         continue;
 560                 if (WARN(cpu_hwcaps_ptrs[caps->capability],
 561                         "Duplicate entry for capability %d\n",
 562                         caps->capability))
 563                         continue;
 564                 cpu_hwcaps_ptrs[caps->capability] = caps;
 565         }
 566 }
 567
 568 static void __init init_cpu_hwcaps_indirect_list(void)
 569 {
 570         init_cpu_hwcaps_indirect_list_from_array(arm64_features);
 571         init_cpu_hwcaps_indirect_list_from_array(arm64_errata);
 572 }
 573
 574 static void __init setup_boot_cpu_capabilities(void);
 575
 576 void __init init_cpu_features(struct cpuinfo_arm64 *info)
 577 {
 578         /* Before we start using the tables, make sure it is sorted */
 579         sort_ftr_regs();
 580
 581         init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
 582         init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
 583         init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
 584         init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
 585         init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
 586         init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
 587         init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
 588         init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
 589         init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
 590         init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
 591         init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
 592         init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
 593         init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0);
 594
 595         if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
 596                 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
 597                 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
 598                 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
 599                 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
 600                 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
 601                 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
 602                 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
 603                 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
 604                 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
 605                 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
 606                 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
 607                 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
 608                 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
 609                 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
 610                 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
 611                 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
 612         }
 613
 614         if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
 615                 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr);
 616                 sve_init_vq_map();
 617         }
 618
 619         /*
 620          * Initialize the indirect array of CPU hwcaps capabilities pointers
 621          * before we handle the boot CPU below.
 622          */
 623         init_cpu_hwcaps_indirect_list();
 624
 625         /*
 626          * Detect and enable early CPU capabilities based on the boot CPU,
 627          * after we have initialised the CPU feature infrastructure.
 628          */
 629         setup_boot_cpu_capabilities();
 630 }
 631
 632 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
 633 {
 634         const struct arm64_ftr_bits *ftrp;
 635
 636         for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
 637                 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
 638                 s64 ftr_new = arm64_ftr_value(ftrp, new);
 639
 640                 if (ftr_cur == ftr_new)
 641                         continue;
 642                 /* Find a safe value */
 643                 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
 644                 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
 645         }
 646
 647 }
 648
 649 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
 650 {
 651         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
 652
 653         BUG_ON(!regp);
 654         update_cpu_ftr_reg(regp, val);
 655         if ((boot & regp->strict_mask) == (val & regp->strict_mask))
 656                 return 0;
 657         pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
 658                         regp->name, boot, cpu, val);
 659         return 1;
 660 }
 661
 662 /*
 663  * Update system wide CPU feature registers with the values from a
 664  * non-boot CPU. Also performs SANITY checks to make sure that there
 665  * aren't any insane variations from that of the boot CPU.
 666  */
 667 void update_cpu_features(int cpu,
 668                          struct cpuinfo_arm64 *info,
 669                          struct cpuinfo_arm64 *boot)
 670 {
 671         int taint = 0;
 672
 673         /*
 674          * The kernel can handle differing I-cache policies, but otherwise
 675          * caches should look identical. Userspace JITs will make use of
 676          * *minLine.
 677          */
 678         taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
 679                                       info->reg_ctr, boot->reg_ctr);
 680
 681         /*
 682          * Userspace may perform DC ZVA instructions. Mismatched block sizes
 683          * could result in too much or too little memory being zeroed if a
 684          * process is preempted and migrated between CPUs.
 685          */
 686         taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
 687                                       info->reg_dczid, boot->reg_dczid);
 688
 689         /* If different, timekeeping will be broken (especially with KVM) */
 690         taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
 691                                       info->reg_cntfrq, boot->reg_cntfrq);
 692
 693         /*
 694          * The kernel uses self-hosted debug features and expects CPUs to
 695          * support identical debug features. We presently need CTX_CMPs, WRPs,
 696          * and BRPs to be identical.
 697          * ID_AA64DFR1 is currently RES0.
 698          */
 699         taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
 700                                       info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
 701         taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
 702                                       info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
 703         /*
 704          * Even in big.LITTLE, processors should be identical instruction-set
 705          * wise.
 706          */
 707         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
 708                                       info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
 709         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
 710                                       info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
 711
 712         /*
 713          * Differing PARange support is fine as long as all peripherals and
 714          * memory are mapped within the minimum PARange of all CPUs.
 715          * Linux should not care about secure memory.
 716          */
 717         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
 718                                       info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
 719         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
 720                                       info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
 721         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
 722                                       info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
 723
 724         /*
 725          * EL3 is not our concern.
 726          */
 727         taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
 728                                       info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
 729         taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
 730                                       info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
 731
 732         taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu,
 733                                       info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0);
 734
 735         /*
 736          * If we have AArch32, we care about 32-bit features for compat.
 737          * If the system doesn't support AArch32, don't update them.
 738          */
 739         if (id_aa64pfr0_32bit_el0(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
 740                 id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
 741
 742                 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
 743                                         info->reg_id_dfr0, boot->reg_id_dfr0);
 744                 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
 745                                         info->reg_id_isar0, boot->reg_id_isar0);
 746                 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
 747                                         info->reg_id_isar1, boot->reg_id_isar1);
 748                 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
 749                                         info->reg_id_isar2, boot->reg_id_isar2);
 750                 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
 751                                         info->reg_id_isar3, boot->reg_id_isar3);
 752                 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
 753                                         info->reg_id_isar4, boot->reg_id_isar4);
 754                 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
 755                                         info->reg_id_isar5, boot->reg_id_isar5);
 756
 757                 /*
 758                  * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
 759                  * ACTLR formats could differ across CPUs and therefore would have to
 760                  * be trapped for virtualization anyway.
 761                  */
 762                 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
 763                                         info->reg_id_mmfr0, boot->reg_id_mmfr0);
 764                 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
 765                                         info->reg_id_mmfr1, boot->reg_id_mmfr1);
 766                 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
 767                                         info->reg_id_mmfr2, boot->reg_id_mmfr2);
 768                 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
 769                                         info->reg_id_mmfr3, boot->reg_id_mmfr3);
 770                 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
 771                                         info->reg_id_pfr0, boot->reg_id_pfr0);
 772                 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
 773                                         info->reg_id_pfr1, boot->reg_id_pfr1);
 774                 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
 775                                         info->reg_mvfr0, boot->reg_mvfr0);
 776                 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
 777                                         info->reg_mvfr1, boot->reg_mvfr1);
 778                 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
 779                                         info->reg_mvfr2, boot->reg_mvfr2);
 780         }
 781
 782         if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
 783                 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu,
 784                                         info->reg_zcr, boot->reg_zcr);
 785
 786                 /* Probe vector lengths, unless we already gave up on SVE */
 787                 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
 788                     !sys_caps_initialised)
 789                         sve_update_vq_map();
 790         }
 791
 792         /*
 793          * Mismatched CPU features are a recipe for disaster. Don't even
 794          * pretend to support them.
 795          */
 796         if (taint) {
 797                 pr_warn_once("Unsupported CPU feature variation detected.\n");
 798                 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
 799         }
 800 }
 801
 802 u64 read_sanitised_ftr_reg(u32 id)
 803 {
 804         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
 805
 806         /* We shouldn't get a request for an unsupported register */
 807         BUG_ON(!regp);
 808         return regp->sys_val;
 809 }
 810
 811 #define read_sysreg_case(r)     \
 812         case r:         return read_sysreg_s(r)
 813
 814 /*
 815  * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
 816  * Read the system register on the current CPU
 817  */
 818 static u64 __read_sysreg_by_encoding(u32 sys_id)
 819 {
 820         switch (sys_id) {
 821         read_sysreg_case(SYS_ID_PFR0_EL1);
 822         read_sysreg_case(SYS_ID_PFR1_EL1);
 823         read_sysreg_case(SYS_ID_DFR0_EL1);
 824         read_sysreg_case(SYS_ID_MMFR0_EL1);
 825         read_sysreg_case(SYS_ID_MMFR1_EL1);
 826         read_sysreg_case(SYS_ID_MMFR2_EL1);
 827         read_sysreg_case(SYS_ID_MMFR3_EL1);
 828         read_sysreg_case(SYS_ID_ISAR0_EL1);
 829         read_sysreg_case(SYS_ID_ISAR1_EL1);
 830         read_sysreg_case(SYS_ID_ISAR2_EL1);
 831         read_sysreg_case(SYS_ID_ISAR3_EL1);
 832         read_sysreg_case(SYS_ID_ISAR4_EL1);
 833         read_sysreg_case(SYS_ID_ISAR5_EL1);
 834         read_sysreg_case(SYS_MVFR0_EL1);
 835         read_sysreg_case(SYS_MVFR1_EL1);
 836         read_sysreg_case(SYS_MVFR2_EL1);
 837
 838         read_sysreg_case(SYS_ID_AA64PFR0_EL1);
 839         read_sysreg_case(SYS_ID_AA64PFR1_EL1);
 840         read_sysreg_case(SYS_ID_AA64ZFR0_EL1);
 841         read_sysreg_case(SYS_ID_AA64DFR0_EL1);
 842         read_sysreg_case(SYS_ID_AA64DFR1_EL1);
 843         read_sysreg_case(SYS_ID_AA64MMFR0_EL1);
 844         read_sysreg_case(SYS_ID_AA64MMFR1_EL1);
 845         read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
 846         read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
 847         read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
 848
 849         read_sysreg_case(SYS_CNTFRQ_EL0);
 850         read_sysreg_case(SYS_CTR_EL0);
 851         read_sysreg_case(SYS_DCZID_EL0);
 852
 853         default:
 854                 BUG();
 855                 return 0;
 856         }
 857 }
 858
 859 #include <linux/irqchip/arm-gic-v3.h>
 860
 861 static bool
 862 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
 863 {
 864         int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);
 865
 866         return val >= entry->min_field_value;
 867 }
 868
 869 static bool
 870 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
 871 {
 872         u64 val;
 873
 874         WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
 875         if (scope == SCOPE_SYSTEM)
 876                 val = read_sanitised_ftr_reg(entry->sys_reg);
 877         else
 878                 val = __read_sysreg_by_encoding(entry->sys_reg);
 879
 880         return feature_matches(val, entry);
 881 }
 882
 883 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
 884 {
 885         bool has_sre;
 886
 887         if (!has_cpuid_feature(entry, scope))
 888                 return false;
 889
 890         has_sre = gic_enable_sre();
 891         if (!has_sre)
 892                 pr_warn_once("%s present but disabled by higher exception level\n",
 893                              entry->desc);
 894
 895         return has_sre;
 896 }
 897
 898 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
 899 {
 900         u32 midr = read_cpuid_id();
 901
 902         /* Cavium ThunderX pass 1.x and 2.x */
 903         return midr_is_cpu_model_range(midr, MIDR_THUNDERX,
 904                 MIDR_CPU_VAR_REV(0, 0),
 905                 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK));
 906 }
 907
 908 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused)
 909 {
 910         u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
 911
 912         return cpuid_feature_extract_signed_field(pfr0,
 913                                         ID_AA64PFR0_FP_SHIFT) < 0;
 914 }
 915
 916 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry,
 917                           int scope)
 918 {
 919         u64 ctr;
 920
 921         if (scope == SCOPE_SYSTEM)
 922                 ctr = arm64_ftr_reg_ctrel0.sys_val;
 923         else
 924                 ctr = read_cpuid_effective_cachetype();
 925
 926         return ctr & BIT(CTR_IDC_SHIFT);
 927 }
 928
 929 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused)
 930 {
 931         /*
 932          * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively
 933          * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses
 934          * to the CTR_EL0 on this CPU and emulate it with the real/safe
 935          * value.
 936          */
 937         if (!(read_cpuid_cachetype() & BIT(CTR_IDC_SHIFT)))
 938                 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
 939 }
 940
 941 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry,
 942                           int scope)
 943 {
 944         u64 ctr;
 945
 946         if (scope == SCOPE_SYSTEM)
 947                 ctr = arm64_ftr_reg_ctrel0.sys_val;
 948         else
 949                 ctr = read_cpuid_cachetype();
 950
 951         return ctr & BIT(CTR_DIC_SHIFT);
 952 }
 953
 954 static bool __maybe_unused
 955 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope)
 956 {
 957         /*
 958          * Kdump isn't guaranteed to power-off all secondary CPUs, CNP
 959          * may share TLB entries with a CPU stuck in the crashed
 960          * kernel.
 961          */
 962          if (is_kdump_kernel())
 963                 return false;
 964
 965         return has_cpuid_feature(entry, scope);
 966 }
 967
 968 static bool __meltdown_safe = true;
 969 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
 970
 971 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
 972                                 int scope)
 973 {
 974         /* List of CPUs that are not vulnerable and don't need KPTI */
 975         static const struct midr_range kpti_safe_list[] = {
 976                 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
 977                 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
 978                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
 979                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
 980                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
 981                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
 982                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
 983                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
 984                 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110),
 985                 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL),
 986                 { /* sentinel */ }
 987         };
 988         char const *str = "kpti command line option";
 989         bool meltdown_safe;
 990
 991         meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list);
 992
 993         /* Defer to CPU feature registers */
 994         if (has_cpuid_feature(entry, scope))
 995                 meltdown_safe = true;
 996
 997         if (!meltdown_safe)
 998                 __meltdown_safe = false;
 999
1000         /*
1001          * For reasons that aren't entirely clear, enabling KPTI on Cavium
1002          * ThunderX leads to apparent I-cache corruption of kernel text, which
1003          * ends as well as you might imagine. Don't even try.
1004          */
1005         if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_27456)) {
1006                 str = "ARM64_WORKAROUND_CAVIUM_27456";
1007                 __kpti_forced = -1;
1008         }
1009
1010         /* Useful for KASLR robustness */
1011         if (IS_ENABLED(CONFIG_RANDOMIZE_BASE) && kaslr_offset() > 0) {
1012                 if (!__kpti_forced) {
1013                         str = "KASLR";
1014                         __kpti_forced = 1;
1015                 }
1016         }
1017
1018         if (cpu_mitigations_off() && !__kpti_forced) {
1019                 str = "mitigations=off";
1020                 __kpti_forced = -1;
1021         }
1022
1023         if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) {
1024                 pr_info_once("kernel page table isolation disabled by kernel configuration\n");
1025                 return false;
1026         }
1027
1028         /* Forced? */
1029         if (__kpti_forced) {
1030                 pr_info_once("kernel page table isolation forced %s by %s\n",
1031                              __kpti_forced > 0 ? "ON" : "OFF", str);
1032                 return __kpti_forced > 0;
1033         }
1034
1035         return !meltdown_safe;
1036 }
1037
1038 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1039 static void
1040 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1041 {
1042         typedef void (kpti_remap_fn)(int, int, phys_addr_t);
1043         extern kpti_remap_fn idmap_kpti_install_ng_mappings;
1044         kpti_remap_fn *remap_fn;
1045
1046         static bool kpti_applied = false;
1047         int cpu = smp_processor_id();
1048
1049         /*
1050          * We don't need to rewrite the page-tables if either we've done
1051          * it already or we have KASLR enabled and therefore have not
1052          * created any global mappings at all.
1053          */
1054         if (kpti_applied || kaslr_offset() > 0)
1055                 return;
1056
1057         remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings);
1058
1059         cpu_install_idmap();
1060         remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir));
1061         cpu_uninstall_idmap();
1062
1063         if (!cpu)
1064                 kpti_applied = true;
1065
1066         return;
1067 }
1068 #else
1069 static void
1070 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1071 {
1072 }
1073 #endif  /* CONFIG_UNMAP_KERNEL_AT_EL0 */
1074
1075 static int __init parse_kpti(char *str)
1076 {
1077         bool enabled;
1078         int ret = strtobool(str, &enabled);
1079
1080         if (ret)
1081                 return ret;
1082
1083         __kpti_forced = enabled ? 1 : -1;
1084         return 0;
1085 }
1086 early_param("kpti", parse_kpti);
1087
1088 #ifdef CONFIG_ARM64_HW_AFDBM
1089 static inline void __cpu_enable_hw_dbm(void)
1090 {
1091         u64 tcr = read_sysreg(tcr_el1) | TCR_HD;
1092
1093         write_sysreg(tcr, tcr_el1);
1094         isb();
1095 }
1096
1097 static bool cpu_has_broken_dbm(void)
1098 {
1099         /* List of CPUs which have broken DBM support. */
1100         static const struct midr_range cpus[] = {
1101 #ifdef CONFIG_ARM64_ERRATUM_1024718
1102                 MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0),  // A55 r0p0 -r1p0
1103 #endif
1104                 {},
1105         };
1106
1107         return is_midr_in_range_list(read_cpuid_id(), cpus);
1108 }
1109
1110 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap)
1111 {
1112         return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) &&
1113                !cpu_has_broken_dbm();
1114 }
1115
1116 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap)
1117 {
1118         if (cpu_can_use_dbm(cap))
1119                 __cpu_enable_hw_dbm();
1120 }
1121
1122 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap,
1123                        int __unused)
1124 {
1125         static bool detected = false;
1126         /*
1127          * DBM is a non-conflicting feature. i.e, the kernel can safely
1128          * run a mix of CPUs with and without the feature. So, we
1129          * unconditionally enable the capability to allow any late CPU
1130          * to use the feature. We only enable the control bits on the
1131          * CPU, if it actually supports.
1132          *
1133          * We have to make sure we print the "feature" detection only
1134          * when at least one CPU actually uses it. So check if this CPU
1135          * can actually use it and print the message exactly once.
1136          *
1137          * This is safe as all CPUs (including secondary CPUs - due to the
1138          * LOCAL_CPU scope - and the hotplugged CPUs - via verification)
1139          * goes through the "matches" check exactly once. Also if a CPU
1140          * matches the criteria, it is guaranteed that the CPU will turn
1141          * the DBM on, as the capability is unconditionally enabled.
1142          */
1143         if (!detected && cpu_can_use_dbm(cap)) {
1144                 detected = true;
1145                 pr_info("detected: Hardware dirty bit management\n");
1146         }
1147
1148         return true;
1149 }
1150
1151 #endif
1152
1153 #ifdef CONFIG_ARM64_VHE
1154 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
1155 {
1156         return is_kernel_in_hyp_mode();
1157 }
1158
1159 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused)
1160 {
1161         /*
1162          * Copy register values that aren't redirected by hardware.
1163          *
1164          * Before code patching, we only set tpidr_el1, all CPUs need to copy
1165          * this value to tpidr_el2 before we patch the code. Once we've done
1166          * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to
1167          * do anything here.
1168          */
1169         if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN))
1170                 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2);
1171 }
1172 #endif
1173
1174 static void cpu_has_fwb(const struct arm64_cpu_capabilities *__unused)
1175 {
1176         u64 val = read_sysreg_s(SYS_CLIDR_EL1);
1177
1178         /* Check that CLIDR_EL1.LOU{U,IS} are both 0 */
1179         WARN_ON(val & (7 << 27 | 7 << 21));
1180 }
1181
1182 #ifdef CONFIG_ARM64_SSBD
1183 static int ssbs_emulation_handler(struct pt_regs *regs, u32 instr)
1184 {
1185         if (user_mode(regs))
1186                 return 1;
1187
1188         if (instr & BIT(PSTATE_Imm_shift))
1189                 regs->pstate |= PSR_SSBS_BIT;
1190         else
1191                 regs->pstate &= ~PSR_SSBS_BIT;
1192
1193         arm64_skip_faulting_instruction(regs, 4);
1194         return 0;
1195 }
1196
1197 static struct undef_hook ssbs_emulation_hook = {
1198         .instr_mask     = ~(1U << PSTATE_Imm_shift),
1199         .instr_val      = 0xd500401f | PSTATE_SSBS,
1200         .fn             = ssbs_emulation_handler,
1201 };
1202
1203 static void cpu_enable_ssbs(const struct arm64_cpu_capabilities *__unused)
1204 {
1205         static bool undef_hook_registered = false;
1206         static DEFINE_RAW_SPINLOCK(hook_lock);
1207
1208         raw_spin_lock(&hook_lock);
1209         if (!undef_hook_registered) {
1210                 register_undef_hook(&ssbs_emulation_hook);
1211                 undef_hook_registered = true;
1212         }
1213         raw_spin_unlock(&hook_lock);
1214
1215         if (arm64_get_ssbd_state() == ARM64_SSBD_FORCE_DISABLE) {
1216                 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_DSSBS);
1217                 arm64_set_ssbd_mitigation(false);
1218         } else {
1219                 arm64_set_ssbd_mitigation(true);
1220         }
1221 }
1222 #endif /* CONFIG_ARM64_SSBD */
1223
1224 #ifdef CONFIG_ARM64_PAN
1225 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused)
1226 {
1227         /*
1228          * We modify PSTATE. This won't work from irq context as the PSTATE
1229          * is discarded once we return from the exception.
1230          */
1231         WARN_ON_ONCE(in_interrupt());
1232
1233         sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0);
1234         asm(SET_PSTATE_PAN(1));
1235 }
1236 #endif /* CONFIG_ARM64_PAN */
1237
1238 #ifdef CONFIG_ARM64_RAS_EXTN
1239 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused)
1240 {
1241         /* Firmware may have left a deferred SError in this register. */
1242         write_sysreg_s(0, SYS_DISR_EL1);
1243 }
1244 #endif /* CONFIG_ARM64_RAS_EXTN */
1245
1246 #ifdef CONFIG_ARM64_PTR_AUTH
1247 static void cpu_enable_address_auth(struct arm64_cpu_capabilities const *cap)
1248 {
1249         sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ENIA | SCTLR_ELx_ENIB |
1250                                        SCTLR_ELx_ENDA | SCTLR_ELx_ENDB);
1251 }
1252 #endif /* CONFIG_ARM64_PTR_AUTH */
1253
1254 #ifdef CONFIG_ARM64_PSEUDO_NMI
1255 static bool enable_pseudo_nmi;
1256
1257 static int __init early_enable_pseudo_nmi(char *p)
1258 {
1259         return strtobool(p, &enable_pseudo_nmi);
1260 }
1261 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi);
1262
1263 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry,
1264                                    int scope)
1265 {
1266         return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope);
1267 }
1268 #endif
1269
1270 static const struct arm64_cpu_capabilities arm64_features[] = {
1271         {
1272                 .desc = "GIC system register CPU interface",
1273                 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
1274                 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1275                 .matches = has_useable_gicv3_cpuif,
1276                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1277                 .field_pos = ID_AA64PFR0_GIC_SHIFT,
1278                 .sign = FTR_UNSIGNED,
1279                 .min_field_value = 1,
1280         },
1281 #ifdef CONFIG_ARM64_PAN
1282         {
1283                 .desc = "Privileged Access Never",
1284                 .capability = ARM64_HAS_PAN,
1285                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1286                 .matches = has_cpuid_feature,
1287                 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1288                 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
1289                 .sign = FTR_UNSIGNED,
1290                 .min_field_value = 1,
1291                 .cpu_enable = cpu_enable_pan,
1292         },
1293 #endif /* CONFIG_ARM64_PAN */
1294 #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
1295         {
1296                 .desc = "LSE atomic instructions",
1297                 .capability = ARM64_HAS_LSE_ATOMICS,
1298                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1299                 .matches = has_cpuid_feature,
1300                 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1301                 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
1302                 .sign = FTR_UNSIGNED,
1303                 .min_field_value = 2,
1304         },
1305 #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
1306         {
1307                 .desc = "Software prefetching using PRFM",
1308                 .capability = ARM64_HAS_NO_HW_PREFETCH,
1309                 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1310                 .matches = has_no_hw_prefetch,
1311         },
1312 #ifdef CONFIG_ARM64_UAO
1313         {
1314                 .desc = "User Access Override",
1315                 .capability = ARM64_HAS_UAO,
1316                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1317                 .matches = has_cpuid_feature,
1318                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1319                 .field_pos = ID_AA64MMFR2_UAO_SHIFT,
1320                 .min_field_value = 1,
1321                 /*
1322                  * We rely on stop_machine() calling uao_thread_switch() to set
1323                  * UAO immediately after patching.
1324                  */
1325         },
1326 #endif /* CONFIG_ARM64_UAO */
1327 #ifdef CONFIG_ARM64_PAN
1328         {
1329                 .capability = ARM64_ALT_PAN_NOT_UAO,
1330                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1331                 .matches = cpufeature_pan_not_uao,
1332         },
1333 #endif /* CONFIG_ARM64_PAN */
1334 #ifdef CONFIG_ARM64_VHE
1335         {
1336                 .desc = "Virtualization Host Extensions",
1337                 .capability = ARM64_HAS_VIRT_HOST_EXTN,
1338                 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1339                 .matches = runs_at_el2,
1340                 .cpu_enable = cpu_copy_el2regs,
1341         },
1342 #endif  /* CONFIG_ARM64_VHE */
1343         {
1344                 .desc = "32-bit EL0 Support",
1345                 .capability = ARM64_HAS_32BIT_EL0,
1346                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1347                 .matches = has_cpuid_feature,
1348                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1349                 .sign = FTR_UNSIGNED,
1350                 .field_pos = ID_AA64PFR0_EL0_SHIFT,
1351                 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
1352         },
1353         {
1354                 .desc = "Kernel page table isolation (KPTI)",
1355                 .capability = ARM64_UNMAP_KERNEL_AT_EL0,
1356                 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
1357                 /*
1358                  * The ID feature fields below are used to indicate that
1359                  * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for
1360                  * more details.
1361                  */
1362                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1363                 .field_pos = ID_AA64PFR0_CSV3_SHIFT,
1364                 .min_field_value = 1,
1365                 .matches = unmap_kernel_at_el0,
1366                 .cpu_enable = kpti_install_ng_mappings,
1367         },
1368         {
1369                 /* FP/SIMD is not implemented */
1370                 .capability = ARM64_HAS_NO_FPSIMD,
1371                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1372                 .min_field_value = 0,
1373                 .matches = has_no_fpsimd,
1374         },
1375 #ifdef CONFIG_ARM64_PMEM
1376         {
1377                 .desc = "Data cache clean to Point of Persistence",
1378                 .capability = ARM64_HAS_DCPOP,
1379                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1380                 .matches = has_cpuid_feature,
1381                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1382                 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
1383                 .min_field_value = 1,
1384         },
1385         {
1386                 .desc = "Data cache clean to Point of Deep Persistence",
1387                 .capability = ARM64_HAS_DCPODP,
1388                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1389                 .matches = has_cpuid_feature,
1390                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1391                 .sign = FTR_UNSIGNED,
1392                 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
1393                 .min_field_value = 2,
1394         },
1395 #endif
1396 #ifdef CONFIG_ARM64_SVE
1397         {
1398                 .desc = "Scalable Vector Extension",
1399                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1400                 .capability = ARM64_SVE,
1401                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1402                 .sign = FTR_UNSIGNED,
1403                 .field_pos = ID_AA64PFR0_SVE_SHIFT,
1404                 .min_field_value = ID_AA64PFR0_SVE,
1405                 .matches = has_cpuid_feature,
1406                 .cpu_enable = sve_kernel_enable,
1407         },
1408 #endif /* CONFIG_ARM64_SVE */
1409 #ifdef CONFIG_ARM64_RAS_EXTN
1410         {
1411                 .desc = "RAS Extension Support",
1412                 .capability = ARM64_HAS_RAS_EXTN,
1413                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1414                 .matches = has_cpuid_feature,
1415                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1416                 .sign = FTR_UNSIGNED,
1417                 .field_pos = ID_AA64PFR0_RAS_SHIFT,
1418                 .min_field_value = ID_AA64PFR0_RAS_V1,
1419                 .cpu_enable = cpu_clear_disr,
1420         },
1421 #endif /* CONFIG_ARM64_RAS_EXTN */
1422         {
1423                 .desc = "Data cache clean to the PoU not required for I/D coherence",
1424                 .capability = ARM64_HAS_CACHE_IDC,
1425                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1426                 .matches = has_cache_idc,
1427                 .cpu_enable = cpu_emulate_effective_ctr,
1428         },
1429         {
1430                 .desc = "Instruction cache invalidation not required for I/D coherence",
1431                 .capability = ARM64_HAS_CACHE_DIC,
1432                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1433                 .matches = has_cache_dic,
1434         },
1435         {
1436                 .desc = "Stage-2 Force Write-Back",
1437                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1438                 .capability = ARM64_HAS_STAGE2_FWB,
1439                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1440                 .sign = FTR_UNSIGNED,
1441                 .field_pos = ID_AA64MMFR2_FWB_SHIFT,
1442                 .min_field_value = 1,
1443                 .matches = has_cpuid_feature,
1444                 .cpu_enable = cpu_has_fwb,
1445         },
1446 #ifdef CONFIG_ARM64_HW_AFDBM
1447         {
1448                 /*
1449                  * Since we turn this on always, we don't want the user to
1450                  * think that the feature is available when it may not be.
1451                  * So hide the description.
1452                  *
1453                  * .desc = "Hardware pagetable Dirty Bit Management",
1454                  *
1455                  */
1456                 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1457                 .capability = ARM64_HW_DBM,
1458                 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1459                 .sign = FTR_UNSIGNED,
1460                 .field_pos = ID_AA64MMFR1_HADBS_SHIFT,
1461                 .min_field_value = 2,
1462                 .matches = has_hw_dbm,
1463                 .cpu_enable = cpu_enable_hw_dbm,
1464         },
1465 #endif
1466         {
1467                 .desc = "CRC32 instructions",
1468                 .capability = ARM64_HAS_CRC32,
1469                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1470                 .matches = has_cpuid_feature,
1471                 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1472                 .field_pos = ID_AA64ISAR0_CRC32_SHIFT,
1473                 .min_field_value = 1,
1474         },
1475 #ifdef CONFIG_ARM64_SSBD
1476         {
1477                 .desc = "Speculative Store Bypassing Safe (SSBS)",
1478                 .capability = ARM64_SSBS,
1479                 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1480                 .matches = has_cpuid_feature,
1481                 .sys_reg = SYS_ID_AA64PFR1_EL1,
1482                 .field_pos = ID_AA64PFR1_SSBS_SHIFT,
1483                 .sign = FTR_UNSIGNED,
1484                 .min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY,
1485                 .cpu_enable = cpu_enable_ssbs,
1486         },
1487 #endif
1488 #ifdef CONFIG_ARM64_CNP
1489         {
1490                 .desc = "Common not Private translations",
1491                 .capability = ARM64_HAS_CNP,
1492                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1493                 .matches = has_useable_cnp,
1494                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1495                 .sign = FTR_UNSIGNED,
1496                 .field_pos = ID_AA64MMFR2_CNP_SHIFT,
1497                 .min_field_value = 1,
1498                 .cpu_enable = cpu_enable_cnp,
1499         },
1500 #endif
1501         {
1502                 .desc = "Speculation barrier (SB)",
1503                 .capability = ARM64_HAS_SB,
1504                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1505                 .matches = has_cpuid_feature,
1506                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1507                 .field_pos = ID_AA64ISAR1_SB_SHIFT,
1508                 .sign = FTR_UNSIGNED,
1509                 .min_field_value = 1,
1510         },
1511 #ifdef CONFIG_ARM64_PTR_AUTH
1512         {
1513                 .desc = "Address authentication (architected algorithm)",
1514                 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH,
1515                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1516                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1517                 .sign = FTR_UNSIGNED,
1518                 .field_pos = ID_AA64ISAR1_APA_SHIFT,
1519                 .min_field_value = ID_AA64ISAR1_APA_ARCHITECTED,
1520                 .matches = has_cpuid_feature,
1521                 .cpu_enable = cpu_enable_address_auth,
1522         },
1523         {
1524                 .desc = "Address authentication (IMP DEF algorithm)",
1525                 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF,
1526                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1527                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1528                 .sign = FTR_UNSIGNED,
1529                 .field_pos = ID_AA64ISAR1_API_SHIFT,
1530                 .min_field_value = ID_AA64ISAR1_API_IMP_DEF,
1531                 .matches = has_cpuid_feature,
1532                 .cpu_enable = cpu_enable_address_auth,
1533         },
1534         {
1535                 .desc = "Generic authentication (architected algorithm)",
1536                 .capability = ARM64_HAS_GENERIC_AUTH_ARCH,
1537                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1538                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1539                 .sign = FTR_UNSIGNED,
1540                 .field_pos = ID_AA64ISAR1_GPA_SHIFT,
1541                 .min_field_value = ID_AA64ISAR1_GPA_ARCHITECTED,
1542                 .matches = has_cpuid_feature,
1543         },
1544         {
1545                 .desc = "Generic authentication (IMP DEF algorithm)",
1546                 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF,
1547                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1548                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1549                 .sign = FTR_UNSIGNED,
1550                 .field_pos = ID_AA64ISAR1_GPI_SHIFT,
1551                 .min_field_value = ID_AA64ISAR1_GPI_IMP_DEF,
1552                 .matches = has_cpuid_feature,
1553         },
1554 #endif /* CONFIG_ARM64_PTR_AUTH */
1555 #ifdef CONFIG_ARM64_PSEUDO_NMI
1556         {
1557                 /*
1558                  * Depends on having GICv3
1559                  */
1560                 .desc = "IRQ priority masking",
1561                 .capability = ARM64_HAS_IRQ_PRIO_MASKING,
1562                 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1563                 .matches = can_use_gic_priorities,
1564                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1565                 .field_pos = ID_AA64PFR0_GIC_SHIFT,
1566                 .sign = FTR_UNSIGNED,
1567                 .min_field_value = 1,
1568         },
1569 #endif
1570         {},
1571 };
1572
1573 #define HWCAP_CPUID_MATCH(reg, field, s, min_value)                             \
1574                 .matches = has_cpuid_feature,                                   \
1575                 .sys_reg = reg,                                                 \
1576                 .field_pos = field,                                             \
1577                 .sign = s,                                                      \
1578                 .min_field_value = min_value,
1579
1580 #define __HWCAP_CAP(name, cap_type, cap)                                        \
1581                 .desc = name,                                                   \
1582                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,                            \
1583                 .hwcap_type = cap_type,                                         \
1584                 .hwcap = cap,                                                   \
1585
1586 #define HWCAP_CAP(reg, field, s, min_value, cap_type, cap)                      \
1587         {                                                                       \
1588                 __HWCAP_CAP(#cap, cap_type, cap)                                \
1589                 HWCAP_CPUID_MATCH(reg, field, s, min_value)                     \
1590         }
1591
1592 #define HWCAP_MULTI_CAP(list, cap_type, cap)                                    \
1593         {                                                                       \
1594                 __HWCAP_CAP(#cap, cap_type, cap)                                \
1595                 .matches = cpucap_multi_entry_cap_matches,                      \
1596                 .match_list = list,                                             \
1597         }
1598
1599 #ifdef CONFIG_ARM64_PTR_AUTH
1600 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = {
1601         {
1602                 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_APA_SHIFT,
1603                                   FTR_UNSIGNED, ID_AA64ISAR1_APA_ARCHITECTED)
1604         },
1605         {
1606                 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_API_SHIFT,
1607                                   FTR_UNSIGNED, ID_AA64ISAR1_API_IMP_DEF)
1608         },
1609         {},
1610 };
1611
1612 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = {
1613         {
1614                 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPA_SHIFT,
1615                                   FTR_UNSIGNED, ID_AA64ISAR1_GPA_ARCHITECTED)
1616         },
1617         {
1618                 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPI_SHIFT,
1619                                   FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP_DEF)
1620         },
1621         {},
1622 };
1623 #endif
1624
1625 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
1626         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_PMULL),
1627         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AES),
1628         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA1),
1629         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2),
1630         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512),
1631         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32),
1632         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS),
1633         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM),
1634         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3),
1635         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3),
1636         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM4),
1637         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP),
1638         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM),
1639         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM),
1640         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2),
1641         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP),
1642         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP),
1643         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD),
1644         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP),
1645         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT),
1646         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP),
1647         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP),
1648         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT),
1649         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA),
1650         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC),
1651         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC),
1652         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FRINTTS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FRINT),
1653         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_SB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB),
1654         HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT),
1655 #ifdef CONFIG_ARM64_SVE
1656         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE),
1657         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SVEVER_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SVEVER_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2),
1658         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES, CAP_HWCAP, KERNEL_HWCAP_SVEAES),
1659         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES_PMULL, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL),
1660         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BITPERM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BITPERM, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM),
1661         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SHA3_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SHA3, CAP_HWCAP, KERNEL_HWCAP_SVESHA3),
1662         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SM4_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SM4, CAP_HWCAP, KERNEL_HWCAP_SVESM4),
1663 #endif
1664         HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, KERNEL_HWCAP_SSBS),
1665 #ifdef CONFIG_ARM64_PTR_AUTH
1666         HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA),
1667         HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG),
1668 #endif
1669         {},
1670 };
1671
1672 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
1673 #ifdef CONFIG_COMPAT
1674         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
1675         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
1676         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
1677         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
1678         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
1679 #endif
1680         {},
1681 };
1682
1683 static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
1684 {
1685         switch (cap->hwcap_type) {
1686         case CAP_HWCAP:
1687                 cpu_set_feature(cap->hwcap);
1688                 break;
1689 #ifdef CONFIG_COMPAT
1690         case CAP_COMPAT_HWCAP:
1691                 compat_elf_hwcap |= (u32)cap->hwcap;
1692                 break;
1693         case CAP_COMPAT_HWCAP2:
1694                 compat_elf_hwcap2 |= (u32)cap->hwcap;
1695                 break;
1696 #endif
1697         default:
1698                 WARN_ON(1);
1699                 break;
1700         }
1701 }
1702
1703 /* Check if we have a particular HWCAP enabled */
1704 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
1705 {
1706         bool rc;
1707
1708         switch (cap->hwcap_type) {
1709         case CAP_HWCAP:
1710                 rc = cpu_have_feature(cap->hwcap);
1711                 break;
1712 #ifdef CONFIG_COMPAT
1713         case CAP_COMPAT_HWCAP:
1714                 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
1715                 break;
1716         case CAP_COMPAT_HWCAP2:
1717                 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
1718                 break;
1719 #endif
1720         default:
1721                 WARN_ON(1);
1722                 rc = false;
1723         }
1724
1725         return rc;
1726 }
1727
1728 static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
1729 {
1730         /* We support emulation of accesses to CPU ID feature registers */
1731         cpu_set_named_feature(CPUID);
1732         for (; hwcaps->matches; hwcaps++)
1733                 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps)))
1734                         cap_set_elf_hwcap(hwcaps);
1735 }
1736
1737 static void update_cpu_capabilities(u16 scope_mask)
1738 {
1739         int i;
1740         const struct arm64_cpu_capabilities *caps;
1741
1742         scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1743         for (i = 0; i < ARM64_NCAPS; i++) {
1744                 caps = cpu_hwcaps_ptrs[i];
1745                 if (!caps || !(caps->type & scope_mask) ||
1746                     cpus_have_cap(caps->capability) ||
1747                     !caps->matches(caps, cpucap_default_scope(caps)))
1748                         continue;
1749
1750                 if (caps->desc)
1751                         pr_info("detected: %s\n", caps->desc);
1752                 cpus_set_cap(caps->capability);
1753
1754                 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU))
1755                         set_bit(caps->capability, boot_capabilities);
1756         }
1757 }
1758
1759 /*
1760  * Enable all the available capabilities on this CPU. The capabilities
1761  * with BOOT_CPU scope are handled separately and hence skipped here.
1762  */
1763 static int cpu_enable_non_boot_scope_capabilities(void *__unused)
1764 {
1765         int i;
1766         u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU;
1767
1768         for_each_available_cap(i) {
1769                 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[i];
1770
1771                 if (WARN_ON(!cap))
1772                         continue;
1773
1774                 if (!(cap->type & non_boot_scope))
1775                         continue;
1776
1777                 if (cap->cpu_enable)
1778                         cap->cpu_enable(cap);
1779         }
1780         return 0;
1781 }
1782
1783 /*
1784  * Run through the enabled capabilities and enable() it on all active
1785  * CPUs
1786  */
1787 static void __init enable_cpu_capabilities(u16 scope_mask)
1788 {
1789         int i;
1790         const struct arm64_cpu_capabilities *caps;
1791         bool boot_scope;
1792
1793         scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1794         boot_scope = !!(scope_mask & SCOPE_BOOT_CPU);
1795
1796         for (i = 0; i < ARM64_NCAPS; i++) {
1797                 unsigned int num;
1798
1799                 caps = cpu_hwcaps_ptrs[i];
1800                 if (!caps || !(caps->type & scope_mask))
1801                         continue;
1802                 num = caps->capability;
1803                 if (!cpus_have_cap(num))
1804                         continue;
1805
1806                 /* Ensure cpus_have_const_cap(num) works */
1807                 static_branch_enable(&cpu_hwcap_keys[num]);
1808
1809                 if (boot_scope && caps->cpu_enable)
1810                         /*
1811                          * Capabilities with SCOPE_BOOT_CPU scope are finalised
1812                          * before any secondary CPU boots. Thus, each secondary
1813                          * will enable the capability as appropriate via
1814                          * check_local_cpu_capabilities(). The only exception is
1815                          * the boot CPU, for which the capability must be
1816                          * enabled here. This approach avoids costly
1817                          * stop_machine() calls for this case.
1818                          */
1819                         caps->cpu_enable(caps);
1820         }
1821
1822         /*
1823          * For all non-boot scope capabilities, use stop_machine()
1824          * as it schedules the work allowing us to modify PSTATE,
1825          * instead of on_each_cpu() which uses an IPI, giving us a
1826          * PSTATE that disappears when we return.
1827          */
1828         if (!boot_scope)
1829                 stop_machine(cpu_enable_non_boot_scope_capabilities,
1830                              NULL, cpu_online_mask);
1831 }
1832
1833 /*
1834  * Run through the list of capabilities to check for conflicts.
1835  * If the system has already detected a capability, take necessary
1836  * action on this CPU.
1837  *
1838  * Returns "false" on conflicts.
1839  */
1840 static bool verify_local_cpu_caps(u16 scope_mask)
1841 {
1842         int i;
1843         bool cpu_has_cap, system_has_cap;
1844         const struct arm64_cpu_capabilities *caps;
1845
1846         scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1847
1848         for (i = 0; i < ARM64_NCAPS; i++) {
1849                 caps = cpu_hwcaps_ptrs[i];
1850                 if (!caps || !(caps->type & scope_mask))
1851                         continue;
1852
1853                 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU);
1854                 system_has_cap = cpus_have_cap(caps->capability);
1855
1856                 if (system_has_cap) {
1857                         /*
1858                          * Check if the new CPU misses an advertised feature,
1859                          * which is not safe to miss.
1860                          */
1861                         if (!cpu_has_cap && !cpucap_late_cpu_optional(caps))
1862                                 break;
1863                         /*
1864                          * We have to issue cpu_enable() irrespective of
1865                          * whether the CPU has it or not, as it is enabeld
1866                          * system wide. It is upto the call back to take
1867                          * appropriate action on this CPU.
1868                          */
1869                         if (caps->cpu_enable)
1870                                 caps->cpu_enable(caps);
1871                 } else {
1872                         /*
1873                          * Check if the CPU has this capability if it isn't
1874                          * safe to have when the system doesn't.
1875                          */
1876                         if (cpu_has_cap && !cpucap_late_cpu_permitted(caps))
1877                                 break;
1878                 }
1879         }
1880
1881         if (i < ARM64_NCAPS) {
1882                 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n",
1883                         smp_processor_id(), caps->capability,
1884                         caps->desc, system_has_cap, cpu_has_cap);
1885                 return false;
1886         }
1887
1888         return true;
1889 }
1890
1891 /*
1892  * Check for CPU features that are used in early boot
1893  * based on the Boot CPU value.
1894  */
1895 static void check_early_cpu_features(void)
1896 {
1897         verify_cpu_asid_bits();
1898         /*
1899          * Early features are used by the kernel already. If there
1900          * is a conflict, we cannot proceed further.
1901          */
1902         if (!verify_local_cpu_caps(SCOPE_BOOT_CPU))
1903                 cpu_panic_kernel();
1904 }
1905
1906 static void
1907 verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
1908 {
1909
1910         for (; caps->matches; caps++)
1911                 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
1912                         pr_crit("CPU%d: missing HWCAP: %s\n",
1913                                         smp_processor_id(), caps->desc);
1914                         cpu_die_early();
1915                 }
1916 }
1917
1918 static void verify_sve_features(void)
1919 {
1920         u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1);
1921         u64 zcr = read_zcr_features();
1922
1923         unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK;
1924         unsigned int len = zcr & ZCR_ELx_LEN_MASK;
1925
1926         if (len < safe_len || sve_verify_vq_map()) {
1927                 pr_crit("CPU%d: SVE: vector length support mismatch\n",
1928                         smp_processor_id());
1929                 cpu_die_early();
1930         }
1931
1932         /* Add checks on other ZCR bits here if necessary */
1933 }
1934
1935
1936 /*
1937  * Run through the enabled system capabilities and enable() it on this CPU.
1938  * The capabilities were decided based on the available CPUs at the boot time.
1939  * Any new CPU should match the system wide status of the capability. If the
1940  * new CPU doesn't have a capability which the system now has enabled, we
1941  * cannot do anything to fix it up and could cause unexpected failures. So
1942  * we park the CPU.
1943  */
1944 static void verify_local_cpu_capabilities(void)
1945 {
1946         /*
1947          * The capabilities with SCOPE_BOOT_CPU are checked from
1948          * check_early_cpu_features(), as they need to be verified
1949          * on all secondary CPUs.
1950          */
1951         if (!verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU))
1952                 cpu_die_early();
1953
1954         verify_local_elf_hwcaps(arm64_elf_hwcaps);
1955
1956         if (system_supports_32bit_el0())
1957                 verify_local_elf_hwcaps(compat_elf_hwcaps);
1958
1959         if (system_supports_sve())
1960                 verify_sve_features();
1961 }
1962
1963 void check_local_cpu_capabilities(void)
1964 {
1965         /*
1966          * All secondary CPUs should conform to the early CPU features
1967          * in use by the kernel based on boot CPU.
1968          */
1969         check_early_cpu_features();
1970
1971         /*
1972          * If we haven't finalised the system capabilities, this CPU gets
1973          * a chance to update the errata work arounds and local features.
1974          * Otherwise, this CPU should verify that it has all the system
1975          * advertised capabilities.
1976          */
1977         if (!sys_caps_initialised)
1978                 update_cpu_capabilities(SCOPE_LOCAL_CPU);
1979         else
1980                 verify_local_cpu_capabilities();
1981 }
1982
1983 static void __init setup_boot_cpu_capabilities(void)
1984 {
1985         /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */
1986         update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU);
1987         /* Enable the SCOPE_BOOT_CPU capabilities alone right away */
1988         enable_cpu_capabilities(SCOPE_BOOT_CPU);
1989 }
1990
1991 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready);
1992 EXPORT_SYMBOL(arm64_const_caps_ready);
1993
1994 static void __init mark_const_caps_ready(void)
1995 {
1996         static_branch_enable(&arm64_const_caps_ready);
1997 }
1998
1999 bool this_cpu_has_cap(unsigned int n)
2000 {
2001         if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) {
2002                 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n];
2003
2004                 if (cap)
2005                         return cap->matches(cap, SCOPE_LOCAL_CPU);
2006         }
2007
2008         return false;
2009 }
2010
2011 void cpu_set_feature(unsigned int num)
2012 {
2013         WARN_ON(num >= MAX_CPU_FEATURES);
2014         elf_hwcap |= BIT(num);
2015 }
2016 EXPORT_SYMBOL_GPL(cpu_set_feature);
2017
2018 bool cpu_have_feature(unsigned int num)
2019 {
2020         WARN_ON(num >= MAX_CPU_FEATURES);
2021         return elf_hwcap & BIT(num);
2022 }
2023 EXPORT_SYMBOL_GPL(cpu_have_feature);
2024
2025 unsigned long cpu_get_elf_hwcap(void)
2026 {
2027         /*
2028          * We currently only populate the first 32 bits of AT_HWCAP. Please
2029          * note that for userspace compatibility we guarantee that bits 62
2030          * and 63 will always be returned as 0.
2031          */
2032         return lower_32_bits(elf_hwcap);
2033 }
2034
2035 unsigned long cpu_get_elf_hwcap2(void)
2036 {
2037         return upper_32_bits(elf_hwcap);
2038 }
2039
2040 static void __init setup_system_capabilities(void)
2041 {
2042         /*
2043          * We have finalised the system-wide safe feature
2044          * registers, finalise the capabilities that depend
2045          * on it. Also enable all the available capabilities,
2046          * that are not enabled already.
2047          */
2048         update_cpu_capabilities(SCOPE_SYSTEM);
2049         enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU);
2050 }
2051
2052 void __init setup_cpu_features(void)
2053 {
2054         u32 cwg;
2055
2056         setup_system_capabilities();
2057         mark_const_caps_ready();
2058         setup_elf_hwcaps(arm64_elf_hwcaps);
2059
2060         if (system_supports_32bit_el0())
2061                 setup_elf_hwcaps(compat_elf_hwcaps);
2062
2063         if (system_uses_ttbr0_pan())
2064                 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n");
2065
2066         sve_setup();
2067         minsigstksz_setup();
2068
2069         /* Advertise that we have computed the system capabilities */
2070         set_sys_caps_initialised();
2071
2072         /*
2073          * Check for sane CTR_EL0.CWG value.
2074          */
2075         cwg = cache_type_cwg();
2076         if (!cwg)
2077                 pr_warn("No Cache Writeback Granule information, assuming %d\n",
2078                         ARCH_DMA_MINALIGN);
2079 }
2080
2081 static bool __maybe_unused
2082 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused)
2083 {
2084         return (cpus_have_const_cap(ARM64_HAS_PAN) && !cpus_have_const_cap(ARM64_HAS_UAO));
2085 }
2086
2087 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap)
2088 {
2089         cpu_replace_ttbr1(lm_alias(swapper_pg_dir));
2090 }
2091
2092 /*
2093  * We emulate only the following system register space.
2094  * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7]
2095  * See Table C5-6 System instruction encodings for System register accesses,
2096  * ARMv8 ARM(ARM DDI 0487A.f) for more details.
2097  */
2098 static inline bool __attribute_const__ is_emulated(u32 id)
2099 {
2100         return (sys_reg_Op0(id) == 0x3 &&
2101                 sys_reg_CRn(id) == 0x0 &&
2102                 sys_reg_Op1(id) == 0x0 &&
2103                 (sys_reg_CRm(id) == 0 ||
2104                  ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7))));
2105 }
2106
2107 /*
2108  * With CRm == 0, reg should be one of :
2109  * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
2110  */
2111 static inline int emulate_id_reg(u32 id, u64 *valp)
2112 {
2113         switch (id) {
2114         case SYS_MIDR_EL1:
2115                 *valp = read_cpuid_id();
2116                 break;
2117         case SYS_MPIDR_EL1:
2118                 *valp = SYS_MPIDR_SAFE_VAL;
2119                 break;
2120         case SYS_REVIDR_EL1:
2121                 /* IMPLEMENTATION DEFINED values are emulated with 0 */
2122                 *valp = 0;
2123                 break;
2124         default:
2125                 return -EINVAL;
2126         }
2127
2128         return 0;
2129 }
2130
2131 static int emulate_sys_reg(u32 id, u64 *valp)
2132 {
2133         struct arm64_ftr_reg *regp;
2134
2135         if (!is_emulated(id))
2136                 return -EINVAL;
2137
2138         if (sys_reg_CRm(id) == 0)
2139                 return emulate_id_reg(id, valp);
2140
2141         regp = get_arm64_ftr_reg(id);
2142         if (regp)
2143                 *valp = arm64_ftr_reg_user_value(regp);
2144         else
2145                 /*
2146                  * The untracked registers are either IMPLEMENTATION DEFINED
2147                  * (e.g, ID_AFR0_EL1) or reserved RAZ.
2148                  */
2149                 *valp = 0;
2150         return 0;
2151 }
2152
2153 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt)
2154 {
2155         int rc;
2156         u64 val;
2157
2158         rc = emulate_sys_reg(sys_reg, &val);
2159         if (!rc) {
2160                 pt_regs_write_reg(regs, rt, val);
2161                 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
2162         }
2163         return rc;
2164 }
2165
2166 static int emulate_mrs(struct pt_regs *regs, u32 insn)
2167 {
2168         u32 sys_reg, rt;
2169
2170         /*
2171          * sys_reg values are defined as used in mrs/msr instruction.
2172          * shift the imm value to get the encoding.
2173          */
2174         sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5;
2175         rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
2176         return do_emulate_mrs(regs, sys_reg, rt);
2177 }
2178
2179 static struct undef_hook mrs_hook = {
2180         .instr_mask = 0xfff00000,
2181         .instr_val  = 0xd5300000,
2182         .pstate_mask = PSR_AA32_MODE_MASK,
2183         .pstate_val = PSR_MODE_EL0t,
2184         .fn = emulate_mrs,
2185 };
2186
2187 static int __init enable_mrs_emulation(void)
2188 {
2189         register_undef_hook(&mrs_hook);
2190         return 0;
2191 }
2192
2193 core_initcall(enable_mrs_emulation);
2194
2195 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr,
2196                           char *buf)
2197 {
2198         if (__meltdown_safe)
2199                 return sprintf(buf, "Not affected\n");
2200
2201         if (arm64_kernel_unmapped_at_el0())
2202                 return sprintf(buf, "Mitigation: PTI\n");
2203
2204         return sprintf(buf, "Vulnerable\n");
2205 }