arch/arm64/include/asm/insn.h

   1 /*
   2  * Copyright (C) 2013 Huawei Ltd.
   3  * Author: Jiang Liu <liuj97@gmail.com>
   4  *
   5  * Copyright (C) 2014 Zi Shen Lim <zlim.lnx@gmail.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #ifndef __ASM_INSN_H
  20 #define __ASM_INSN_H
  21 #include <linux/types.h>
  22
  23 /* A64 instructions are always 32 bits. */
  24 #define AARCH64_INSN_SIZE               4
  25
  26 #ifndef __ASSEMBLY__
  27 /*
  28  * ARM Architecture Reference Manual for ARMv8 Profile-A, Issue A.a
  29  * Section C3.1 "A64 instruction index by encoding":
  30  * AArch64 main encoding table
  31  *  Bit position
  32  *   28 27 26 25        Encoding Group
  33  *   0  0  -  -         Unallocated
  34  *   1  0  0  -         Data processing, immediate
  35  *   1  0  1  -         Branch, exception generation and system instructions
  36  *   -  1  -  0         Loads and stores
  37  *   -  1  0  1         Data processing - register
  38  *   0  1  1  1         Data processing - SIMD and floating point
  39  *   1  1  1  1         Data processing - SIMD and floating point
  40  * "-" means "don't care"
  41  */
  42 enum aarch64_insn_encoding_class {
  43         AARCH64_INSN_CLS_UNKNOWN,       /* UNALLOCATED */
  44         AARCH64_INSN_CLS_DP_IMM,        /* Data processing - immediate */
  45         AARCH64_INSN_CLS_DP_REG,        /* Data processing - register */
  46         AARCH64_INSN_CLS_DP_FPSIMD,     /* Data processing - SIMD and FP */
  47         AARCH64_INSN_CLS_LDST,          /* Loads and stores */
  48         AARCH64_INSN_CLS_BR_SYS,        /* Branch, exception generation and
  49                                          * system instructions */
  50 };
  51
  52 enum aarch64_insn_hint_op {
  53         AARCH64_INSN_HINT_NOP   = 0x0 << 5,
  54         AARCH64_INSN_HINT_YIELD = 0x1 << 5,
  55         AARCH64_INSN_HINT_WFE   = 0x2 << 5,
  56         AARCH64_INSN_HINT_WFI   = 0x3 << 5,
  57         AARCH64_INSN_HINT_SEV   = 0x4 << 5,
  58         AARCH64_INSN_HINT_SEVL  = 0x5 << 5,
  59 };
  60
  61 enum aarch64_insn_imm_type {
  62         AARCH64_INSN_IMM_ADR,
  63         AARCH64_INSN_IMM_26,
  64         AARCH64_INSN_IMM_19,
  65         AARCH64_INSN_IMM_16,
  66         AARCH64_INSN_IMM_14,
  67         AARCH64_INSN_IMM_12,
  68         AARCH64_INSN_IMM_9,
  69         AARCH64_INSN_IMM_7,
  70         AARCH64_INSN_IMM_6,
  71         AARCH64_INSN_IMM_S,
  72         AARCH64_INSN_IMM_R,
  73         AARCH64_INSN_IMM_MAX
  74 };
  75
  76 enum aarch64_insn_register_type {
  77         AARCH64_INSN_REGTYPE_RT,
  78         AARCH64_INSN_REGTYPE_RN,
  79         AARCH64_INSN_REGTYPE_RT2,
  80         AARCH64_INSN_REGTYPE_RM,
  81         AARCH64_INSN_REGTYPE_RD,
  82 };
  83
  84 enum aarch64_insn_register {
  85         AARCH64_INSN_REG_0  = 0,
  86         AARCH64_INSN_REG_1  = 1,
  87         AARCH64_INSN_REG_2  = 2,
  88         AARCH64_INSN_REG_3  = 3,
  89         AARCH64_INSN_REG_4  = 4,
  90         AARCH64_INSN_REG_5  = 5,
  91         AARCH64_INSN_REG_6  = 6,
  92         AARCH64_INSN_REG_7  = 7,
  93         AARCH64_INSN_REG_8  = 8,
  94         AARCH64_INSN_REG_9  = 9,
  95         AARCH64_INSN_REG_10 = 10,
  96         AARCH64_INSN_REG_11 = 11,
  97         AARCH64_INSN_REG_12 = 12,
  98         AARCH64_INSN_REG_13 = 13,
  99         AARCH64_INSN_REG_14 = 14,
 100         AARCH64_INSN_REG_15 = 15,
 101         AARCH64_INSN_REG_16 = 16,
 102         AARCH64_INSN_REG_17 = 17,
 103         AARCH64_INSN_REG_18 = 18,
 104         AARCH64_INSN_REG_19 = 19,
 105         AARCH64_INSN_REG_20 = 20,
 106         AARCH64_INSN_REG_21 = 21,
 107         AARCH64_INSN_REG_22 = 22,
 108         AARCH64_INSN_REG_23 = 23,
 109         AARCH64_INSN_REG_24 = 24,
 110         AARCH64_INSN_REG_25 = 25,
 111         AARCH64_INSN_REG_26 = 26,
 112         AARCH64_INSN_REG_27 = 27,
 113         AARCH64_INSN_REG_28 = 28,
 114         AARCH64_INSN_REG_29 = 29,
 115         AARCH64_INSN_REG_FP = 29, /* Frame pointer */
 116         AARCH64_INSN_REG_30 = 30,
 117         AARCH64_INSN_REG_LR = 30, /* Link register */
 118         AARCH64_INSN_REG_ZR = 31, /* Zero: as source register */
 119         AARCH64_INSN_REG_SP = 31  /* Stack pointer: as load/store base reg */
 120 };
 121
 122 enum aarch64_insn_variant {
 123         AARCH64_INSN_VARIANT_32BIT,
 124         AARCH64_INSN_VARIANT_64BIT
 125 };
 126
 127 enum aarch64_insn_condition {
 128         AARCH64_INSN_COND_EQ = 0x0, /* == */
 129         AARCH64_INSN_COND_NE = 0x1, /* != */
 130         AARCH64_INSN_COND_CS = 0x2, /* unsigned >= */
 131         AARCH64_INSN_COND_CC = 0x3, /* unsigned < */
 132         AARCH64_INSN_COND_MI = 0x4, /* < 0 */
 133         AARCH64_INSN_COND_PL = 0x5, /* >= 0 */
 134         AARCH64_INSN_COND_VS = 0x6, /* overflow */
 135         AARCH64_INSN_COND_VC = 0x7, /* no overflow */
 136         AARCH64_INSN_COND_HI = 0x8, /* unsigned > */
 137         AARCH64_INSN_COND_LS = 0x9, /* unsigned <= */
 138         AARCH64_INSN_COND_GE = 0xa, /* signed >= */
 139         AARCH64_INSN_COND_LT = 0xb, /* signed < */
 140         AARCH64_INSN_COND_GT = 0xc, /* signed > */
 141         AARCH64_INSN_COND_LE = 0xd, /* signed <= */
 142         AARCH64_INSN_COND_AL = 0xe, /* always */
 143 };
 144
 145 enum aarch64_insn_branch_type {
 146         AARCH64_INSN_BRANCH_NOLINK,
 147         AARCH64_INSN_BRANCH_LINK,
 148         AARCH64_INSN_BRANCH_RETURN,
 149         AARCH64_INSN_BRANCH_COMP_ZERO,
 150         AARCH64_INSN_BRANCH_COMP_NONZERO,
 151 };
 152
 153 enum aarch64_insn_size_type {
 154         AARCH64_INSN_SIZE_8,
 155         AARCH64_INSN_SIZE_16,
 156         AARCH64_INSN_SIZE_32,
 157         AARCH64_INSN_SIZE_64,
 158 };
 159
 160 enum aarch64_insn_ldst_type {
 161         AARCH64_INSN_LDST_LOAD_REG_OFFSET,
 162         AARCH64_INSN_LDST_STORE_REG_OFFSET,
 163         AARCH64_INSN_LDST_LOAD_PAIR_PRE_INDEX,
 164         AARCH64_INSN_LDST_STORE_PAIR_PRE_INDEX,
 165         AARCH64_INSN_LDST_LOAD_PAIR_POST_INDEX,
 166         AARCH64_INSN_LDST_STORE_PAIR_POST_INDEX,
 167 };
 168
 169 enum aarch64_insn_adsb_type {
 170         AARCH64_INSN_ADSB_ADD,
 171         AARCH64_INSN_ADSB_SUB,
 172         AARCH64_INSN_ADSB_ADD_SETFLAGS,
 173         AARCH64_INSN_ADSB_SUB_SETFLAGS
 174 };
 175
 176 enum aarch64_insn_movewide_type {
 177         AARCH64_INSN_MOVEWIDE_ZERO,
 178         AARCH64_INSN_MOVEWIDE_KEEP,
 179         AARCH64_INSN_MOVEWIDE_INVERSE
 180 };
 181
 182 enum aarch64_insn_bitfield_type {
 183         AARCH64_INSN_BITFIELD_MOVE,
 184         AARCH64_INSN_BITFIELD_MOVE_UNSIGNED,
 185         AARCH64_INSN_BITFIELD_MOVE_SIGNED
 186 };
 187
 188 #define __AARCH64_INSN_FUNCS(abbr, mask, val)   \
 189 static __always_inline bool aarch64_insn_is_##abbr(u32 code) \
 190 { return (code & (mask)) == (val); } \
 191 static __always_inline u32 aarch64_insn_get_##abbr##_value(void) \
 192 { return (val); }
 193
 194 __AARCH64_INSN_FUNCS(str_reg,   0x3FE0EC00, 0x38206800)
 195 __AARCH64_INSN_FUNCS(ldr_reg,   0x3FE0EC00, 0x38606800)
 196 __AARCH64_INSN_FUNCS(stp_post,  0x7FC00000, 0x28800000)
 197 __AARCH64_INSN_FUNCS(ldp_post,  0x7FC00000, 0x28C00000)
 198 __AARCH64_INSN_FUNCS(stp_pre,   0x7FC00000, 0x29800000)
 199 __AARCH64_INSN_FUNCS(ldp_pre,   0x7FC00000, 0x29C00000)
 200 __AARCH64_INSN_FUNCS(add_imm,   0x7F000000, 0x11000000)
 201 __AARCH64_INSN_FUNCS(adds_imm,  0x7F000000, 0x31000000)
 202 __AARCH64_INSN_FUNCS(sub_imm,   0x7F000000, 0x51000000)
 203 __AARCH64_INSN_FUNCS(subs_imm,  0x7F000000, 0x71000000)
 204 __AARCH64_INSN_FUNCS(movn,      0x7F800000, 0x12800000)
 205 __AARCH64_INSN_FUNCS(sbfm,      0x7F800000, 0x13000000)
 206 __AARCH64_INSN_FUNCS(bfm,       0x7F800000, 0x33000000)
 207 __AARCH64_INSN_FUNCS(movz,      0x7F800000, 0x52800000)
 208 __AARCH64_INSN_FUNCS(ubfm,      0x7F800000, 0x53000000)
 209 __AARCH64_INSN_FUNCS(movk,      0x7F800000, 0x72800000)
 210 __AARCH64_INSN_FUNCS(add,       0x7F200000, 0x0B000000)
 211 __AARCH64_INSN_FUNCS(adds,      0x7F200000, 0x2B000000)
 212 __AARCH64_INSN_FUNCS(sub,       0x7F200000, 0x4B000000)
 213 __AARCH64_INSN_FUNCS(subs,      0x7F200000, 0x6B000000)
 214 __AARCH64_INSN_FUNCS(b,         0xFC000000, 0x14000000)
 215 __AARCH64_INSN_FUNCS(bl,        0xFC000000, 0x94000000)
 216 __AARCH64_INSN_FUNCS(cbz,       0xFE000000, 0x34000000)
 217 __AARCH64_INSN_FUNCS(cbnz,      0xFE000000, 0x35000000)
 218 __AARCH64_INSN_FUNCS(bcond,     0xFF000010, 0x54000000)
 219 __AARCH64_INSN_FUNCS(svc,       0xFFE0001F, 0xD4000001)
 220 __AARCH64_INSN_FUNCS(hvc,       0xFFE0001F, 0xD4000002)
 221 __AARCH64_INSN_FUNCS(smc,       0xFFE0001F, 0xD4000003)
 222 __AARCH64_INSN_FUNCS(brk,       0xFFE0001F, 0xD4200000)
 223 __AARCH64_INSN_FUNCS(hint,      0xFFFFF01F, 0xD503201F)
 224 __AARCH64_INSN_FUNCS(br,        0xFFFFFC1F, 0xD61F0000)
 225 __AARCH64_INSN_FUNCS(blr,       0xFFFFFC1F, 0xD63F0000)
 226 __AARCH64_INSN_FUNCS(ret,       0xFFFFFC1F, 0xD65F0000)
 227
 228 #undef  __AARCH64_INSN_FUNCS
 229
 230 bool aarch64_insn_is_nop(u32 insn);
 231
 232 int aarch64_insn_read(void *addr, u32 *insnp);
 233 int aarch64_insn_write(void *addr, u32 insn);
 234 enum aarch64_insn_encoding_class aarch64_get_insn_class(u32 insn);
 235 u32 aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type,
 236                                   u32 insn, u64 imm);
 237 u32 aarch64_insn_gen_branch_imm(unsigned long pc, unsigned long addr,
 238                                 enum aarch64_insn_branch_type type);
 239 u32 aarch64_insn_gen_comp_branch_imm(unsigned long pc, unsigned long addr,
 240                                      enum aarch64_insn_register reg,
 241                                      enum aarch64_insn_variant variant,
 242                                      enum aarch64_insn_branch_type type);
 243 u32 aarch64_insn_gen_cond_branch_imm(unsigned long pc, unsigned long addr,
 244                                      enum aarch64_insn_condition cond);
 245 u32 aarch64_insn_gen_hint(enum aarch64_insn_hint_op op);
 246 u32 aarch64_insn_gen_nop(void);
 247 u32 aarch64_insn_gen_branch_reg(enum aarch64_insn_register reg,
 248                                 enum aarch64_insn_branch_type type);
 249 u32 aarch64_insn_gen_load_store_reg(enum aarch64_insn_register reg,
 250                                     enum aarch64_insn_register base,
 251                                     enum aarch64_insn_register offset,
 252                                     enum aarch64_insn_size_type size,
 253                                     enum aarch64_insn_ldst_type type);
 254 u32 aarch64_insn_gen_load_store_pair(enum aarch64_insn_register reg1,
 255                                      enum aarch64_insn_register reg2,
 256                                      enum aarch64_insn_register base,
 257                                      int offset,
 258                                      enum aarch64_insn_variant variant,
 259                                      enum aarch64_insn_ldst_type type);
 260 u32 aarch64_insn_gen_add_sub_imm(enum aarch64_insn_register dst,
 261                                  enum aarch64_insn_register src,
 262                                  int imm, enum aarch64_insn_variant variant,
 263                                  enum aarch64_insn_adsb_type type);
 264 u32 aarch64_insn_gen_bitfield(enum aarch64_insn_register dst,
 265                               enum aarch64_insn_register src,
 266                               int immr, int imms,
 267                               enum aarch64_insn_variant variant,
 268                               enum aarch64_insn_bitfield_type type);
 269 u32 aarch64_insn_gen_movewide(enum aarch64_insn_register dst,
 270                               int imm, int shift,
 271                               enum aarch64_insn_variant variant,
 272                               enum aarch64_insn_movewide_type type);
 273 u32 aarch64_insn_gen_add_sub_shifted_reg(enum aarch64_insn_register dst,
 274                                          enum aarch64_insn_register src,
 275                                          enum aarch64_insn_register reg,
 276                                          int shift,
 277                                          enum aarch64_insn_variant variant,
 278                                          enum aarch64_insn_adsb_type type);
 279
 280 bool aarch64_insn_hotpatch_safe(u32 old_insn, u32 new_insn);
 281
 282 int aarch64_insn_patch_text_nosync(void *addr, u32 insn);
 283 int aarch64_insn_patch_text_sync(void *addrs[], u32 insns[], int cnt);
 284 int aarch64_insn_patch_text(void *addrs[], u32 insns[], int cnt);
 285 #endif /* __ASSEMBLY__ */
 286
 287 #endif  /* __ASM_INSN_H */