arch/arm64/boot/dts/xilinx/zynqmp.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * dts file for Xilinx ZynqMP
   4  *
   5  * (C) Copyright 2014 - 2021, Xilinx, Inc.
   6  *
   7  * Michal Simek <michal.simek@amd.com>
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  */
  14
  15 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
  16 #include <dt-bindings/gpio/gpio.h>
  17 #include <dt-bindings/power/xlnx-zynqmp-power.h>
  18 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
  19
  20 / {
  21         compatible = "xlnx,zynqmp";
  22         #address-cells = <2>;
  23         #size-cells = <2>;
  24
  25         cpus {
  26                 #address-cells = <1>;
  27                 #size-cells = <0>;
  28
  29                 cpu0: cpu@0 {
  30                         compatible = "arm,cortex-a53";
  31                         device_type = "cpu";
  32                         enable-method = "psci";
  33                         operating-points-v2 = <&cpu_opp_table>;
  34                         reg = <0x0>;
  35                         cpu-idle-states = <&CPU_SLEEP_0>;
  36                 };
  37
  38                 cpu1: cpu@1 {
  39                         compatible = "arm,cortex-a53";
  40                         device_type = "cpu";
  41                         enable-method = "psci";
  42                         reg = <0x1>;
  43                         operating-points-v2 = <&cpu_opp_table>;
  44                         cpu-idle-states = <&CPU_SLEEP_0>;
  45                 };
  46
  47                 cpu2: cpu@2 {
  48                         compatible = "arm,cortex-a53";
  49                         device_type = "cpu";
  50                         enable-method = "psci";
  51                         reg = <0x2>;
  52                         operating-points-v2 = <&cpu_opp_table>;
  53                         cpu-idle-states = <&CPU_SLEEP_0>;
  54                 };
  55
  56                 cpu3: cpu@3 {
  57                         compatible = "arm,cortex-a53";
  58                         device_type = "cpu";
  59                         enable-method = "psci";
  60                         reg = <0x3>;
  61                         operating-points-v2 = <&cpu_opp_table>;
  62                         cpu-idle-states = <&CPU_SLEEP_0>;
  63                 };
  64
  65                 idle-states {
  66                         entry-method = "psci";
  67
  68                         CPU_SLEEP_0: cpu-sleep-0 {
  69                                 compatible = "arm,idle-state";
  70                                 arm,psci-suspend-param = <0x40000000>;
  71                                 local-timer-stop;
  72                                 entry-latency-us = <300>;
  73                                 exit-latency-us = <600>;
  74                                 min-residency-us = <10000>;
  75                         };
  76                 };
  77         };
  78
  79         cpu_opp_table: opp-table-cpu {
  80                 compatible = "operating-points-v2";
  81                 opp-shared;
  82                 opp00 {
  83                         opp-hz = /bits/ 64 <1199999988>;
  84                         opp-microvolt = <1000000>;
  85                         clock-latency-ns = <500000>;
  86                 };
  87                 opp01 {
  88                         opp-hz = /bits/ 64 <599999994>;
  89                         opp-microvolt = <1000000>;
  90                         clock-latency-ns = <500000>;
  91                 };
  92                 opp02 {
  93                         opp-hz = /bits/ 64 <399999996>;
  94                         opp-microvolt = <1000000>;
  95                         clock-latency-ns = <500000>;
  96                 };
  97                 opp03 {
  98                         opp-hz = /bits/ 64 <299999997>;
  99                         opp-microvolt = <1000000>;
 100                         clock-latency-ns = <500000>;
 101                 };
 102         };
 103
 104         reserved-memory {
 105                 #address-cells = <2>;
 106                 #size-cells = <2>;
 107                 ranges;
 108
 109                 rproc_0_fw_image: memory@3ed00000 {
 110                         no-map;
 111                         reg = <0x0 0x3ed00000 0x0 0x40000>;
 112                 };
 113
 114                 rproc_1_fw_image: memory@3ef00000 {
 115                         no-map;
 116                         reg = <0x0 0x3ef00000 0x0 0x40000>;
 117                 };
 118         };
 119
 120         zynqmp_ipi: zynqmp_ipi {
 121                 bootph-all;
 122                 compatible = "xlnx,zynqmp-ipi-mailbox";
 123                 interrupt-parent = <&gic>;
 124                 interrupts = <0 35 4>;
 125                 xlnx,ipi-id = <0>;
 126                 #address-cells = <2>;
 127                 #size-cells = <2>;
 128                 ranges;
 129
 130                 ipi_mailbox_pmu1: mailbox@ff9905c0 {
 131                         bootph-all;
 132                         reg = <0x0 0xff9905c0 0x0 0x20>,
 133                               <0x0 0xff9905e0 0x0 0x20>,
 134                               <0x0 0xff990e80 0x0 0x20>,
 135                               <0x0 0xff990ea0 0x0 0x20>;
 136                         reg-names = "local_request_region",
 137                                     "local_response_region",
 138                                     "remote_request_region",
 139                                     "remote_response_region";
 140                         #mbox-cells = <1>;
 141                         xlnx,ipi-id = <4>;
 142                 };
 143         };
 144
 145         dcc: dcc {
 146                 compatible = "arm,dcc";
 147                 status = "disabled";
 148                 bootph-all;
 149         };
 150
 151         pmu {
 152                 compatible = "arm,armv8-pmuv3";
 153                 interrupt-parent = <&gic>;
 154                 interrupts = <0 143 4>,
 155                              <0 144 4>,
 156                              <0 145 4>,
 157                              <0 146 4>;
 158         };
 159
 160         psci {
 161                 compatible = "arm,psci-0.2";
 162                 method = "smc";
 163         };
 164
 165         firmware {
 166                 zynqmp_firmware: zynqmp-firmware {
 167                         compatible = "xlnx,zynqmp-firmware";
 168                         #power-domain-cells = <1>;
 169                         method = "smc";
 170                         bootph-all;
 171
 172                         zynqmp_power: zynqmp-power {
 173                                 bootph-all;
 174                                 compatible = "xlnx,zynqmp-power";
 175                                 interrupt-parent = <&gic>;
 176                                 interrupts = <0 35 4>;
 177                                 mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>;
 178                                 mbox-names = "tx", "rx";
 179                         };
 180
 181                         nvmem_firmware {
 182                                 compatible = "xlnx,zynqmp-nvmem-fw";
 183                                 #address-cells = <1>;
 184                                 #size-cells = <1>;
 185
 186                                 soc_revision: soc_revision@0 {
 187                                         reg = <0x0 0x4>;
 188                                 };
 189                         };
 190
 191                         zynqmp_pcap: pcap {
 192                                 compatible = "xlnx,zynqmp-pcap-fpga";
 193                         };
 194
 195                         xlnx_aes: zynqmp-aes {
 196                                 compatible = "xlnx,zynqmp-aes";
 197                         };
 198
 199                         zynqmp_reset: reset-controller {
 200                                 compatible = "xlnx,zynqmp-reset";
 201                                 #reset-cells = <1>;
 202                         };
 203
 204                         pinctrl0: pinctrl {
 205                                 compatible = "xlnx,zynqmp-pinctrl";
 206                                 status = "disabled";
 207                         };
 208
 209                         modepin_gpio: gpio {
 210                                 compatible = "xlnx,zynqmp-gpio-modepin";
 211                                 gpio-controller;
 212                                 #gpio-cells = <2>;
 213                         };
 214                 };
 215         };
 216
 217         timer {
 218                 compatible = "arm,armv8-timer";
 219                 interrupt-parent = <&gic>;
 220                 interrupts = <1 13 0xf08>,
 221                              <1 14 0xf08>,
 222                              <1 11 0xf08>,
 223                              <1 10 0xf08>;
 224         };
 225
 226         fpga_full: fpga-full {
 227                 compatible = "fpga-region";
 228                 fpga-mgr = <&zynqmp_pcap>;
 229                 #address-cells = <2>;
 230                 #size-cells = <2>;
 231                 ranges;
 232         };
 233
 234         remoteproc {
 235                 compatible = "xlnx,zynqmp-r5fss";
 236                 xlnx,cluster-mode = <1>;
 237
 238                 r5f-0 {
 239                         compatible = "xlnx,zynqmp-r5f";
 240                         power-domains = <&zynqmp_firmware PD_RPU_0>;
 241                         memory-region = <&rproc_0_fw_image>;
 242                 };
 243
 244                 r5f-1 {
 245                         compatible = "xlnx,zynqmp-r5f";
 246                         power-domains = <&zynqmp_firmware PD_RPU_1>;
 247                         memory-region = <&rproc_1_fw_image>;
 248                 };
 249         };
 250
 251         amba: axi {
 252                 compatible = "simple-bus";
 253                 bootph-all;
 254                 #address-cells = <2>;
 255                 #size-cells = <2>;
 256                 ranges;
 257
 258                 can0: can@ff060000 {
 259                         compatible = "xlnx,zynq-can-1.0";
 260                         status = "disabled";
 261                         clock-names = "can_clk", "pclk";
 262                         reg = <0x0 0xff060000 0x0 0x1000>;
 263                         interrupts = <0 23 4>;
 264                         interrupt-parent = <&gic>;
 265                         tx-fifo-depth = <0x40>;
 266                         rx-fifo-depth = <0x40>;
 267                         power-domains = <&zynqmp_firmware PD_CAN_0>;
 268                 };
 269
 270                 can1: can@ff070000 {
 271                         compatible = "xlnx,zynq-can-1.0";
 272                         status = "disabled";
 273                         clock-names = "can_clk", "pclk";
 274                         reg = <0x0 0xff070000 0x0 0x1000>;
 275                         interrupts = <0 24 4>;
 276                         interrupt-parent = <&gic>;
 277                         tx-fifo-depth = <0x40>;
 278                         rx-fifo-depth = <0x40>;
 279                         power-domains = <&zynqmp_firmware PD_CAN_1>;
 280                 };
 281
 282                 cci: cci@fd6e0000 {
 283                         compatible = "arm,cci-400";
 284                         status = "disabled";
 285                         reg = <0x0 0xfd6e0000 0x0 0x9000>;
 286                         ranges = <0x0 0x0 0xfd6e0000 0x10000>;
 287                         #address-cells = <1>;
 288                         #size-cells = <1>;
 289
 290                         pmu@9000 {
 291                                 compatible = "arm,cci-400-pmu,r1";
 292                                 reg = <0x9000 0x5000>;
 293                                 interrupt-parent = <&gic>;
 294                                 interrupts = <0 123 4>,
 295                                              <0 123 4>,
 296                                              <0 123 4>,
 297                                              <0 123 4>,
 298                                              <0 123 4>;
 299                         };
 300                 };
 301
 302                 /* GDMA */
 303                 fpd_dma_chan1: dma-controller@fd500000 {
 304                         status = "disabled";
 305                         compatible = "xlnx,zynqmp-dma-1.0";
 306                         reg = <0x0 0xfd500000 0x0 0x1000>;
 307                         interrupt-parent = <&gic>;
 308                         interrupts = <0 124 4>;
 309                         clock-names = "clk_main", "clk_apb";
 310                         #dma-cells = <1>;
 311                         xlnx,bus-width = <128>;
 312                         iommus = <&smmu 0x14e8>;
 313                         power-domains = <&zynqmp_firmware PD_GDMA>;
 314                 };
 315
 316                 fpd_dma_chan2: dma-controller@fd510000 {
 317                         status = "disabled";
 318                         compatible = "xlnx,zynqmp-dma-1.0";
 319                         reg = <0x0 0xfd510000 0x0 0x1000>;
 320                         interrupt-parent = <&gic>;
 321                         interrupts = <0 125 4>;
 322                         clock-names = "clk_main", "clk_apb";
 323                         #dma-cells = <1>;
 324                         xlnx,bus-width = <128>;
 325                         iommus = <&smmu 0x14e9>;
 326                         power-domains = <&zynqmp_firmware PD_GDMA>;
 327                 };
 328
 329                 fpd_dma_chan3: dma-controller@fd520000 {
 330                         status = "disabled";
 331                         compatible = "xlnx,zynqmp-dma-1.0";
 332                         reg = <0x0 0xfd520000 0x0 0x1000>;
 333                         interrupt-parent = <&gic>;
 334                         interrupts = <0 126 4>;
 335                         clock-names = "clk_main", "clk_apb";
 336                         #dma-cells = <1>;
 337                         xlnx,bus-width = <128>;
 338                         iommus = <&smmu 0x14ea>;
 339                         power-domains = <&zynqmp_firmware PD_GDMA>;
 340                 };
 341
 342                 fpd_dma_chan4: dma-controller@fd530000 {
 343                         status = "disabled";
 344                         compatible = "xlnx,zynqmp-dma-1.0";
 345                         reg = <0x0 0xfd530000 0x0 0x1000>;
 346                         interrupt-parent = <&gic>;
 347                         interrupts = <0 127 4>;
 348                         clock-names = "clk_main", "clk_apb";
 349                         #dma-cells = <1>;
 350                         xlnx,bus-width = <128>;
 351                         iommus = <&smmu 0x14eb>;
 352                         power-domains = <&zynqmp_firmware PD_GDMA>;
 353                 };
 354
 355                 fpd_dma_chan5: dma-controller@fd540000 {
 356                         status = "disabled";
 357                         compatible = "xlnx,zynqmp-dma-1.0";
 358                         reg = <0x0 0xfd540000 0x0 0x1000>;
 359                         interrupt-parent = <&gic>;
 360                         interrupts = <0 128 4>;
 361                         clock-names = "clk_main", "clk_apb";
 362                         #dma-cells = <1>;
 363                         xlnx,bus-width = <128>;
 364                         iommus = <&smmu 0x14ec>;
 365                         power-domains = <&zynqmp_firmware PD_GDMA>;
 366                 };
 367
 368                 fpd_dma_chan6: dma-controller@fd550000 {
 369                         status = "disabled";
 370                         compatible = "xlnx,zynqmp-dma-1.0";
 371                         reg = <0x0 0xfd550000 0x0 0x1000>;
 372                         interrupt-parent = <&gic>;
 373                         interrupts = <0 129 4>;
 374                         clock-names = "clk_main", "clk_apb";
 375                         #dma-cells = <1>;
 376                         xlnx,bus-width = <128>;
 377                         iommus = <&smmu 0x14ed>;
 378                         power-domains = <&zynqmp_firmware PD_GDMA>;
 379                 };
 380
 381                 fpd_dma_chan7: dma-controller@fd560000 {
 382                         status = "disabled";
 383                         compatible = "xlnx,zynqmp-dma-1.0";
 384                         reg = <0x0 0xfd560000 0x0 0x1000>;
 385                         interrupt-parent = <&gic>;
 386                         interrupts = <0 130 4>;
 387                         clock-names = "clk_main", "clk_apb";
 388                         #dma-cells = <1>;
 389                         xlnx,bus-width = <128>;
 390                         iommus = <&smmu 0x14ee>;
 391                         power-domains = <&zynqmp_firmware PD_GDMA>;
 392                 };
 393
 394                 fpd_dma_chan8: dma-controller@fd570000 {
 395                         status = "disabled";
 396                         compatible = "xlnx,zynqmp-dma-1.0";
 397                         reg = <0x0 0xfd570000 0x0 0x1000>;
 398                         interrupt-parent = <&gic>;
 399                         interrupts = <0 131 4>;
 400                         clock-names = "clk_main", "clk_apb";
 401                         #dma-cells = <1>;
 402                         xlnx,bus-width = <128>;
 403                         iommus = <&smmu 0x14ef>;
 404                         power-domains = <&zynqmp_firmware PD_GDMA>;
 405                 };
 406
 407                 gic: interrupt-controller@f9010000 {
 408                         compatible = "arm,gic-400";
 409                         #interrupt-cells = <3>;
 410                         reg = <0x0 0xf9010000 0x0 0x10000>,
 411                               <0x0 0xf9020000 0x0 0x20000>,
 412                               <0x0 0xf9040000 0x0 0x20000>,
 413                               <0x0 0xf9060000 0x0 0x20000>;
 414                         interrupt-controller;
 415                         interrupt-parent = <&gic>;
 416                         interrupts = <1 9 0xf04>;
 417                 };
 418
 419                 gpu: gpu@fd4b0000 {
 420                         status = "disabled";
 421                         compatible = "xlnx,zynqmp-mali", "arm,mali-400";
 422                         reg = <0x0 0xfd4b0000 0x0 0x10000>;
 423                         interrupt-parent = <&gic>;
 424                         interrupts = <0 132 4>, <0 132 4>, <0 132 4>,
 425                                      <0 132 4>, <0 132 4>, <0 132 4>;
 426                         interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", "ppmmu1";
 427                         clock-names = "bus", "core";
 428                         power-domains = <&zynqmp_firmware PD_GPU>;
 429                 };
 430
 431                 /* LPDDMA default allows only secured access. inorder to enable
 432                  * These dma channels, Users should ensure that these dma
 433                  * Channels are allowed for non secure access.
 434                  */
 435                 lpd_dma_chan1: dma-controller@ffa80000 {
 436                         status = "disabled";
 437                         compatible = "xlnx,zynqmp-dma-1.0";
 438                         reg = <0x0 0xffa80000 0x0 0x1000>;
 439                         interrupt-parent = <&gic>;
 440                         interrupts = <0 77 4>;
 441                         clock-names = "clk_main", "clk_apb";
 442                         #dma-cells = <1>;
 443                         xlnx,bus-width = <64>;
 444                         iommus = <&smmu 0x868>;
 445                         power-domains = <&zynqmp_firmware PD_ADMA>;
 446                 };
 447
 448                 lpd_dma_chan2: dma-controller@ffa90000 {
 449                         status = "disabled";
 450                         compatible = "xlnx,zynqmp-dma-1.0";
 451                         reg = <0x0 0xffa90000 0x0 0x1000>;
 452                         interrupt-parent = <&gic>;
 453                         interrupts = <0 78 4>;
 454                         clock-names = "clk_main", "clk_apb";
 455                         #dma-cells = <1>;
 456                         xlnx,bus-width = <64>;
 457                         iommus = <&smmu 0x869>;
 458                         power-domains = <&zynqmp_firmware PD_ADMA>;
 459                 };
 460
 461                 lpd_dma_chan3: dma-controller@ffaa0000 {
 462                         status = "disabled";
 463                         compatible = "xlnx,zynqmp-dma-1.0";
 464                         reg = <0x0 0xffaa0000 0x0 0x1000>;
 465                         interrupt-parent = <&gic>;
 466                         interrupts = <0 79 4>;
 467                         clock-names = "clk_main", "clk_apb";
 468                         #dma-cells = <1>;
 469                         xlnx,bus-width = <64>;
 470                         iommus = <&smmu 0x86a>;
 471                         power-domains = <&zynqmp_firmware PD_ADMA>;
 472                 };
 473
 474                 lpd_dma_chan4: dma-controller@ffab0000 {
 475                         status = "disabled";
 476                         compatible = "xlnx,zynqmp-dma-1.0";
 477                         reg = <0x0 0xffab0000 0x0 0x1000>;
 478                         interrupt-parent = <&gic>;
 479                         interrupts = <0 80 4>;
 480                         clock-names = "clk_main", "clk_apb";
 481                         #dma-cells = <1>;
 482                         xlnx,bus-width = <64>;
 483                         iommus = <&smmu 0x86b>;
 484                         power-domains = <&zynqmp_firmware PD_ADMA>;
 485                 };
 486
 487                 lpd_dma_chan5: dma-controller@ffac0000 {
 488                         status = "disabled";
 489                         compatible = "xlnx,zynqmp-dma-1.0";
 490                         reg = <0x0 0xffac0000 0x0 0x1000>;
 491                         interrupt-parent = <&gic>;
 492                         interrupts = <0 81 4>;
 493                         clock-names = "clk_main", "clk_apb";
 494                         #dma-cells = <1>;
 495                         xlnx,bus-width = <64>;
 496                         iommus = <&smmu 0x86c>;
 497                         power-domains = <&zynqmp_firmware PD_ADMA>;
 498                 };
 499
 500                 lpd_dma_chan6: dma-controller@ffad0000 {
 501                         status = "disabled";
 502                         compatible = "xlnx,zynqmp-dma-1.0";
 503                         reg = <0x0 0xffad0000 0x0 0x1000>;
 504                         interrupt-parent = <&gic>;
 505                         interrupts = <0 82 4>;
 506                         clock-names = "clk_main", "clk_apb";
 507                         #dma-cells = <1>;
 508                         xlnx,bus-width = <64>;
 509                         iommus = <&smmu 0x86d>;
 510                         power-domains = <&zynqmp_firmware PD_ADMA>;
 511                 };
 512
 513                 lpd_dma_chan7: dma-controller@ffae0000 {
 514                         status = "disabled";
 515                         compatible = "xlnx,zynqmp-dma-1.0";
 516                         reg = <0x0 0xffae0000 0x0 0x1000>;
 517                         interrupt-parent = <&gic>;
 518                         interrupts = <0 83 4>;
 519                         clock-names = "clk_main", "clk_apb";
 520                         #dma-cells = <1>;
 521                         xlnx,bus-width = <64>;
 522                         iommus = <&smmu 0x86e>;
 523                         power-domains = <&zynqmp_firmware PD_ADMA>;
 524                 };
 525
 526                 lpd_dma_chan8: dma-controller@ffaf0000 {
 527                         status = "disabled";
 528                         compatible = "xlnx,zynqmp-dma-1.0";
 529                         reg = <0x0 0xffaf0000 0x0 0x1000>;
 530                         interrupt-parent = <&gic>;
 531                         interrupts = <0 84 4>;
 532                         clock-names = "clk_main", "clk_apb";
 533                         #dma-cells = <1>;
 534                         xlnx,bus-width = <64>;
 535                         iommus = <&smmu 0x86f>;
 536                         power-domains = <&zynqmp_firmware PD_ADMA>;
 537                 };
 538
 539                 mc: memory-controller@fd070000 {
 540                         compatible = "xlnx,zynqmp-ddrc-2.40a";
 541                         reg = <0x0 0xfd070000 0x0 0x30000>;
 542                         interrupt-parent = <&gic>;
 543                         interrupts = <0 112 4>;
 544                 };
 545
 546                 nand0: nand-controller@ff100000 {
 547                         compatible = "xlnx,zynqmp-nand-controller", "arasan,nfc-v3p10";
 548                         status = "disabled";
 549                         reg = <0x0 0xff100000 0x0 0x1000>;
 550                         clock-names = "controller", "bus";
 551                         interrupt-parent = <&gic>;
 552                         interrupts = <0 14 4>;
 553                         #address-cells = <1>;
 554                         #size-cells = <0>;
 555                         iommus = <&smmu 0x872>;
 556                         power-domains = <&zynqmp_firmware PD_NAND>;
 557                 };
 558
 559                 gem0: ethernet@ff0b0000 {
 560                         compatible = "xlnx,zynqmp-gem", "cdns,gem";
 561                         status = "disabled";
 562                         interrupt-parent = <&gic>;
 563                         interrupts = <0 57 4>, <0 57 4>;
 564                         reg = <0x0 0xff0b0000 0x0 0x1000>;
 565                         clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
 566                         #address-cells = <1>;
 567                         #size-cells = <0>;
 568                         iommus = <&smmu 0x874>;
 569                         power-domains = <&zynqmp_firmware PD_ETH_0>;
 570                         resets = <&zynqmp_reset ZYNQMP_RESET_GEM0>;
 571                         reset-names = "gem0_rst";
 572                 };
 573
 574                 gem1: ethernet@ff0c0000 {
 575                         compatible = "xlnx,zynqmp-gem", "cdns,gem";
 576                         status = "disabled";
 577                         interrupt-parent = <&gic>;
 578                         interrupts = <0 59 4>, <0 59 4>;
 579                         reg = <0x0 0xff0c0000 0x0 0x1000>;
 580                         clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
 581                         #address-cells = <1>;
 582                         #size-cells = <0>;
 583                         iommus = <&smmu 0x875>;
 584                         power-domains = <&zynqmp_firmware PD_ETH_1>;
 585                         resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>;
 586                         reset-names = "gem1_rst";
 587                 };
 588
 589                 gem2: ethernet@ff0d0000 {
 590                         compatible = "xlnx,zynqmp-gem", "cdns,gem";
 591                         status = "disabled";
 592                         interrupt-parent = <&gic>;
 593                         interrupts = <0 61 4>, <0 61 4>;
 594                         reg = <0x0 0xff0d0000 0x0 0x1000>;
 595                         clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
 596                         #address-cells = <1>;
 597                         #size-cells = <0>;
 598                         iommus = <&smmu 0x876>;
 599                         power-domains = <&zynqmp_firmware PD_ETH_2>;
 600                         resets = <&zynqmp_reset ZYNQMP_RESET_GEM2>;
 601                         reset-names = "gem2_rst";
 602                 };
 603
 604                 gem3: ethernet@ff0e0000 {
 605                         compatible = "xlnx,zynqmp-gem", "cdns,gem";
 606                         status = "disabled";
 607                         interrupt-parent = <&gic>;
 608                         interrupts = <0 63 4>, <0 63 4>;
 609                         reg = <0x0 0xff0e0000 0x0 0x1000>;
 610                         clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
 611                         #address-cells = <1>;
 612                         #size-cells = <0>;
 613                         iommus = <&smmu 0x877>;
 614                         power-domains = <&zynqmp_firmware PD_ETH_3>;
 615                         resets = <&zynqmp_reset ZYNQMP_RESET_GEM3>;
 616                         reset-names = "gem3_rst";
 617                 };
 618
 619                 gpio: gpio@ff0a0000 {
 620                         compatible = "xlnx,zynqmp-gpio-1.0";
 621                         status = "disabled";
 622                         #gpio-cells = <0x2>;
 623                         gpio-controller;
 624                         interrupt-parent = <&gic>;
 625                         interrupts = <0 16 4>;
 626                         interrupt-controller;
 627                         #interrupt-cells = <2>;
 628                         reg = <0x0 0xff0a0000 0x0 0x1000>;
 629                         power-domains = <&zynqmp_firmware PD_GPIO>;
 630                 };
 631
 632                 i2c0: i2c@ff020000 {
 633                         compatible = "cdns,i2c-r1p14";
 634                         status = "disabled";
 635                         interrupt-parent = <&gic>;
 636                         interrupts = <0 17 4>;
 637                         reg = <0x0 0xff020000 0x0 0x1000>;
 638                         #address-cells = <1>;
 639                         #size-cells = <0>;
 640                         power-domains = <&zynqmp_firmware PD_I2C_0>;
 641                 };
 642
 643                 i2c1: i2c@ff030000 {
 644                         compatible = "cdns,i2c-r1p14";
 645                         status = "disabled";
 646                         interrupt-parent = <&gic>;
 647                         interrupts = <0 18 4>;
 648                         reg = <0x0 0xff030000 0x0 0x1000>;
 649                         #address-cells = <1>;
 650                         #size-cells = <0>;
 651                         power-domains = <&zynqmp_firmware PD_I2C_1>;
 652                 };
 653
 654                 pcie: pcie@fd0e0000 {
 655                         compatible = "xlnx,nwl-pcie-2.11";
 656                         status = "disabled";
 657                         #address-cells = <3>;
 658                         #size-cells = <2>;
 659                         #interrupt-cells = <1>;
 660                         msi-controller;
 661                         device_type = "pci";
 662                         interrupt-parent = <&gic>;
 663                         interrupts = <0 118 4>,
 664                                      <0 117 4>,
 665                                      <0 116 4>,
 666                                      <0 115 4>, /* MSI_1 [63...32] */
 667                                      <0 114 4>; /* MSI_0 [31...0] */
 668                         interrupt-names = "misc", "dummy", "intx",
 669                                           "msi1", "msi0";
 670                         msi-parent = <&pcie>;
 671                         reg = <0x0 0xfd0e0000 0x0 0x1000>,
 672                               <0x0 0xfd480000 0x0 0x1000>,
 673                               <0x80 0x00000000 0x0 0x1000000>;
 674                         reg-names = "breg", "pcireg", "cfg";
 675                         ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000>,/* non-prefetchable memory */
 676                                  <0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
 677                         bus-range = <0x00 0xff>;
 678                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 679                         interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
 680                                         <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
 681                                         <0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
 682                                         <0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
 683                         iommus = <&smmu 0x4d0>;
 684                         power-domains = <&zynqmp_firmware PD_PCIE>;
 685                         pcie_intc: legacy-interrupt-controller {
 686                                 interrupt-controller;
 687                                 #address-cells = <0>;
 688                                 #interrupt-cells = <1>;
 689                         };
 690                 };
 691
 692                 qspi: spi@ff0f0000 {
 693                         bootph-all;
 694                         compatible = "xlnx,zynqmp-qspi-1.0";
 695                         status = "disabled";
 696                         clock-names = "ref_clk", "pclk";
 697                         interrupts = <0 15 4>;
 698                         interrupt-parent = <&gic>;
 699                         num-cs = <1>;
 700                         reg = <0x0 0xff0f0000 0x0 0x1000>,
 701                               <0x0 0xc0000000 0x0 0x8000000>;
 702                         #address-cells = <1>;
 703                         #size-cells = <0>;
 704                         iommus = <&smmu 0x873>;
 705                         power-domains = <&zynqmp_firmware PD_QSPI>;
 706                 };
 707
 708                 psgtr: phy@fd400000 {
 709                         compatible = "xlnx,zynqmp-psgtr-v1.1";
 710                         status = "disabled";
 711                         reg = <0x0 0xfd400000 0x0 0x40000>,
 712                               <0x0 0xfd3d0000 0x0 0x1000>;
 713                         reg-names = "serdes", "siou";
 714                         #phy-cells = <4>;
 715                 };
 716
 717                 rtc: rtc@ffa60000 {
 718                         compatible = "xlnx,zynqmp-rtc";
 719                         status = "disabled";
 720                         reg = <0x0 0xffa60000 0x0 0x100>;
 721                         interrupt-parent = <&gic>;
 722                         interrupts = <0 26 4>, <0 27 4>;
 723                         interrupt-names = "alarm", "sec";
 724                         calibration = <0x7FFF>;
 725                 };
 726
 727                 sata: ahci@fd0c0000 {
 728                         compatible = "ceva,ahci-1v84";
 729                         status = "disabled";
 730                         reg = <0x0 0xfd0c0000 0x0 0x2000>;
 731                         interrupt-parent = <&gic>;
 732                         interrupts = <0 133 4>;
 733                         power-domains = <&zynqmp_firmware PD_SATA>;
 734                         resets = <&zynqmp_reset ZYNQMP_RESET_SATA>;
 735                         iommus = <&smmu 0x4c0>, <&smmu 0x4c1>,
 736                                  <&smmu 0x4c2>, <&smmu 0x4c3>;
 737                 };
 738
 739                 sdhci0: mmc@ff160000 {
 740                         bootph-all;
 741                         compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
 742                         status = "disabled";
 743                         interrupt-parent = <&gic>;
 744                         interrupts = <0 48 4>;
 745                         reg = <0x0 0xff160000 0x0 0x1000>;
 746                         clock-names = "clk_xin", "clk_ahb";
 747                         iommus = <&smmu 0x870>;
 748                         #clock-cells = <1>;
 749                         clock-output-names = "clk_out_sd0", "clk_in_sd0";
 750                         power-domains = <&zynqmp_firmware PD_SD_0>;
 751                         resets = <&zynqmp_reset ZYNQMP_RESET_SDIO0>;
 752                 };
 753
 754                 sdhci1: mmc@ff170000 {
 755                         bootph-all;
 756                         compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
 757                         status = "disabled";
 758                         interrupt-parent = <&gic>;
 759                         interrupts = <0 49 4>;
 760                         reg = <0x0 0xff170000 0x0 0x1000>;
 761                         clock-names = "clk_xin", "clk_ahb";
 762                         iommus = <&smmu 0x871>;
 763                         #clock-cells = <1>;
 764                         clock-output-names = "clk_out_sd1", "clk_in_sd1";
 765                         power-domains = <&zynqmp_firmware PD_SD_1>;
 766                         resets = <&zynqmp_reset ZYNQMP_RESET_SDIO1>;
 767                 };
 768
 769                 smmu: iommu@fd800000 {
 770                         compatible = "arm,mmu-500";
 771                         reg = <0x0 0xfd800000 0x0 0x20000>;
 772                         #iommu-cells = <1>;
 773                         status = "disabled";
 774                         #global-interrupts = <1>;
 775                         interrupt-parent = <&gic>;
 776                         interrupts = <0 155 4>,
 777                                 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
 778                                 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
 779                                 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
 780                                 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;
 781                 };
 782
 783                 spi0: spi@ff040000 {
 784                         compatible = "cdns,spi-r1p6";
 785                         status = "disabled";
 786                         interrupt-parent = <&gic>;
 787                         interrupts = <0 19 4>;
 788                         reg = <0x0 0xff040000 0x0 0x1000>;
 789                         clock-names = "ref_clk", "pclk";
 790                         #address-cells = <1>;
 791                         #size-cells = <0>;
 792                         power-domains = <&zynqmp_firmware PD_SPI_0>;
 793                 };
 794
 795                 spi1: spi@ff050000 {
 796                         compatible = "cdns,spi-r1p6";
 797                         status = "disabled";
 798                         interrupt-parent = <&gic>;
 799                         interrupts = <0 20 4>;
 800                         reg = <0x0 0xff050000 0x0 0x1000>;
 801                         clock-names = "ref_clk", "pclk";
 802                         #address-cells = <1>;
 803                         #size-cells = <0>;
 804                         power-domains = <&zynqmp_firmware PD_SPI_1>;
 805                 };
 806
 807                 ttc0: timer@ff110000 {
 808                         compatible = "cdns,ttc";
 809                         status = "disabled";
 810                         interrupt-parent = <&gic>;
 811                         interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
 812                         reg = <0x0 0xff110000 0x0 0x1000>;
 813                         timer-width = <32>;
 814                         power-domains = <&zynqmp_firmware PD_TTC_0>;
 815                 };
 816
 817                 ttc1: timer@ff120000 {
 818                         compatible = "cdns,ttc";
 819                         status = "disabled";
 820                         interrupt-parent = <&gic>;
 821                         interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
 822                         reg = <0x0 0xff120000 0x0 0x1000>;
 823                         timer-width = <32>;
 824                         power-domains = <&zynqmp_firmware PD_TTC_1>;
 825                 };
 826
 827                 ttc2: timer@ff130000 {
 828                         compatible = "cdns,ttc";
 829                         status = "disabled";
 830                         interrupt-parent = <&gic>;
 831                         interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
 832                         reg = <0x0 0xff130000 0x0 0x1000>;
 833                         timer-width = <32>;
 834                         power-domains = <&zynqmp_firmware PD_TTC_2>;
 835                 };
 836
 837                 ttc3: timer@ff140000 {
 838                         compatible = "cdns,ttc";
 839                         status = "disabled";
 840                         interrupt-parent = <&gic>;
 841                         interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
 842                         reg = <0x0 0xff140000 0x0 0x1000>;
 843                         timer-width = <32>;
 844                         power-domains = <&zynqmp_firmware PD_TTC_3>;
 845                 };
 846
 847                 uart0: serial@ff000000 {
 848                         bootph-all;
 849                         compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
 850                         status = "disabled";
 851                         interrupt-parent = <&gic>;
 852                         interrupts = <0 21 4>;
 853                         reg = <0x0 0xff000000 0x0 0x1000>;
 854                         clock-names = "uart_clk", "pclk";
 855                         power-domains = <&zynqmp_firmware PD_UART_0>;
 856                 };
 857
 858                 uart1: serial@ff010000 {
 859                         bootph-all;
 860                         compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
 861                         status = "disabled";
 862                         interrupt-parent = <&gic>;
 863                         interrupts = <0 22 4>;
 864                         reg = <0x0 0xff010000 0x0 0x1000>;
 865                         clock-names = "uart_clk", "pclk";
 866                         power-domains = <&zynqmp_firmware PD_UART_1>;
 867                 };
 868
 869                 usb0: usb@ff9d0000 {
 870                         #address-cells = <2>;
 871                         #size-cells = <2>;
 872                         status = "disabled";
 873                         compatible = "xlnx,zynqmp-dwc3";
 874                         reg = <0x0 0xff9d0000 0x0 0x100>;
 875                         power-domains = <&zynqmp_firmware PD_USB_0>;
 876                         resets = <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>,
 877                                  <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>,
 878                                  <&zynqmp_reset ZYNQMP_RESET_USB0_APB>;
 879                         reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
 880                         reset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>;
 881                         ranges;
 882
 883                         dwc3_0: usb@fe200000 {
 884                                 compatible = "snps,dwc3";
 885                                 reg = <0x0 0xfe200000 0x0 0x40000>;
 886                                 interrupt-parent = <&gic>;
 887                                 interrupt-names = "dwc_usb3", "otg";
 888                                 interrupts = <0 65 4>, <0 69 4>;
 889                                 clock-names = "bus_early", "ref";
 890                                 iommus = <&smmu 0x860>;
 891                                 snps,quirk-frame-length-adjustment = <0x20>;
 892                                 snps,resume-hs-terminations;
 893                                 /* dma-coherent; */
 894                         };
 895                 };
 896
 897                 usb1: usb@ff9e0000 {
 898                         #address-cells = <2>;
 899                         #size-cells = <2>;
 900                         status = "disabled";
 901                         compatible = "xlnx,zynqmp-dwc3";
 902                         reg = <0x0 0xff9e0000 0x0 0x100>;
 903                         power-domains = <&zynqmp_firmware PD_USB_1>;
 904                         resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>,
 905                                  <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>,
 906                                  <&zynqmp_reset ZYNQMP_RESET_USB1_APB>;
 907                         reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
 908                         ranges;
 909
 910                         dwc3_1: usb@fe300000 {
 911                                 compatible = "snps,dwc3";
 912                                 reg = <0x0 0xfe300000 0x0 0x40000>;
 913                                 interrupt-parent = <&gic>;
 914                                 interrupt-names = "dwc_usb3", "otg";
 915                                 interrupts = <0 70 4>, <0 74 4>;
 916                                 clock-names = "bus_early", "ref";
 917                                 iommus = <&smmu 0x861>;
 918                                 snps,quirk-frame-length-adjustment = <0x20>;
 919                                 snps,resume-hs-terminations;
 920                                 /* dma-coherent; */
 921                         };
 922                 };
 923
 924                 watchdog0: watchdog@fd4d0000 {
 925                         compatible = "cdns,wdt-r1p2";
 926                         status = "disabled";
 927                         interrupt-parent = <&gic>;
 928                         interrupts = <0 113 1>;
 929                         reg = <0x0 0xfd4d0000 0x0 0x1000>;
 930                         timeout-sec = <60>;
 931                         reset-on-timeout;
 932                 };
 933
 934                 lpd_watchdog: watchdog@ff150000 {
 935                         compatible = "cdns,wdt-r1p2";
 936                         status = "disabled";
 937                         interrupt-parent = <&gic>;
 938                         interrupts = <0 52 1>;
 939                         reg = <0x0 0xff150000 0x0 0x1000>;
 940                         timeout-sec = <10>;
 941                 };
 942
 943                 xilinx_ams: ams@ffa50000 {
 944                         compatible = "xlnx,zynqmp-ams";
 945                         status = "disabled";
 946                         interrupt-parent = <&gic>;
 947                         interrupts = <0 56 4>;
 948                         reg = <0x0 0xffa50000 0x0 0x800>;
 949                         #address-cells = <1>;
 950                         #size-cells = <1>;
 951                         #io-channel-cells = <1>;
 952                         ranges = <0 0 0xffa50800 0x800>;
 953
 954                         ams_ps: ams-ps@0 {
 955                                 compatible = "xlnx,zynqmp-ams-ps";
 956                                 status = "disabled";
 957                                 reg = <0x0 0x400>;
 958                         };
 959
 960                         ams_pl: ams-pl@400 {
 961                                 compatible = "xlnx,zynqmp-ams-pl";
 962                                 status = "disabled";
 963                                 reg = <0x400 0x400>;
 964                                 #address-cells = <1>;
 965                                 #size-cells = <0>;
 966                         };
 967                 };
 968
 969                 zynqmp_dpdma: dma-controller@fd4c0000 {
 970                         compatible = "xlnx,zynqmp-dpdma";
 971                         status = "disabled";
 972                         reg = <0x0 0xfd4c0000 0x0 0x1000>;
 973                         interrupts = <0 122 4>;
 974                         interrupt-parent = <&gic>;
 975                         clock-names = "axi_clk";
 976                         power-domains = <&zynqmp_firmware PD_DP>;
 977                         #dma-cells = <1>;
 978                 };
 979
 980                 zynqmp_dpsub: display@fd4a0000 {
 981                         bootph-all;
 982                         compatible = "xlnx,zynqmp-dpsub-1.7";
 983                         status = "disabled";
 984                         reg = <0x0 0xfd4a0000 0x0 0x1000>,
 985                               <0x0 0xfd4aa000 0x0 0x1000>,
 986                               <0x0 0xfd4ab000 0x0 0x1000>,
 987                               <0x0 0xfd4ac000 0x0 0x1000>;
 988                         reg-names = "dp", "blend", "av_buf", "aud";
 989                         interrupts = <0 119 4>;
 990                         interrupt-parent = <&gic>;
 991                         clock-names = "dp_apb_clk", "dp_aud_clk",
 992                                       "dp_vtc_pixel_clk_in";
 993                         power-domains = <&zynqmp_firmware PD_DP>;
 994                         resets = <&zynqmp_reset ZYNQMP_RESET_DP>;
 995                         dma-names = "vid0", "vid1", "vid2", "gfx0";
 996                         dmas = <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO0>,
 997                                <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>,
 998                                <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>,
 999                                <&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>;
1000
1001                         ports {
1002                                 #address-cells = <1>;
1003                                 #size-cells = <0>;
1004
1005                                 port@0 {
1006                                         reg = <0>;
1007                                 };
1008                                 port@1 {
1009                                         reg = <1>;
1010                                 };
1011                                 port@2 {
1012                                         reg = <2>;
1013                                 };
1014                                 port@3 {
1015                                         reg = <3>;
1016                                 };
1017                                 port@4 {
1018                                         reg = <4>;
1019                                 };
1020                                 port@5 {
1021                                         reg = <5>;
1022                                 };
1023                         };
1024                 };
1025         };
1026 };