arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * dts file for Xilinx ZynqMP SM-K26 rev1/B/A
   4  *
   5  * (C) Copyright 2020 - 2021, Xilinx, Inc.
   6  *
   7  * Michal Simek <michal.simek@xilinx.com>
   8  */
   9
  10 /dts-v1/;
  11
  12 #include "zynqmp.dtsi"
  13 #include "zynqmp-clk-ccf.dtsi"
  14 #include <dt-bindings/input/input.h>
  15 #include <dt-bindings/gpio/gpio.h>
  16 #include <dt-bindings/phy/phy.h>
  17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
  18
  19 / {
  20         model = "ZynqMP SM-K26 Rev1/B/A";
  21         compatible = "xlnx,zynqmp-sm-k26-rev1", "xlnx,zynqmp-sm-k26-revB",
  22                      "xlnx,zynqmp-sm-k26-revA", "xlnx,zynqmp-sm-k26",
  23                      "xlnx,zynqmp";
  24
  25         aliases {
  26                 i2c0 = &i2c0;
  27                 i2c1 = &i2c1;
  28                 mmc0 = &sdhci0;
  29                 mmc1 = &sdhci1;
  30                 nvmem0 = &eeprom;
  31                 nvmem1 = &eeprom_cc;
  32                 rtc0 = &rtc;
  33                 serial0 = &uart0;
  34                 serial1 = &uart1;
  35                 serial2 = &dcc;
  36                 spi0 = &qspi;
  37                 spi1 = &spi0;
  38                 spi2 = &spi1;
  39                 usb0 = &usb0;
  40                 usb1 = &usb1;
  41         };
  42
  43         chosen {
  44                 bootargs = "earlycon";
  45                 stdout-path = "serial1:115200n8";
  46         };
  47
  48         memory@0 {
  49                 device_type = "memory"; /* 4GB */
  50                 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
  51         };
  52
  53         gpio-keys {
  54                 compatible = "gpio-keys";
  55                 autorepeat;
  56                 key-fwuen {
  57                         label = "fwuen";
  58                         gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
  59                         linux,code = <BTN_MISC>;
  60                         wakeup-source;
  61                         autorepeat;
  62                 };
  63         };
  64
  65         leds {
  66                 compatible = "gpio-leds";
  67                 ds35-led {
  68                         label = "heartbeat";
  69                         gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
  70                         linux,default-trigger = "heartbeat";
  71                 };
  72
  73                 ds36-led {
  74                         label = "vbus_det";
  75                         gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
  76                         default-state = "on";
  77                 };
  78         };
  79
  80         ams {
  81                 compatible = "iio-hwmon";
  82                 io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,
  83                         <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,
  84                         <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,
  85                         <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>,
  86                         <&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>,
  87                         <&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>,
  88                         <&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>,
  89                         <&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>,
  90                         <&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>,
  91                         <&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>;
  92         };
  93 };
  94
  95 &modepin_gpio {
  96         label = "modepin";
  97 };
  98
  99 &uart1 { /* MIO36/MIO37 */
 100         status = "okay";
 101 };
 102
 103 &pinctrl0 {
 104         status = "okay";
 105         pinctrl_sdhci0_default: sdhci0-default {
 106                 conf {
 107                         groups = "sdio0_0_grp";
 108                         slew-rate = <SLEW_RATE_SLOW>;
 109                         power-source = <IO_STANDARD_LVCMOS18>;
 110                         bias-disable;
 111                 };
 112
 113                 mux {
 114                         groups = "sdio0_0_grp";
 115                         function = "sdio0";
 116                 };
 117         };
 118 };
 119
 120 &qspi { /* MIO 0-5 - U143 */
 121         status = "okay";
 122         spi_flash: flash@0 { /* MT25QU512A */
 123                 compatible = "mt25qu512a", "jedec,spi-nor"; /* 64MB */
 124                 #address-cells = <1>;
 125                 #size-cells = <1>;
 126                 reg = <0>;
 127                 spi-tx-bus-width = <1>;
 128                 spi-rx-bus-width = <4>;
 129                 spi-max-frequency = <40000000>; /* 40MHz */
 130                 partition@0 {
 131                         label = "Image Selector";
 132                         reg = <0x0 0x80000>; /* 512KB */
 133                         read-only;
 134                         lock;
 135                 };
 136                 partition@80000 {
 137                         label = "Image Selector Golden";
 138                         reg = <0x80000 0x80000>; /* 512KB */
 139                         read-only;
 140                         lock;
 141                 };
 142                 partition@100000 {
 143                         label = "Persistent Register";
 144                         reg = <0x100000 0x20000>; /* 128KB */
 145                 };
 146                 partition@120000 {
 147                         label = "Persistent Register Backup";
 148                         reg = <0x120000 0x20000>; /* 128KB */
 149                 };
 150                 partition@140000 {
 151                         label = "Open_1";
 152                         reg = <0x140000 0xC0000>; /* 768KB */
 153                 };
 154                 partition@200000 {
 155                         label = "Image A (FSBL, PMU, ATF, U-Boot)";
 156                         reg = <0x200000 0xD00000>; /* 13MB */
 157                 };
 158                 partition@f00000 {
 159                         label = "ImgSel Image A Catch";
 160                         reg = <0xF00000 0x80000>; /* 512KB */
 161                         read-only;
 162                         lock;
 163                 };
 164                 partition@f80000 {
 165                         label = "Image B (FSBL, PMU, ATF, U-Boot)";
 166                         reg = <0xF80000 0xD00000>; /* 13MB */
 167                 };
 168                 partition@1c80000 {
 169                         label = "ImgSel Image B Catch";
 170                         reg = <0x1C80000 0x80000>; /* 512KB */
 171                         read-only;
 172                         lock;
 173                 };
 174                 partition@1d00000 {
 175                         label = "Open_2";
 176                         reg = <0x1D00000 0x100000>; /* 1MB */
 177                 };
 178                 partition@1e00000 {
 179                         label = "Recovery Image";
 180                         reg = <0x1E00000 0x200000>; /* 2MB */
 181                         read-only;
 182                         lock;
 183                 };
 184                 partition@2000000 {
 185                         label = "Recovery Image Backup";
 186                         reg = <0x2000000 0x200000>; /* 2MB */
 187                         read-only;
 188                         lock;
 189                 };
 190                 partition@2200000 {
 191                         label = "U-Boot storage variables";
 192                         reg = <0x2200000 0x20000>; /* 128KB */
 193                 };
 194                 partition@2220000 {
 195                         label = "U-Boot storage variables backup";
 196                         reg = <0x2220000 0x20000>; /* 128KB */
 197                 };
 198                 partition@2240000 {
 199                         label = "SHA256";
 200                         reg = <0x2240000 0x40000>; /* 256B but 256KB sector */
 201                         read-only;
 202                         lock;
 203                 };
 204                 partition@2280000 {
 205                         label = "Secure OS Storage";
 206                         reg = <0x2280000 0x20000>; /* 128KB */
 207                 };
 208                 partition@22A0000 {
 209                         label = "User";
 210                         reg = <0x22A0000 0x1d60000>; /* 29.375 MB */
 211                 };
 212         };
 213 };
 214
 215 &sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A */
 216         status = "okay";
 217         pinctrl-names = "default";
 218         pinctrl-0 = <&pinctrl_sdhci0_default>;
 219         non-removable;
 220         disable-wp;
 221         bus-width = <8>;
 222         xlnx,mio-bank = <0>;
 223         assigned-clock-rates = <187498123>;
 224 };
 225
 226 &spi1 { /* MIO6, 9-11 */
 227         status = "okay";
 228         label = "TPM";
 229         num-cs = <1>;
 230         tpm@0 { /* slm9670 - U144 */
 231                 compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
 232                 reg = <0>;
 233                 spi-max-frequency = <18500000>;
 234         };
 235 };
 236
 237 &i2c1 {
 238         status = "okay";
 239         clock-frequency = <400000>;
 240         scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
 241         sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
 242
 243         eeprom: eeprom@50 { /* u46 - also at address 0x58 */
 244                 compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */
 245                 reg = <0x50>;
 246                 /* WP pin EE_WP_EN connected to slg7x644092@68 */
 247         };
 248
 249         eeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */
 250                 compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */
 251                 reg = <0x51>;
 252         };
 253
 254         /* da9062@30 - u170 - also at address 0x31 */
 255         /* da9131@33 - u167 */
 256         da9131: pmic@33 {
 257                 compatible = "dlg,da9131";
 258                 reg = <0x33>;
 259                 regulators {
 260                         da9131_buck1: buck1 {
 261                                 regulator-name = "da9131_buck1";
 262                                 regulator-boot-on;
 263                                 regulator-always-on;
 264                         };
 265                         da9131_buck2: buck2 {
 266                                 regulator-name = "da9131_buck2";
 267                                 regulator-boot-on;
 268                                 regulator-always-on;
 269                         };
 270                 };
 271         };
 272
 273         /* da9130@32 - u166 */
 274         da9130: pmic@32 {
 275                 compatible = "dlg,da9130";
 276                 reg = <0x32>;
 277                 regulators {
 278                         da9130_buck1: buck1 {
 279                                 regulator-name = "da9130_buck1";
 280                                 regulator-boot-on;
 281                                 regulator-always-on;
 282                         };
 283                 };
 284         };
 285
 286         /* slg7x644091@70 - u168 NOT accessible due to address conflict with stdp4320 */
 287         /*
 288          * stdp4320 - u27 FW has below two issues to be fixed in next board revision.
 289          * Device acknowledging to addresses 0x5C, 0x5D, 0x70, 0x72, 0x76.
 290          * Address conflict with slg7x644091@70 making both the devices NOT accessible.
 291          * With the FW fix, stdp4320 should respond to address 0x73 only.
 292          */
 293         /* slg7x644092@68 - u169 */
 294         /* Also connected via JA1C as C23/C24 */
 295 };
 296
 297 &gpio {
 298         status = "okay";
 299         gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */
 300                           "QSPI_CS_B", "SPI_CLK", "LED1", "LED2", "SPI_CS_B", /* 5 - 9 */
 301                           "SPI_MISO", "SPI_MOSI", "FWUEN", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
 302                           "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
 303                           "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST", "I2C1_SCL", /* 20 - 24 */
 304                           "I2C1_SDA", "", "", "", "", /* 25 - 29 */
 305                           "", "", "", "", "", /* 30 - 34 */
 306                           "", "", "", "", "", /* 35 - 39 */
 307                           "", "", "", "", "", /* 40 - 44 */
 308                           "", "", "", "", "", /* 45 - 49 */
 309                           "", "", "", "", "", /* 50 - 54 */
 310                           "", "", "", "", "", /* 55 - 59 */
 311                           "", "", "", "", "", /* 60 - 64 */
 312                           "", "", "", "", "", /* 65 - 69 */
 313                           "", "", "", "", "", /* 70 - 74 */
 314                           "", "", "", /* 75 - 77, MIO end and EMIO start */
 315                           "", "", /* 78 - 79 */
 316                           "", "", "", "", "", /* 80 - 84 */
 317                           "", "", "", "", "", /* 85 - 89 */
 318                           "", "", "", "", "", /* 90 - 94 */
 319                           "", "", "", "", "", /* 95 - 99 */
 320                           "", "", "", "", "", /* 100 - 104 */
 321                           "", "", "", "", "", /* 105 - 109 */
 322                           "", "", "", "", "", /* 110 - 114 */
 323                           "", "", "", "", "", /* 115 - 119 */
 324                           "", "", "", "", "", /* 120 - 124 */
 325                           "", "", "", "", "", /* 125 - 129 */
 326                           "", "", "", "", "", /* 130 - 134 */
 327                           "", "", "", "", "", /* 135 - 139 */
 328                           "", "", "", "", "", /* 140 - 144 */
 329                           "", "", "", "", "", /* 145 - 149 */
 330                           "", "", "", "", "", /* 150 - 154 */
 331                           "", "", "", "", "", /* 155 - 159 */
 332                           "", "", "", "", "", /* 160 - 164 */
 333                           "", "", "", "", "", /* 165 - 169 */
 334                           "", "", "", ""; /* 170 - 173 */
 335 };
 336
 337 &xilinx_ams {
 338         status = "okay";
 339 };
 340
 341 &ams_ps {
 342         status = "okay";
 343 };
 344
 345 &ams_pl {
 346         status = "okay";
 347 };
 348
 349 &zynqmp_dpsub {
 350         status = "okay";
 351 };
 352
 353 &rtc {
 354         status = "okay";
 355 };
 356
 357 &lpd_dma_chan1 {
 358         status = "okay";
 359 };
 360
 361 &lpd_dma_chan2 {
 362         status = "okay";
 363 };
 364
 365 &lpd_dma_chan3 {
 366         status = "okay";
 367 };
 368
 369 &lpd_dma_chan4 {
 370         status = "okay";
 371 };
 372
 373 &lpd_dma_chan5 {
 374         status = "okay";
 375 };
 376
 377 &lpd_dma_chan6 {
 378         status = "okay";
 379 };
 380
 381 &lpd_dma_chan7 {
 382         status = "okay";
 383 };
 384
 385 &lpd_dma_chan8 {
 386         status = "okay";
 387 };
 388
 389 &fpd_dma_chan1 {
 390         status = "okay";
 391 };
 392
 393 &fpd_dma_chan2 {
 394         status = "okay";
 395 };
 396
 397 &fpd_dma_chan3 {
 398         status = "okay";
 399 };
 400
 401 &fpd_dma_chan4 {
 402         status = "okay";
 403 };
 404
 405 &fpd_dma_chan5 {
 406         status = "okay";
 407 };
 408
 409 &fpd_dma_chan6 {
 410         status = "okay";
 411 };
 412
 413 &fpd_dma_chan7 {
 414         status = "okay";
 415 };
 416
 417 &fpd_dma_chan8 {
 418         status = "okay";
 419 };
 420
 421 &gpu {
 422         status = "okay";
 423 };
 424
 425 &lpd_watchdog {
 426         status = "okay";
 427 };
 428
 429 &watchdog0 {
 430         status = "okay";
 431 };
 432
 433 &cpu_opp_table {
 434         opp00 {
 435                 opp-hz = /bits/ 64 <1333333333>;
 436         };
 437         opp01 {
 438                 opp-hz = /bits/ 64 <666666666>;
 439         };
 440         opp02 {
 441                 opp-hz = /bits/ 64 <444444444>;
 442         };
 443         opp03 {
 444                 opp-hz = /bits/ 64 <333333333>;
 445         };
 446 };