arch/arm64/boot/dts/renesas/r8a77990.dtsi

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Device Tree Source for the R-Car E3 (R8A77990) SoC
   4  *
   5  * Copyright (C) 2018 Renesas Electronics Corp.
   6  */
   7
   8 #include <dt-bindings/clock/r8a77990-cpg-mssr.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/power/r8a77990-sysc.h>
  11
  12 / {
  13         compatible = "renesas,r8a77990";
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16
  17         cpus {
  18                 #address-cells = <1>;
  19                 #size-cells = <0>;
  20
  21                 a53_0: cpu@0 {
  22                         compatible = "arm,cortex-a53", "arm,armv8";
  23                         reg = <0>;
  24                         device_type = "cpu";
  25                         power-domains = <&sysc R8A77990_PD_CA53_CPU0>;
  26                         next-level-cache = <&L2_CA53>;
  27                         enable-method = "psci";
  28                 };
  29
  30                 a53_1: cpu@1 {
  31                         compatible = "arm,cortex-a53", "arm,armv8";
  32                         reg = <1>;
  33                         device_type = "cpu";
  34                         power-domains = <&sysc R8A77990_PD_CA53_CPU1>;
  35                         next-level-cache = <&L2_CA53>;
  36                         enable-method = "psci";
  37                 };
  38
  39                 L2_CA53: cache-controller-0 {
  40                         compatible = "cache";
  41                         power-domains = <&sysc R8A77990_PD_CA53_SCU>;
  42                         cache-unified;
  43                         cache-level = <2>;
  44                 };
  45         };
  46
  47         extal_clk: extal {
  48                 compatible = "fixed-clock";
  49                 #clock-cells = <0>;
  50                 /* This value must be overridden by the board */
  51                 clock-frequency = <0>;
  52         };
  53
  54         pmu_a53 {
  55                 compatible = "arm,cortex-a53-pmu";
  56                 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
  57                                       <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
  58                 interrupt-affinity = <&a53_0>, <&a53_1>;
  59         };
  60
  61         psci {
  62                 compatible = "arm,psci-1.0", "arm,psci-0.2";
  63                 method = "smc";
  64         };
  65
  66         /* External SCIF clock - to be overridden by boards that provide it */
  67         scif_clk: scif {
  68                 compatible = "fixed-clock";
  69                 #clock-cells = <0>;
  70                 clock-frequency = <0>;
  71         };
  72
  73         soc: soc {
  74                 compatible = "simple-bus";
  75                 interrupt-parent = <&gic>;
  76                 #address-cells = <2>;
  77                 #size-cells = <2>;
  78                 ranges;
  79
  80                 rwdt: watchdog@e6020000 {
  81                         compatible = "renesas,r8a77990-wdt",
  82                                      "renesas,rcar-gen3-wdt";
  83                         reg = <0 0xe6020000 0 0x0c>;
  84                         clocks = <&cpg CPG_MOD 402>;
  85                         power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
  86                         resets = <&cpg 402>;
  87                         status = "disabled";
  88                 };
  89
  90                 gpio0: gpio@e6050000 {
  91                         compatible = "renesas,gpio-r8a77990",
  92                                      "renesas,rcar-gen3-gpio";
  93                         reg = <0 0xe6050000 0 0x50>;
  94                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
  95                         #gpio-cells = <2>;
  96                         gpio-controller;
  97                         gpio-ranges = <&pfc 0 0 18>;
  98                         #interrupt-cells = <2>;
  99                         interrupt-controller;
 100                         clocks = <&cpg CPG_MOD 912>;
 101                         power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
 102                         resets = <&cpg 912>;
 103                 };
 104
 105                 gpio1: gpio@e6051000 {
 106                         compatible = "renesas,gpio-r8a77990",
 107                                      "renesas,rcar-gen3-gpio";
 108                         reg = <0 0xe6051000 0 0x50>;
 109                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 110                         #gpio-cells = <2>;
 111                         gpio-controller;
 112                         gpio-ranges = <&pfc 0 32 23>;
 113                         #interrupt-cells = <2>;
 114                         interrupt-controller;
 115                         clocks = <&cpg CPG_MOD 911>;
 116                         power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
 117                         resets = <&cpg 911>;
 118                 };
 119
 120                 gpio2: gpio@e6052000 {
 121                         compatible = "renesas,gpio-r8a77990",
 122                                      "renesas,rcar-gen3-gpio";
 123                         reg = <0 0xe6052000 0 0x50>;
 124                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 125                         #gpio-cells = <2>;
 126                         gpio-controller;
 127                         gpio-ranges = <&pfc 0 64 26>;
 128                         #interrupt-cells = <2>;
 129                         interrupt-controller;
 130                         clocks = <&cpg CPG_MOD 910>;
 131                         power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
 132                         resets = <&cpg 910>;
 133                 };
 134
 135                 gpio3: gpio@e6053000 {
 136                         compatible = "renesas,gpio-r8a77990",
 137                                      "renesas,rcar-gen3-gpio";
 138                         reg = <0 0xe6053000 0 0x50>;
 139                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 140                         #gpio-cells = <2>;
 141                         gpio-controller;
 142                         gpio-ranges = <&pfc 0 96 16>;
 143                         #interrupt-cells = <2>;
 144                         interrupt-controller;
 145                         clocks = <&cpg CPG_MOD 909>;
 146                         power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
 147                         resets = <&cpg 909>;
 148                 };
 149
 150                 gpio4: gpio@e6054000 {
 151                         compatible = "renesas,gpio-r8a77990",
 152                                      "renesas,rcar-gen3-gpio";
 153                         reg = <0 0xe6054000 0 0x50>;
 154                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 155                         #gpio-cells = <2>;
 156                         gpio-controller;
 157                         gpio-ranges = <&pfc 0 128 11>;
 158                         #interrupt-cells = <2>;
 159                         interrupt-controller;
 160                         clocks = <&cpg CPG_MOD 908>;
 161                         power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
 162                         resets = <&cpg 908>;
 163                 };
 164
 165                 gpio5: gpio@e6055000 {
 166                         compatible = "renesas,gpio-r8a77990",
 167                                      "renesas,rcar-gen3-gpio";
 168                         reg = <0 0xe6055000 0 0x50>;
 169                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 170                         #gpio-cells = <2>;
 171                         gpio-controller;
 172                         gpio-ranges = <&pfc 0 160 20>;
 173                         #interrupt-cells = <2>;
 174                         interrupt-controller;
 175                         clocks = <&cpg CPG_MOD 907>;
 176                         power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
 177                         resets = <&cpg 907>;
 178                 };
 179
 180                 gpio6: gpio@e6055400 {
 181                         compatible = "renesas,gpio-r8a77990",
 182                                      "renesas,rcar-gen3-gpio";
 183                         reg = <0 0xe6055400 0 0x50>;
 184                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 185                         #gpio-cells = <2>;
 186                         gpio-controller;
 187                         gpio-ranges = <&pfc 0 192 18>;
 188                         #interrupt-cells = <2>;
 189                         interrupt-controller;
 190                         clocks = <&cpg CPG_MOD 906>;
 191                         power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
 192                         resets = <&cpg 906>;
 193                 };
 194
 195                 pfc: pin-controller@e6060000 {
 196                         compatible = "renesas,pfc-r8a77990";
 197                         reg = <0 0xe6060000 0 0x508>;
 198                 };
 199
 200                 cpg: clock-controller@e6150000 {
 201                         compatible = "renesas,r8a77990-cpg-mssr";
 202                         reg = <0 0xe6150000 0 0x1000>;
 203                         clocks = <&extal_clk>;
 204                         clock-names = "extal";
 205                         #clock-cells = <2>;
 206                         #power-domain-cells = <0>;
 207                         #reset-cells = <1>;
 208                 };
 209
 210                 rst: reset-controller@e6160000 {
 211                         compatible = "renesas,r8a77990-rst";
 212                         reg = <0 0xe6160000 0 0x0200>;
 213                 };
 214
 215                 sysc: system-controller@e6180000 {
 216                         compatible = "renesas,r8a77990-sysc";
 217                         reg = <0 0xe6180000 0 0x0400>;
 218                         #power-domain-cells = <1>;
 219                 };
 220
 221                 ipmmu_ds0: mmu@e6740000 {
 222                         compatible = "renesas,ipmmu-r8a77990";
 223                         reg = <0 0xe6740000 0 0x1000>;
 224                         renesas,ipmmu-main = <&ipmmu_mm 0>;
 225                         power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
 226                         #iommu-cells = <1>;
 227                 };
 228
 229                 ipmmu_ds1: mmu@e7740000 {
 230                         compatible = "renesas,ipmmu-r8a77990";
 231                         reg = <0 0xe7740000 0 0x1000>;
 232                         renesas,ipmmu-main = <&ipmmu_mm 1>;
 233                         power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
 234                         #iommu-cells = <1>;
 235                 };
 236
 237                 ipmmu_hc: mmu@e6570000 {
 238                         compatible = "renesas,ipmmu-r8a77990";
 239                         reg = <0 0xe6570000 0 0x1000>;
 240                         renesas,ipmmu-main = <&ipmmu_mm 2>;
 241                         power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
 242                         #iommu-cells = <1>;
 243                 };
 244
 245                 ipmmu_mm: mmu@e67b0000 {
 246                         compatible = "renesas,ipmmu-r8a77990";
 247                         reg = <0 0xe67b0000 0 0x1000>;
 248                         interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
 249                                      <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
 250                         power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
 251                         #iommu-cells = <1>;
 252                 };
 253
 254                 ipmmu_mp: mmu@ec670000 {
 255                         compatible = "renesas,ipmmu-r8a77990";
 256                         reg = <0 0xec670000 0 0x1000>;
 257                         renesas,ipmmu-main = <&ipmmu_mm 4>;
 258                         power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
 259                         #iommu-cells = <1>;
 260                 };
 261
 262                 ipmmu_pv0: mmu@fd800000 {
 263                         compatible = "renesas,ipmmu-r8a77990";
 264                         reg = <0 0xfd800000 0 0x1000>;
 265                         renesas,ipmmu-main = <&ipmmu_mm 6>;
 266                         power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
 267                         #iommu-cells = <1>;
 268                 };
 269
 270                 ipmmu_rt: mmu@ffc80000 {
 271                         compatible = "renesas,ipmmu-r8a77990";
 272                         reg = <0 0xffc80000 0 0x1000>;
 273                         renesas,ipmmu-main = <&ipmmu_mm 10>;
 274                         power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
 275                         #iommu-cells = <1>;
 276                 };
 277
 278                 ipmmu_vc0: mmu@fe6b0000 {
 279                         compatible = "renesas,ipmmu-r8a77990";
 280                         reg = <0 0xfe6b0000 0 0x1000>;
 281                         renesas,ipmmu-main = <&ipmmu_mm 12>;
 282                         power-domains = <&sysc R8A77990_PD_A3VC>;
 283                         #iommu-cells = <1>;
 284                 };
 285
 286                 ipmmu_vi0: mmu@febd0000 {
 287                         compatible = "renesas,ipmmu-r8a77990";
 288                         reg = <0 0xfebd0000 0 0x1000>;
 289                         renesas,ipmmu-main = <&ipmmu_mm 14>;
 290                         power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
 291                         #iommu-cells = <1>;
 292                 };
 293
 294                 ipmmu_vp0: mmu@fe990000 {
 295                         compatible = "renesas,ipmmu-r8a77990";
 296                         reg = <0 0xfe990000 0 0x1000>;
 297                         renesas,ipmmu-main = <&ipmmu_mm 16>;
 298                         power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
 299                         #iommu-cells = <1>;
 300                 };
 301
 302                 avb: ethernet@e6800000 {
 303                         compatible = "renesas,etheravb-r8a77990",
 304                                      "renesas,etheravb-rcar-gen3";
 305                         reg = <0 0xe6800000 0 0x800>;
 306                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
 307                                      <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 308                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 309                                      <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 310                                      <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
 311                                      <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
 312                                      <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
 313                                      <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
 314                                      <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
 315                                      <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
 316                                      <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 317                                      <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
 318                                      <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
 319                                      <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
 320                                      <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 321                                      <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 322                                      <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 323                                      <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
 324                                      <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
 325                                      <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
 326                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 327                                      <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 328                                      <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
 329                                      <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
 330                                      <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 331                         interrupt-names = "ch0", "ch1", "ch2", "ch3",
 332                                           "ch4", "ch5", "ch6", "ch7",
 333                                           "ch8", "ch9", "ch10", "ch11",
 334                                           "ch12", "ch13", "ch14", "ch15",
 335                                           "ch16", "ch17", "ch18", "ch19",
 336                                           "ch20", "ch21", "ch22", "ch23",
 337                                           "ch24";
 338                         clocks = <&cpg CPG_MOD 812>;
 339                         power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
 340                         resets = <&cpg 812>;
 341                         phy-mode = "rgmii";
 342                         #address-cells = <1>;
 343                         #size-cells = <0>;
 344                         status = "disabled";
 345                 };
 346
 347                 pwm0: pwm@e6e30000 {
 348                         compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
 349                         reg = <0 0xe6e30000 0 0x8>;
 350                         clocks = <&cpg CPG_MOD 523>;
 351                         power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
 352                         resets = <&cpg 523>;
 353                         #pwm-cells = <2>;
 354                         status = "disabled";
 355                 };
 356
 357                 pwm1: pwm@e6e31000 {
 358                         compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
 359                         reg = <0 0xe6e31000 0 0x8>;
 360                         clocks = <&cpg CPG_MOD 523>;
 361                         power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
 362                         resets = <&cpg 523>;
 363                         #pwm-cells = <2>;
 364                         status = "disabled";
 365                 };
 366
 367                 pwm2: pwm@e6e32000 {
 368                         compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
 369                         reg = <0 0xe6e32000 0 0x8>;
 370                         clocks = <&cpg CPG_MOD 523>;
 371                         power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
 372                         resets = <&cpg 523>;
 373                         #pwm-cells = <2>;
 374                         status = "disabled";
 375                 };
 376
 377                 pwm3: pwm@e6e33000 {
 378                         compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
 379                         reg = <0 0xe6e33000 0 0x8>;
 380                         clocks = <&cpg CPG_MOD 523>;
 381                         power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
 382                         resets = <&cpg 523>;
 383                         #pwm-cells = <2>;
 384                         status = "disabled";
 385                 };
 386
 387                 pwm4: pwm@e6e34000 {
 388                         compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
 389                         reg = <0 0xe6e34000 0 0x8>;
 390                         clocks = <&cpg CPG_MOD 523>;
 391                         power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
 392                         resets = <&cpg 523>;
 393                         #pwm-cells = <2>;
 394                         status = "disabled";
 395                 };
 396
 397                 pwm5: pwm@e6e35000 {
 398                         compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
 399                         reg = <0 0xe6e35000 0 0x8>;
 400                         clocks = <&cpg CPG_MOD 523>;
 401                         power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
 402                         resets = <&cpg 523>;
 403                         #pwm-cells = <2>;
 404                         status = "disabled";
 405                 };
 406
 407                 pwm6: pwm@e6e36000 {
 408                         compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
 409                         reg = <0 0xe6e36000 0 0x8>;
 410                         clocks = <&cpg CPG_MOD 523>;
 411                         power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
 412                         resets = <&cpg 523>;
 413                         #pwm-cells = <2>;
 414                         status = "disabled";
 415                 };
 416
 417                 scif2: serial@e6e88000 {
 418                         compatible = "renesas,scif-r8a77990",
 419                                      "renesas,rcar-gen3-scif", "renesas,scif";
 420                         reg = <0 0xe6e88000 0 64>;
 421                         interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
 422                         clocks = <&cpg CPG_MOD 310>,
 423                                  <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
 424                                  <&scif_clk>;
 425                         clock-names = "fck", "brg_int", "scif_clk";
 426
 427                         power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
 428                         resets = <&cpg 310>;
 429                         status = "disabled";
 430                 };
 431
 432                 xhci0: usb@ee000000 {
 433                         compatible = "renesas,xhci-r8a77990",
 434                                      "renesas,rcar-gen3-xhci";
 435                         reg = <0 0xee000000 0 0xc00>;
 436                         interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 437                         clocks = <&cpg CPG_MOD 328>;
 438                         power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
 439                         resets = <&cpg 328>;
 440                         status = "disabled";
 441                 };
 442
 443                 ohci0: usb@ee080000 {
 444                         compatible = "generic-ohci";
 445                         reg = <0 0xee080000 0 0x100>;
 446                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 447                         clocks = <&cpg CPG_MOD 703>;
 448                         phys = <&usb2_phy0>;
 449                         phy-names = "usb";
 450                         power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
 451                         resets = <&cpg 703>;
 452                         status = "disabled";
 453                 };
 454
 455                 ehci0: usb@ee080100 {
 456                         compatible = "generic-ehci";
 457                         reg = <0 0xee080100 0 0x100>;
 458                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 459                         clocks = <&cpg CPG_MOD 703>;
 460                         phys = <&usb2_phy0>;
 461                         phy-names = "usb";
 462                         companion = <&ohci0>;
 463                         power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
 464                         resets = <&cpg 703>;
 465                         status = "disabled";
 466                 };
 467
 468                 usb2_phy0: usb-phy@ee080200 {
 469                         compatible = "renesas,usb2-phy-r8a77990",
 470                                      "renesas,rcar-gen3-usb2-phy";
 471                         reg = <0 0xee080200 0 0x700>;
 472                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 473                         clocks = <&cpg CPG_MOD 703>;
 474                         power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
 475                         resets = <&cpg 703>;
 476                         #phy-cells = <0>;
 477                         status = "disabled";
 478                 };
 479
 480                 gic: interrupt-controller@f1010000 {
 481                         compatible = "arm,gic-400";
 482                         #interrupt-cells = <3>;
 483                         #address-cells = <0>;
 484                         interrupt-controller;
 485                         reg = <0x0 0xf1010000 0 0x1000>,
 486                               <0x0 0xf1020000 0 0x20000>,
 487                               <0x0 0xf1040000 0 0x20000>,
 488                               <0x0 0xf1060000 0 0x20000>;
 489                         interrupts = <GIC_PPI 9
 490                                         (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 491                         clocks = <&cpg CPG_MOD 408>;
 492                         clock-names = "clk";
 493                         power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
 494                         resets = <&cpg 408>;
 495                 };
 496
 497                 prr: chipid@fff00044 {
 498                         compatible = "renesas,prr";
 499                         reg = <0 0xfff00044 0 4>;
 500                 };
 501         };
 502
 503         timer {
 504                 compatible = "arm,armv8-timer";
 505                 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 506                                       <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 507                                       <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 508                                       <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
 509         };
 510 };