3 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
4 select ARCH_HAS_ELF_RANDOMIZE
5 select ARCH_HAS_GCOV_PROFILE_ALL
6 select ARCH_HAS_SG_CHAIN
7 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
8 select ARCH_USE_CMPXCHG_LOCKREF
9 select ARCH_SUPPORTS_ATOMIC_RMW
10 select ARCH_WANT_OPTIONAL_GPIOLIB
11 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
12 select ARCH_WANT_FRAME_POINTERS
16 select AUDIT_ARCH_COMPAT_GENERIC
17 select ARM_GIC_V2M if PCI_MSI
19 select ARM_GIC_V3_ITS if PCI_MSI
20 select BUILDTIME_EXTABLE_SORT
21 select CLONE_BACKWARDS
23 select CPU_PM if (SUSPEND || CPU_IDLE)
24 select DCACHE_WORD_ACCESS
25 select GENERIC_ALLOCATOR
26 select GENERIC_CLOCKEVENTS
27 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
28 select GENERIC_CPU_AUTOPROBE
29 select GENERIC_EARLY_IOREMAP
30 select GENERIC_IRQ_PROBE
31 select GENERIC_IRQ_SHOW
32 select GENERIC_PCI_IOMAP
33 select GENERIC_SCHED_CLOCK
34 select GENERIC_SMP_IDLE_THREAD
35 select GENERIC_STRNCPY_FROM_USER
36 select GENERIC_STRNLEN_USER
37 select GENERIC_TIME_VSYSCALL
38 select HANDLE_DOMAIN_IRQ
39 select HARDIRQS_SW_RESEND
40 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
41 select HAVE_ARCH_AUDITSYSCALL
42 select HAVE_ARCH_BITREVERSE
43 select HAVE_ARCH_JUMP_LABEL
45 select HAVE_ARCH_SECCOMP_FILTER
46 select HAVE_ARCH_TRACEHOOK
48 select HAVE_C_RECORDMCOUNT
49 select HAVE_CC_STACKPROTECTOR
50 select HAVE_CMPXCHG_DOUBLE
51 select HAVE_DEBUG_BUGVERBOSE
52 select HAVE_DEBUG_KMEMLEAK
53 select HAVE_DMA_API_DEBUG
55 select HAVE_DMA_CONTIGUOUS
56 select HAVE_DYNAMIC_FTRACE
57 select HAVE_EFFICIENT_UNALIGNED_ACCESS
58 select HAVE_FTRACE_MCOUNT_RECORD
59 select HAVE_FUNCTION_TRACER
60 select HAVE_FUNCTION_GRAPH_TRACER
61 select HAVE_GENERIC_DMA_COHERENT
62 select HAVE_HW_BREAKPOINT if PERF_EVENTS
64 select HAVE_PATA_PLATFORM
65 select HAVE_PERF_EVENTS
67 select HAVE_PERF_USER_STACK_DUMP
68 select HAVE_RCU_TABLE_FREE
69 select HAVE_SYSCALL_TRACEPOINTS
71 select MODULES_USE_ELF_RELA
74 select OF_EARLY_FLATTREE
75 select OF_RESERVED_MEM
76 select PERF_USE_VMALLOC
81 select SYSCTL_EXCEPTION_TRACE
82 select HAVE_CONTEXT_TRACKING
84 ARM 64-bit (AArch64) Linux support.
89 config ARCH_PHYS_ADDR_T_64BIT
98 config STACKTRACE_SUPPORT
101 config LOCKDEP_SUPPORT
104 config TRACE_IRQFLAGS_SUPPORT
107 config RWSEM_XCHGADD_ALGORITHM
110 config GENERIC_HWEIGHT
116 config GENERIC_CALIBRATE_DELAY
122 config HAVE_GENERIC_RCU_GUP
125 config ARCH_DMA_ADDR_T_64BIT
128 config NEED_DMA_MAP_STATE
131 config NEED_SG_DMA_LENGTH
140 config KERNEL_MODE_NEON
143 config FIX_EARLYCON_MEM
146 config PGTABLE_LEVELS
148 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
149 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
150 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
151 default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48
153 source "init/Kconfig"
155 source "kernel/Kconfig.freezer"
157 menu "Platform selection"
162 This enables support for Samsung Exynos SoC family
165 bool "ARMv8 based Samsung Exynos7"
167 select COMMON_CLK_SAMSUNG
168 select HAVE_S3C2410_WATCHDOG if WATCHDOG
169 select HAVE_S3C_RTC if RTC_CLASS
171 select PINCTRL_EXYNOS
174 This enables support for Samsung Exynos7 SoC family
176 config ARCH_FSL_LS2085A
177 bool "Freescale LS2085A SOC"
179 This enables support for Freescale LS2085A SOC.
182 bool "Mediatek MT65xx & MT81xx ARMv8 SoC"
186 Support for Mediatek MT65xx & MT81xx ARMv8 SoCs
189 bool "Qualcomm Platforms"
192 This enables support for the ARMv8 based Qualcomm chipsets.
195 bool "AMD Seattle SoC Family"
197 This enables support for AMD Seattle SOC Family
200 bool "NVIDIA Tegra SoC Family"
201 select ARCH_HAS_RESET_CONTROLLER
202 select ARCH_REQUIRE_GPIOLIB
206 select GENERIC_CLOCKEVENTS
209 select RESET_CONTROLLER
211 This enables support for the NVIDIA Tegra SoC family.
213 config ARCH_TEGRA_132_SOC
214 bool "NVIDIA Tegra132 SoC"
215 depends on ARCH_TEGRA
216 select PINCTRL_TEGRA124
217 select USB_ULPI if USB_PHY
218 select USB_ULPI_VIEWPORT if USB_PHY
220 Enable support for NVIDIA Tegra132 SoC, based on the Denver
221 ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC,
222 but contains an NVIDIA Denver CPU complex in place of
223 Tegra124's "4+1" Cortex-A15 CPU complex.
226 bool "Spreadtrum SoC platform"
228 Support for Spreadtrum ARM based SoCs
231 bool "Cavium Inc. Thunder SoC Family"
233 This enables support for Cavium's Thunder Family of SoCs.
236 bool "ARMv8 software model (Versatile Express)"
237 select ARCH_REQUIRE_GPIOLIB
238 select COMMON_CLK_VERSATILE
239 select POWER_RESET_VEXPRESS
240 select VEXPRESS_CONFIG
242 This enables support for the ARMv8 software model (Versatile
246 bool "AppliedMicro X-Gene SOC Family"
248 This enables support for AppliedMicro X-Gene SOC Family
251 bool "Xilinx ZynqMP Family"
253 This enables support for Xilinx ZynqMP Family
262 This feature enables support for PCI bus system. If you say Y
263 here, the kernel will include drivers and infrastructure code
264 to support PCI bus devices.
269 config PCI_DOMAINS_GENERIC
275 source "drivers/pci/Kconfig"
276 source "drivers/pci/pcie/Kconfig"
277 source "drivers/pci/hotplug/Kconfig"
281 menu "Kernel Features"
283 menu "ARM errata workarounds via the alternatives framework"
285 config ARM64_ERRATUM_826319
286 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
289 This option adds an alternative code sequence to work around ARM
290 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
291 AXI master interface and an L2 cache.
293 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
294 and is unable to accept a certain write via this interface, it will
295 not progress on read data presented on the read data channel and the
298 The workaround promotes data cache clean instructions to
299 data cache clean-and-invalidate.
300 Please note that this does not necessarily enable the workaround,
301 as it depends on the alternative framework, which will only patch
302 the kernel if an affected CPU is detected.
306 config ARM64_ERRATUM_827319
307 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
310 This option adds an alternative code sequence to work around ARM
311 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
312 master interface and an L2 cache.
314 Under certain conditions this erratum can cause a clean line eviction
315 to occur at the same time as another transaction to the same address
316 on the AMBA 5 CHI interface, which can cause data corruption if the
317 interconnect reorders the two transactions.
319 The workaround promotes data cache clean instructions to
320 data cache clean-and-invalidate.
321 Please note that this does not necessarily enable the workaround,
322 as it depends on the alternative framework, which will only patch
323 the kernel if an affected CPU is detected.
327 config ARM64_ERRATUM_824069
328 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
331 This option adds an alternative code sequence to work around ARM
332 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
333 to a coherent interconnect.
335 If a Cortex-A53 processor is executing a store or prefetch for
336 write instruction at the same time as a processor in another
337 cluster is executing a cache maintenance operation to the same
338 address, then this erratum might cause a clean cache line to be
339 incorrectly marked as dirty.
341 The workaround promotes data cache clean instructions to
342 data cache clean-and-invalidate.
343 Please note that this option does not necessarily enable the
344 workaround, as it depends on the alternative framework, which will
345 only patch the kernel if an affected CPU is detected.
349 config ARM64_ERRATUM_819472
350 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
353 This option adds an alternative code sequence to work around ARM
354 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
355 present when it is connected to a coherent interconnect.
357 If the processor is executing a load and store exclusive sequence at
358 the same time as a processor in another cluster is executing a cache
359 maintenance operation to the same address, then this erratum might
360 cause data corruption.
362 The workaround promotes data cache clean instructions to
363 data cache clean-and-invalidate.
364 Please note that this does not necessarily enable the workaround,
365 as it depends on the alternative framework, which will only patch
366 the kernel if an affected CPU is detected.
370 config ARM64_ERRATUM_832075
371 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
374 This option adds an alternative code sequence to work around ARM
375 erratum 832075 on Cortex-A57 parts up to r1p2.
377 Affected Cortex-A57 parts might deadlock when exclusive load/store
378 instructions to Write-Back memory are mixed with Device loads.
380 The workaround is to promote device loads to use Load-Acquire
382 Please note that this does not necessarily enable the workaround,
383 as it depends on the alternative framework, which will only patch
384 the kernel if an affected CPU is detected.
388 config ARM64_ERRATUM_845719
389 bool "Cortex-A53: 845719: a load might read incorrect data"
393 This option adds an alternative code sequence to work around ARM
394 erratum 845719 on Cortex-A53 parts up to r0p4.
396 When running a compat (AArch32) userspace on an affected Cortex-A53
397 part, a load at EL0 from a virtual address that matches the bottom 32
398 bits of the virtual address used by a recent load at (AArch64) EL1
399 might return incorrect data.
401 The workaround is to write the contextidr_el1 register on exception
402 return to a 32-bit task.
403 Please note that this does not necessarily enable the workaround,
404 as it depends on the alternative framework, which will only patch
405 the kernel if an affected CPU is detected.
414 default ARM64_4K_PAGES
416 Page size (translation granule) configuration.
418 config ARM64_4K_PAGES
421 This feature enables 4KB pages support.
423 config ARM64_64K_PAGES
426 This feature enables 64KB pages support (4KB by default)
427 allowing only two levels of page tables and faster TLB
428 look-up. AArch32 emulation is not available when this feature
434 prompt "Virtual address space size"
435 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
436 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
438 Allows choosing one of multiple possible virtual address
439 space sizes. The level of translation table is determined by
440 a combination of page size and virtual address space size.
442 config ARM64_VA_BITS_39
444 depends on ARM64_4K_PAGES
446 config ARM64_VA_BITS_42
448 depends on ARM64_64K_PAGES
450 config ARM64_VA_BITS_48
457 default 39 if ARM64_VA_BITS_39
458 default 42 if ARM64_VA_BITS_42
459 default 48 if ARM64_VA_BITS_48
461 config CPU_BIG_ENDIAN
462 bool "Build big-endian kernel"
464 Say Y if you plan on running a kernel in big-endian mode.
467 bool "Symmetric Multi-Processing"
469 This enables support for systems with more than one CPU. If
470 you say N here, the kernel will run on single and
471 multiprocessor machines, but will use only one CPU of a
472 multiprocessor machine. If you say Y here, the kernel will run
473 on many, but not all, single processor machines. On a single
474 processor machine, the kernel will run faster if you say N
477 If you don't know what to do here, say N.
480 bool "Multi-core scheduler support"
483 Multi-core scheduler support improves the CPU scheduler's decision
484 making when dealing with multi-core CPU chips at a cost of slightly
485 increased overhead in some places. If unsure say N here.
488 bool "SMT scheduler support"
491 Improves the CPU scheduler's decision making when dealing with
492 MultiThreading at a cost of slightly increased overhead in some
493 places. If unsure say N here.
496 int "Maximum number of CPUs (2-4096)"
499 # These have to remain sorted largest to smallest
503 bool "Support for hot-pluggable CPUs"
506 Say Y here to experiment with turning CPUs off and on. CPUs
507 can be controlled through /sys/devices/system/cpu.
509 source kernel/Kconfig.preempt
519 config ARCH_HAS_HOLES_MEMORYMODEL
520 def_bool y if SPARSEMEM
522 config ARCH_SPARSEMEM_ENABLE
524 select SPARSEMEM_VMEMMAP_ENABLE
526 config ARCH_SPARSEMEM_DEFAULT
527 def_bool ARCH_SPARSEMEM_ENABLE
529 config ARCH_SELECT_MEMORY_MODEL
530 def_bool ARCH_SPARSEMEM_ENABLE
532 config HAVE_ARCH_PFN_VALID
533 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
535 config HW_PERF_EVENTS
536 bool "Enable hardware performance counter support for perf events"
537 depends on PERF_EVENTS
540 Enable hardware performance counter support for perf events. If
541 disabled, perf events will use software events only.
543 config SYS_SUPPORTS_HUGETLBFS
546 config ARCH_WANT_GENERAL_HUGETLB
549 config ARCH_WANT_HUGE_PMD_SHARE
550 def_bool y if !ARM64_64K_PAGES
552 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
555 config ARCH_HAS_CACHE_LINE_SIZE
561 bool "Enable seccomp to safely compute untrusted bytecode"
563 This kernel feature is useful for number crunching applications
564 that may need to compute untrusted bytecode during their
565 execution. By using pipes or other transports made available to
566 the process as file descriptors supporting the read/write
567 syscalls, it's possible to isolate those applications in
568 their own address space using seccomp. Once seccomp is
569 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
570 and the task is only allowed to execute a few safe syscalls
571 defined by each seccomp mode.
578 bool "Xen guest support on ARM64"
579 depends on ARM64 && OF
582 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
584 config FORCE_MAX_ZONEORDER
586 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
589 menuconfig ARMV8_DEPRECATED
590 bool "Emulate deprecated/obsolete ARMv8 instructions"
593 Legacy software support may require certain instructions
594 that have been deprecated or obsoleted in the architecture.
596 Enable this config to enable selective emulation of these
604 bool "Emulate SWP/SWPB instructions"
606 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
607 they are always undefined. Say Y here to enable software
608 emulation of these instructions for userspace using LDXR/STXR.
610 In some older versions of glibc [<=2.8] SWP is used during futex
611 trylock() operations with the assumption that the code will not
612 be preempted. This invalid assumption may be more likely to fail
613 with SWP emulation enabled, leading to deadlock of the user
616 NOTE: when accessing uncached shared regions, LDXR/STXR rely
617 on an external transaction monitoring block called a global
618 monitor to maintain update atomicity. If your system does not
619 implement a global monitor, this option can cause programs that
620 perform SWP operations to uncached memory to deadlock.
624 config CP15_BARRIER_EMULATION
625 bool "Emulate CP15 Barrier instructions"
627 The CP15 barrier instructions - CP15ISB, CP15DSB, and
628 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
629 strongly recommended to use the ISB, DSB, and DMB
630 instructions instead.
632 Say Y here to enable software emulation of these
633 instructions for AArch32 userspace code. When this option is
634 enabled, CP15 barrier usage is traced which can help
635 identify software that needs updating.
639 config SETEND_EMULATION
640 bool "Emulate SETEND instruction"
642 The SETEND instruction alters the data-endianness of the
643 AArch32 EL0, and is deprecated in ARMv8.
645 Say Y here to enable software emulation of the instruction
646 for AArch32 userspace code.
648 Note: All the cpus on the system must have mixed endian support at EL0
649 for this feature to be enabled. If a new CPU - which doesn't support mixed
650 endian - is hotplugged in after this feature has been enabled, there could
651 be unexpected results in the applications.
661 string "Default kernel command string"
664 Provide a set of default command-line options at build time by
665 entering them here. As a minimum, you should specify the the
666 root device (e.g. root=/dev/nfs).
669 bool "Always use the default kernel command string"
671 Always use the default kernel command string, even if the boot
672 loader passes other arguments to the kernel.
673 This is useful if you cannot or don't want to change the
674 command-line options your boot loader passes to the kernel.
680 bool "UEFI runtime support"
681 depends on OF && !CPU_BIG_ENDIAN
684 select EFI_PARAMS_FROM_FDT
685 select EFI_RUNTIME_WRAPPERS
690 This option provides support for runtime services provided
691 by UEFI firmware (such as non-volatile variables, realtime
692 clock, and platform reset). A UEFI stub is also provided to
693 allow the kernel to be booted as an EFI application. This
694 is only useful on systems that have UEFI firmware.
697 bool "Enable support for SMBIOS (DMI) tables"
701 This enables SMBIOS/DMI feature for systems.
703 This option is only useful on systems that have UEFI firmware.
704 However, even with this option, the resultant kernel should
705 continue to boot on existing non-UEFI platforms.
709 menu "Userspace binary formats"
711 source "fs/Kconfig.binfmt"
714 bool "Kernel support for 32-bit EL0"
715 depends on !ARM64_64K_PAGES || EXPERT
716 select COMPAT_BINFMT_ELF
718 select OLD_SIGSUSPEND3
719 select COMPAT_OLD_SIGACTION
721 This option enables support for a 32-bit EL0 running under a 64-bit
722 kernel at EL1. AArch32-specific components such as system calls,
723 the user helper functions, VFP support and the ptrace interface are
724 handled appropriately by the kernel.
726 If you also enabled CONFIG_ARM64_64K_PAGES, please be aware that you
727 will only be able to execute AArch32 binaries that were compiled with
728 64k aligned segments.
730 If you want to execute 32-bit userspace applications, say Y.
732 config SYSVIPC_COMPAT
734 depends on COMPAT && SYSVIPC
738 menu "Power management options"
740 source "kernel/power/Kconfig"
742 config ARCH_SUSPEND_POSSIBLE
747 menu "CPU Power Management"
749 source "drivers/cpuidle/Kconfig"
751 source "drivers/cpufreq/Kconfig"
757 source "drivers/Kconfig"
759 source "drivers/firmware/Kconfig"
763 source "arch/arm64/kvm/Kconfig"
765 source "arch/arm64/Kconfig.debug"
767 source "security/Kconfig"
769 source "crypto/Kconfig"
771 source "arch/arm64/crypto/Kconfig"