2 * arch/arm/plat-omap/include/mach/mux.h
4 * Table of the Omap register configurations for the FUNC_MUX and
5 * PULL_DWN combinations.
7 * Copyright (C) 2004 - 2008 Texas Instruments Inc.
8 * Copyright (C) 2003 - 2008 Nokia Corporation
10 * Written by Tony Lindgren
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 * NOTE: Please use the following naming style for new pin entries.
27 * For example, W8_1610_MMC2_DAT0, where:
29 * - 1610 = 1510 or 1610, none if common for both 1510 and 1610
30 * - MMC2_DAT0 = function
33 #ifndef __ASM_ARCH_MUX_H
34 #define __ASM_ARCH_MUX_H
36 #define PU_PD_SEL_NA 0 /* No pu_pd reg available */
37 #define PULL_DWN_CTRL_NA 0 /* No pull-down control needed */
39 #ifdef CONFIG_OMAP_MUX_DEBUG
40 #define MUX_REG(reg, mode_offset, mode) .mux_reg_name = "FUNC_MUX_CTRL_"#reg, \
41 .mux_reg = FUNC_MUX_CTRL_##reg, \
42 .mask_offset = mode_offset, \
45 #define PULL_REG(reg, bit, status) .pull_name = "PULL_DWN_CTRL_"#reg, \
46 .pull_reg = PULL_DWN_CTRL_##reg, \
50 #define PU_PD_REG(reg, status) .pu_pd_name = "PU_PD_SEL_"#reg, \
51 .pu_pd_reg = PU_PD_SEL_##reg, \
54 #define MUX_REG_7XX(reg, mode_offset, mode) .mux_reg_name = "OMAP7XX_IO_CONF_"#reg, \
55 .mux_reg = OMAP7XX_IO_CONF_##reg, \
56 .mask_offset = mode_offset, \
59 #define PULL_REG_7XX(reg, bit, status) .pull_name = "OMAP7XX_IO_CONF_"#reg, \
60 .pull_reg = OMAP7XX_IO_CONF_##reg, \
66 #define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \
67 .mask_offset = mode_offset, \
70 #define PULL_REG(reg, bit, status) .pull_reg = PULL_DWN_CTRL_##reg, \
74 #define PU_PD_REG(reg, status) .pu_pd_reg = PU_PD_SEL_##reg, \
77 #define MUX_REG_7XX(reg, mode_offset, mode) \
78 .mux_reg = OMAP7XX_IO_CONF_##reg, \
79 .mask_offset = mode_offset, \
82 #define PULL_REG_7XX(reg, bit, status) .pull_reg = OMAP7XX_IO_CONF_##reg, \
86 #endif /* CONFIG_OMAP_MUX_DEBUG */
88 #define MUX_CFG(desc, mux_reg, mode_offset, mode, \
89 pull_reg, pull_bit, pull_status, \
90 pu_pd_reg, pu_pd_status, debug_status) \
93 .debug = debug_status, \
94 MUX_REG(mux_reg, mode_offset, mode) \
95 PULL_REG(pull_reg, pull_bit, pull_status) \
96 PU_PD_REG(pu_pd_reg, pu_pd_status) \
101 * OMAP730/850 has a slightly different config for the pin mux.
102 * - config regs are the OMAP7XX_IO_CONF_x regs (see omap730.h) regs and
103 * not the FUNC_MUX_CTRL_x regs from hardware.h
104 * - for pull-up/down, only has one enable bit which is is in the same register
107 #define MUX_CFG_7XX(desc, mux_reg, mode_offset, mode, \
108 pull_bit, pull_status, debug_status)\
111 .debug = debug_status, \
112 MUX_REG_7XX(mux_reg, mode_offset, mode) \
113 PULL_REG_7XX(mux_reg, pull_bit, pull_status) \
117 #define MUX_CFG_24XX(desc, reg_offset, mode, \
118 pull_en, pull_mode, dbg) \
122 .mux_reg = reg_offset, \
124 .pull_val = pull_en, \
125 .pu_pd_val = pull_mode, \
128 /* 24xx/34xx mux bit defines */
129 #define OMAP2_PULL_ENA (1 << 3)
130 #define OMAP2_PULL_UP (1 << 4)
131 #define OMAP2_ALTELECTRICALSEL (1 << 5)
133 /* 34xx specific mux bit defines */
134 #define OMAP3_INPUT_EN (1 << 8)
135 #define OMAP3_OFF_EN (1 << 9)
136 #define OMAP3_OFFOUT_EN (1 << 10)
137 #define OMAP3_OFFOUT_VAL (1 << 11)
138 #define OMAP3_OFF_PULL_EN (1 << 12)
139 #define OMAP3_OFF_PULL_UP (1 << 13)
140 #define OMAP3_WAKEUP_EN (1 << 14)
142 /* 34xx mux mode options for each pin. See TRM for options */
143 #define OMAP34XX_MUX_MODE0 0
144 #define OMAP34XX_MUX_MODE1 1
145 #define OMAP34XX_MUX_MODE2 2
146 #define OMAP34XX_MUX_MODE3 3
147 #define OMAP34XX_MUX_MODE4 4
148 #define OMAP34XX_MUX_MODE5 5
149 #define OMAP34XX_MUX_MODE6 6
150 #define OMAP34XX_MUX_MODE7 7
152 /* 34xx active pin states */
153 #define OMAP34XX_PIN_OUTPUT 0
154 #define OMAP34XX_PIN_INPUT OMAP3_INPUT_EN
155 #define OMAP34XX_PIN_INPUT_PULLUP (OMAP2_PULL_ENA | OMAP3_INPUT_EN \
157 #define OMAP34XX_PIN_INPUT_PULLDOWN (OMAP2_PULL_ENA | OMAP3_INPUT_EN)
159 /* 34xx off mode states */
160 #define OMAP34XX_PIN_OFF_NONE 0
161 #define OMAP34XX_PIN_OFF_OUTPUT_HIGH (OMAP3_OFF_EN | OMAP3_OFFOUT_EN \
163 #define OMAP34XX_PIN_OFF_OUTPUT_LOW (OMAP3_OFF_EN | OMAP3_OFFOUT_EN)
164 #define OMAP34XX_PIN_OFF_INPUT_PULLUP (OMAP3_OFF_EN | OMAP3_OFF_PULL_EN \
166 #define OMAP34XX_PIN_OFF_INPUT_PULLDOWN (OMAP3_OFF_EN | OMAP3_OFF_PULL_EN)
167 #define OMAP34XX_PIN_OFF_WAKEUPENABLE OMAP3_WAKEUP_EN
169 #define MUX_CFG_34XX(desc, reg_offset, mux_value) { \
172 .mux_reg = reg_offset, \
173 .mux_val = mux_value \
178 const unsigned int mux_reg;
181 #if defined(CONFIG_ARCH_OMAP34XX)
182 u16 mux_val; /* Wake-up, off mode, pull, mux mode */
185 #if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP24XX)
186 const unsigned char mask_offset;
187 const unsigned char mask;
189 const char *pull_name;
190 const unsigned int pull_reg;
191 const unsigned char pull_val;
192 const unsigned char pull_bit;
194 const char *pu_pd_name;
195 const unsigned int pu_pd_reg;
196 const unsigned char pu_pd_val;
199 #if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
200 const char *mux_reg_name;
206 /* OMAP 730 keyboard */
229 enum omap1xxx_index {
230 /* UART1 (BT_UART_GATING)*/
234 /* UART2 (COM_UART_GATING)*/
240 /* UART3 (GIGA_UART_GATING) */
246 UART3_BCLK, /* 12MHz clock out */
253 /* USB master generic */
336 V5_1610_MMC2_DATDIR0,
337 W19_1610_MMC2_DATDIR1,
340 /* OMAP-1610 External Trace Interface */
363 /* OMAP-1610 uWire */
382 /* OMAP-1610 Flash */
383 L3_1610_FLASH_CS2B_OE,
384 M8_1610_FLASH_CS2B_WE,
394 /* OMAP-1710 MMC CMDDIR and DATDIR0 */
397 P20_1710_MMC_DATDIR0,
399 /* OMAP-1610 USB0 alternate pin configuration */
442 /* Power management */
451 /* CompactFlash controller */
458 /* parallel camera */
482 enum omap24xx_index {
489 /* 24xx Menelaus interrupt */
495 /* 24xx GPMC chipselects, wait pin monitoring */
504 Y15_24XX_MCBSP2_CLKX,
542 /* 24xx external DMA requests */
561 F19_24XX_MMC_DAT_DIR0,
562 E20_24XX_MMC_DAT_DIR1,
563 F18_24XX_MMC_DAT_DIR2,
564 E18_24XX_MMC_DAT_DIR3,
565 G18_24XX_MMC_CMD_DIR,
590 AA4_24XX_USB2_TLLSE0,
607 /* 24xx Menelaus Keypad GPIO */
626 AD9_2430_USB0HS_DATA3,
627 Y11_2430_USB0HS_DATA4,
628 AD7_2430_USB0HS_DATA5,
629 AE7_2430_USB0HS_DATA6,
630 AD4_2430_USB0HS_DATA2,
631 AF9_2430_USB0HS_DATA0,
632 AE6_2430_USB0HS_DATA1,
637 AC7_2430_USB0HS_DATA7,
642 AB2_2430_MCBSP1_CLKR,
649 AC10_2430_MCBSP2_FSX,
650 AD16_2430_MCBSP2_CLX,
653 AC10_2430_MCBSP2_FSX_OFF,
654 AD16_2430_MCBSP2_CLX_OFF,
655 AE13_2430_MCBSP2_DX_OFF,
656 AD13_2430_MCBSP2_DR_OFF,
658 AC9_2430_MCBSP3_CLKX,
666 AC25_2430_MCBSP4_FSX,
668 AE16_2430_MCBSP5_CLKX,
669 AF12_2430_MCBSP5_FSX,
675 AD15_2430_MCSPI1_SIMO,
676 AE17_2430_MCSPI1_SOMI,
679 /* Touchscreen GPIO */
684 enum omap34xx_index {
695 /* PHY - HSUSB: 12-pin ULPI PHY: Port 1*/
696 Y8_3430_USB1HS_PHY_CLK,
697 Y9_3430_USB1HS_PHY_STP,
698 AA14_3430_USB1HS_PHY_DIR,
699 AA11_3430_USB1HS_PHY_NXT,
700 W13_3430_USB1HS_PHY_DATA0,
701 W12_3430_USB1HS_PHY_DATA1,
702 W11_3430_USB1HS_PHY_DATA2,
703 Y11_3430_USB1HS_PHY_DATA3,
704 W9_3430_USB1HS_PHY_DATA4,
705 Y12_3430_USB1HS_PHY_DATA5,
706 W8_3430_USB1HS_PHY_DATA6,
707 Y13_3430_USB1HS_PHY_DATA7,
709 /* PHY - HSUSB: 12-pin ULPI PHY: Port 2*/
710 AA8_3430_USB2HS_PHY_CLK,
711 AA10_3430_USB2HS_PHY_STP,
712 AA9_3430_USB2HS_PHY_DIR,
713 AB11_3430_USB2HS_PHY_NXT,
714 AB10_3430_USB2HS_PHY_DATA0,
715 AB9_3430_USB2HS_PHY_DATA1,
716 W3_3430_USB2HS_PHY_DATA2,
717 T4_3430_USB2HS_PHY_DATA3,
718 T3_3430_USB2HS_PHY_DATA4,
719 R3_3430_USB2HS_PHY_DATA5,
720 R4_3430_USB2HS_PHY_DATA6,
721 T2_3430_USB2HS_PHY_DATA7,
724 /* TLL - HSUSB: 12-pin TLL Port 1*/
725 Y8_3430_USB1HS_TLL_CLK,
726 Y9_3430_USB1HS_TLL_STP,
727 AA14_3430_USB1HS_TLL_DIR,
728 AA11_3430_USB1HS_TLL_NXT,
729 W13_3430_USB1HS_TLL_DATA0,
730 W12_3430_USB1HS_TLL_DATA1,
731 W11_3430_USB1HS_TLL_DATA2,
732 Y11_3430_USB1HS_TLL_DATA3,
733 W9_3430_USB1HS_TLL_DATA4,
734 Y12_3430_USB1HS_TLL_DATA5,
735 W8_3430_USB1HS_TLL_DATA6,
736 Y13_3430_USB1HS_TLL_DATA7,
738 /* TLL - HSUSB: 12-pin TLL Port 2*/
739 AA8_3430_USB2HS_TLL_CLK,
740 AA10_3430_USB2HS_TLL_STP,
741 AA9_3430_USB2HS_TLL_DIR,
742 AB11_3430_USB2HS_TLL_NXT,
743 AB10_3430_USB2HS_TLL_DATA0,
744 AB9_3430_USB2HS_TLL_DATA1,
745 W3_3430_USB2HS_TLL_DATA2,
746 T4_3430_USB2HS_TLL_DATA3,
747 T3_3430_USB2HS_TLL_DATA4,
748 R3_3430_USB2HS_TLL_DATA5,
749 R4_3430_USB2HS_TLL_DATA6,
750 T2_3430_USB2HS_TLL_DATA7,
752 /* TLL - HSUSB: 12-pin TLL Port 3*/
753 AA6_3430_USB3HS_TLL_CLK,
754 AB3_3430_USB3HS_TLL_STP,
755 AA3_3430_USB3HS_TLL_DIR,
756 Y3_3430_USB3HS_TLL_NXT,
757 AA5_3430_USB3HS_TLL_DATA0,
758 Y4_3430_USB3HS_TLL_DATA1,
759 Y5_3430_USB3HS_TLL_DATA2,
760 W5_3430_USB3HS_TLL_DATA3,
761 AB12_3430_USB3HS_TLL_DATA4,
762 AB13_3430_USB3HS_TLL_DATA5,
763 AA13_3430_USB3HS_TLL_DATA6,
764 AA12_3430_USB3HS_TLL_DATA7,
766 /* PHY FSUSB: FS Serial for Port 1 (multiple PHY modes supported) */
767 AF10_3430_USB1FS_PHY_MM1_RXDP,
768 AG9_3430_USB1FS_PHY_MM1_RXDM,
769 W13_3430_USB1FS_PHY_MM1_RXRCV,
770 W12_3430_USB1FS_PHY_MM1_TXSE0,
771 W11_3430_USB1FS_PHY_MM1_TXDAT,
772 Y11_3430_USB1FS_PHY_MM1_TXEN_N,
774 /* PHY FSUSB: FS Serial for Port 2 (multiple PHY modes supported) */
775 AF7_3430_USB2FS_PHY_MM2_RXDP,
776 AH7_3430_USB2FS_PHY_MM2_RXDM,
777 AB10_3430_USB2FS_PHY_MM2_RXRCV,
778 AB9_3430_USB2FS_PHY_MM2_TXSE0,
779 W3_3430_USB2FS_PHY_MM2_TXDAT,
780 T4_3430_USB2FS_PHY_MM2_TXEN_N,
782 /* PHY FSUSB: FS Serial for Port 3 (multiple PHY modes supported) */
783 AH3_3430_USB3FS_PHY_MM3_RXDP,
784 AE3_3430_USB3FS_PHY_MM3_RXDM,
785 AD1_3430_USB3FS_PHY_MM3_RXRCV,
786 AE1_3430_USB3FS_PHY_MM3_TXSE0,
787 AD2_3430_USB3FS_PHY_MM3_TXDAT,
788 AC1_3430_USB3FS_PHY_MM3_TXEN_N,
791 * - normally these are bidirectional, no internal pullup/pulldown
792 * - "_UP" suffix (GPIO3_UP) if internal pullup is configured
793 * - "_DOWN" suffix (GPIO3_DOWN) with internal pulldown
794 * - "_OUT" suffix (GPIO3_OUT) for output-only pins (unlike 24xx)
804 AG4_34XX_GPIO134_OUT,
805 AF4_34XX_GPIO135_OUT,
806 AE4_34XX_GPIO136_OUT,
811 H19_34XX_GPIO164_OUT,
814 /* OMAP3 SDRC CKE signals to SDR/DDR ram chips */
850 /* SYS_NIRQ T2 INT1 */
853 /* EHCI GPIO's for OMAP3EVM (Rev >= E) */
859 struct omap_mux_cfg {
860 struct pin_config *pins;
862 int (*cfg_reg)(const struct pin_config *cfg);
865 #ifdef CONFIG_OMAP_MUX
866 /* setup pin muxing in Linux */
867 extern int omap1_mux_init(void);
868 extern int omap2_mux_init(void);
869 extern int omap_mux_register(struct omap_mux_cfg *);
870 extern int omap_cfg_reg(unsigned long reg_cfg);
872 /* boot loader does it all (no warnings from CONFIG_OMAP_MUX_WARNINGS) */
873 static inline int omap1_mux_init(void) { return 0; }
874 static inline int omap2_mux_init(void) { return 0; }
875 static inline int omap_cfg_reg(unsigned long reg_cfg) { return 0; }