arch/arm/plat-omap/include/plat/mux.h

   1 /*
   2  * arch/arm/plat-omap/include/mach/mux.h
   3  *
   4  * Table of the Omap register configurations for the FUNC_MUX and
   5  * PULL_DWN combinations.
   6  *
   7  * Copyright (C) 2004 - 2008 Texas Instruments Inc.
   8  * Copyright (C) 2003 - 2008 Nokia Corporation
   9  *
  10  * Written by Tony Lindgren
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2 of the License, or
  15  * (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  25  *
  26  * NOTE: Please use the following naming style for new pin entries.
  27  *       For example, W8_1610_MMC2_DAT0, where:
  28  *       - W8        = ball
  29  *       - 1610      = 1510 or 1610, none if common for both 1510 and 1610
  30  *       - MMC2_DAT0 = function
  31  */
  32
  33 #ifndef __ASM_ARCH_MUX_H
  34 #define __ASM_ARCH_MUX_H
  35
  36 #define PU_PD_SEL_NA            0       /* No pu_pd reg available */
  37 #define PULL_DWN_CTRL_NA        0       /* No pull-down control needed */
  38
  39 #ifdef  CONFIG_OMAP_MUX_DEBUG
  40 #define MUX_REG(reg, mode_offset, mode) .mux_reg_name = "FUNC_MUX_CTRL_"#reg, \
  41                                         .mux_reg = FUNC_MUX_CTRL_##reg, \
  42                                         .mask_offset = mode_offset, \
  43                                         .mask = mode,
  44
  45 #define PULL_REG(reg, bit, status)      .pull_name = "PULL_DWN_CTRL_"#reg, \
  46                                         .pull_reg = PULL_DWN_CTRL_##reg, \
  47                                         .pull_bit = bit, \
  48                                         .pull_val = status,
  49
  50 #define PU_PD_REG(reg, status)          .pu_pd_name = "PU_PD_SEL_"#reg, \
  51                                         .pu_pd_reg = PU_PD_SEL_##reg, \
  52                                         .pu_pd_val = status,
  53
  54 #define MUX_REG_7XX(reg, mode_offset, mode) .mux_reg_name = "OMAP7XX_IO_CONF_"#reg, \
  55                                         .mux_reg = OMAP7XX_IO_CONF_##reg, \
  56                                         .mask_offset = mode_offset, \
  57                                         .mask = mode,
  58
  59 #define PULL_REG_7XX(reg, bit, status)  .pull_name = "OMAP7XX_IO_CONF_"#reg, \
  60                                         .pull_reg = OMAP7XX_IO_CONF_##reg, \
  61                                         .pull_bit = bit, \
  62                                         .pull_val = status,
  63
  64 #else
  65
  66 #define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \
  67                                         .mask_offset = mode_offset, \
  68                                         .mask = mode,
  69
  70 #define PULL_REG(reg, bit, status)      .pull_reg = PULL_DWN_CTRL_##reg, \
  71                                         .pull_bit = bit, \
  72                                         .pull_val = status,
  73
  74 #define PU_PD_REG(reg, status)          .pu_pd_reg = PU_PD_SEL_##reg, \
  75                                         .pu_pd_val = status,
  76
  77 #define MUX_REG_7XX(reg, mode_offset, mode) \
  78                                         .mux_reg = OMAP7XX_IO_CONF_##reg, \
  79                                         .mask_offset = mode_offset, \
  80                                         .mask = mode,
  81
  82 #define PULL_REG_7XX(reg, bit, status)  .pull_reg = OMAP7XX_IO_CONF_##reg, \
  83                                         .pull_bit = bit, \
  84                                         .pull_val = status,
  85
  86 #endif /* CONFIG_OMAP_MUX_DEBUG */
  87
  88 #define MUX_CFG(desc, mux_reg, mode_offset, mode,       \
  89                 pull_reg, pull_bit, pull_status,        \
  90                 pu_pd_reg, pu_pd_status, debug_status)  \
  91 {                                                       \
  92         .name =  desc,                                  \
  93         .debug = debug_status,                          \
  94         MUX_REG(mux_reg, mode_offset, mode)             \
  95         PULL_REG(pull_reg, pull_bit, pull_status)       \
  96         PU_PD_REG(pu_pd_reg, pu_pd_status)              \
  97 },
  98
  99
 100 /*
 101  * OMAP730/850 has a slightly different config for the pin mux.
 102  * - config regs are the OMAP7XX_IO_CONF_x regs (see omap730.h) regs and
 103  *   not the FUNC_MUX_CTRL_x regs from hardware.h
 104  * - for pull-up/down, only has one enable bit which is is in the same register
 105  *   as mux config
 106  */
 107 #define MUX_CFG_7XX(desc, mux_reg, mode_offset, mode,   \
 108                    pull_bit, pull_status, debug_status)\
 109 {                                                       \
 110         .name =  desc,                                  \
 111         .debug = debug_status,                          \
 112         MUX_REG_7XX(mux_reg, mode_offset, mode)         \
 113         PULL_REG_7XX(mux_reg, pull_bit, pull_status)    \
 114         PU_PD_REG(NA, 0)                \
 115 },
 116
 117 #define MUX_CFG_24XX(desc, reg_offset, mode,                    \
 118                                 pull_en, pull_mode, dbg)        \
 119 {                                                               \
 120         .name           = desc,                                 \
 121         .debug          = dbg,                                  \
 122         .mux_reg        = reg_offset,                           \
 123         .mask           = mode,                                 \
 124         .pull_val       = pull_en,                              \
 125         .pu_pd_val      = pull_mode,                            \
 126 },
 127
 128 /* 24xx/34xx mux bit defines */
 129 #define OMAP2_PULL_ENA          (1 << 3)
 130 #define OMAP2_PULL_UP           (1 << 4)
 131 #define OMAP2_ALTELECTRICALSEL  (1 << 5)
 132
 133 /* 34xx specific mux bit defines */
 134 #define OMAP3_INPUT_EN          (1 << 8)
 135 #define OMAP3_OFF_EN            (1 << 9)
 136 #define OMAP3_OFFOUT_EN         (1 << 10)
 137 #define OMAP3_OFFOUT_VAL        (1 << 11)
 138 #define OMAP3_OFF_PULL_EN       (1 << 12)
 139 #define OMAP3_OFF_PULL_UP       (1 << 13)
 140 #define OMAP3_WAKEUP_EN         (1 << 14)
 141
 142 /* 34xx mux mode options for each pin. See TRM for options */
 143 #define OMAP34XX_MUX_MODE0      0
 144 #define OMAP34XX_MUX_MODE1      1
 145 #define OMAP34XX_MUX_MODE2      2
 146 #define OMAP34XX_MUX_MODE3      3
 147 #define OMAP34XX_MUX_MODE4      4
 148 #define OMAP34XX_MUX_MODE5      5
 149 #define OMAP34XX_MUX_MODE6      6
 150 #define OMAP34XX_MUX_MODE7      7
 151
 152 /* 34xx active pin states */
 153 #define OMAP34XX_PIN_OUTPUT             0
 154 #define OMAP34XX_PIN_INPUT              OMAP3_INPUT_EN
 155 #define OMAP34XX_PIN_INPUT_PULLUP       (OMAP2_PULL_ENA | OMAP3_INPUT_EN \
 156                                                 | OMAP2_PULL_UP)
 157 #define OMAP34XX_PIN_INPUT_PULLDOWN     (OMAP2_PULL_ENA | OMAP3_INPUT_EN)
 158
 159 /* 34xx off mode states */
 160 #define OMAP34XX_PIN_OFF_NONE           0
 161 #define OMAP34XX_PIN_OFF_OUTPUT_HIGH    (OMAP3_OFF_EN | OMAP3_OFFOUT_EN \
 162                                                 | OMAP3_OFFOUT_VAL)
 163 #define OMAP34XX_PIN_OFF_OUTPUT_LOW     (OMAP3_OFF_EN | OMAP3_OFFOUT_EN)
 164 #define OMAP34XX_PIN_OFF_INPUT_PULLUP   (OMAP3_OFF_EN | OMAP3_OFF_PULL_EN \
 165                                                 | OMAP3_OFF_PULL_UP)
 166 #define OMAP34XX_PIN_OFF_INPUT_PULLDOWN (OMAP3_OFF_EN | OMAP3_OFF_PULL_EN)
 167 #define OMAP34XX_PIN_OFF_WAKEUPENABLE   OMAP3_WAKEUP_EN
 168
 169 #define MUX_CFG_34XX(desc, reg_offset, mux_value) {             \
 170         .name           = desc,                                 \
 171         .debug          = 0,                                    \
 172         .mux_reg        = reg_offset,                           \
 173         .mux_val        = mux_value                             \
 174 },
 175
 176 struct pin_config {
 177         char                    *name;
 178         const unsigned int      mux_reg;
 179         unsigned char           debug;
 180
 181 #if     defined(CONFIG_ARCH_OMAP34XX)
 182         u16                     mux_val; /* Wake-up, off mode, pull, mux mode */
 183 #endif
 184
 185 #if     defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP24XX)
 186         const unsigned char mask_offset;
 187         const unsigned char mask;
 188
 189         const char *pull_name;
 190         const unsigned int pull_reg;
 191         const unsigned char pull_val;
 192         const unsigned char pull_bit;
 193
 194         const char *pu_pd_name;
 195         const unsigned int pu_pd_reg;
 196         const unsigned char pu_pd_val;
 197 #endif
 198
 199 #if     defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
 200         const char *mux_reg_name;
 201 #endif
 202
 203 };
 204
 205 enum omap7xx_index {
 206         /* OMAP 730 keyboard */
 207         E2_7XX_KBR0,
 208         J7_7XX_KBR1,
 209         E1_7XX_KBR2,
 210         F3_7XX_KBR3,
 211         D2_7XX_KBR4,
 212         C2_7XX_KBC0,
 213         D3_7XX_KBC1,
 214         E4_7XX_KBC2,
 215         F4_7XX_KBC3,
 216         E3_7XX_KBC4,
 217
 218         /* USB */
 219         AA17_7XX_USB_DM,
 220         W16_7XX_USB_PU_EN,
 221         W17_7XX_USB_VBUSI,
 222
 223         /* MMC */
 224         MMC_7XX_CMD,
 225         MMC_7XX_CLK,
 226         MMC_7XX_DAT0,
 227 };
 228
 229 enum omap1xxx_index {
 230         /* UART1 (BT_UART_GATING)*/
 231         UART1_TX = 0,
 232         UART1_RTS,
 233
 234         /* UART2 (COM_UART_GATING)*/
 235         UART2_TX,
 236         UART2_RX,
 237         UART2_CTS,
 238         UART2_RTS,
 239
 240         /* UART3 (GIGA_UART_GATING) */
 241         UART3_TX,
 242         UART3_RX,
 243         UART3_CTS,
 244         UART3_RTS,
 245         UART3_CLKREQ,
 246         UART3_BCLK,     /* 12MHz clock out */
 247         Y15_1610_UART3_RTS,
 248
 249         /* PWT & PWL */
 250         PWT,
 251         PWL,
 252
 253         /* USB master generic */
 254         R18_USB_VBUS,
 255         R18_1510_USB_GPIO0,
 256         W4_USB_PUEN,
 257         W4_USB_CLKO,
 258         W4_USB_HIGHZ,
 259         W4_GPIO58,
 260
 261         /* USB1 master */
 262         USB1_SUSP,
 263         USB1_SEO,
 264         W13_1610_USB1_SE0,
 265         USB1_TXEN,
 266         USB1_TXD,
 267         USB1_VP,
 268         USB1_VM,
 269         USB1_RCV,
 270         USB1_SPEED,
 271         R13_1610_USB1_SPEED,
 272         R13_1710_USB1_SE0,
 273
 274         /* USB2 master */
 275         USB2_SUSP,
 276         USB2_VP,
 277         USB2_TXEN,
 278         USB2_VM,
 279         USB2_RCV,
 280         USB2_SEO,
 281         USB2_TXD,
 282
 283         /* OMAP-1510 GPIO */
 284         R18_1510_GPIO0,
 285         R19_1510_GPIO1,
 286         M14_1510_GPIO2,
 287
 288         /* OMAP1610 GPIO */
 289         P18_1610_GPIO3,
 290         Y15_1610_GPIO17,
 291
 292         /* OMAP-1710 GPIO */
 293         R18_1710_GPIO0,
 294         V2_1710_GPIO10,
 295         N21_1710_GPIO14,
 296         W15_1710_GPIO40,
 297
 298         /* MPUIO */
 299         MPUIO2,
 300         N15_1610_MPUIO2,
 301         MPUIO4,
 302         MPUIO5,
 303         T20_1610_MPUIO5,
 304         W11_1610_MPUIO6,
 305         V10_1610_MPUIO7,
 306         W11_1610_MPUIO9,
 307         V10_1610_MPUIO10,
 308         W10_1610_MPUIO11,
 309         E20_1610_MPUIO13,
 310         U20_1610_MPUIO14,
 311         E19_1610_MPUIO15,
 312
 313         /* MCBSP2 */
 314         MCBSP2_CLKR,
 315         MCBSP2_CLKX,
 316         MCBSP2_DR,
 317         MCBSP2_DX,
 318         MCBSP2_FSR,
 319         MCBSP2_FSX,
 320
 321         /* MCBSP3 */
 322         MCBSP3_CLKX,
 323
 324         /* Misc ballouts */
 325         BALLOUT_V8_ARMIO3,
 326         N20_HDQ,
 327
 328         /* OMAP-1610 MMC2 */
 329         W8_1610_MMC2_DAT0,
 330         V8_1610_MMC2_DAT1,
 331         W15_1610_MMC2_DAT2,
 332         R10_1610_MMC2_DAT3,
 333         Y10_1610_MMC2_CLK,
 334         Y8_1610_MMC2_CMD,
 335         V9_1610_MMC2_CMDDIR,
 336         V5_1610_MMC2_DATDIR0,
 337         W19_1610_MMC2_DATDIR1,
 338         R18_1610_MMC2_CLKIN,
 339
 340         /* OMAP-1610 External Trace Interface */
 341         M19_1610_ETM_PSTAT0,
 342         L15_1610_ETM_PSTAT1,
 343         L18_1610_ETM_PSTAT2,
 344         L19_1610_ETM_D0,
 345         J19_1610_ETM_D6,
 346         J18_1610_ETM_D7,
 347
 348         /* OMAP16XX GPIO */
 349         P20_1610_GPIO4,
 350         V9_1610_GPIO7,
 351         W8_1610_GPIO9,
 352         N20_1610_GPIO11,
 353         N19_1610_GPIO13,
 354         P10_1610_GPIO22,
 355         V5_1610_GPIO24,
 356         AA20_1610_GPIO_41,
 357         W19_1610_GPIO48,
 358         M7_1610_GPIO62,
 359         V14_16XX_GPIO37,
 360         R9_16XX_GPIO18,
 361         L14_16XX_GPIO49,
 362
 363         /* OMAP-1610 uWire */
 364         V19_1610_UWIRE_SCLK,
 365         U18_1610_UWIRE_SDI,
 366         W21_1610_UWIRE_SDO,
 367         N14_1610_UWIRE_CS0,
 368         P15_1610_UWIRE_CS3,
 369         N15_1610_UWIRE_CS1,
 370
 371         /* OMAP-1610 SPI */
 372         U19_1610_SPIF_SCK,
 373         U18_1610_SPIF_DIN,
 374         P20_1610_SPIF_DIN,
 375         W21_1610_SPIF_DOUT,
 376         R18_1610_SPIF_DOUT,
 377         N14_1610_SPIF_CS0,
 378         N15_1610_SPIF_CS1,
 379         T19_1610_SPIF_CS2,
 380         P15_1610_SPIF_CS3,
 381
 382         /* OMAP-1610 Flash */
 383         L3_1610_FLASH_CS2B_OE,
 384         M8_1610_FLASH_CS2B_WE,
 385
 386         /* First MMC */
 387         MMC_CMD,
 388         MMC_DAT1,
 389         MMC_DAT2,
 390         MMC_DAT0,
 391         MMC_CLK,
 392         MMC_DAT3,
 393
 394         /* OMAP-1710 MMC CMDDIR and DATDIR0 */
 395         M15_1710_MMC_CLKI,
 396         P19_1710_MMC_CMDDIR,
 397         P20_1710_MMC_DATDIR0,
 398
 399         /* OMAP-1610 USB0 alternate pin configuration */
 400         W9_USB0_TXEN,
 401         AA9_USB0_VP,
 402         Y5_USB0_RCV,
 403         R9_USB0_VM,
 404         V6_USB0_TXD,
 405         W5_USB0_SE0,
 406         V9_USB0_SPEED,
 407         V9_USB0_SUSP,
 408
 409         /* USB2 */
 410         W9_USB2_TXEN,
 411         AA9_USB2_VP,
 412         Y5_USB2_RCV,
 413         R9_USB2_VM,
 414         V6_USB2_TXD,
 415         W5_USB2_SE0,
 416
 417         /* 16XX UART */
 418         R13_1610_UART1_TX,
 419         V14_16XX_UART1_RX,
 420         R14_1610_UART1_CTS,
 421         AA15_1610_UART1_RTS,
 422         R9_16XX_UART2_RX,
 423         L14_16XX_UART3_RX,
 424
 425         /* I2C OMAP-1610 */
 426         I2C_SCL,
 427         I2C_SDA,
 428
 429         /* Keypad */
 430         F18_1610_KBC0,
 431         D20_1610_KBC1,
 432         D19_1610_KBC2,
 433         E18_1610_KBC3,
 434         C21_1610_KBC4,
 435         G18_1610_KBR0,
 436         F19_1610_KBR1,
 437         H14_1610_KBR2,
 438         E20_1610_KBR3,
 439         E19_1610_KBR4,
 440         N19_1610_KBR5,
 441
 442         /* Power management */
 443         T20_1610_LOW_PWR,
 444
 445         /* MCLK Settings */
 446         V5_1710_MCLK_ON,
 447         V5_1710_MCLK_OFF,
 448         R10_1610_MCLK_ON,
 449         R10_1610_MCLK_OFF,
 450
 451         /* CompactFlash controller */
 452         P11_1610_CF_CD2,
 453         R11_1610_CF_IOIS16,
 454         V10_1610_CF_IREQ,
 455         W10_1610_CF_RESET,
 456         W11_1610_CF_CD1,
 457
 458         /* parallel camera */
 459         J15_1610_CAM_LCLK,
 460         J18_1610_CAM_D7,
 461         J19_1610_CAM_D6,
 462         J14_1610_CAM_D5,
 463         K18_1610_CAM_D4,
 464         K19_1610_CAM_D3,
 465         K15_1610_CAM_D2,
 466         K14_1610_CAM_D1,
 467         L19_1610_CAM_D0,
 468         L18_1610_CAM_VS,
 469         L15_1610_CAM_HS,
 470         M19_1610_CAM_RSTZ,
 471         Y15_1610_CAM_OUTCLK,
 472
 473         /* serial camera */
 474         H19_1610_CAM_EXCLK,
 475         Y12_1610_CCP_CLKP,
 476         W13_1610_CCP_CLKM,
 477         W14_1610_CCP_DATAP,
 478         Y14_1610_CCP_DATAM,
 479
 480 };
 481
 482 enum omap24xx_index {
 483         /* 24xx I2C */
 484         M19_24XX_I2C1_SCL,
 485         L15_24XX_I2C1_SDA,
 486         J15_24XX_I2C2_SCL,
 487         H19_24XX_I2C2_SDA,
 488
 489         /* 24xx Menelaus interrupt */
 490         W19_24XX_SYS_NIRQ,
 491
 492         /* 24xx clock */
 493         W14_24XX_SYS_CLKOUT,
 494
 495         /* 24xx GPMC chipselects, wait pin monitoring */
 496         E2_GPMC_NCS2,
 497         L2_GPMC_NCS7,
 498         L3_GPMC_WAIT0,
 499         N7_GPMC_WAIT1,
 500         M1_GPMC_WAIT2,
 501         P1_GPMC_WAIT3,
 502
 503         /* 242X McBSP */
 504         Y15_24XX_MCBSP2_CLKX,
 505         R14_24XX_MCBSP2_FSX,
 506         W15_24XX_MCBSP2_DR,
 507         V15_24XX_MCBSP2_DX,
 508
 509         /* 24xx GPIO */
 510         M21_242X_GPIO11,
 511         P21_242X_GPIO12,
 512         AA10_242X_GPIO13,
 513         AA6_242X_GPIO14,
 514         AA4_242X_GPIO15,
 515         Y11_242X_GPIO16,
 516         AA12_242X_GPIO17,
 517         AA8_242X_GPIO58,
 518         Y20_24XX_GPIO60,
 519         W4__24XX_GPIO74,
 520         N15_24XX_GPIO85,
 521         M15_24XX_GPIO92,
 522         P20_24XX_GPIO93,
 523         P18_24XX_GPIO95,
 524         M18_24XX_GPIO96,
 525         L14_24XX_GPIO97,
 526         J15_24XX_GPIO99,
 527         V14_24XX_GPIO117,
 528         P14_24XX_GPIO125,
 529
 530         /* 242x DBG GPIO */
 531         V4_242X_GPIO49,
 532         W2_242X_GPIO50,
 533         U4_242X_GPIO51,
 534         V3_242X_GPIO52,
 535         V2_242X_GPIO53,
 536         V6_242X_GPIO53,
 537         T4_242X_GPIO54,
 538         Y4_242X_GPIO54,
 539         T3_242X_GPIO55,
 540         U2_242X_GPIO56,
 541
 542         /* 24xx external DMA requests */
 543         AA10_242X_DMAREQ0,
 544         AA6_242X_DMAREQ1,
 545         E4_242X_DMAREQ2,
 546         G4_242X_DMAREQ3,
 547         D3_242X_DMAREQ4,
 548         E3_242X_DMAREQ5,
 549
 550         /* UART3 */
 551         K15_24XX_UART3_TX,
 552         K14_24XX_UART3_RX,
 553
 554         /* MMC/SDIO */
 555         G19_24XX_MMC_CLKO,
 556         H18_24XX_MMC_CMD,
 557         F20_24XX_MMC_DAT0,
 558         H14_24XX_MMC_DAT1,
 559         E19_24XX_MMC_DAT2,
 560         D19_24XX_MMC_DAT3,
 561         F19_24XX_MMC_DAT_DIR0,
 562         E20_24XX_MMC_DAT_DIR1,
 563         F18_24XX_MMC_DAT_DIR2,
 564         E18_24XX_MMC_DAT_DIR3,
 565         G18_24XX_MMC_CMD_DIR,
 566         H15_24XX_MMC_CLKI,
 567
 568         /* Full speed USB */
 569         J20_24XX_USB0_PUEN,
 570         J19_24XX_USB0_VP,
 571         K20_24XX_USB0_VM,
 572         J18_24XX_USB0_RCV,
 573         K19_24XX_USB0_TXEN,
 574         J14_24XX_USB0_SE0,
 575         K18_24XX_USB0_DAT,
 576
 577         N14_24XX_USB1_SE0,
 578         W12_24XX_USB1_SE0,
 579         P15_24XX_USB1_DAT,
 580         R13_24XX_USB1_DAT,
 581         W20_24XX_USB1_TXEN,
 582         P13_24XX_USB1_TXEN,
 583         V19_24XX_USB1_RCV,
 584         V12_24XX_USB1_RCV,
 585
 586         AA10_24XX_USB2_SE0,
 587         Y11_24XX_USB2_DAT,
 588         AA12_24XX_USB2_TXEN,
 589         AA6_24XX_USB2_RCV,
 590         AA4_24XX_USB2_TLLSE0,
 591
 592         /* Keypad GPIO*/
 593         T19_24XX_KBR0,
 594         R19_24XX_KBR1,
 595         V18_24XX_KBR2,
 596         M21_24XX_KBR3,
 597         E5__24XX_KBR4,
 598         M18_24XX_KBR5,
 599         R20_24XX_KBC0,
 600         M14_24XX_KBC1,
 601         H19_24XX_KBC2,
 602         V17_24XX_KBC3,
 603         P21_24XX_KBC4,
 604         L14_24XX_KBC5,
 605         N19_24XX_KBC6,
 606
 607         /* 24xx Menelaus Keypad GPIO */
 608         B3__24XX_KBR5,
 609         AA4_24XX_KBC2,
 610         B13_24XX_KBC6,
 611
 612         /* 2430 USB */
 613         AD9_2430_USB0_PUEN,
 614         Y11_2430_USB0_VP,
 615         AD7_2430_USB0_VM,
 616         AE7_2430_USB0_RCV,
 617         AD4_2430_USB0_TXEN,
 618         AF9_2430_USB0_SE0,
 619         AE6_2430_USB0_DAT,
 620         AD24_2430_USB1_SE0,
 621         AB24_2430_USB1_RCV,
 622         Y25_2430_USB1_TXEN,
 623         AA26_2430_USB1_DAT,
 624
 625         /* 2430 HS-USB */
 626         AD9_2430_USB0HS_DATA3,
 627         Y11_2430_USB0HS_DATA4,
 628         AD7_2430_USB0HS_DATA5,
 629         AE7_2430_USB0HS_DATA6,
 630         AD4_2430_USB0HS_DATA2,
 631         AF9_2430_USB0HS_DATA0,
 632         AE6_2430_USB0HS_DATA1,
 633         AE8_2430_USB0HS_CLK,
 634         AD8_2430_USB0HS_DIR,
 635         AE5_2430_USB0HS_STP,
 636         AE9_2430_USB0HS_NXT,
 637         AC7_2430_USB0HS_DATA7,
 638
 639         /* 2430 McBSP */
 640         AD6_2430_MCBSP_CLKS,
 641
 642         AB2_2430_MCBSP1_CLKR,
 643         AD5_2430_MCBSP1_FSR,
 644         AA1_2430_MCBSP1_DX,
 645         AF3_2430_MCBSP1_DR,
 646         AB3_2430_MCBSP1_FSX,
 647         Y9_2430_MCBSP1_CLKX,
 648
 649         AC10_2430_MCBSP2_FSX,
 650         AD16_2430_MCBSP2_CLX,
 651         AE13_2430_MCBSP2_DX,
 652         AD13_2430_MCBSP2_DR,
 653         AC10_2430_MCBSP2_FSX_OFF,
 654         AD16_2430_MCBSP2_CLX_OFF,
 655         AE13_2430_MCBSP2_DX_OFF,
 656         AD13_2430_MCBSP2_DR_OFF,
 657
 658         AC9_2430_MCBSP3_CLKX,
 659         AE4_2430_MCBSP3_FSX,
 660         AE2_2430_MCBSP3_DR,
 661         AF4_2430_MCBSP3_DX,
 662
 663         N3_2430_MCBSP4_CLKX,
 664         AD23_2430_MCBSP4_DR,
 665         AB25_2430_MCBSP4_DX,
 666         AC25_2430_MCBSP4_FSX,
 667
 668         AE16_2430_MCBSP5_CLKX,
 669         AF12_2430_MCBSP5_FSX,
 670         K7_2430_MCBSP5_DX,
 671         M1_2430_MCBSP5_DR,
 672
 673         /* 2430 McSPI*/
 674         Y18_2430_MCSPI1_CLK,
 675         AD15_2430_MCSPI1_SIMO,
 676         AE17_2430_MCSPI1_SOMI,
 677         U1_2430_MCSPI1_CS0,
 678
 679         /* Touchscreen GPIO */
 680         AF19_2430_GPIO_85,
 681
 682 };
 683
 684 enum omap34xx_index {
 685         /* 34xx I2C */
 686         K21_34XX_I2C1_SCL,
 687         J21_34XX_I2C1_SDA,
 688         AF15_34XX_I2C2_SCL,
 689         AE15_34XX_I2C2_SDA,
 690         AF14_34XX_I2C3_SCL,
 691         AG14_34XX_I2C3_SDA,
 692         AD26_34XX_I2C4_SCL,
 693         AE26_34XX_I2C4_SDA,
 694
 695         /* PHY - HSUSB: 12-pin ULPI PHY: Port 1*/
 696         Y8_3430_USB1HS_PHY_CLK,
 697         Y9_3430_USB1HS_PHY_STP,
 698         AA14_3430_USB1HS_PHY_DIR,
 699         AA11_3430_USB1HS_PHY_NXT,
 700         W13_3430_USB1HS_PHY_DATA0,
 701         W12_3430_USB1HS_PHY_DATA1,
 702         W11_3430_USB1HS_PHY_DATA2,
 703         Y11_3430_USB1HS_PHY_DATA3,
 704         W9_3430_USB1HS_PHY_DATA4,
 705         Y12_3430_USB1HS_PHY_DATA5,
 706         W8_3430_USB1HS_PHY_DATA6,
 707         Y13_3430_USB1HS_PHY_DATA7,
 708
 709         /* PHY - HSUSB: 12-pin ULPI PHY: Port 2*/
 710         AA8_3430_USB2HS_PHY_CLK,
 711         AA10_3430_USB2HS_PHY_STP,
 712         AA9_3430_USB2HS_PHY_DIR,
 713         AB11_3430_USB2HS_PHY_NXT,
 714         AB10_3430_USB2HS_PHY_DATA0,
 715         AB9_3430_USB2HS_PHY_DATA1,
 716         W3_3430_USB2HS_PHY_DATA2,
 717         T4_3430_USB2HS_PHY_DATA3,
 718         T3_3430_USB2HS_PHY_DATA4,
 719         R3_3430_USB2HS_PHY_DATA5,
 720         R4_3430_USB2HS_PHY_DATA6,
 721         T2_3430_USB2HS_PHY_DATA7,
 722
 723
 724         /* TLL - HSUSB: 12-pin TLL Port 1*/
 725         Y8_3430_USB1HS_TLL_CLK,
 726         Y9_3430_USB1HS_TLL_STP,
 727         AA14_3430_USB1HS_TLL_DIR,
 728         AA11_3430_USB1HS_TLL_NXT,
 729         W13_3430_USB1HS_TLL_DATA0,
 730         W12_3430_USB1HS_TLL_DATA1,
 731         W11_3430_USB1HS_TLL_DATA2,
 732         Y11_3430_USB1HS_TLL_DATA3,
 733         W9_3430_USB1HS_TLL_DATA4,
 734         Y12_3430_USB1HS_TLL_DATA5,
 735         W8_3430_USB1HS_TLL_DATA6,
 736         Y13_3430_USB1HS_TLL_DATA7,
 737
 738         /* TLL - HSUSB: 12-pin TLL Port 2*/
 739         AA8_3430_USB2HS_TLL_CLK,
 740         AA10_3430_USB2HS_TLL_STP,
 741         AA9_3430_USB2HS_TLL_DIR,
 742         AB11_3430_USB2HS_TLL_NXT,
 743         AB10_3430_USB2HS_TLL_DATA0,
 744         AB9_3430_USB2HS_TLL_DATA1,
 745         W3_3430_USB2HS_TLL_DATA2,
 746         T4_3430_USB2HS_TLL_DATA3,
 747         T3_3430_USB2HS_TLL_DATA4,
 748         R3_3430_USB2HS_TLL_DATA5,
 749         R4_3430_USB2HS_TLL_DATA6,
 750         T2_3430_USB2HS_TLL_DATA7,
 751
 752         /* TLL - HSUSB: 12-pin TLL Port 3*/
 753         AA6_3430_USB3HS_TLL_CLK,
 754         AB3_3430_USB3HS_TLL_STP,
 755         AA3_3430_USB3HS_TLL_DIR,
 756         Y3_3430_USB3HS_TLL_NXT,
 757         AA5_3430_USB3HS_TLL_DATA0,
 758         Y4_3430_USB3HS_TLL_DATA1,
 759         Y5_3430_USB3HS_TLL_DATA2,
 760         W5_3430_USB3HS_TLL_DATA3,
 761         AB12_3430_USB3HS_TLL_DATA4,
 762         AB13_3430_USB3HS_TLL_DATA5,
 763         AA13_3430_USB3HS_TLL_DATA6,
 764         AA12_3430_USB3HS_TLL_DATA7,
 765
 766         /* PHY FSUSB: FS Serial for Port 1 (multiple PHY modes supported) */
 767         AF10_3430_USB1FS_PHY_MM1_RXDP,
 768         AG9_3430_USB1FS_PHY_MM1_RXDM,
 769         W13_3430_USB1FS_PHY_MM1_RXRCV,
 770         W12_3430_USB1FS_PHY_MM1_TXSE0,
 771         W11_3430_USB1FS_PHY_MM1_TXDAT,
 772         Y11_3430_USB1FS_PHY_MM1_TXEN_N,
 773
 774         /* PHY FSUSB: FS Serial for Port 2 (multiple PHY modes supported) */
 775         AF7_3430_USB2FS_PHY_MM2_RXDP,
 776         AH7_3430_USB2FS_PHY_MM2_RXDM,
 777         AB10_3430_USB2FS_PHY_MM2_RXRCV,
 778         AB9_3430_USB2FS_PHY_MM2_TXSE0,
 779         W3_3430_USB2FS_PHY_MM2_TXDAT,
 780         T4_3430_USB2FS_PHY_MM2_TXEN_N,
 781
 782         /* PHY FSUSB: FS Serial for Port 3 (multiple PHY modes supported) */
 783         AH3_3430_USB3FS_PHY_MM3_RXDP,
 784         AE3_3430_USB3FS_PHY_MM3_RXDM,
 785         AD1_3430_USB3FS_PHY_MM3_RXRCV,
 786         AE1_3430_USB3FS_PHY_MM3_TXSE0,
 787         AD2_3430_USB3FS_PHY_MM3_TXDAT,
 788         AC1_3430_USB3FS_PHY_MM3_TXEN_N,
 789
 790         /* 34xx GPIO
 791          *  - normally these are bidirectional, no internal pullup/pulldown
 792          *  - "_UP" suffix (GPIO3_UP) if internal pullup is configured
 793          *  - "_DOWN" suffix (GPIO3_DOWN) with internal pulldown
 794          *  - "_OUT" suffix (GPIO3_OUT) for output-only pins (unlike 24xx)
 795          */
 796         AF26_34XX_GPIO0,
 797         AF22_34XX_GPIO9,
 798         AG9_34XX_GPIO23,
 799         AH8_34XX_GPIO29,
 800         U8_34XX_GPIO54_OUT,
 801         U8_34XX_GPIO54_DOWN,
 802         L8_34XX_GPIO63,
 803         G25_34XX_GPIO86_OUT,
 804         AG4_34XX_GPIO134_OUT,
 805         AF4_34XX_GPIO135_OUT,
 806         AE4_34XX_GPIO136_OUT,
 807         AF6_34XX_GPIO140_UP,
 808         AE6_34XX_GPIO141,
 809         AF5_34XX_GPIO142,
 810         AE5_34XX_GPIO143,
 811         H19_34XX_GPIO164_OUT,
 812         J25_34XX_GPIO170,
 813
 814         /* OMAP3 SDRC CKE signals to SDR/DDR ram chips */
 815         H16_34XX_SDRC_CKE0,
 816         H17_34XX_SDRC_CKE1,
 817
 818         /* MMC1 */
 819         N28_3430_MMC1_CLK,
 820         M27_3430_MMC1_CMD,
 821         N27_3430_MMC1_DAT0,
 822         N26_3430_MMC1_DAT1,
 823         N25_3430_MMC1_DAT2,
 824         P28_3430_MMC1_DAT3,
 825         P27_3430_MMC1_DAT4,
 826         P26_3430_MMC1_DAT5,
 827         R27_3430_MMC1_DAT6,
 828         R25_3430_MMC1_DAT7,
 829
 830         /* MMC2 */
 831         AE2_3430_MMC2_CLK,
 832         AG5_3430_MMC2_CMD,
 833         AH5_3430_MMC2_DAT0,
 834         AH4_3430_MMC2_DAT1,
 835         AG4_3430_MMC2_DAT2,
 836         AF4_3430_MMC2_DAT3,
 837         AE4_3430_MMC2_DAT4,
 838         AH3_3430_MMC2_DAT5,
 839         AF3_3430_MMC2_DAT6,
 840         AE3_3430_MMC2_DAT7,
 841
 842         /* MMC3 */
 843         AF10_3430_MMC3_CLK,
 844         AC3_3430_MMC3_CMD,
 845         AE11_3430_MMC3_DAT0,
 846         AH9_3430_MMC3_DAT1,
 847         AF13_3430_MMC3_DAT2,
 848         AF13_3430_MMC3_DAT3,
 849
 850         /* SYS_NIRQ T2 INT1 */
 851         AF26_34XX_SYS_NIRQ,
 852
 853         /* EHCI GPIO's for OMAP3EVM (Rev >= E) */
 854         AH14_34XX_GPIO21,
 855         AF9_34XX_GPIO22,
 856         U3_34XX_GPIO61,
 857 };
 858
 859 struct omap_mux_cfg {
 860         struct pin_config       *pins;
 861         unsigned long           size;
 862         int                     (*cfg_reg)(const struct pin_config *cfg);
 863 };
 864
 865 #ifdef  CONFIG_OMAP_MUX
 866 /* setup pin muxing in Linux */
 867 extern int omap1_mux_init(void);
 868 extern int omap2_mux_init(void);
 869 extern int omap_mux_register(struct omap_mux_cfg *);
 870 extern int omap_cfg_reg(unsigned long reg_cfg);
 871 #else
 872 /* boot loader does it all (no warnings from CONFIG_OMAP_MUX_WARNINGS) */
 873 static inline int omap1_mux_init(void) { return 0; }
 874 static inline int omap2_mux_init(void) { return 0; }
 875 static inline int omap_cfg_reg(unsigned long reg_cfg) { return 0; }
 876 #endif
 877
 878 #endif