arch/arm/mm/mmu.c

   1 /*
   2  *  linux/arch/arm/mm/mmu.c
   3  *
   4  *  Copyright (C) 1995-2005 Russell King
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 #include <linux/module.h>
  11 #include <linux/kernel.h>
  12 #include <linux/errno.h>
  13 #include <linux/init.h>
  14 #include <linux/mman.h>
  15 #include <linux/nodemask.h>
  16 #include <linux/memblock.h>
  17 #include <linux/fs.h>
  18 #include <linux/vmalloc.h>
  19
  20 #include <asm/cp15.h>
  21 #include <asm/cputype.h>
  22 #include <asm/sections.h>
  23 #include <asm/cachetype.h>
  24 #include <asm/setup.h>
  25 #include <asm/sizes.h>
  26 #include <asm/smp_plat.h>
  27 #include <asm/tlb.h>
  28 #include <asm/highmem.h>
  29 #include <asm/system_info.h>
  30 #include <asm/traps.h>
  31
  32 #include <asm/mach/arch.h>
  33 #include <asm/mach/map.h>
  34 #include <asm/mach/pci.h>
  35
  36 #include "mm.h"
  37
  38 /*
  39  * empty_zero_page is a special page that is used for
  40  * zero-initialized data and COW.
  41  */
  42 struct page *empty_zero_page;
  43 EXPORT_SYMBOL(empty_zero_page);
  44
  45 /*
  46  * The pmd table for the upper-most set of pages.
  47  */
  48 pmd_t *top_pmd;
  49
  50 #define CPOLICY_UNCACHED        0
  51 #define CPOLICY_BUFFERED        1
  52 #define CPOLICY_WRITETHROUGH    2
  53 #define CPOLICY_WRITEBACK       3
  54 #define CPOLICY_WRITEALLOC      4
  55
  56 static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
  57 static unsigned int ecc_mask __initdata = 0;
  58 pgprot_t pgprot_user;
  59 pgprot_t pgprot_kernel;
  60
  61 EXPORT_SYMBOL(pgprot_user);
  62 EXPORT_SYMBOL(pgprot_kernel);
  63
  64 struct cachepolicy {
  65         const char      policy[16];
  66         unsigned int    cr_mask;
  67         pmdval_t        pmd;
  68         pteval_t        pte;
  69 };
  70
  71 static struct cachepolicy cache_policies[] __initdata = {
  72         {
  73                 .policy         = "uncached",
  74                 .cr_mask        = CR_W|CR_C,
  75                 .pmd            = PMD_SECT_UNCACHED,
  76                 .pte            = L_PTE_MT_UNCACHED,
  77         }, {
  78                 .policy         = "buffered",
  79                 .cr_mask        = CR_C,
  80                 .pmd            = PMD_SECT_BUFFERED,
  81                 .pte            = L_PTE_MT_BUFFERABLE,
  82         }, {
  83                 .policy         = "writethrough",
  84                 .cr_mask        = 0,
  85                 .pmd            = PMD_SECT_WT,
  86                 .pte            = L_PTE_MT_WRITETHROUGH,
  87         }, {
  88                 .policy         = "writeback",
  89                 .cr_mask        = 0,
  90                 .pmd            = PMD_SECT_WB,
  91                 .pte            = L_PTE_MT_WRITEBACK,
  92         }, {
  93                 .policy         = "writealloc",
  94                 .cr_mask        = 0,
  95                 .pmd            = PMD_SECT_WBWA,
  96                 .pte            = L_PTE_MT_WRITEALLOC,
  97         }
  98 };
  99
 100 /*
 101  * These are useful for identifying cache coherency
 102  * problems by allowing the cache or the cache and
 103  * writebuffer to be turned off.  (Note: the write
 104  * buffer should not be on and the cache off).
 105  */
 106 static int __init early_cachepolicy(char *p)
 107 {
 108         int i;
 109
 110         for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
 111                 int len = strlen(cache_policies[i].policy);
 112
 113                 if (memcmp(p, cache_policies[i].policy, len) == 0) {
 114                         cachepolicy = i;
 115                         cr_alignment &= ~cache_policies[i].cr_mask;
 116                         cr_no_alignment &= ~cache_policies[i].cr_mask;
 117                         break;
 118                 }
 119         }
 120         if (i == ARRAY_SIZE(cache_policies))
 121                 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
 122         /*
 123          * This restriction is partly to do with the way we boot; it is
 124          * unpredictable to have memory mapped using two different sets of
 125          * memory attributes (shared, type, and cache attribs).  We can not
 126          * change these attributes once the initial assembly has setup the
 127          * page tables.
 128          */
 129         if (cpu_architecture() >= CPU_ARCH_ARMv6) {
 130                 printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");
 131                 cachepolicy = CPOLICY_WRITEBACK;
 132         }
 133         flush_cache_all();
 134         set_cr(cr_alignment);
 135         return 0;
 136 }
 137 early_param("cachepolicy", early_cachepolicy);
 138
 139 static int __init early_nocache(char *__unused)
 140 {
 141         char *p = "buffered";
 142         printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
 143         early_cachepolicy(p);
 144         return 0;
 145 }
 146 early_param("nocache", early_nocache);
 147
 148 static int __init early_nowrite(char *__unused)
 149 {
 150         char *p = "uncached";
 151         printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
 152         early_cachepolicy(p);
 153         return 0;
 154 }
 155 early_param("nowb", early_nowrite);
 156
 157 #ifndef CONFIG_ARM_LPAE
 158 static int __init early_ecc(char *p)
 159 {
 160         if (memcmp(p, "on", 2) == 0)
 161                 ecc_mask = PMD_PROTECTION;
 162         else if (memcmp(p, "off", 3) == 0)
 163                 ecc_mask = 0;
 164         return 0;
 165 }
 166 early_param("ecc", early_ecc);
 167 #endif
 168
 169 static int __init noalign_setup(char *__unused)
 170 {
 171         cr_alignment &= ~CR_A;
 172         cr_no_alignment &= ~CR_A;
 173         set_cr(cr_alignment);
 174         return 1;
 175 }
 176 __setup("noalign", noalign_setup);
 177
 178 #ifndef CONFIG_SMP
 179 void adjust_cr(unsigned long mask, unsigned long set)
 180 {
 181         unsigned long flags;
 182
 183         mask &= ~CR_A;
 184
 185         set &= mask;
 186
 187         local_irq_save(flags);
 188
 189         cr_no_alignment = (cr_no_alignment & ~mask) | set;
 190         cr_alignment = (cr_alignment & ~mask) | set;
 191
 192         set_cr((get_cr() & ~mask) | set);
 193
 194         local_irq_restore(flags);
 195 }
 196 #endif
 197
 198 #define PROT_PTE_DEVICE         L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
 199 #define PROT_SECT_DEVICE        PMD_TYPE_SECT|PMD_SECT_AP_WRITE
 200
 201 static struct mem_type mem_types[] = {
 202         [MT_DEVICE] = {           /* Strongly ordered / ARMv6 shared device */
 203                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
 204                                   L_PTE_SHARED,
 205                 .prot_l1        = PMD_TYPE_TABLE,
 206                 .prot_sect      = PROT_SECT_DEVICE | PMD_SECT_S,
 207                 .domain         = DOMAIN_IO,
 208         },
 209         [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
 210                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
 211                 .prot_l1        = PMD_TYPE_TABLE,
 212                 .prot_sect      = PROT_SECT_DEVICE,
 213                 .domain         = DOMAIN_IO,
 214         },
 215         [MT_DEVICE_CACHED] = {    /* ioremap_cached */
 216                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
 217                 .prot_l1        = PMD_TYPE_TABLE,
 218                 .prot_sect      = PROT_SECT_DEVICE | PMD_SECT_WB,
 219                 .domain         = DOMAIN_IO,
 220         },
 221         [MT_DEVICE_WC] = {      /* ioremap_wc */
 222                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
 223                 .prot_l1        = PMD_TYPE_TABLE,
 224                 .prot_sect      = PROT_SECT_DEVICE,
 225                 .domain         = DOMAIN_IO,
 226         },
 227         [MT_UNCACHED] = {
 228                 .prot_pte       = PROT_PTE_DEVICE,
 229                 .prot_l1        = PMD_TYPE_TABLE,
 230                 .prot_sect      = PMD_TYPE_SECT | PMD_SECT_XN,
 231                 .domain         = DOMAIN_IO,
 232         },
 233         [MT_CACHECLEAN] = {
 234                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
 235                 .domain    = DOMAIN_KERNEL,
 236         },
 237 #ifndef CONFIG_ARM_LPAE
 238         [MT_MINICLEAN] = {
 239                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
 240                 .domain    = DOMAIN_KERNEL,
 241         },
 242 #endif
 243         [MT_LOW_VECTORS] = {
 244                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 245                                 L_PTE_RDONLY,
 246                 .prot_l1   = PMD_TYPE_TABLE,
 247                 .domain    = DOMAIN_USER,
 248         },
 249         [MT_HIGH_VECTORS] = {
 250                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 251                                 L_PTE_USER | L_PTE_RDONLY,
 252                 .prot_l1   = PMD_TYPE_TABLE,
 253                 .domain    = DOMAIN_USER,
 254         },
 255         [MT_MEMORY] = {
 256                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
 257                 .prot_l1   = PMD_TYPE_TABLE,
 258                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
 259                 .domain    = DOMAIN_KERNEL,
 260         },
 261         [MT_ROM] = {
 262                 .prot_sect = PMD_TYPE_SECT,
 263                 .domain    = DOMAIN_KERNEL,
 264         },
 265         [MT_MEMORY_NONCACHED] = {
 266                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 267                                 L_PTE_MT_BUFFERABLE,
 268                 .prot_l1   = PMD_TYPE_TABLE,
 269                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
 270                 .domain    = DOMAIN_KERNEL,
 271         },
 272         [MT_MEMORY_DTCM] = {
 273                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 274                                 L_PTE_XN,
 275                 .prot_l1   = PMD_TYPE_TABLE,
 276                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
 277                 .domain    = DOMAIN_KERNEL,
 278         },
 279         [MT_MEMORY_ITCM] = {
 280                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
 281                 .prot_l1   = PMD_TYPE_TABLE,
 282                 .domain    = DOMAIN_KERNEL,
 283         },
 284         [MT_MEMORY_SO] = {
 285                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 286                                 L_PTE_MT_UNCACHED,
 287                 .prot_l1   = PMD_TYPE_TABLE,
 288                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S |
 289                                 PMD_SECT_UNCACHED | PMD_SECT_XN,
 290                 .domain    = DOMAIN_KERNEL,
 291         },
 292         [MT_MEMORY_DMA_READY] = {
 293                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
 294                 .prot_l1   = PMD_TYPE_TABLE,
 295                 .domain    = DOMAIN_KERNEL,
 296         },
 297 };
 298
 299 const struct mem_type *get_mem_type(unsigned int type)
 300 {
 301         return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
 302 }
 303 EXPORT_SYMBOL(get_mem_type);
 304
 305 /*
 306  * Adjust the PMD section entries according to the CPU in use.
 307  */
 308 static void __init build_mem_type_table(void)
 309 {
 310         struct cachepolicy *cp;
 311         unsigned int cr = get_cr();
 312         pteval_t user_pgprot, kern_pgprot, vecs_pgprot;
 313         int cpu_arch = cpu_architecture();
 314         int i;
 315
 316         if (cpu_arch < CPU_ARCH_ARMv6) {
 317 #if defined(CONFIG_CPU_DCACHE_DISABLE)
 318                 if (cachepolicy > CPOLICY_BUFFERED)
 319                         cachepolicy = CPOLICY_BUFFERED;
 320 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
 321                 if (cachepolicy > CPOLICY_WRITETHROUGH)
 322                         cachepolicy = CPOLICY_WRITETHROUGH;
 323 #endif
 324         }
 325         if (cpu_arch < CPU_ARCH_ARMv5) {
 326                 if (cachepolicy >= CPOLICY_WRITEALLOC)
 327                         cachepolicy = CPOLICY_WRITEBACK;
 328                 ecc_mask = 0;
 329         }
 330         if (is_smp())
 331                 cachepolicy = CPOLICY_WRITEALLOC;
 332
 333         /*
 334          * Strip out features not present on earlier architectures.
 335          * Pre-ARMv5 CPUs don't have TEX bits.  Pre-ARMv6 CPUs or those
 336          * without extended page tables don't have the 'Shared' bit.
 337          */
 338         if (cpu_arch < CPU_ARCH_ARMv5)
 339                 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
 340                         mem_types[i].prot_sect &= ~PMD_SECT_TEX(7);
 341         if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3())
 342                 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
 343                         mem_types[i].prot_sect &= ~PMD_SECT_S;
 344
 345         /*
 346          * ARMv5 and lower, bit 4 must be set for page tables (was: cache
 347          * "update-able on write" bit on ARM610).  However, Xscale and
 348          * Xscale3 require this bit to be cleared.
 349          */
 350         if (cpu_is_xscale() || cpu_is_xsc3()) {
 351                 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
 352                         mem_types[i].prot_sect &= ~PMD_BIT4;
 353                         mem_types[i].prot_l1 &= ~PMD_BIT4;
 354                 }
 355         } else if (cpu_arch < CPU_ARCH_ARMv6) {
 356                 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
 357                         if (mem_types[i].prot_l1)
 358                                 mem_types[i].prot_l1 |= PMD_BIT4;
 359                         if (mem_types[i].prot_sect)
 360                                 mem_types[i].prot_sect |= PMD_BIT4;
 361                 }
 362         }
 363
 364         /*
 365          * Mark the device areas according to the CPU/architecture.
 366          */
 367         if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
 368                 if (!cpu_is_xsc3()) {
 369                         /*
 370                          * Mark device regions on ARMv6+ as execute-never
 371                          * to prevent speculative instruction fetches.
 372                          */
 373                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
 374                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
 375                         mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
 376                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
 377                 }
 378                 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
 379                         /*
 380                          * For ARMv7 with TEX remapping,
 381                          * - shared device is SXCB=1100
 382                          * - nonshared device is SXCB=0100
 383                          * - write combine device mem is SXCB=0001
 384                          * (Uncached Normal memory)
 385                          */
 386                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
 387                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
 388                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
 389                 } else if (cpu_is_xsc3()) {
 390                         /*
 391                          * For Xscale3,
 392                          * - shared device is TEXCB=00101
 393                          * - nonshared device is TEXCB=01000
 394                          * - write combine device mem is TEXCB=00100
 395                          * (Inner/Outer Uncacheable in xsc3 parlance)
 396                          */
 397                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED;
 398                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
 399                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
 400                 } else {
 401                         /*
 402                          * For ARMv6 and ARMv7 without TEX remapping,
 403                          * - shared device is TEXCB=00001
 404                          * - nonshared device is TEXCB=01000
 405                          * - write combine device mem is TEXCB=00100
 406                          * (Uncached Normal in ARMv6 parlance).
 407                          */
 408                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
 409                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
 410                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
 411                 }
 412         } else {
 413                 /*
 414                  * On others, write combining is "Uncached/Buffered"
 415                  */
 416                 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
 417         }
 418
 419         /*
 420          * Now deal with the memory-type mappings
 421          */
 422         cp = &cache_policies[cachepolicy];
 423         vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
 424
 425         /*
 426          * Only use write-through for non-SMP systems
 427          */
 428         if (!is_smp() && cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH)
 429                 vecs_pgprot = cache_policies[CPOLICY_WRITETHROUGH].pte;
 430
 431         /*
 432          * Enable CPU-specific coherency if supported.
 433          * (Only available on XSC3 at the moment.)
 434          */
 435         if (arch_is_coherent() && cpu_is_xsc3()) {
 436                 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
 437                 mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
 438                 mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED;
 439                 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
 440                 mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
 441         }
 442         /*
 443          * ARMv6 and above have extended page tables.
 444          */
 445         if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
 446 #ifndef CONFIG_ARM_LPAE
 447                 /*
 448                  * Mark cache clean areas and XIP ROM read only
 449                  * from SVC mode and no access from userspace.
 450                  */
 451                 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 452                 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 453                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 454 #endif
 455
 456                 if (is_smp()) {
 457                         /*
 458                          * Mark memory with the "shared" attribute
 459                          * for SMP systems
 460                          */
 461                         user_pgprot |= L_PTE_SHARED;
 462                         kern_pgprot |= L_PTE_SHARED;
 463                         vecs_pgprot |= L_PTE_SHARED;
 464                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
 465                         mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
 466                         mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
 467                         mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
 468                         mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
 469                         mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
 470                         mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED;
 471                         mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
 472                         mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
 473                 }
 474         }
 475
 476         /*
 477          * Non-cacheable Normal - intended for memory areas that must
 478          * not cause dirty cache line writebacks when used
 479          */
 480         if (cpu_arch >= CPU_ARCH_ARMv6) {
 481                 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
 482                         /* Non-cacheable Normal is XCB = 001 */
 483                         mem_types[MT_MEMORY_NONCACHED].prot_sect |=
 484                                 PMD_SECT_BUFFERED;
 485                 } else {
 486                         /* For both ARMv6 and non-TEX-remapping ARMv7 */
 487                         mem_types[MT_MEMORY_NONCACHED].prot_sect |=
 488                                 PMD_SECT_TEX(1);
 489                 }
 490         } else {
 491                 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
 492         }
 493
 494 #ifdef CONFIG_ARM_LPAE
 495         /*
 496          * Do not generate access flag faults for the kernel mappings.
 497          */
 498         for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
 499                 mem_types[i].prot_pte |= PTE_EXT_AF;
 500                 if (mem_types[i].prot_sect)
 501                         mem_types[i].prot_sect |= PMD_SECT_AF;
 502         }
 503         kern_pgprot |= PTE_EXT_AF;
 504         vecs_pgprot |= PTE_EXT_AF;
 505 #endif
 506
 507         for (i = 0; i < 16; i++) {
 508                 unsigned long v = pgprot_val(protection_map[i]);
 509                 protection_map[i] = __pgprot(v | user_pgprot);
 510         }
 511
 512         mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
 513         mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
 514
 515         pgprot_user   = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
 516         pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
 517                                  L_PTE_DIRTY | kern_pgprot);
 518
 519         mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
 520         mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
 521         mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
 522         mem_types[MT_MEMORY].prot_pte |= kern_pgprot;
 523         mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot;
 524         mem_types[MT_MEMORY_NONCACHED].prot_sect |= ecc_mask;
 525         mem_types[MT_ROM].prot_sect |= cp->pmd;
 526
 527         switch (cp->pmd) {
 528         case PMD_SECT_WT:
 529                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
 530                 break;
 531         case PMD_SECT_WB:
 532         case PMD_SECT_WBWA:
 533                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
 534                 break;
 535         }
 536         printk("Memory policy: ECC %sabled, Data cache %s\n",
 537                 ecc_mask ? "en" : "dis", cp->policy);
 538
 539         for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
 540                 struct mem_type *t = &mem_types[i];
 541                 if (t->prot_l1)
 542                         t->prot_l1 |= PMD_DOMAIN(t->domain);
 543                 if (t->prot_sect)
 544                         t->prot_sect |= PMD_DOMAIN(t->domain);
 545         }
 546 }
 547
 548 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
 549 pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
 550                               unsigned long size, pgprot_t vma_prot)
 551 {
 552         if (!pfn_valid(pfn))
 553                 return pgprot_noncached(vma_prot);
 554         else if (file->f_flags & O_SYNC)
 555                 return pgprot_writecombine(vma_prot);
 556         return vma_prot;
 557 }
 558 EXPORT_SYMBOL(phys_mem_access_prot);
 559 #endif
 560
 561 #define vectors_base()  (vectors_high() ? 0xffff0000 : 0)
 562
 563 static void __init *early_alloc_aligned(unsigned long sz, unsigned long align)
 564 {
 565         void *ptr = __va(memblock_alloc(sz, align));
 566         memset(ptr, 0, sz);
 567         return ptr;
 568 }
 569
 570 static void __init *early_alloc(unsigned long sz)
 571 {
 572         return early_alloc_aligned(sz, sz);
 573 }
 574
 575 static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot)
 576 {
 577         if (pmd_none(*pmd)) {
 578                 pte_t *pte = early_alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE);
 579                 __pmd_populate(pmd, __pa(pte), prot);
 580         }
 581         BUG_ON(pmd_bad(*pmd));
 582         return pte_offset_kernel(pmd, addr);
 583 }
 584
 585 static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
 586                                   unsigned long end, unsigned long pfn,
 587                                   const struct mem_type *type)
 588 {
 589         pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1);
 590         do {
 591                 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0);
 592                 pfn++;
 593         } while (pte++, addr += PAGE_SIZE, addr != end);
 594 }
 595
 596 static void __init alloc_init_section(pud_t *pud, unsigned long addr,
 597                                       unsigned long end, phys_addr_t phys,
 598                                       const struct mem_type *type)
 599 {
 600         pmd_t *pmd = pmd_offset(pud, addr);
 601
 602         /*
 603          * Try a section mapping - end, addr and phys must all be aligned
 604          * to a section boundary.  Note that PMDs refer to the individual
 605          * L1 entries, whereas PGDs refer to a group of L1 entries making
 606          * up one logical pointer to an L2 table.
 607          */
 608         if (type->prot_sect && ((addr | end | phys) & ~SECTION_MASK) == 0) {
 609                 pmd_t *p = pmd;
 610
 611 #ifndef CONFIG_ARM_LPAE
 612                 if (addr & SECTION_SIZE)
 613                         pmd++;
 614 #endif
 615
 616                 do {
 617                         *pmd = __pmd(phys | type->prot_sect);
 618                         phys += SECTION_SIZE;
 619                 } while (pmd++, addr += SECTION_SIZE, addr != end);
 620
 621                 flush_pmd_entry(p);
 622         } else {
 623                 /*
 624                  * No need to loop; pte's aren't interested in the
 625                  * individual L1 entries.
 626                  */
 627                 alloc_init_pte(pmd, addr, end, __phys_to_pfn(phys), type);
 628         }
 629 }
 630
 631 static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
 632         unsigned long end, unsigned long phys, const struct mem_type *type)
 633 {
 634         pud_t *pud = pud_offset(pgd, addr);
 635         unsigned long next;
 636
 637         do {
 638                 next = pud_addr_end(addr, end);
 639                 alloc_init_section(pud, addr, next, phys, type);
 640                 phys += next - addr;
 641         } while (pud++, addr = next, addr != end);
 642 }
 643
 644 #ifndef CONFIG_ARM_LPAE
 645 static void __init create_36bit_mapping(struct map_desc *md,
 646                                         const struct mem_type *type)
 647 {
 648         unsigned long addr, length, end;
 649         phys_addr_t phys;
 650         pgd_t *pgd;
 651
 652         addr = md->virtual;
 653         phys = __pfn_to_phys(md->pfn);
 654         length = PAGE_ALIGN(md->length);
 655
 656         if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
 657                 printk(KERN_ERR "MM: CPU does not support supersection "
 658                        "mapping for 0x%08llx at 0x%08lx\n",
 659                        (long long)__pfn_to_phys((u64)md->pfn), addr);
 660                 return;
 661         }
 662
 663         /* N.B. ARMv6 supersections are only defined to work with domain 0.
 664          *      Since domain assignments can in fact be arbitrary, the
 665          *      'domain == 0' check below is required to insure that ARMv6
 666          *      supersections are only allocated for domain 0 regardless
 667          *      of the actual domain assignments in use.
 668          */
 669         if (type->domain) {
 670                 printk(KERN_ERR "MM: invalid domain in supersection "
 671                        "mapping for 0x%08llx at 0x%08lx\n",
 672                        (long long)__pfn_to_phys((u64)md->pfn), addr);
 673                 return;
 674         }
 675
 676         if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
 677                 printk(KERN_ERR "MM: cannot create mapping for 0x%08llx"
 678                        " at 0x%08lx invalid alignment\n",
 679                        (long long)__pfn_to_phys((u64)md->pfn), addr);
 680                 return;
 681         }
 682
 683         /*
 684          * Shift bits [35:32] of address into bits [23:20] of PMD
 685          * (See ARMv6 spec).
 686          */
 687         phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
 688
 689         pgd = pgd_offset_k(addr);
 690         end = addr + length;
 691         do {
 692                 pud_t *pud = pud_offset(pgd, addr);
 693                 pmd_t *pmd = pmd_offset(pud, addr);
 694                 int i;
 695
 696                 for (i = 0; i < 16; i++)
 697                         *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER);
 698
 699                 addr += SUPERSECTION_SIZE;
 700                 phys += SUPERSECTION_SIZE;
 701                 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
 702         } while (addr != end);
 703 }
 704 #endif  /* !CONFIG_ARM_LPAE */
 705
 706 /*
 707  * Create the page directory entries and any necessary
 708  * page tables for the mapping specified by `md'.  We
 709  * are able to cope here with varying sizes and address
 710  * offsets, and we take full advantage of sections and
 711  * supersections.
 712  */
 713 static void __init create_mapping(struct map_desc *md)
 714 {
 715         unsigned long addr, length, end;
 716         phys_addr_t phys;
 717         const struct mem_type *type;
 718         pgd_t *pgd;
 719
 720         if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
 721                 printk(KERN_WARNING "BUG: not creating mapping for 0x%08llx"
 722                        " at 0x%08lx in user region\n",
 723                        (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
 724                 return;
 725         }
 726
 727         if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
 728             md->virtual >= PAGE_OFFSET &&
 729             (md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) {
 730                 printk(KERN_WARNING "BUG: mapping for 0x%08llx"
 731                        " at 0x%08lx out of vmalloc space\n",
 732                        (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
 733         }
 734
 735         type = &mem_types[md->type];
 736
 737 #ifndef CONFIG_ARM_LPAE
 738         /*
 739          * Catch 36-bit addresses
 740          */
 741         if (md->pfn >= 0x100000) {
 742                 create_36bit_mapping(md, type);
 743                 return;
 744         }
 745 #endif
 746
 747         addr = md->virtual & PAGE_MASK;
 748         phys = __pfn_to_phys(md->pfn);
 749         length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
 750
 751         if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
 752                 printk(KERN_WARNING "BUG: map for 0x%08llx at 0x%08lx can not "
 753                        "be mapped using pages, ignoring.\n",
 754                        (long long)__pfn_to_phys(md->pfn), addr);
 755                 return;
 756         }
 757
 758         pgd = pgd_offset_k(addr);
 759         end = addr + length;
 760         do {
 761                 unsigned long next = pgd_addr_end(addr, end);
 762
 763                 alloc_init_pud(pgd, addr, next, phys, type);
 764
 765                 phys += next - addr;
 766                 addr = next;
 767         } while (pgd++, addr != end);
 768 }
 769
 770 /*
 771  * Create the architecture specific mappings
 772  */
 773 void __init iotable_init(struct map_desc *io_desc, int nr)
 774 {
 775         struct map_desc *md;
 776         struct vm_struct *vm;
 777
 778         if (!nr)
 779                 return;
 780
 781         vm = early_alloc_aligned(sizeof(*vm) * nr, __alignof__(*vm));
 782
 783         for (md = io_desc; nr; md++, nr--) {
 784                 create_mapping(md);
 785                 vm->addr = (void *)(md->virtual & PAGE_MASK);
 786                 vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
 787                 vm->phys_addr = __pfn_to_phys(md->pfn);
 788                 vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING;
 789                 vm->flags |= VM_ARM_MTYPE(md->type);
 790                 vm->caller = iotable_init;
 791                 vm_area_add_early(vm++);
 792         }
 793 }
 794
 795 void __init vm_reserve_area_early(unsigned long addr, unsigned long size,
 796                                   void *caller)
 797 {
 798         struct vm_struct *vm;
 799
 800         vm = early_alloc_aligned(sizeof(*vm), __alignof__(*vm));
 801         vm->addr = (void *)addr;
 802         vm->size = size;
 803         vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING;
 804         vm->caller = caller;
 805         vm_area_add_early(vm);
 806 }
 807
 808 #ifndef CONFIG_ARM_LPAE
 809
 810 /*
 811  * The Linux PMD is made of two consecutive section entries covering 2MB
 812  * (see definition in include/asm/pgtable-2level.h).  However a call to
 813  * create_mapping() may optimize static mappings by using individual
 814  * 1MB section mappings.  This leaves the actual PMD potentially half
 815  * initialized if the top or bottom section entry isn't used, leaving it
 816  * open to problems if a subsequent ioremap() or vmalloc() tries to use
 817  * the virtual space left free by that unused section entry.
 818  *
 819  * Let's avoid the issue by inserting dummy vm entries covering the unused
 820  * PMD halves once the static mappings are in place.
 821  */
 822
 823 static void __init pmd_empty_section_gap(unsigned long addr)
 824 {
 825         vm_reserve_area_early(addr, SECTION_SIZE, pmd_empty_section_gap);
 826 }
 827
 828 static void __init fill_pmd_gaps(void)
 829 {
 830         struct vm_struct *vm;
 831         unsigned long addr, next = 0;
 832         pmd_t *pmd;
 833
 834         /* we're still single threaded hence no lock needed here */
 835         for (vm = vmlist; vm; vm = vm->next) {
 836                 if (!(vm->flags & VM_ARM_STATIC_MAPPING))
 837                         continue;
 838                 addr = (unsigned long)vm->addr;
 839                 if (addr < next)
 840                         continue;
 841
 842                 /*
 843                  * Check if this vm starts on an odd section boundary.
 844                  * If so and the first section entry for this PMD is free
 845                  * then we block the corresponding virtual address.
 846                  */
 847                 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
 848                         pmd = pmd_off_k(addr);
 849                         if (pmd_none(*pmd))
 850                                 pmd_empty_section_gap(addr & PMD_MASK);
 851                 }
 852
 853                 /*
 854                  * Then check if this vm ends on an odd section boundary.
 855                  * If so and the second section entry for this PMD is empty
 856                  * then we block the corresponding virtual address.
 857                  */
 858                 addr += vm->size;
 859                 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
 860                         pmd = pmd_off_k(addr) + 1;
 861                         if (pmd_none(*pmd))
 862                                 pmd_empty_section_gap(addr);
 863                 }
 864
 865                 /* no need to look at any vm entry until we hit the next PMD */
 866                 next = (addr + PMD_SIZE - 1) & PMD_MASK;
 867         }
 868 }
 869
 870 #else
 871 #define fill_pmd_gaps() do { } while (0)
 872 #endif
 873
 874 #if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H)
 875 static void __init pci_reserve_io(void)
 876 {
 877         struct vm_struct *vm;
 878         unsigned long addr;
 879
 880         /* we're still single threaded hence no lock needed here */
 881         for (vm = vmlist; vm; vm = vm->next) {
 882                 if (!(vm->flags & VM_ARM_STATIC_MAPPING))
 883                         continue;
 884                 addr = (unsigned long)vm->addr;
 885                 addr &= ~(SZ_2M - 1);
 886                 if (addr == PCI_IO_VIRT_BASE)
 887                         return;
 888
 889         }
 890         vm_reserve_area_early(PCI_IO_VIRT_BASE, SZ_2M, pci_reserve_io);
 891 }
 892 #else
 893 #define pci_reserve_io() do { } while (0)
 894 #endif
 895
 896 static void * __initdata vmalloc_min =
 897         (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET);
 898
 899 /*
 900  * vmalloc=size forces the vmalloc area to be exactly 'size'
 901  * bytes. This can be used to increase (or decrease) the vmalloc
 902  * area - the default is 240m.
 903  */
 904 static int __init early_vmalloc(char *arg)
 905 {
 906         unsigned long vmalloc_reserve = memparse(arg, NULL);
 907
 908         if (vmalloc_reserve < SZ_16M) {
 909                 vmalloc_reserve = SZ_16M;
 910                 printk(KERN_WARNING
 911                         "vmalloc area too small, limiting to %luMB\n",
 912                         vmalloc_reserve >> 20);
 913         }
 914
 915         if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) {
 916                 vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M);
 917                 printk(KERN_WARNING
 918                         "vmalloc area is too big, limiting to %luMB\n",
 919                         vmalloc_reserve >> 20);
 920         }
 921
 922         vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve);
 923         return 0;
 924 }
 925 early_param("vmalloc", early_vmalloc);
 926
 927 phys_addr_t arm_lowmem_limit __initdata = 0;
 928
 929 void __init sanity_check_meminfo(void)
 930 {
 931         int i, j, highmem = 0;
 932
 933         for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
 934                 struct membank *bank = &meminfo.bank[j];
 935                 *bank = meminfo.bank[i];
 936
 937                 if (bank->start > ULONG_MAX)
 938                         highmem = 1;
 939
 940 #ifdef CONFIG_HIGHMEM
 941                 if (__va(bank->start) >= vmalloc_min ||
 942                     __va(bank->start) < (void *)PAGE_OFFSET)
 943                         highmem = 1;
 944
 945                 bank->highmem = highmem;
 946
 947                 /*
 948                  * Split those memory banks which are partially overlapping
 949                  * the vmalloc area greatly simplifying things later.
 950                  */
 951                 if (!highmem && __va(bank->start) < vmalloc_min &&
 952                     bank->size > vmalloc_min - __va(bank->start)) {
 953                         if (meminfo.nr_banks >= NR_BANKS) {
 954                                 printk(KERN_CRIT "NR_BANKS too low, "
 955                                                  "ignoring high memory\n");
 956                         } else {
 957                                 memmove(bank + 1, bank,
 958                                         (meminfo.nr_banks - i) * sizeof(*bank));
 959                                 meminfo.nr_banks++;
 960                                 i++;
 961                                 bank[1].size -= vmalloc_min - __va(bank->start);
 962                                 bank[1].start = __pa(vmalloc_min - 1) + 1;
 963                                 bank[1].highmem = highmem = 1;
 964                                 j++;
 965                         }
 966                         bank->size = vmalloc_min - __va(bank->start);
 967                 }
 968 #else
 969                 bank->highmem = highmem;
 970
 971                 /*
 972                  * Highmem banks not allowed with !CONFIG_HIGHMEM.
 973                  */
 974                 if (highmem) {
 975                         printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx "
 976                                "(!CONFIG_HIGHMEM).\n",
 977                                (unsigned long long)bank->start,
 978                                (unsigned long long)bank->start + bank->size - 1);
 979                         continue;
 980                 }
 981
 982                 /*
 983                  * Check whether this memory bank would entirely overlap
 984                  * the vmalloc area.
 985                  */
 986                 if (__va(bank->start) >= vmalloc_min ||
 987                     __va(bank->start) < (void *)PAGE_OFFSET) {
 988                         printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx "
 989                                "(vmalloc region overlap).\n",
 990                                (unsigned long long)bank->start,
 991                                (unsigned long long)bank->start + bank->size - 1);
 992                         continue;
 993                 }
 994
 995                 /*
 996                  * Check whether this memory bank would partially overlap
 997                  * the vmalloc area.
 998                  */
 999                 if (__va(bank->start + bank->size) > vmalloc_min ||
1000                     __va(bank->start + bank->size) < __va(bank->start)) {
1001                         unsigned long newsize = vmalloc_min - __va(bank->start);
1002                         printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx "
1003                                "to -%.8llx (vmalloc region overlap).\n",
1004                                (unsigned long long)bank->start,
1005                                (unsigned long long)bank->start + bank->size - 1,
1006                                (unsigned long long)bank->start + newsize - 1);
1007                         bank->size = newsize;
1008                 }
1009 #endif
1010                 if (!bank->highmem && bank->start + bank->size > arm_lowmem_limit)
1011                         arm_lowmem_limit = bank->start + bank->size;
1012
1013                 j++;
1014         }
1015 #ifdef CONFIG_HIGHMEM
1016         if (highmem) {
1017                 const char *reason = NULL;
1018
1019                 if (cache_is_vipt_aliasing()) {
1020                         /*
1021                          * Interactions between kmap and other mappings
1022                          * make highmem support with aliasing VIPT caches
1023                          * rather difficult.
1024                          */
1025                         reason = "with VIPT aliasing cache";
1026                 }
1027                 if (reason) {
1028                         printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n",
1029                                 reason);
1030                         while (j > 0 && meminfo.bank[j - 1].highmem)
1031                                 j--;
1032                 }
1033         }
1034 #endif
1035         meminfo.nr_banks = j;
1036         high_memory = __va(arm_lowmem_limit - 1) + 1;
1037         memblock_set_current_limit(arm_lowmem_limit);
1038 }
1039
1040 static inline void prepare_page_table(void)
1041 {
1042         unsigned long addr;
1043         phys_addr_t end;
1044
1045         /*
1046          * Clear out all the mappings below the kernel image.
1047          */
1048         for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE)
1049                 pmd_clear(pmd_off_k(addr));
1050
1051 #ifdef CONFIG_XIP_KERNEL
1052         /* The XIP kernel is mapped in the module area -- skip over it */
1053         addr = ((unsigned long)_etext + PMD_SIZE - 1) & PMD_MASK;
1054 #endif
1055         for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE)
1056                 pmd_clear(pmd_off_k(addr));
1057
1058         /*
1059          * Find the end of the first block of lowmem.
1060          */
1061         end = memblock.memory.regions[0].base + memblock.memory.regions[0].size;
1062         if (end >= arm_lowmem_limit)
1063                 end = arm_lowmem_limit;
1064
1065         /*
1066          * Clear out all the kernel space mappings, except for the first
1067          * memory bank, up to the vmalloc region.
1068          */
1069         for (addr = __phys_to_virt(end);
1070              addr < VMALLOC_START; addr += PMD_SIZE)
1071                 pmd_clear(pmd_off_k(addr));
1072 }
1073
1074 #ifdef CONFIG_ARM_LPAE
1075 /* the first page is reserved for pgd */
1076 #define SWAPPER_PG_DIR_SIZE     (PAGE_SIZE + \
1077                                  PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t))
1078 #else
1079 #define SWAPPER_PG_DIR_SIZE     (PTRS_PER_PGD * sizeof(pgd_t))
1080 #endif
1081
1082 /*
1083  * Reserve the special regions of memory
1084  */
1085 void __init arm_mm_memblock_reserve(void)
1086 {
1087         /*
1088          * Reserve the page tables.  These are already in use,
1089          * and can only be in node 0.
1090          */
1091         memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE);
1092
1093 #ifdef CONFIG_SA1111
1094         /*
1095          * Because of the SA1111 DMA bug, we want to preserve our
1096          * precious DMA-able memory...
1097          */
1098         memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
1099 #endif
1100 }
1101
1102 /*
1103  * Set up the device mappings.  Since we clear out the page tables for all
1104  * mappings above VMALLOC_START, we will remove any debug device mappings.
1105  * This means you have to be careful how you debug this function, or any
1106  * called function.  This means you can't use any function or debugging
1107  * method which may touch any device, otherwise the kernel _will_ crash.
1108  */
1109 static void __init devicemaps_init(struct machine_desc *mdesc)
1110 {
1111         struct map_desc map;
1112         unsigned long addr;
1113         void *vectors;
1114
1115         /*
1116          * Allocate the vector page early.
1117          */
1118         vectors = early_alloc(PAGE_SIZE);
1119
1120         early_trap_init(vectors);
1121
1122         for (addr = VMALLOC_START; addr; addr += PMD_SIZE)
1123                 pmd_clear(pmd_off_k(addr));
1124
1125         /*
1126          * Map the kernel if it is XIP.
1127          * It is always first in the modulearea.
1128          */
1129 #ifdef CONFIG_XIP_KERNEL
1130         map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
1131         map.virtual = MODULES_VADDR;
1132         map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK;
1133         map.type = MT_ROM;
1134         create_mapping(&map);
1135 #endif
1136
1137         /*
1138          * Map the cache flushing regions.
1139          */
1140 #ifdef FLUSH_BASE
1141         map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
1142         map.virtual = FLUSH_BASE;
1143         map.length = SZ_1M;
1144         map.type = MT_CACHECLEAN;
1145         create_mapping(&map);
1146 #endif
1147 #ifdef FLUSH_BASE_MINICACHE
1148         map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
1149         map.virtual = FLUSH_BASE_MINICACHE;
1150         map.length = SZ_1M;
1151         map.type = MT_MINICLEAN;
1152         create_mapping(&map);
1153 #endif
1154
1155         /*
1156          * Create a mapping for the machine vectors at the high-vectors
1157          * location (0xffff0000).  If we aren't using high-vectors, also
1158          * create a mapping at the low-vectors virtual address.
1159          */
1160         map.pfn = __phys_to_pfn(virt_to_phys(vectors));
1161         map.virtual = 0xffff0000;
1162         map.length = PAGE_SIZE;
1163         map.type = MT_HIGH_VECTORS;
1164         create_mapping(&map);
1165
1166         if (!vectors_high()) {
1167                 map.virtual = 0;
1168                 map.type = MT_LOW_VECTORS;
1169                 create_mapping(&map);
1170         }
1171
1172         /*
1173          * Ask the machine support to map in the statically mapped devices.
1174          */
1175         if (mdesc->map_io)
1176                 mdesc->map_io();
1177         fill_pmd_gaps();
1178
1179         /* Reserve fixed i/o space in VMALLOC region */
1180         pci_reserve_io();
1181
1182         /*
1183          * Finally flush the caches and tlb to ensure that we're in a
1184          * consistent state wrt the writebuffer.  This also ensures that
1185          * any write-allocated cache lines in the vector page are written
1186          * back.  After this point, we can start to touch devices again.
1187          */
1188         local_flush_tlb_all();
1189         flush_cache_all();
1190 }
1191
1192 static void __init kmap_init(void)
1193 {
1194 #ifdef CONFIG_HIGHMEM
1195         pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE),
1196                 PKMAP_BASE, _PAGE_KERNEL_TABLE);
1197 #endif
1198 }
1199
1200 static void __init map_lowmem(void)
1201 {
1202         struct memblock_region *reg;
1203
1204         /* Map all the lowmem memory banks. */
1205         for_each_memblock(memory, reg) {
1206                 phys_addr_t start = reg->base;
1207                 phys_addr_t end = start + reg->size;
1208                 struct map_desc map;
1209
1210                 if (end > arm_lowmem_limit)
1211                         end = arm_lowmem_limit;
1212                 if (start >= end)
1213                         break;
1214
1215                 map.pfn = __phys_to_pfn(start);
1216                 map.virtual = __phys_to_virt(start);
1217                 map.length = end - start;
1218                 map.type = MT_MEMORY;
1219
1220                 create_mapping(&map);
1221         }
1222 }
1223
1224 /*
1225  * paging_init() sets up the page tables, initialises the zone memory
1226  * maps, and sets up the zero page, bad page and bad page tables.
1227  */
1228 void __init paging_init(struct machine_desc *mdesc)
1229 {
1230         void *zero_page;
1231
1232         memblock_set_current_limit(arm_lowmem_limit);
1233
1234         build_mem_type_table();
1235         prepare_page_table();
1236         map_lowmem();
1237         dma_contiguous_remap();
1238         devicemaps_init(mdesc);
1239         kmap_init();
1240
1241         top_pmd = pmd_off_k(0xffff0000);
1242
1243         /* allocate the zero page. */
1244         zero_page = early_alloc(PAGE_SIZE);
1245
1246         bootmem_init();
1247
1248         empty_zero_page = virt_to_page(zero_page);
1249         __flush_dcache_page(NULL, empty_zero_page);
1250 }