1 /* linux/arch/arm/mach-s3c6410/mach-smdk6410.c
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
14 #include <linux/kernel.h>
15 #include <linux/types.h>
16 #include <linux/interrupt.h>
17 #include <linux/list.h>
18 #include <linux/timer.h>
19 #include <linux/init.h>
20 #include <linux/serial_core.h>
21 #include <linux/platform_device.h>
23 #include <linux/i2c.h>
25 #include <linux/gpio.h>
26 #include <linux/delay.h>
27 #include <linux/smsc911x.h>
28 #include <linux/regulator/fixed.h>
30 #ifdef CONFIG_SMDK6410_WM1190_EV1
31 #include <linux/mfd/wm8350/core.h>
32 #include <linux/mfd/wm8350/pmic.h>
35 #include <video/platform_lcd.h>
37 #include <asm/mach/arch.h>
38 #include <asm/mach/map.h>
39 #include <asm/mach/irq.h>
41 #include <mach/hardware.h>
42 #include <mach/regs-fb.h>
46 #include <asm/mach-types.h>
48 #include <plat/regs-serial.h>
49 #include <plat/regs-modem.h>
50 #include <plat/regs-gpio.h>
51 #include <plat/regs-sys.h>
52 #include <plat/regs-srom.h>
55 #include <plat/gpio-cfg.h>
57 #include <plat/s3c6410.h>
58 #include <plat/clock.h>
59 #include <plat/devs.h>
62 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
63 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
64 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
66 static struct s3c2410_uartcfg smdk6410_uartcfgs[] __initdata = {
97 /* framebuffer and LCD setup. */
99 /* GPF15 = LCD backlight control
100 * GPF13 => Panel power
101 * GPN5 = LCD nRESET signal
102 * PWM_TOUT1 => backlight brightness
105 static void smdk6410_lcd_power_set(struct plat_lcd_data *pd,
109 gpio_direction_output(S3C64XX_GPF(13), 1);
110 gpio_direction_output(S3C64XX_GPF(15), 1);
112 /* fire nRESET on power up */
113 gpio_direction_output(S3C64XX_GPN(5), 0);
115 gpio_direction_output(S3C64XX_GPN(5), 1);
118 gpio_direction_output(S3C64XX_GPF(15), 0);
119 gpio_direction_output(S3C64XX_GPF(13), 0);
123 static struct plat_lcd_data smdk6410_lcd_power_data = {
124 .set_power = smdk6410_lcd_power_set,
127 static struct platform_device smdk6410_lcd_powerdev = {
128 .name = "platform-lcd",
129 .dev.parent = &s3c_device_fb.dev,
130 .dev.platform_data = &smdk6410_lcd_power_data,
133 static struct s3c_fb_pd_win smdk6410_fb_win0 = {
134 /* this is to ensure we use win0 */
150 /* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
151 static struct s3c_fb_platdata smdk6410_lcd_pdata __initdata = {
152 .setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
153 .win[0] = &smdk6410_fb_win0,
154 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
155 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
159 * Configuring Ethernet on SMDK6410
161 * Both CS8900A and LAN9115 chips share one chip select mediated by CFG6.
162 * The constant address below corresponds to nCS1
164 * 1) Set CFGB2 p3 ON others off, no other CFGB selects "ethernet"
165 * 2) CFG6 needs to be switched to "LAN9115" side
168 static struct resource smdk6410_smsc911x_resources[] = {
170 .start = S3C64XX_PA_XM0CSN1,
171 .end = S3C64XX_PA_XM0CSN1 + SZ_64K - 1,
172 .flags = IORESOURCE_MEM,
175 .start = S3C_EINT(10),
177 .flags = IORESOURCE_IRQ | IRQ_TYPE_LEVEL_LOW,
181 static struct smsc911x_platform_config smdk6410_smsc911x_pdata = {
182 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
183 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
184 .flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY,
185 .phy_interface = PHY_INTERFACE_MODE_MII,
189 static struct platform_device smdk6410_smsc911x = {
192 .num_resources = ARRAY_SIZE(smdk6410_smsc911x_resources),
193 .resource = &smdk6410_smsc911x_resources[0],
195 .platform_data = &smdk6410_smsc911x_pdata,
199 #ifdef CONFIG_REGULATOR
200 static struct regulator_consumer_supply smdk6410_b_pwr_5v_consumers[] = {
204 .dev_name = "0-001b",
209 .dev_name = "0-001b",
213 static struct regulator_init_data smdk6410_b_pwr_5v_data = {
217 .num_consumer_supplies = ARRAY_SIZE(smdk6410_b_pwr_5v_consumers),
218 .consumer_supplies = smdk6410_b_pwr_5v_consumers,
221 static struct fixed_voltage_config smdk6410_b_pwr_5v_pdata = {
222 .supply_name = "B_PWR_5V",
223 .microvolts = 5000000,
224 .init_data = &smdk6410_b_pwr_5v_data,
228 static struct platform_device smdk6410_b_pwr_5v = {
229 .name = "reg-fixed-voltage",
232 .platform_data = &smdk6410_b_pwr_5v_pdata,
237 static struct map_desc smdk6410_iodesc[] = {};
239 static struct platform_device *smdk6410_devices[] __initdata = {
240 #ifdef CONFIG_SMDK6410_SD_CH0
243 #ifdef CONFIG_SMDK6410_SD_CH1
250 &s3c_device_usb_hsotg,
252 #ifdef CONFIG_REGULATOR
255 &smdk6410_lcd_powerdev,
260 #ifdef CONFIG_SMDK6410_WM1190_EV1
261 /* S3C64xx internal logic & PLL */
262 static struct regulator_init_data wm8350_dcdc1_data = {
264 .name = "PVDD_INT/PVDD_PLL",
273 static struct regulator_init_data wm8350_dcdc3_data = {
281 .mode = REGULATOR_MODE_NORMAL,
284 .initial_state = PM_SUSPEND_MEM,
288 /* USB, EXT, PCM, ADC/DAC, USB, MMC */
289 static struct regulator_consumer_supply wm8350_dcdc4_consumers[] = {
293 .dev_name = "0-001b",
297 static struct regulator_init_data wm8350_dcdc4_data = {
299 .name = "PVDD_HI/PVDD_EXT/PVDD_SYS/PVCCM2MTV",
304 .num_consumer_supplies = ARRAY_SIZE(wm8350_dcdc4_consumers),
305 .consumer_supplies = wm8350_dcdc4_consumers,
309 static struct regulator_consumer_supply dcdc6_consumers[] = {
315 static struct regulator_init_data wm8350_dcdc6_data = {
321 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
323 .num_consumer_supplies = ARRAY_SIZE(dcdc6_consumers),
324 .consumer_supplies = dcdc6_consumers,
328 static struct regulator_init_data wm8350_ldo1_data = {
330 .name = "PVDD_ALIVE",
339 static struct regulator_init_data wm8350_ldo2_data = {
349 static struct regulator_init_data wm8350_ldo3_data = {
358 /* OTGi/1190-EV1 HPVDD & AVDD */
359 static struct regulator_init_data wm8350_ldo4_data = {
361 .name = "PVDD_OTGI/HPVDD/AVDD",
371 struct regulator_init_data *initdata;
372 } wm1190_regulators[] = {
373 { WM8350_DCDC_1, &wm8350_dcdc1_data },
374 { WM8350_DCDC_3, &wm8350_dcdc3_data },
375 { WM8350_DCDC_4, &wm8350_dcdc4_data },
376 { WM8350_DCDC_6, &wm8350_dcdc6_data },
377 { WM8350_LDO_1, &wm8350_ldo1_data },
378 { WM8350_LDO_2, &wm8350_ldo2_data },
379 { WM8350_LDO_3, &wm8350_ldo3_data },
380 { WM8350_LDO_4, &wm8350_ldo4_data },
383 static int __init smdk6410_wm8350_init(struct wm8350 *wm8350)
387 /* Configure the IRQ line */
388 s3c_gpio_setpull(S3C64XX_GPN(12), S3C_GPIO_PULL_UP);
390 /* Instantiate the regulators */
391 for (i = 0; i < ARRAY_SIZE(wm1190_regulators); i++)
392 wm8350_register_regulator(wm8350,
393 wm1190_regulators[i].regulator,
394 wm1190_regulators[i].initdata);
399 static struct wm8350_platform_data __initdata smdk6410_wm8350_pdata = {
400 .init = smdk6410_wm8350_init,
402 .irq_base = IRQ_BOARD_START,
406 static struct i2c_board_info i2c_devs0[] __initdata = {
407 { I2C_BOARD_INFO("24c08", 0x50), },
408 { I2C_BOARD_INFO("wm8580", 0x1b), },
410 #ifdef CONFIG_SMDK6410_WM1190_EV1
411 { I2C_BOARD_INFO("wm8350", 0x1a),
412 .platform_data = &smdk6410_wm8350_pdata,
418 static struct i2c_board_info i2c_devs1[] __initdata = {
419 { I2C_BOARD_INFO("24c128", 0x57), }, /* Samsung S524AD0XD1 */
422 static void __init smdk6410_map_io(void)
426 s3c64xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc));
427 s3c24xx_init_clocks(12000000);
428 s3c24xx_init_uarts(smdk6410_uartcfgs, ARRAY_SIZE(smdk6410_uartcfgs));
430 /* set the LCD type */
432 tmp = __raw_readl(S3C64XX_SPCON);
433 tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
434 tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
435 __raw_writel(tmp, S3C64XX_SPCON);
437 /* remove the lcd bypass */
438 tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
439 tmp &= ~MIFPCON_LCD_BYPASS;
440 __raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
443 static void __init smdk6410_machine_init(void)
447 s3c_i2c0_set_platdata(NULL);
448 s3c_i2c1_set_platdata(NULL);
449 s3c_fb_set_platdata(&smdk6410_lcd_pdata);
451 /* configure nCS1 width to 16 bits */
453 cs1 = __raw_readl(S3C64XX_SROM_BW) &
454 ~(S3C64XX_SROM_BW__CS_MASK << S3C64XX_SROM_BW__NCS1__SHIFT);
455 cs1 |= ((1 << S3C64XX_SROM_BW__DATAWIDTH__SHIFT) |
456 (1 << S3C64XX_SROM_BW__WAITENABLE__SHIFT) |
457 (1 << S3C64XX_SROM_BW__BYTEENABLE__SHIFT)) <<
458 S3C64XX_SROM_BW__NCS1__SHIFT;
459 __raw_writel(cs1, S3C64XX_SROM_BW);
461 /* set timing for nCS1 suitable for ethernet chip */
463 __raw_writel((0 << S3C64XX_SROM_BCX__PMC__SHIFT) |
464 (6 << S3C64XX_SROM_BCX__TACP__SHIFT) |
465 (4 << S3C64XX_SROM_BCX__TCAH__SHIFT) |
466 (1 << S3C64XX_SROM_BCX__TCOH__SHIFT) |
467 (0xe << S3C64XX_SROM_BCX__TACC__SHIFT) |
468 (4 << S3C64XX_SROM_BCX__TCOS__SHIFT) |
469 (0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1);
471 gpio_request(S3C64XX_GPN(5), "LCD power");
472 gpio_request(S3C64XX_GPF(13), "LCD power");
473 gpio_request(S3C64XX_GPF(15), "LCD power");
475 i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
476 i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
478 platform_add_devices(smdk6410_devices, ARRAY_SIZE(smdk6410_devices));
481 MACHINE_START(SMDK6410, "SMDK6410")
482 /* Maintainer: Ben Dooks <ben@fluff.org> */
483 .phys_io = S3C_PA_UART & 0xfff00000,
484 .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
485 .boot_params = S3C64XX_PA_SDRAM + 0x100,
487 .init_irq = s3c6410_init_irq,
488 .map_io = smdk6410_map_io,
489 .init_machine = smdk6410_machine_init,
490 .timer = &s3c24xx_timer,