arch/arm/mach-integrator/integrator_ap.c

   1 /*
   2  *  linux/arch/arm/mach-integrator/integrator_ap.c
   3  *
   4  *  Copyright (C) 2000-2003 Deep Blue Solutions Ltd
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #include <linux/types.h>
  21 #include <linux/kernel.h>
  22 #include <linux/init.h>
  23 #include <linux/list.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/slab.h>
  26 #include <linux/string.h>
  27 #include <linux/syscore_ops.h>
  28 #include <linux/amba/bus.h>
  29 #include <linux/amba/kmi.h>
  30 #include <linux/clocksource.h>
  31 #include <linux/clockchips.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/io.h>
  34 #include <linux/mtd/physmap.h>
  35 #include <linux/clk.h>
  36 #include <linux/platform_data/clk-integrator.h>
  37 #include <video/vga.h>
  38
  39 #include <mach/hardware.h>
  40 #include <mach/platform.h>
  41 #include <asm/hardware/arm_timer.h>
  42 #include <asm/setup.h>
  43 #include <asm/param.h>          /* HZ */
  44 #include <asm/mach-types.h>
  45 #include <asm/sched_clock.h>
  46
  47 #include <mach/lm.h>
  48 #include <mach/irqs.h>
  49
  50 #include <asm/mach/arch.h>
  51 #include <asm/mach/irq.h>
  52 #include <asm/mach/map.h>
  53 #include <asm/mach/pci.h>
  54 #include <asm/mach/time.h>
  55
  56 #include <plat/fpga-irq.h>
  57
  58 #include "common.h"
  59
  60 /*
  61  * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
  62  * is the (PA >> 12).
  63  *
  64  * Setup a VA for the Integrator interrupt controller (for header #0,
  65  * just for now).
  66  */
  67 #define VA_IC_BASE      __io_address(INTEGRATOR_IC_BASE)
  68 #define VA_SC_BASE      __io_address(INTEGRATOR_SC_BASE)
  69 #define VA_EBI_BASE     __io_address(INTEGRATOR_EBI_BASE)
  70 #define VA_CMIC_BASE    __io_address(INTEGRATOR_HDR_IC)
  71
  72 /*
  73  * Logical      Physical
  74  * e8000000     40000000        PCI memory              PHYS_PCI_MEM_BASE       (max 512M)
  75  * ec000000     61000000        PCI config space        PHYS_PCI_CONFIG_BASE    (max 16M)
  76  * ed000000     62000000        PCI V3 regs             PHYS_PCI_V3_BASE        (max 64k)
  77  * fee00000     60000000        PCI IO                  PHYS_PCI_IO_BASE        (max 16M)
  78  * ef000000                     Cache flush
  79  * f1000000     10000000        Core module registers
  80  * f1100000     11000000        System controller registers
  81  * f1200000     12000000        EBI registers
  82  * f1300000     13000000        Counter/Timer
  83  * f1400000     14000000        Interrupt controller
  84  * f1600000     16000000        UART 0
  85  * f1700000     17000000        UART 1
  86  * f1a00000     1a000000        Debug LEDs
  87  * f1b00000     1b000000        GPIO
  88  */
  89
  90 static struct map_desc ap_io_desc[] __initdata = {
  91         {
  92                 .virtual        = IO_ADDRESS(INTEGRATOR_HDR_BASE),
  93                 .pfn            = __phys_to_pfn(INTEGRATOR_HDR_BASE),
  94                 .length         = SZ_4K,
  95                 .type           = MT_DEVICE
  96         }, {
  97                 .virtual        = IO_ADDRESS(INTEGRATOR_SC_BASE),
  98                 .pfn            = __phys_to_pfn(INTEGRATOR_SC_BASE),
  99                 .length         = SZ_4K,
 100                 .type           = MT_DEVICE
 101         }, {
 102                 .virtual        = IO_ADDRESS(INTEGRATOR_EBI_BASE),
 103                 .pfn            = __phys_to_pfn(INTEGRATOR_EBI_BASE),
 104                 .length         = SZ_4K,
 105                 .type           = MT_DEVICE
 106         }, {
 107                 .virtual        = IO_ADDRESS(INTEGRATOR_CT_BASE),
 108                 .pfn            = __phys_to_pfn(INTEGRATOR_CT_BASE),
 109                 .length         = SZ_4K,
 110                 .type           = MT_DEVICE
 111         }, {
 112                 .virtual        = IO_ADDRESS(INTEGRATOR_IC_BASE),
 113                 .pfn            = __phys_to_pfn(INTEGRATOR_IC_BASE),
 114                 .length         = SZ_4K,
 115                 .type           = MT_DEVICE
 116         }, {
 117                 .virtual        = IO_ADDRESS(INTEGRATOR_UART0_BASE),
 118                 .pfn            = __phys_to_pfn(INTEGRATOR_UART0_BASE),
 119                 .length         = SZ_4K,
 120                 .type           = MT_DEVICE
 121         }, {
 122                 .virtual        = IO_ADDRESS(INTEGRATOR_UART1_BASE),
 123                 .pfn            = __phys_to_pfn(INTEGRATOR_UART1_BASE),
 124                 .length         = SZ_4K,
 125                 .type           = MT_DEVICE
 126         }, {
 127                 .virtual        = IO_ADDRESS(INTEGRATOR_DBG_BASE),
 128                 .pfn            = __phys_to_pfn(INTEGRATOR_DBG_BASE),
 129                 .length         = SZ_4K,
 130                 .type           = MT_DEVICE
 131         }, {
 132                 .virtual        = IO_ADDRESS(INTEGRATOR_AP_GPIO_BASE),
 133                 .pfn            = __phys_to_pfn(INTEGRATOR_AP_GPIO_BASE),
 134                 .length         = SZ_4K,
 135                 .type           = MT_DEVICE
 136         }, {
 137                 .virtual        = PCI_MEMORY_VADDR,
 138                 .pfn            = __phys_to_pfn(PHYS_PCI_MEM_BASE),
 139                 .length         = SZ_16M,
 140                 .type           = MT_DEVICE
 141         }, {
 142                 .virtual        = PCI_CONFIG_VADDR,
 143                 .pfn            = __phys_to_pfn(PHYS_PCI_CONFIG_BASE),
 144                 .length         = SZ_16M,
 145                 .type           = MT_DEVICE
 146         }, {
 147                 .virtual        = PCI_V3_VADDR,
 148                 .pfn            = __phys_to_pfn(PHYS_PCI_V3_BASE),
 149                 .length         = SZ_64K,
 150                 .type           = MT_DEVICE
 151         }
 152 };
 153
 154 static void __init ap_map_io(void)
 155 {
 156         iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
 157         vga_base = PCI_MEMORY_VADDR;
 158         pci_map_io_early(__phys_to_pfn(PHYS_PCI_IO_BASE));
 159 }
 160
 161 #define INTEGRATOR_SC_VALID_INT 0x003fffff
 162
 163 static void __init ap_init_irq(void)
 164 {
 165         /* Disable all interrupts initially. */
 166         /* Do the core module ones */
 167         writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
 168
 169         /* do the header card stuff next */
 170         writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
 171         writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
 172
 173         fpga_irq_init(VA_IC_BASE, "SC", IRQ_PIC_START,
 174                 -1, INTEGRATOR_SC_VALID_INT, NULL);
 175         integrator_clk_init(false);
 176 }
 177
 178 #ifdef CONFIG_PM
 179 static unsigned long ic_irq_enable;
 180
 181 static int irq_suspend(void)
 182 {
 183         ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE);
 184         return 0;
 185 }
 186
 187 static void irq_resume(void)
 188 {
 189         /* disable all irq sources */
 190         writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
 191         writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
 192         writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
 193
 194         writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET);
 195 }
 196 #else
 197 #define irq_suspend NULL
 198 #define irq_resume NULL
 199 #endif
 200
 201 static struct syscore_ops irq_syscore_ops = {
 202         .suspend        = irq_suspend,
 203         .resume         = irq_resume,
 204 };
 205
 206 static int __init irq_syscore_init(void)
 207 {
 208         register_syscore_ops(&irq_syscore_ops);
 209
 210         return 0;
 211 }
 212
 213 device_initcall(irq_syscore_init);
 214
 215 /*
 216  * Flash handling.
 217  */
 218 #define SC_CTRLC (VA_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET)
 219 #define SC_CTRLS (VA_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET)
 220 #define EBI_CSR1 (VA_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
 221 #define EBI_LOCK (VA_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)
 222
 223 static int ap_flash_init(struct platform_device *dev)
 224 {
 225         u32 tmp;
 226
 227         writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);
 228
 229         tmp = readl(EBI_CSR1) | INTEGRATOR_EBI_WRITE_ENABLE;
 230         writel(tmp, EBI_CSR1);
 231
 232         if (!(readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE)) {
 233                 writel(0xa05f, EBI_LOCK);
 234                 writel(tmp, EBI_CSR1);
 235                 writel(0, EBI_LOCK);
 236         }
 237         return 0;
 238 }
 239
 240 static void ap_flash_exit(struct platform_device *dev)
 241 {
 242         u32 tmp;
 243
 244         writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);
 245
 246         tmp = readl(EBI_CSR1) & ~INTEGRATOR_EBI_WRITE_ENABLE;
 247         writel(tmp, EBI_CSR1);
 248
 249         if (readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE) {
 250                 writel(0xa05f, EBI_LOCK);
 251                 writel(tmp, EBI_CSR1);
 252                 writel(0, EBI_LOCK);
 253         }
 254 }
 255
 256 static void ap_flash_set_vpp(struct platform_device *pdev, int on)
 257 {
 258         void __iomem *reg = on ? SC_CTRLS : SC_CTRLC;
 259
 260         writel(INTEGRATOR_SC_CTRL_nFLVPPEN, reg);
 261 }
 262
 263 static struct physmap_flash_data ap_flash_data = {
 264         .width          = 4,
 265         .init           = ap_flash_init,
 266         .exit           = ap_flash_exit,
 267         .set_vpp        = ap_flash_set_vpp,
 268 };
 269
 270 static struct resource cfi_flash_resource = {
 271         .start          = INTEGRATOR_FLASH_BASE,
 272         .end            = INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1,
 273         .flags          = IORESOURCE_MEM,
 274 };
 275
 276 static struct platform_device cfi_flash_device = {
 277         .name           = "physmap-flash",
 278         .id             = 0,
 279         .dev            = {
 280                 .platform_data  = &ap_flash_data,
 281         },
 282         .num_resources  = 1,
 283         .resource       = &cfi_flash_resource,
 284 };
 285
 286 static void __init ap_init(void)
 287 {
 288         unsigned long sc_dec;
 289         int i;
 290
 291         platform_device_register(&cfi_flash_device);
 292
 293         sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET);
 294         for (i = 0; i < 4; i++) {
 295                 struct lm_device *lmdev;
 296
 297                 if ((sc_dec & (16 << i)) == 0)
 298                         continue;
 299
 300                 lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
 301                 if (!lmdev)
 302                         continue;
 303
 304                 lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
 305                 lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
 306                 lmdev->resource.flags = IORESOURCE_MEM;
 307                 lmdev->irq = IRQ_AP_EXPINT0 + i;
 308                 lmdev->id = i;
 309
 310                 lm_device_register(lmdev);
 311         }
 312 }
 313
 314 /*
 315  * Where is the timer (VA)?
 316  */
 317 #define TIMER0_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER0_BASE)
 318 #define TIMER1_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER1_BASE)
 319 #define TIMER2_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER2_BASE)
 320
 321 static unsigned long timer_reload;
 322
 323 static u32 notrace integrator_read_sched_clock(void)
 324 {
 325         return -readl((void __iomem *) TIMER2_VA_BASE + TIMER_VALUE);
 326 }
 327
 328 static void integrator_clocksource_init(unsigned long inrate)
 329 {
 330         void __iomem *base = (void __iomem *)TIMER2_VA_BASE;
 331         u32 ctrl = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC;
 332         unsigned long rate = inrate;
 333
 334         if (rate >= 1500000) {
 335                 rate /= 16;
 336                 ctrl |= TIMER_CTRL_DIV16;
 337         }
 338
 339         writel(0xffff, base + TIMER_LOAD);
 340         writel(ctrl, base + TIMER_CTRL);
 341
 342         clocksource_mmio_init(base + TIMER_VALUE, "timer2",
 343                         rate, 200, 16, clocksource_mmio_readl_down);
 344         setup_sched_clock(integrator_read_sched_clock, 16, rate);
 345 }
 346
 347 static void __iomem * const clkevt_base = (void __iomem *)TIMER1_VA_BASE;
 348
 349 /*
 350  * IRQ handler for the timer
 351  */
 352 static irqreturn_t integrator_timer_interrupt(int irq, void *dev_id)
 353 {
 354         struct clock_event_device *evt = dev_id;
 355
 356         /* clear the interrupt */
 357         writel(1, clkevt_base + TIMER_INTCLR);
 358
 359         evt->event_handler(evt);
 360
 361         return IRQ_HANDLED;
 362 }
 363
 364 static void clkevt_set_mode(enum clock_event_mode mode, struct clock_event_device *evt)
 365 {
 366         u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE;
 367
 368         /* Disable timer */
 369         writel(ctrl, clkevt_base + TIMER_CTRL);
 370
 371         switch (mode) {
 372         case CLOCK_EVT_MODE_PERIODIC:
 373                 /* Enable the timer and start the periodic tick */
 374                 writel(timer_reload, clkevt_base + TIMER_LOAD);
 375                 ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
 376                 writel(ctrl, clkevt_base + TIMER_CTRL);
 377                 break;
 378         case CLOCK_EVT_MODE_ONESHOT:
 379                 /* Leave the timer disabled, .set_next_event will enable it */
 380                 ctrl &= ~TIMER_CTRL_PERIODIC;
 381                 writel(ctrl, clkevt_base + TIMER_CTRL);
 382                 break;
 383         case CLOCK_EVT_MODE_UNUSED:
 384         case CLOCK_EVT_MODE_SHUTDOWN:
 385         case CLOCK_EVT_MODE_RESUME:
 386         default:
 387                 /* Just leave in disabled state */
 388                 break;
 389         }
 390
 391 }
 392
 393 static int clkevt_set_next_event(unsigned long next, struct clock_event_device *evt)
 394 {
 395         unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);
 396
 397         writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
 398         writel(next, clkevt_base + TIMER_LOAD);
 399         writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
 400
 401         return 0;
 402 }
 403
 404 static struct clock_event_device integrator_clockevent = {
 405         .name           = "timer1",
 406         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 407         .set_mode       = clkevt_set_mode,
 408         .set_next_event = clkevt_set_next_event,
 409         .rating         = 300,
 410 };
 411
 412 static struct irqaction integrator_timer_irq = {
 413         .name           = "timer",
 414         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 415         .handler        = integrator_timer_interrupt,
 416         .dev_id         = &integrator_clockevent,
 417 };
 418
 419 static void integrator_clockevent_init(unsigned long inrate)
 420 {
 421         unsigned long rate = inrate;
 422         unsigned int ctrl = 0;
 423
 424         /* Calculate and program a divisor */
 425         if (rate > 0x100000 * HZ) {
 426                 rate /= 256;
 427                 ctrl |= TIMER_CTRL_DIV256;
 428         } else if (rate > 0x10000 * HZ) {
 429                 rate /= 16;
 430                 ctrl |= TIMER_CTRL_DIV16;
 431         }
 432         timer_reload = rate / HZ;
 433         writel(ctrl, clkevt_base + TIMER_CTRL);
 434
 435         setup_irq(IRQ_TIMERINT1, &integrator_timer_irq);
 436         clockevents_config_and_register(&integrator_clockevent,
 437                                         rate,
 438                                         1,
 439                                         0xffffU);
 440 }
 441
 442 void __init ap_init_early(void)
 443 {
 444 }
 445
 446 /*
 447  * Set up timer(s).
 448  */
 449 static void __init ap_init_timer(void)
 450 {
 451         struct clk *clk;
 452         unsigned long rate;
 453
 454         clk = clk_get_sys("ap_timer", NULL);
 455         BUG_ON(IS_ERR(clk));
 456         clk_enable(clk);
 457         rate = clk_get_rate(clk);
 458
 459         writel(0, TIMER0_VA_BASE + TIMER_CTRL);
 460         writel(0, TIMER1_VA_BASE + TIMER_CTRL);
 461         writel(0, TIMER2_VA_BASE + TIMER_CTRL);
 462
 463         integrator_clocksource_init(rate);
 464         integrator_clockevent_init(rate);
 465 }
 466
 467 static struct sys_timer ap_timer = {
 468         .init           = ap_init_timer,
 469 };
 470
 471 MACHINE_START(INTEGRATOR, "ARM-Integrator")
 472         /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
 473         .atag_offset    = 0x100,
 474         .reserve        = integrator_reserve,
 475         .map_io         = ap_map_io,
 476         .nr_irqs        = NR_IRQS_INTEGRATOR_AP,
 477         .init_early     = ap_init_early,
 478         .init_irq       = ap_init_irq,
 479         .handle_irq     = fpga_handle_irq,
 480         .timer          = &ap_timer,
 481         .init_machine   = ap_init,
 482         .restart        = integrator_restart,
 483 MACHINE_END