arch/arm/boot/dts/versatile-ab.dts

   1 /dts-v1/;
   2 /include/ "skeleton.dtsi"
   3
   4 / {
   5         model = "ARM Versatile AB";
   6         compatible = "arm,versatile-ab";
   7         #address-cells = <1>;
   8         #size-cells = <1>;
   9         interrupt-parent = <&vic>;
  10
  11         aliases {
  12                 serial0 = &uart0;
  13                 serial1 = &uart1;
  14                 serial2 = &uart2;
  15                 i2c0 = &i2c0;
  16         };
  17
  18         chosen {
  19                 stdout-path = &uart0;
  20         };
  21
  22         memory {
  23                 reg = <0x0 0x08000000>;
  24         };
  25
  26         xtal24mhz: xtal24mhz@24M {
  27                 #clock-cells = <0>;
  28                 compatible = "fixed-clock";
  29                 clock-frequency = <24000000>;
  30         };
  31
  32         core-module@10000000 {
  33                 compatible = "arm,core-module-versatile", "syscon", "simple-mfd";
  34                 reg = <0x10000000 0x200>;
  35
  36                 led@08.0 {
  37                         compatible = "register-bit-led";
  38                         offset = <0x08>;
  39                         mask = <0x01>;
  40                         label = "versatile:0";
  41                         linux,default-trigger = "heartbeat";
  42                         default-state = "on";
  43                 };
  44                 led@08.1 {
  45                         compatible = "register-bit-led";
  46                         offset = <0x08>;
  47                         mask = <0x02>;
  48                         label = "versatile:1";
  49                         linux,default-trigger = "mmc0";
  50                         default-state = "off";
  51                 };
  52                 led@08.2 {
  53                         compatible = "register-bit-led";
  54                         offset = <0x08>;
  55                         mask = <0x04>;
  56                         label = "versatile:2";
  57                         linux,default-trigger = "cpu0";
  58                         default-state = "off";
  59                 };
  60                 led@08.3 {
  61                         compatible = "register-bit-led";
  62                         offset = <0x08>;
  63                         mask = <0x08>;
  64                         label = "versatile:3";
  65                         default-state = "off";
  66                 };
  67                 led@08.4 {
  68                         compatible = "register-bit-led";
  69                         offset = <0x08>;
  70                         mask = <0x10>;
  71                         label = "versatile:4";
  72                         default-state = "off";
  73                 };
  74                 led@08.5 {
  75                         compatible = "register-bit-led";
  76                         offset = <0x08>;
  77                         mask = <0x20>;
  78                         label = "versatile:5";
  79                         default-state = "off";
  80                 };
  81                 led@08.6 {
  82                         compatible = "register-bit-led";
  83                         offset = <0x08>;
  84                         mask = <0x40>;
  85                         label = "versatile:6";
  86                         default-state = "off";
  87                 };
  88                 led@08.7 {
  89                         compatible = "register-bit-led";
  90                         offset = <0x08>;
  91                         mask = <0x80>;
  92                         label = "versatile:7";
  93                         default-state = "off";
  94                 };
  95
  96                 /* OSC1 on AB, OSC4 on PB */
  97                 osc1: cm_aux_osc@24M {
  98                         #clock-cells = <0>;
  99                         compatible = "arm,versatile-cm-auxosc";
 100                         clocks = <&xtal24mhz>;
 101                 };
 102
 103                 /* The timer clock is the 24 MHz oscillator divided to 1MHz */
 104                 timclk: timclk@1M {
 105                         #clock-cells = <0>;
 106                         compatible = "fixed-factor-clock";
 107                         clock-div = <24>;
 108                         clock-mult = <1>;
 109                         clocks = <&xtal24mhz>;
 110                 };
 111
 112                 pclk: pclk@24M {
 113                         #clock-cells = <0>;
 114                         compatible = "fixed-factor-clock";
 115                         clock-div = <1>;
 116                         clock-mult = <1>;
 117                         clocks = <&xtal24mhz>;
 118                 };
 119         };
 120
 121         flash@34000000 {
 122                 compatible = "arm,versatile-flash";
 123                 reg = <0x34000000 0x4000000>;
 124                 bank-width = <4>;
 125         };
 126
 127         i2c0: i2c@10002000 {
 128                 #address-cells = <1>;
 129                 #size-cells = <0>;
 130                 compatible = "arm,versatile-i2c";
 131                 reg = <0x10002000 0x1000>;
 132
 133                 rtc@68 {
 134                         compatible = "dallas,ds1338";
 135                         reg = <0x68>;
 136                 };
 137         };
 138
 139         net@10010000 {
 140                 compatible = "smsc,lan91c111";
 141                 reg = <0x10010000 0x10000>;
 142                 interrupts = <25>;
 143         };
 144
 145         lcd@10008000 {
 146                 compatible = "arm,versatile-lcd";
 147                 reg = <0x10008000 0x1000>;
 148         };
 149
 150         amba {
 151                 compatible = "simple-bus";
 152                 #address-cells = <1>;
 153                 #size-cells = <1>;
 154                 ranges;
 155
 156                 vic: intc@10140000 {
 157                         compatible = "arm,versatile-vic";
 158                         interrupt-controller;
 159                         #interrupt-cells = <1>;
 160                         reg = <0x10140000 0x1000>;
 161                         clear-mask = <0xffffffff>;
 162                         valid-mask = <0xffffffff>;
 163                 };
 164
 165                 sic: intc@10003000 {
 166                         compatible = "arm,versatile-sic";
 167                         interrupt-controller;
 168                         #interrupt-cells = <1>;
 169                         reg = <0x10003000 0x1000>;
 170                         interrupt-parent = <&vic>;
 171                         interrupts = <31>; /* Cascaded to vic */
 172                         clear-mask = <0xffffffff>;
 173                         /*
 174                          * Valid interrupt lines mask according to
 175                          * table 4-36 page 4-50 of ARM DUI 0225D
 176                          */
 177                         valid-mask = <0x0760031b>;
 178                 };
 179
 180                 dma@10130000 {
 181                         compatible = "arm,pl081", "arm,primecell";
 182                         reg = <0x10130000 0x1000>;
 183                         interrupts = <17>;
 184                         clocks = <&pclk>;
 185                         clock-names = "apb_pclk";
 186                 };
 187
 188                 uart0: uart@101f1000 {
 189                         compatible = "arm,pl011", "arm,primecell";
 190                         reg = <0x101f1000 0x1000>;
 191                         interrupts = <12>;
 192                         clocks = <&xtal24mhz>, <&pclk>;
 193                         clock-names = "uartclk", "apb_pclk";
 194                 };
 195
 196                 uart1: uart@101f2000 {
 197                         compatible = "arm,pl011", "arm,primecell";
 198                         reg = <0x101f2000 0x1000>;
 199                         interrupts = <13>;
 200                         clocks = <&xtal24mhz>, <&pclk>;
 201                         clock-names = "uartclk", "apb_pclk";
 202                 };
 203
 204                 uart2: uart@101f3000 {
 205                         compatible = "arm,pl011", "arm,primecell";
 206                         reg = <0x101f3000 0x1000>;
 207                         interrupts = <14>;
 208                         clocks = <&xtal24mhz>, <&pclk>;
 209                         clock-names = "uartclk", "apb_pclk";
 210                 };
 211
 212                 smc@10100000 {
 213                         compatible = "arm,primecell";
 214                         reg = <0x10100000 0x1000>;
 215                         clocks = <&pclk>;
 216                         clock-names = "apb_pclk";
 217                 };
 218
 219                 mpmc@10110000 {
 220                         compatible = "arm,primecell";
 221                         reg = <0x10110000 0x1000>;
 222                         clocks = <&pclk>;
 223                         clock-names = "apb_pclk";
 224                 };
 225
 226                 display@10120000 {
 227                         compatible = "arm,pl110", "arm,primecell";
 228                         reg = <0x10120000 0x1000>;
 229                         interrupts = <16>;
 230                         clocks = <&osc1>, <&pclk>;
 231                         clock-names = "clcd", "apb_pclk";
 232                 };
 233
 234                 sctl@101e0000 {
 235                         compatible = "arm,primecell";
 236                         reg = <0x101e0000 0x1000>;
 237                         clocks = <&pclk>;
 238                         clock-names = "apb_pclk";
 239                 };
 240
 241                 watchdog@101e1000 {
 242                         compatible = "arm,primecell";
 243                         reg = <0x101e1000 0x1000>;
 244                         interrupts = <0>;
 245                         clocks = <&pclk>;
 246                         clock-names = "apb_pclk";
 247                 };
 248
 249                 timer@101e2000 {
 250                         compatible = "arm,sp804", "arm,primecell";
 251                         reg = <0x101e2000 0x1000>;
 252                         interrupts = <4>;
 253                         clocks = <&timclk>, <&timclk>, <&pclk>;
 254                         clock-names = "timer0", "timer1", "apb_pclk";
 255                 };
 256
 257                 timer@101e3000 {
 258                         compatible = "arm,sp804", "arm,primecell";
 259                         reg = <0x101e3000 0x1000>;
 260                         interrupts = <5>;
 261                         clocks = <&timclk>, <&timclk>, <&pclk>;
 262                         clock-names = "timer0", "timer1", "apb_pclk";
 263                 };
 264
 265                 gpio0: gpio@101e4000 {
 266                         compatible = "arm,pl061", "arm,primecell";
 267                         reg = <0x101e4000 0x1000>;
 268                         gpio-controller;
 269                         interrupts = <6>;
 270                         #gpio-cells = <2>;
 271                         interrupt-controller;
 272                         #interrupt-cells = <2>;
 273                         clocks = <&pclk>;
 274                         clock-names = "apb_pclk";
 275                 };
 276
 277                 gpio1: gpio@101e5000 {
 278                         compatible = "arm,pl061", "arm,primecell";
 279                         reg = <0x101e5000 0x1000>;
 280                         interrupts = <7>;
 281                         gpio-controller;
 282                         #gpio-cells = <2>;
 283                         interrupt-controller;
 284                         #interrupt-cells = <2>;
 285                         clocks = <&pclk>;
 286                         clock-names = "apb_pclk";
 287                 };
 288
 289                 rtc@101e8000 {
 290                         compatible = "arm,pl030", "arm,primecell";
 291                         reg = <0x101e8000 0x1000>;
 292                         interrupts = <10>;
 293                         clocks = <&pclk>;
 294                         clock-names = "apb_pclk";
 295                 };
 296
 297                 sci@101f0000 {
 298                         compatible = "arm,primecell";
 299                         reg = <0x101f0000 0x1000>;
 300                         interrupts = <15>;
 301                         clocks = <&pclk>;
 302                         clock-names = "apb_pclk";
 303                 };
 304
 305                 ssp@101f4000 {
 306                         compatible = "arm,pl022", "arm,primecell";
 307                         reg = <0x101f4000 0x1000>;
 308                         interrupts = <11>;
 309                         clocks = <&xtal24mhz>, <&pclk>;
 310                         clock-names = "SSPCLK", "apb_pclk";
 311                 };
 312
 313                 fpga {
 314                         compatible = "arm,versatile-fpga", "simple-bus";
 315                         #address-cells = <1>;
 316                         #size-cells = <1>;
 317                         ranges = <0 0x10000000 0x10000>;
 318
 319                         sysreg@0 {
 320                                 compatible = "arm,versatile-sysreg", "syscon";
 321                                 reg = <0x00000 0x1000>;
 322                         };
 323
 324                         aaci@4000 {
 325                                 compatible = "arm,primecell";
 326                                 reg = <0x4000 0x1000>;
 327                                 interrupts = <24>;
 328                                 clocks = <&pclk>;
 329                                 clock-names = "apb_pclk";
 330                         };
 331                         mmc@5000 {
 332                                 compatible = "arm,pl180", "arm,primecell";
 333                                 reg = <0x5000 0x1000>;
 334                                 interrupts-extended = <&vic 22 &sic 1>;
 335                                 clocks = <&xtal24mhz>, <&pclk>;
 336                                 clock-names = "mclk", "apb_pclk";
 337                         };
 338                         kmi@6000 {
 339                                 compatible = "arm,pl050", "arm,primecell";
 340                                 reg = <0x6000 0x1000>;
 341                                 interrupt-parent = <&sic>;
 342                                 interrupts = <3>;
 343                                 clocks = <&xtal24mhz>, <&pclk>;
 344                                 clock-names = "KMIREFCLK", "apb_pclk";
 345                         };
 346                         kmi@7000 {
 347                                 compatible = "arm,pl050", "arm,primecell";
 348                                 reg = <0x7000 0x1000>;
 349                                 interrupt-parent = <&sic>;
 350                                 interrupts = <4>;
 351                                 clocks = <&xtal24mhz>, <&pclk>;
 352                                 clock-names = "KMIREFCLK", "apb_pclk";
 353                         };
 354                 };
 355         };
 356 };