arch/arm/boot/dts/omap5.dtsi

   1 /*
   2  * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  * Based on "omap4.dtsi"
   8  */
   9
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12 #include <dt-bindings/pinctrl/omap.h>
  13 #include <dt-bindings/clock/omap5.h>
  14
  15 / {
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         compatible = "ti,omap5";
  20         interrupt-parent = <&wakeupgen>;
  21         chosen { };
  22
  23         aliases {
  24                 i2c0 = &i2c1;
  25                 i2c1 = &i2c2;
  26                 i2c2 = &i2c3;
  27                 i2c3 = &i2c4;
  28                 i2c4 = &i2c5;
  29                 serial0 = &uart1;
  30                 serial1 = &uart2;
  31                 serial2 = &uart3;
  32                 serial3 = &uart4;
  33                 serial4 = &uart5;
  34                 serial5 = &uart6;
  35         };
  36
  37         cpus {
  38                 #address-cells = <1>;
  39                 #size-cells = <0>;
  40
  41                 cpu0: cpu@0 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a15";
  44                         reg = <0x0>;
  45
  46                         operating-points = <
  47                                 /* kHz    uV */
  48                                 1000000 1060000
  49                                 1500000 1250000
  50                         >;
  51
  52                         clocks = <&dpll_mpu_ck>;
  53                         clock-names = "cpu";
  54
  55                         clock-latency = <300000>; /* From omap-cpufreq driver */
  56
  57                         /* cooling options */
  58                         #cooling-cells = <2>; /* min followed by max */
  59                 };
  60                 cpu@1 {
  61                         device_type = "cpu";
  62                         compatible = "arm,cortex-a15";
  63                         reg = <0x1>;
  64                 };
  65         };
  66
  67         thermal-zones {
  68                 #include "omap4-cpu-thermal.dtsi"
  69                 #include "omap5-gpu-thermal.dtsi"
  70                 #include "omap5-core-thermal.dtsi"
  71         };
  72
  73         timer {
  74                 compatible = "arm,armv7-timer";
  75                 /* PPI secure/nonsecure IRQ */
  76                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  77                              <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  78                              <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  79                              <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
  80                 interrupt-parent = <&gic>;
  81         };
  82
  83         pmu {
  84                 compatible = "arm,cortex-a15-pmu";
  85                 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
  86                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
  87         };
  88
  89         gic: interrupt-controller@48211000 {
  90                 compatible = "arm,cortex-a15-gic";
  91                 interrupt-controller;
  92                 #interrupt-cells = <3>;
  93                 reg = <0 0x48211000 0 0x1000>,
  94                       <0 0x48212000 0 0x2000>,
  95                       <0 0x48214000 0 0x2000>,
  96                       <0 0x48216000 0 0x2000>;
  97                 interrupt-parent = <&gic>;
  98         };
  99
 100         wakeupgen: interrupt-controller@48281000 {
 101                 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
 102                 interrupt-controller;
 103                 #interrupt-cells = <3>;
 104                 reg = <0 0x48281000 0 0x1000>;
 105                 interrupt-parent = <&gic>;
 106         };
 107
 108         /*
 109          * The soc node represents the soc top level view. It is used for IPs
 110          * that are not memory mapped in the MPU view or for the MPU itself.
 111          */
 112         soc {
 113                 compatible = "ti,omap-infra";
 114                 mpu {
 115                         compatible = "ti,omap4-mpu";
 116                         ti,hwmods = "mpu";
 117                         sram = <&ocmcram>;
 118                 };
 119         };
 120
 121         /*
 122          * XXX: Use a flat representation of the OMAP3 interconnect.
 123          * The real OMAP interconnect network is quite complex.
 124          * Since it will not bring real advantage to represent that in DT for
 125          * the moment, just use a fake OCP bus entry to represent the whole bus
 126          * hierarchy.
 127          */
 128         ocp {
 129                 compatible = "ti,omap5-l3-noc", "simple-bus";
 130                 #address-cells = <1>;
 131                 #size-cells = <1>;
 132                 ranges = <0 0 0 0xc0000000>;
 133                 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
 134                 reg = <0 0x44000000 0 0x2000>,
 135                       <0 0x44800000 0 0x3000>,
 136                       <0 0x45000000 0 0x4000>;
 137                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 138                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 139
 140                 l4_cfg: l4@4a000000 {
 141                         compatible = "ti,omap5-l4-cfg", "simple-bus";
 142                         #address-cells = <1>;
 143                         #size-cells = <1>;
 144                         ranges = <0 0x4a000000 0x22a000>;
 145
 146                         scm_core: scm@2000 {
 147                                 compatible = "ti,omap5-scm-core", "simple-bus";
 148                                 reg = <0x2000 0x1000>;
 149                                 #address-cells = <1>;
 150                                 #size-cells = <1>;
 151                                 ranges = <0 0x2000 0x800>;
 152
 153                                 scm_conf: scm_conf@0 {
 154                                         compatible = "syscon";
 155                                         reg = <0x0 0x800>;
 156                                         #address-cells = <1>;
 157                                         #size-cells = <1>;
 158                                 };
 159                         };
 160
 161                         scm_padconf_core: scm@2800 {
 162                                 compatible = "ti,omap5-scm-padconf-core",
 163                                              "simple-bus";
 164                                 #address-cells = <1>;
 165                                 #size-cells = <1>;
 166                                 ranges = <0 0x2800 0x800>;
 167
 168                                 omap5_pmx_core: pinmux@40 {
 169                                         compatible = "ti,omap5-padconf",
 170                                                      "pinctrl-single";
 171                                         reg = <0x40 0x01b6>;
 172                                         #address-cells = <1>;
 173                                         #size-cells = <0>;
 174                                         #pinctrl-cells = <1>;
 175                                         #interrupt-cells = <1>;
 176                                         interrupt-controller;
 177                                         pinctrl-single,register-width = <16>;
 178                                         pinctrl-single,function-mask = <0x7fff>;
 179                                 };
 180
 181                                 omap5_padconf_global: omap5_padconf_global@5a0 {
 182                                         compatible = "syscon",
 183                                                      "simple-bus";
 184                                         reg = <0x5a0 0xec>;
 185                                         #address-cells = <1>;
 186                                         #size-cells = <1>;
 187                                         ranges = <0 0x5a0 0xec>;
 188
 189                                         pbias_regulator: pbias_regulator@60 {
 190                                                 compatible = "ti,pbias-omap5", "ti,pbias-omap";
 191                                                 reg = <0x60 0x4>;
 192                                                 syscon = <&omap5_padconf_global>;
 193                                                 pbias_mmc_reg: pbias_mmc_omap5 {
 194                                                         regulator-name = "pbias_mmc_omap5";
 195                                                         regulator-min-microvolt = <1800000>;
 196                                                         regulator-max-microvolt = <3300000>;
 197                                                 };
 198                                         };
 199                                 };
 200                         };
 201
 202                         cm_core_aon: cm_core_aon@4000 {
 203                                 compatible = "ti,omap5-cm-core-aon",
 204                                              "simple-bus";
 205                                 reg = <0x4000 0x2000>;
 206                                 #address-cells = <1>;
 207                                 #size-cells = <1>;
 208                                 ranges = <0 0x4000 0x2000>;
 209
 210                                 cm_core_aon_clocks: clocks {
 211                                         #address-cells = <1>;
 212                                         #size-cells = <0>;
 213                                 };
 214
 215                                 cm_core_aon_clockdomains: clockdomains {
 216                                 };
 217                         };
 218
 219                         cm_core: cm_core@8000 {
 220                                 compatible = "ti,omap5-cm-core", "simple-bus";
 221                                 reg = <0x8000 0x3000>;
 222                                 #address-cells = <1>;
 223                                 #size-cells = <1>;
 224                                 ranges = <0 0x8000 0x3000>;
 225
 226                                 cm_core_clocks: clocks {
 227                                         #address-cells = <1>;
 228                                         #size-cells = <0>;
 229                                 };
 230
 231                                 cm_core_clockdomains: clockdomains {
 232                                 };
 233                         };
 234                 };
 235
 236                 l4_wkup: l4@4ae00000 {
 237                         compatible = "ti,omap5-l4-wkup", "simple-bus";
 238                         #address-cells = <1>;
 239                         #size-cells = <1>;
 240                         ranges = <0 0x4ae00000 0x2b000>;
 241
 242                         counter32k: counter@4000 {
 243                                 compatible = "ti,omap-counter32k";
 244                                 reg = <0x4000 0x40>;
 245                                 ti,hwmods = "counter_32k";
 246                         };
 247
 248                         prm: prm@6000 {
 249                                 compatible = "ti,omap5-prm", "simple-bus";
 250                                 reg = <0x6000 0x3000>;
 251                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 252                                 #address-cells = <1>;
 253                                 #size-cells = <1>;
 254                                 ranges = <0 0x6000 0x3000>;
 255
 256                                 prm_clocks: clocks {
 257                                         #address-cells = <1>;
 258                                         #size-cells = <0>;
 259                                 };
 260
 261                                 prm_clockdomains: clockdomains {
 262                                 };
 263                         };
 264
 265                         scrm: scrm@a000 {
 266                                 compatible = "ti,omap5-scrm";
 267                                 reg = <0xa000 0x2000>;
 268
 269                                 scrm_clocks: clocks {
 270                                         #address-cells = <1>;
 271                                         #size-cells = <0>;
 272                                 };
 273
 274                                 scrm_clockdomains: clockdomains {
 275                                 };
 276                         };
 277
 278                         omap5_pmx_wkup: pinmux@c840 {
 279                                 compatible = "ti,omap5-padconf",
 280                                              "pinctrl-single";
 281                                 reg = <0xc840 0x003c>;
 282                                 #address-cells = <1>;
 283                                 #size-cells = <0>;
 284                                 #pinctrl-cells = <1>;
 285                                 #interrupt-cells = <1>;
 286                                 interrupt-controller;
 287                                 pinctrl-single,register-width = <16>;
 288                                 pinctrl-single,function-mask = <0x7fff>;
 289                         };
 290
 291                         omap5_scm_wkup_pad_conf: omap5_scm_wkup_pad_conf@cda0 {
 292                                 compatible = "ti,omap5-scm-wkup-pad-conf",
 293                                              "simple-bus";
 294                                 reg = <0xcda0 0x60>;
 295                                 #address-cells = <1>;
 296                                 #size-cells = <1>;
 297                                 ranges = <0 0xcda0 0x60>;
 298
 299                                 scm_wkup_pad_conf: scm_conf@0 {
 300                                         compatible = "syscon", "simple-bus";
 301                                         reg = <0x0 0x60>;
 302                                         #address-cells = <1>;
 303                                         #size-cells = <1>;
 304                                         ranges = <0 0x0 0x60>;
 305
 306                                         scm_wkup_pad_conf_clocks: clocks@0 {
 307                                                 #address-cells = <1>;
 308                                                 #size-cells = <0>;
 309                                         };
 310                                 };
 311                         };
 312                 };
 313
 314                 ocmcram: ocmcram@40300000 {
 315                         compatible = "mmio-sram";
 316                         reg = <0x40300000 0x20000>; /* 128k */
 317                 };
 318
 319                 sdma: dma-controller@4a056000 {
 320                         compatible = "ti,omap4430-sdma";
 321                         reg = <0x4a056000 0x1000>;
 322                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 323                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 324                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 325                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 326                         #dma-cells = <1>;
 327                         dma-channels = <32>;
 328                         dma-requests = <127>;
 329                         ti,hwmods = "dma_system";
 330                 };
 331
 332                 gpio1: gpio@4ae10000 {
 333                         compatible = "ti,omap4-gpio";
 334                         reg = <0x4ae10000 0x200>;
 335                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 336                         ti,hwmods = "gpio1";
 337                         ti,gpio-always-on;
 338                         gpio-controller;
 339                         #gpio-cells = <2>;
 340                         interrupt-controller;
 341                         #interrupt-cells = <2>;
 342                 };
 343
 344                 gpio2: gpio@48055000 {
 345                         compatible = "ti,omap4-gpio";
 346                         reg = <0x48055000 0x200>;
 347                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 348                         ti,hwmods = "gpio2";
 349                         gpio-controller;
 350                         #gpio-cells = <2>;
 351                         interrupt-controller;
 352                         #interrupt-cells = <2>;
 353                 };
 354
 355                 gpio3: gpio@48057000 {
 356                         compatible = "ti,omap4-gpio";
 357                         reg = <0x48057000 0x200>;
 358                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 359                         ti,hwmods = "gpio3";
 360                         gpio-controller;
 361                         #gpio-cells = <2>;
 362                         interrupt-controller;
 363                         #interrupt-cells = <2>;
 364                 };
 365
 366                 gpio4: gpio@48059000 {
 367                         compatible = "ti,omap4-gpio";
 368                         reg = <0x48059000 0x200>;
 369                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 370                         ti,hwmods = "gpio4";
 371                         gpio-controller;
 372                         #gpio-cells = <2>;
 373                         interrupt-controller;
 374                         #interrupt-cells = <2>;
 375                 };
 376
 377                 gpio5: gpio@4805b000 {
 378                         compatible = "ti,omap4-gpio";
 379                         reg = <0x4805b000 0x200>;
 380                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 381                         ti,hwmods = "gpio5";
 382                         gpio-controller;
 383                         #gpio-cells = <2>;
 384                         interrupt-controller;
 385                         #interrupt-cells = <2>;
 386                 };
 387
 388                 gpio6: gpio@4805d000 {
 389                         compatible = "ti,omap4-gpio";
 390                         reg = <0x4805d000 0x200>;
 391                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 392                         ti,hwmods = "gpio6";
 393                         gpio-controller;
 394                         #gpio-cells = <2>;
 395                         interrupt-controller;
 396                         #interrupt-cells = <2>;
 397                 };
 398
 399                 gpio7: gpio@48051000 {
 400                         compatible = "ti,omap4-gpio";
 401                         reg = <0x48051000 0x200>;
 402                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 403                         ti,hwmods = "gpio7";
 404                         gpio-controller;
 405                         #gpio-cells = <2>;
 406                         interrupt-controller;
 407                         #interrupt-cells = <2>;
 408                 };
 409
 410                 gpio8: gpio@48053000 {
 411                         compatible = "ti,omap4-gpio";
 412                         reg = <0x48053000 0x200>;
 413                         interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 414                         ti,hwmods = "gpio8";
 415                         gpio-controller;
 416                         #gpio-cells = <2>;
 417                         interrupt-controller;
 418                         #interrupt-cells = <2>;
 419                 };
 420
 421                 gpmc: gpmc@50000000 {
 422                         compatible = "ti,omap4430-gpmc";
 423                         reg = <0x50000000 0x1000>;
 424                         #address-cells = <2>;
 425                         #size-cells = <1>;
 426                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 427                         dmas = <&sdma 4>;
 428                         dma-names = "rxtx";
 429                         gpmc,num-cs = <8>;
 430                         gpmc,num-waitpins = <4>;
 431                         ti,hwmods = "gpmc";
 432                         clocks = <&l3_iclk_div>;
 433                         clock-names = "fck";
 434                         interrupt-controller;
 435                         #interrupt-cells = <2>;
 436                         gpio-controller;
 437                         #gpio-cells = <2>;
 438                 };
 439
 440                 i2c1: i2c@48070000 {
 441                         compatible = "ti,omap4-i2c";
 442                         reg = <0x48070000 0x100>;
 443                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 444                         #address-cells = <1>;
 445                         #size-cells = <0>;
 446                         ti,hwmods = "i2c1";
 447                 };
 448
 449                 i2c2: i2c@48072000 {
 450                         compatible = "ti,omap4-i2c";
 451                         reg = <0x48072000 0x100>;
 452                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 453                         #address-cells = <1>;
 454                         #size-cells = <0>;
 455                         ti,hwmods = "i2c2";
 456                 };
 457
 458                 i2c3: i2c@48060000 {
 459                         compatible = "ti,omap4-i2c";
 460                         reg = <0x48060000 0x100>;
 461                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 462                         #address-cells = <1>;
 463                         #size-cells = <0>;
 464                         ti,hwmods = "i2c3";
 465                 };
 466
 467                 i2c4: i2c@4807a000 {
 468                         compatible = "ti,omap4-i2c";
 469                         reg = <0x4807a000 0x100>;
 470                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 471                         #address-cells = <1>;
 472                         #size-cells = <0>;
 473                         ti,hwmods = "i2c4";
 474                 };
 475
 476                 i2c5: i2c@4807c000 {
 477                         compatible = "ti,omap4-i2c";
 478                         reg = <0x4807c000 0x100>;
 479                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 480                         #address-cells = <1>;
 481                         #size-cells = <0>;
 482                         ti,hwmods = "i2c5";
 483                 };
 484
 485                 hwspinlock: spinlock@4a0f6000 {
 486                         compatible = "ti,omap4-hwspinlock";
 487                         reg = <0x4a0f6000 0x1000>;
 488                         ti,hwmods = "spinlock";
 489                         #hwlock-cells = <1>;
 490                 };
 491
 492                 mcspi1: spi@48098000 {
 493                         compatible = "ti,omap4-mcspi";
 494                         reg = <0x48098000 0x200>;
 495                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 496                         #address-cells = <1>;
 497                         #size-cells = <0>;
 498                         ti,hwmods = "mcspi1";
 499                         ti,spi-num-cs = <4>;
 500                         dmas = <&sdma 35>,
 501                                <&sdma 36>,
 502                                <&sdma 37>,
 503                                <&sdma 38>,
 504                                <&sdma 39>,
 505                                <&sdma 40>,
 506                                <&sdma 41>,
 507                                <&sdma 42>;
 508                         dma-names = "tx0", "rx0", "tx1", "rx1",
 509                                     "tx2", "rx2", "tx3", "rx3";
 510                 };
 511
 512                 mcspi2: spi@4809a000 {
 513                         compatible = "ti,omap4-mcspi";
 514                         reg = <0x4809a000 0x200>;
 515                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 516                         #address-cells = <1>;
 517                         #size-cells = <0>;
 518                         ti,hwmods = "mcspi2";
 519                         ti,spi-num-cs = <2>;
 520                         dmas = <&sdma 43>,
 521                                <&sdma 44>,
 522                                <&sdma 45>,
 523                                <&sdma 46>;
 524                         dma-names = "tx0", "rx0", "tx1", "rx1";
 525                 };
 526
 527                 mcspi3: spi@480b8000 {
 528                         compatible = "ti,omap4-mcspi";
 529                         reg = <0x480b8000 0x200>;
 530                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 531                         #address-cells = <1>;
 532                         #size-cells = <0>;
 533                         ti,hwmods = "mcspi3";
 534                         ti,spi-num-cs = <2>;
 535                         dmas = <&sdma 15>, <&sdma 16>;
 536                         dma-names = "tx0", "rx0";
 537                 };
 538
 539                 mcspi4: spi@480ba000 {
 540                         compatible = "ti,omap4-mcspi";
 541                         reg = <0x480ba000 0x200>;
 542                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 543                         #address-cells = <1>;
 544                         #size-cells = <0>;
 545                         ti,hwmods = "mcspi4";
 546                         ti,spi-num-cs = <1>;
 547                         dmas = <&sdma 70>, <&sdma 71>;
 548                         dma-names = "tx0", "rx0";
 549                 };
 550
 551                 uart1: serial@4806a000 {
 552                         compatible = "ti,omap4-uart";
 553                         reg = <0x4806a000 0x100>;
 554                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 555                         ti,hwmods = "uart1";
 556                         clock-frequency = <48000000>;
 557                 };
 558
 559                 uart2: serial@4806c000 {
 560                         compatible = "ti,omap4-uart";
 561                         reg = <0x4806c000 0x100>;
 562                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 563                         ti,hwmods = "uart2";
 564                         clock-frequency = <48000000>;
 565                 };
 566
 567                 uart3: serial@48020000 {
 568                         compatible = "ti,omap4-uart";
 569                         reg = <0x48020000 0x100>;
 570                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 571                         ti,hwmods = "uart3";
 572                         clock-frequency = <48000000>;
 573                 };
 574
 575                 uart4: serial@4806e000 {
 576                         compatible = "ti,omap4-uart";
 577                         reg = <0x4806e000 0x100>;
 578                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 579                         ti,hwmods = "uart4";
 580                         clock-frequency = <48000000>;
 581                 };
 582
 583                 uart5: serial@48066000 {
 584                         compatible = "ti,omap4-uart";
 585                         reg = <0x48066000 0x100>;
 586                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 587                         ti,hwmods = "uart5";
 588                         clock-frequency = <48000000>;
 589                 };
 590
 591                 uart6: serial@48068000 {
 592                         compatible = "ti,omap4-uart";
 593                         reg = <0x48068000 0x100>;
 594                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 595                         ti,hwmods = "uart6";
 596                         clock-frequency = <48000000>;
 597                 };
 598
 599                 mmc1: mmc@4809c000 {
 600                         compatible = "ti,omap4-hsmmc";
 601                         reg = <0x4809c000 0x400>;
 602                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 603                         ti,hwmods = "mmc1";
 604                         ti,dual-volt;
 605                         ti,needs-special-reset;
 606                         dmas = <&sdma 61>, <&sdma 62>;
 607                         dma-names = "tx", "rx";
 608                         pbias-supply = <&pbias_mmc_reg>;
 609                 };
 610
 611                 mmc2: mmc@480b4000 {
 612                         compatible = "ti,omap4-hsmmc";
 613                         reg = <0x480b4000 0x400>;
 614                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 615                         ti,hwmods = "mmc2";
 616                         ti,needs-special-reset;
 617                         dmas = <&sdma 47>, <&sdma 48>;
 618                         dma-names = "tx", "rx";
 619                 };
 620
 621                 mmc3: mmc@480ad000 {
 622                         compatible = "ti,omap4-hsmmc";
 623                         reg = <0x480ad000 0x400>;
 624                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 625                         ti,hwmods = "mmc3";
 626                         ti,needs-special-reset;
 627                         dmas = <&sdma 77>, <&sdma 78>;
 628                         dma-names = "tx", "rx";
 629                 };
 630
 631                 mmc4: mmc@480d1000 {
 632                         compatible = "ti,omap4-hsmmc";
 633                         reg = <0x480d1000 0x400>;
 634                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 635                         ti,hwmods = "mmc4";
 636                         ti,needs-special-reset;
 637                         dmas = <&sdma 57>, <&sdma 58>;
 638                         dma-names = "tx", "rx";
 639                 };
 640
 641                 mmc5: mmc@480d5000 {
 642                         compatible = "ti,omap4-hsmmc";
 643                         reg = <0x480d5000 0x400>;
 644                         interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 645                         ti,hwmods = "mmc5";
 646                         ti,needs-special-reset;
 647                         dmas = <&sdma 59>, <&sdma 60>;
 648                         dma-names = "tx", "rx";
 649                 };
 650
 651                 mmu_dsp: mmu@4a066000 {
 652                         compatible = "ti,omap4-iommu";
 653                         reg = <0x4a066000 0x100>;
 654                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 655                         ti,hwmods = "mmu_dsp";
 656                         #iommu-cells = <0>;
 657                 };
 658
 659                 mmu_ipu: mmu@55082000 {
 660                         compatible = "ti,omap4-iommu";
 661                         reg = <0x55082000 0x100>;
 662                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 663                         ti,hwmods = "mmu_ipu";
 664                         #iommu-cells = <0>;
 665                         ti,iommu-bus-err-back;
 666                 };
 667
 668                 keypad: keypad@4ae1c000 {
 669                         compatible = "ti,omap4-keypad";
 670                         reg = <0x4ae1c000 0x400>;
 671                         ti,hwmods = "kbd";
 672                 };
 673
 674                 mcpdm: mcpdm@40132000 {
 675                         compatible = "ti,omap4-mcpdm";
 676                         reg = <0x40132000 0x7f>, /* MPU private access */
 677                               <0x49032000 0x7f>; /* L3 Interconnect */
 678                         reg-names = "mpu", "dma";
 679                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 680                         ti,hwmods = "mcpdm";
 681                         dmas = <&sdma 65>,
 682                                <&sdma 66>;
 683                         dma-names = "up_link", "dn_link";
 684                         status = "disabled";
 685                 };
 686
 687                 dmic: dmic@4012e000 {
 688                         compatible = "ti,omap4-dmic";
 689                         reg = <0x4012e000 0x7f>, /* MPU private access */
 690                               <0x4902e000 0x7f>; /* L3 Interconnect */
 691                         reg-names = "mpu", "dma";
 692                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 693                         ti,hwmods = "dmic";
 694                         dmas = <&sdma 67>;
 695                         dma-names = "up_link";
 696                         status = "disabled";
 697                 };
 698
 699                 mcbsp1: mcbsp@40122000 {
 700                         compatible = "ti,omap4-mcbsp";
 701                         reg = <0x40122000 0xff>, /* MPU private access */
 702                               <0x49022000 0xff>; /* L3 Interconnect */
 703                         reg-names = "mpu", "dma";
 704                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 705                         interrupt-names = "common";
 706                         ti,buffer-size = <128>;
 707                         ti,hwmods = "mcbsp1";
 708                         dmas = <&sdma 33>,
 709                                <&sdma 34>;
 710                         dma-names = "tx", "rx";
 711                         status = "disabled";
 712                 };
 713
 714                 mcbsp2: mcbsp@40124000 {
 715                         compatible = "ti,omap4-mcbsp";
 716                         reg = <0x40124000 0xff>, /* MPU private access */
 717                               <0x49024000 0xff>; /* L3 Interconnect */
 718                         reg-names = "mpu", "dma";
 719                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 720                         interrupt-names = "common";
 721                         ti,buffer-size = <128>;
 722                         ti,hwmods = "mcbsp2";
 723                         dmas = <&sdma 17>,
 724                                <&sdma 18>;
 725                         dma-names = "tx", "rx";
 726                         status = "disabled";
 727                 };
 728
 729                 mcbsp3: mcbsp@40126000 {
 730                         compatible = "ti,omap4-mcbsp";
 731                         reg = <0x40126000 0xff>, /* MPU private access */
 732                               <0x49026000 0xff>; /* L3 Interconnect */
 733                         reg-names = "mpu", "dma";
 734                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 735                         interrupt-names = "common";
 736                         ti,buffer-size = <128>;
 737                         ti,hwmods = "mcbsp3";
 738                         dmas = <&sdma 19>,
 739                                <&sdma 20>;
 740                         dma-names = "tx", "rx";
 741                         status = "disabled";
 742                 };
 743
 744                 mailbox: mailbox@4a0f4000 {
 745                         compatible = "ti,omap4-mailbox";
 746                         reg = <0x4a0f4000 0x200>;
 747                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 748                         ti,hwmods = "mailbox";
 749                         #mbox-cells = <1>;
 750                         ti,mbox-num-users = <3>;
 751                         ti,mbox-num-fifos = <8>;
 752                         mbox_ipu: mbox_ipu {
 753                                 ti,mbox-tx = <0 0 0>;
 754                                 ti,mbox-rx = <1 0 0>;
 755                         };
 756                         mbox_dsp: mbox_dsp {
 757                                 ti,mbox-tx = <3 0 0>;
 758                                 ti,mbox-rx = <2 0 0>;
 759                         };
 760                 };
 761
 762                 timer1: timer@4ae18000 {
 763                         compatible = "ti,omap5430-timer";
 764                         reg = <0x4ae18000 0x80>;
 765                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 766                         ti,hwmods = "timer1";
 767                         ti,timer-alwon;
 768                         clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>;
 769                         clock-names = "fck";
 770                 };
 771
 772                 timer2: timer@48032000 {
 773                         compatible = "ti,omap5430-timer";
 774                         reg = <0x48032000 0x80>;
 775                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 776                         ti,hwmods = "timer2";
 777                 };
 778
 779                 timer3: timer@48034000 {
 780                         compatible = "ti,omap5430-timer";
 781                         reg = <0x48034000 0x80>;
 782                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 783                         ti,hwmods = "timer3";
 784                 };
 785
 786                 timer4: timer@48036000 {
 787                         compatible = "ti,omap5430-timer";
 788                         reg = <0x48036000 0x80>;
 789                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 790                         ti,hwmods = "timer4";
 791                 };
 792
 793                 timer5: timer@40138000 {
 794                         compatible = "ti,omap5430-timer";
 795                         reg = <0x40138000 0x80>,
 796                               <0x49038000 0x80>;
 797                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 798                         ti,hwmods = "timer5";
 799                         ti,timer-dsp;
 800                         ti,timer-pwm;
 801                 };
 802
 803                 timer6: timer@4013a000 {
 804                         compatible = "ti,omap5430-timer";
 805                         reg = <0x4013a000 0x80>,
 806                               <0x4903a000 0x80>;
 807                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 808                         ti,hwmods = "timer6";
 809                         ti,timer-dsp;
 810                         ti,timer-pwm;
 811                 };
 812
 813                 timer7: timer@4013c000 {
 814                         compatible = "ti,omap5430-timer";
 815                         reg = <0x4013c000 0x80>,
 816                               <0x4903c000 0x80>;
 817                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 818                         ti,hwmods = "timer7";
 819                         ti,timer-dsp;
 820                 };
 821
 822                 timer8: timer@4013e000 {
 823                         compatible = "ti,omap5430-timer";
 824                         reg = <0x4013e000 0x80>,
 825                               <0x4903e000 0x80>;
 826                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 827                         ti,hwmods = "timer8";
 828                         ti,timer-dsp;
 829                         ti,timer-pwm;
 830                 };
 831
 832                 timer9: timer@4803e000 {
 833                         compatible = "ti,omap5430-timer";
 834                         reg = <0x4803e000 0x80>;
 835                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 836                         ti,hwmods = "timer9";
 837                         ti,timer-pwm;
 838                 };
 839
 840                 timer10: timer@48086000 {
 841                         compatible = "ti,omap5430-timer";
 842                         reg = <0x48086000 0x80>;
 843                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 844                         ti,hwmods = "timer10";
 845                         ti,timer-pwm;
 846                 };
 847
 848                 timer11: timer@48088000 {
 849                         compatible = "ti,omap5430-timer";
 850                         reg = <0x48088000 0x80>;
 851                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 852                         ti,hwmods = "timer11";
 853                         ti,timer-pwm;
 854                 };
 855
 856                 wdt2: wdt@4ae14000 {
 857                         compatible = "ti,omap5-wdt", "ti,omap3-wdt";
 858                         reg = <0x4ae14000 0x80>;
 859                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 860                         ti,hwmods = "wd_timer2";
 861                 };
 862
 863                 dmm@4e000000 {
 864                         compatible = "ti,omap5-dmm";
 865                         reg = <0x4e000000 0x800>;
 866                         interrupts = <0 113 0x4>;
 867                         ti,hwmods = "dmm";
 868                 };
 869
 870                 emif1: emif@4c000000 {
 871                         compatible      = "ti,emif-4d5";
 872                         ti,hwmods       = "emif1";
 873                         ti,no-idle-on-init;
 874                         phy-type        = <2>; /* DDR PHY type: Intelli PHY */
 875                         reg = <0x4c000000 0x400>;
 876                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 877                         hw-caps-read-idle-ctrl;
 878                         hw-caps-ll-interface;
 879                         hw-caps-temp-alert;
 880                 };
 881
 882                 emif2: emif@4d000000 {
 883                         compatible      = "ti,emif-4d5";
 884                         ti,hwmods       = "emif2";
 885                         ti,no-idle-on-init;
 886                         phy-type        = <2>; /* DDR PHY type: Intelli PHY */
 887                         reg = <0x4d000000 0x400>;
 888                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 889                         hw-caps-read-idle-ctrl;
 890                         hw-caps-ll-interface;
 891                         hw-caps-temp-alert;
 892                 };
 893
 894                 usb3: omap_dwc3@4a020000 {
 895                         compatible = "ti,dwc3";
 896                         ti,hwmods = "usb_otg_ss";
 897                         reg = <0x4a020000 0x10000>;
 898                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 899                         #address-cells = <1>;
 900                         #size-cells = <1>;
 901                         utmi-mode = <2>;
 902                         ranges;
 903                         dwc3: dwc3@4a030000 {
 904                                 compatible = "snps,dwc3";
 905                                 reg = <0x4a030000 0x10000>;
 906                                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
 907                                              <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
 908                                              <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 909                                 interrupt-names = "peripheral",
 910                                                   "host",
 911                                                   "otg";
 912                                 phys = <&usb2_phy>, <&usb3_phy>;
 913                                 phy-names = "usb2-phy", "usb3-phy";
 914                                 dr_mode = "peripheral";
 915                         };
 916                 };
 917
 918                 ocp2scp@4a080000 {
 919                         compatible = "ti,omap-ocp2scp";
 920                         #address-cells = <1>;
 921                         #size-cells = <1>;
 922                         reg = <0x4a080000 0x20>;
 923                         ranges;
 924                         ti,hwmods = "ocp2scp1";
 925                         usb2_phy: usb2phy@4a084000 {
 926                                 compatible = "ti,omap-usb2";
 927                                 reg = <0x4a084000 0x7c>;
 928                                 syscon-phy-power = <&scm_conf 0x300>;
 929                                 clocks = <&usb_phy_cm_clk32k>,
 930                                          <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>;
 931                                 clock-names = "wkupclk", "refclk";
 932                                 #phy-cells = <0>;
 933                         };
 934
 935                         usb3_phy: usb3phy@4a084400 {
 936                                 compatible = "ti,omap-usb3";
 937                                 reg = <0x4a084400 0x80>,
 938                                       <0x4a084800 0x64>,
 939                                       <0x4a084c00 0x40>;
 940                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
 941                                 syscon-phy-power = <&scm_conf 0x370>;
 942                                 clocks = <&usb_phy_cm_clk32k>,
 943                                          <&sys_clkin>,
 944                                          <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>;
 945                                 clock-names =   "wkupclk",
 946                                                 "sysclk",
 947                                                 "refclk";
 948                                 #phy-cells = <0>;
 949                         };
 950                 };
 951
 952                 usbhstll: usbhstll@4a062000 {
 953                         compatible = "ti,usbhs-tll";
 954                         reg = <0x4a062000 0x1000>;
 955                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 956                         ti,hwmods = "usb_tll_hs";
 957                 };
 958
 959                 usbhshost: usbhshost@4a064000 {
 960                         compatible = "ti,usbhs-host";
 961                         reg = <0x4a064000 0x800>;
 962                         ti,hwmods = "usb_host_hs";
 963                         #address-cells = <1>;
 964                         #size-cells = <1>;
 965                         ranges;
 966                         clocks = <&l3init_60m_fclk>,
 967                                  <&xclk60mhsp1_ck>,
 968                                  <&xclk60mhsp2_ck>;
 969                         clock-names = "refclk_60m_int",
 970                                       "refclk_60m_ext_p1",
 971                                       "refclk_60m_ext_p2";
 972
 973                         usbhsohci: ohci@4a064800 {
 974                                 compatible = "ti,ohci-omap3";
 975                                 reg = <0x4a064800 0x400>;
 976                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 977                                 remote-wakeup-connected;
 978                         };
 979
 980                         usbhsehci: ehci@4a064c00 {
 981                                 compatible = "ti,ehci-omap";
 982                                 reg = <0x4a064c00 0x400>;
 983                                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 984                         };
 985                 };
 986
 987                 bandgap: bandgap@4a0021e0 {
 988                         reg = <0x4a0021e0 0xc
 989                                0x4a00232c 0xc
 990                                0x4a002380 0x2c
 991                                0x4a0023C0 0x3c>;
 992                         interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 993                         compatible = "ti,omap5430-bandgap";
 994
 995                         #thermal-sensor-cells = <1>;
 996                 };
 997
 998                 /* OCP2SCP3 */
 999                 ocp2scp@4a090000 {
1000                         compatible = "ti,omap-ocp2scp";
1001                         #address-cells = <1>;
1002                         #size-cells = <1>;
1003                         reg = <0x4a090000 0x20>;
1004                         ranges;
1005                         ti,hwmods = "ocp2scp3";
1006                         sata_phy: phy@4a096000 {
1007                                 compatible = "ti,phy-pipe3-sata";
1008                                 reg = <0x4A096000 0x80>, /* phy_rx */
1009                                       <0x4A096400 0x64>, /* phy_tx */
1010                                       <0x4A096800 0x40>; /* pll_ctrl */
1011                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1012                                 syscon-phy-power = <&scm_conf 0x374>;
1013                                 clocks = <&sys_clkin>,
1014                                          <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>;
1015                                 clock-names = "sysclk", "refclk";
1016                                 #phy-cells = <0>;
1017                         };
1018                 };
1019
1020                 sata: sata@4a141100 {
1021                         compatible = "snps,dwc-ahci";
1022                         reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
1023                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
1024                         phys = <&sata_phy>;
1025                         phy-names = "sata-phy";
1026                         clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>;
1027                         ti,hwmods = "sata";
1028                         ports-implemented = <0x1>;
1029                 };
1030
1031                 dss: dss@58000000 {
1032                         compatible = "ti,omap5-dss";
1033                         reg = <0x58000000 0x80>;
1034                         status = "disabled";
1035                         ti,hwmods = "dss_core";
1036                         clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
1037                         clock-names = "fck";
1038                         #address-cells = <1>;
1039                         #size-cells = <1>;
1040                         ranges;
1041
1042                         dispc@58001000 {
1043                                 compatible = "ti,omap5-dispc";
1044                                 reg = <0x58001000 0x1000>;
1045                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1046                                 ti,hwmods = "dss_dispc";
1047                                 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
1048                                 clock-names = "fck";
1049                         };
1050
1051                         rfbi: encoder@58002000  {
1052                                 compatible = "ti,omap5-rfbi";
1053                                 reg = <0x58002000 0x100>;
1054                                 status = "disabled";
1055                                 ti,hwmods = "dss_rfbi";
1056                                 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>;
1057                                 clock-names = "fck", "ick";
1058                         };
1059
1060                         dsi1: encoder@58004000 {
1061                                 compatible = "ti,omap5-dsi";
1062                                 reg = <0x58004000 0x200>,
1063                                       <0x58004200 0x40>,
1064                                       <0x58004300 0x40>;
1065                                 reg-names = "proto", "phy", "pll";
1066                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1067                                 status = "disabled";
1068                                 ti,hwmods = "dss_dsi1";
1069                                 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
1070                                          <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
1071                                 clock-names = "fck", "sys_clk";
1072                         };
1073
1074                         dsi2: encoder@58005000 {
1075                                 compatible = "ti,omap5-dsi";
1076                                 reg = <0x58009000 0x200>,
1077                                       <0x58009200 0x40>,
1078                                       <0x58009300 0x40>;
1079                                 reg-names = "proto", "phy", "pll";
1080                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1081                                 status = "disabled";
1082                                 ti,hwmods = "dss_dsi2";
1083                                 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
1084                                          <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
1085                                 clock-names = "fck", "sys_clk";
1086                         };
1087
1088                         hdmi: encoder@58060000 {
1089                                 compatible = "ti,omap5-hdmi";
1090                                 reg = <0x58040000 0x200>,
1091                                       <0x58040200 0x80>,
1092                                       <0x58040300 0x80>,
1093                                       <0x58060000 0x19000>;
1094                                 reg-names = "wp", "pll", "phy", "core";
1095                                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1096                                 status = "disabled";
1097                                 ti,hwmods = "dss_hdmi";
1098                                 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
1099                                          <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
1100                                 clock-names = "fck", "sys_clk";
1101                                 dmas = <&sdma 76>;
1102                                 dma-names = "audio_tx";
1103                         };
1104                 };
1105
1106                 abb_mpu: regulator-abb-mpu {
1107                         compatible = "ti,abb-v2";
1108                         regulator-name = "abb_mpu";
1109                         #address-cells = <0>;
1110                         #size-cells = <0>;
1111                         clocks = <&sys_clkin>;
1112                         ti,settling-time = <50>;
1113                         ti,clock-cycles = <16>;
1114
1115                         reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
1116                               <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
1117                         reg-names = "base-address", "int-address",
1118                                     "efuse-address", "ldo-address";
1119                         ti,tranxdone-status-mask = <0x80>;
1120                         /* LDOVBBMPU_MUX_CTRL */
1121                         ti,ldovbb-override-mask = <0x400>;
1122                         /* LDOVBBMPU_VSET_OUT */
1123                         ti,ldovbb-vset-mask = <0x1F>;
1124
1125                         /*
1126                          * NOTE: only FBB mode used but actual vset will
1127                          * determine final biasing
1128                          */
1129                         ti,abb_info = <
1130                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1131                         1060000         0       0x0     0 0x02000000 0x01F00000
1132                         1250000         0       0x4     0 0x02000000 0x01F00000
1133                         >;
1134                 };
1135
1136                 abb_mm: regulator-abb-mm {
1137                         compatible = "ti,abb-v2";
1138                         regulator-name = "abb_mm";
1139                         #address-cells = <0>;
1140                         #size-cells = <0>;
1141                         clocks = <&sys_clkin>;
1142                         ti,settling-time = <50>;
1143                         ti,clock-cycles = <16>;
1144
1145                         reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
1146                               <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
1147                         reg-names = "base-address", "int-address",
1148                                     "efuse-address", "ldo-address";
1149                         ti,tranxdone-status-mask = <0x80000000>;
1150                         /* LDOVBBMM_MUX_CTRL */
1151                         ti,ldovbb-override-mask = <0x400>;
1152                         /* LDOVBBMM_VSET_OUT */
1153                         ti,ldovbb-vset-mask = <0x1F>;
1154
1155                         /*
1156                          * NOTE: only FBB mode used but actual vset will
1157                          * determine final biasing
1158                          */
1159                         ti,abb_info = <
1160                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1161                         1025000         0       0x0     0 0x02000000 0x01F00000
1162                         1120000         0       0x4     0 0x02000000 0x01F00000
1163                         >;
1164                 };
1165         };
1166 };
1167
1168 &cpu_thermal {
1169         polling-delay = <500>; /* milliseconds */
1170         coefficients = <65 (-1791)>;
1171 };
1172
1173 #include "omap54xx-clocks.dtsi"
1174
1175 &gpu_thermal {
1176         coefficients = <117 (-2992)>;
1177 };
1178
1179 &core_thermal {
1180         coefficients = <0 2000>;
1181 };