arch/arm/boot/dts/imx7d.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
   2 //
   3 // Copyright 2015 Freescale Semiconductor, Inc.
   4 // Copyright 2016 Toradex AG
   5
   6 #include "imx7s.dtsi"
   7 #include <dt-bindings/reset/imx7-reset.h>
   8
   9 / {
  10         cpus {
  11                 cpu0: cpu@0 {
  12                         clock-frequency = <996000000>;
  13                         operating-points-v2 = <&cpu0_opp_table>;
  14                 };
  15
  16                 cpu1: cpu@1 {
  17                         compatible = "arm,cortex-a7";
  18                         device_type = "cpu";
  19                         reg = <1>;
  20                         clock-frequency = <996000000>;
  21                         operating-points-v2 = <&cpu0_opp_table>;
  22                 };
  23         };
  24
  25         cpu0_opp_table: opp-table {
  26                 compatible = "operating-points-v2";
  27                 opp-shared;
  28
  29                 opp-792000000 {
  30                         opp-hz = /bits/ 64 <792000000>;
  31                         opp-microvolt = <975000>;
  32                         clock-latency-ns = <150000>;
  33                 };
  34
  35                 opp-996000000 {
  36                         opp-hz = /bits/ 64 <996000000>;
  37                         opp-microvolt = <1075000>;
  38                         clock-latency-ns = <150000>;
  39                         opp-suspend;
  40                 };
  41         };
  42
  43         usbphynop2: usbphynop2 {
  44                 compatible = "usb-nop-xceiv";
  45                 clocks = <&clks IMX7D_USB_PHY2_CLK>;
  46                 clock-names = "main_clk";
  47                 #phy-cells = <0>;
  48         };
  49
  50         soc {
  51                 etm@3007d000 {
  52                         compatible = "arm,coresight-etm3x", "arm,primecell";
  53                         reg = <0x3007d000 0x1000>;
  54
  55                         /*
  56                          * System will hang if added nosmp in kernel command line
  57                          * without arm,primecell-periphid because amba bus try to
  58                          * read id and core1 power off at this time.
  59                          */
  60                         arm,primecell-periphid = <0xbb956>;
  61                         cpu = <&cpu1>;
  62                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
  63                         clock-names = "apb_pclk";
  64
  65                         port {
  66                                 etm1_out_port: endpoint {
  67                                         remote-endpoint = <&ca_funnel_in_port1>;
  68                                 };
  69                         };
  70                 };
  71         };
  72 };
  73
  74 &aips3 {
  75         usbotg2: usb@30b20000 {
  76                 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
  77                 reg = <0x30b20000 0x200>;
  78                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
  79                 clocks = <&clks IMX7D_USB_CTRL_CLK>;
  80                 fsl,usbphy = <&usbphynop2>;
  81                 fsl,usbmisc = <&usbmisc2 0>;
  82                 phy-clkgate-delay-us = <400>;
  83                 status = "disabled";
  84         };
  85
  86         usbmisc2: usbmisc@30b20200 {
  87                 #index-cells = <1>;
  88                 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
  89                 reg = <0x30b20200 0x200>;
  90         };
  91
  92         fec2: ethernet@30bf0000 {
  93                 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
  94                 reg = <0x30bf0000 0x10000>;
  95                 interrupt-names = "int0", "int1", "int2", "pps";
  96                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
  97                         <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
  98                         <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
  99                         <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 100                 clocks = <&clks IMX7D_ENET2_IPG_ROOT_CLK>,
 101                         <&clks IMX7D_ENET_AXI_ROOT_CLK>,
 102                         <&clks IMX7D_ENET2_TIME_ROOT_CLK>,
 103                         <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
 104                         <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
 105                 clock-names = "ipg", "ahb", "ptp",
 106                         "enet_clk_ref", "enet_out";
 107                 fsl,num-tx-queues=<3>;
 108                 fsl,num-rx-queues=<3>;
 109                 status = "disabled";
 110         };
 111
 112         pcie: pcie@33800000 {
 113                 compatible = "fsl,imx7d-pcie", "snps,dw-pcie";
 114                 reg = <0x33800000 0x4000>,
 115                       <0x4ff00000 0x80000>;
 116                 reg-names = "dbi", "config";
 117                 #address-cells = <3>;
 118                 #size-cells = <2>;
 119                 device_type = "pci";
 120                 bus-range = <0x00 0xff>;
 121                 ranges = <0x81000000 0 0          0x4ff80000 0 0x00010000   /* downstream I/O */
 122                           0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */
 123                 num-lanes = <1>;
 124                 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 125                 interrupt-names = "msi";
 126                 #interrupt-cells = <1>;
 127                 interrupt-map-mask = <0 0 0 0x7>;
 128                 interrupt-map = <0 0 0 1 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 129                                 <0 0 0 2 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 130                                 <0 0 0 3 &intc GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
 131                                 <0 0 0 4 &intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 132                 clocks = <&clks IMX7D_PCIE_CTRL_ROOT_CLK>,
 133                          <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>,
 134                          <&clks IMX7D_PCIE_PHY_ROOT_CLK>;
 135                 clock-names = "pcie", "pcie_bus", "pcie_phy";
 136                 assigned-clocks = <&clks IMX7D_PCIE_CTRL_ROOT_SRC>,
 137                                   <&clks IMX7D_PCIE_PHY_ROOT_SRC>;
 138                 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>,
 139                                          <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
 140
 141                 fsl,max-link-speed = <2>;
 142                 power-domains = <&pgc_pcie_phy>;
 143                 resets = <&src IMX7_RESET_PCIEPHY>,
 144                          <&src IMX7_RESET_PCIE_CTRL_APPS_EN>;
 145                 reset-names = "pciephy", "apps";
 146                 status = "disabled";
 147         };
 148 };
 149
 150 &ca_funnel_ports {
 151         port@1 {
 152                 reg = <1>;
 153                 ca_funnel_in_port1: endpoint {
 154                         slave-mode;
 155                         remote-endpoint = <&etm1_out_port>;
 156                 };
 157         };
 158 };