2 * Device Tree include file for SolidRun Clearfog 88F6828 based boards
4 * Copyright (C) 2015 Russell King
6 * This board is in development; the contents of this file work with
7 * the A1 rev 2.0 of the board, which does not represent final
8 * production board. Things will change, don't expect this file to
9 * remain compatible info the future.
11 * This file is dual-licensed: you can use it either under the terms
12 * of the GPL or the X11 license, at your option. Note that this dual
13 * licensing only applies to this file, and not this project as a
16 * a) This file is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License
18 * version 2 as published by the Free Software Foundation.
20 * This file is distributed in the hope that it will be useful
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
27 * b) Permission is hereby granted, free of charge, to any person
28 * obtaining a copy of this software and associated documentation
29 * files (the "Software"), to deal in the Software without
30 * restriction, including without limitation the rights to use
31 * copy, modify, merge, publish, distribute, sublicense, and/or
32 * sell copies of the Software, and to permit persons to whom the
33 * Software is furnished to do so, subject to the following
36 * The above copyright notice and this permission notice shall be
37 * included in all copies or substantial portions of the Software.
39 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
40 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
41 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
43 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
44 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
45 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
46 * OTHER DEALINGS IN THE SOFTWARE.
49 #include "armada-388.dtsi"
50 #include "armada-38x-solidrun-microsom.dtsi"
54 /* So that mvebu u-boot can update the MAC addresses */
61 stdout-path = "serial0:115200n8";
64 reg_3p3v: regulator-3p3v {
65 compatible = "regulator-fixed";
66 regulator-name = "3P3V";
67 regulator-min-microvolt = <3300000>;
68 regulator-max-microvolt = <3300000>;
76 buffer-manager = <&bm>;
84 buffer-manager = <&bm>;
96 /* Is there anything on this? */
97 clock-frequency = <100000>;
98 pinctrl-0 = <&i2c0_pins>;
99 pinctrl-names = "default";
103 * PCA9655 GPIO expander, up to 1MHz clock.
121 expander0: gpio-expander@20 {
123 * This is how it should be:
124 * compatible = "onnn,pca9655",
126 * but you can't do this because of
129 compatible = "nxp,pca9555";
136 gpios = <0 GPIO_ACTIVE_LOW>;
138 line-name = "pcie1.0-clkreq";
142 gpios = <3 GPIO_ACTIVE_LOW>;
144 line-name = "pcie1.0-w-disable";
148 gpios = <5 GPIO_ACTIVE_LOW>;
150 line-name = "usb3-current-limit";
154 gpios = <6 GPIO_ACTIVE_HIGH>;
156 line-name = "usb3-power";
160 gpios = <11 GPIO_ACTIVE_HIGH>;
162 line-name = "m.2 devslp";
165 /* SFP loss of signal */
167 gpios = <12 GPIO_ACTIVE_HIGH>;
169 line-name = "sfp-los";
172 /* SFP laser fault */
174 gpios = <13 GPIO_ACTIVE_HIGH>;
176 line-name = "sfp-tx-fault";
179 /* SFP transmit disable */
181 gpios = <14 GPIO_ACTIVE_HIGH>;
183 line-name = "sfp-tx-disable";
186 /* SFP module present */
188 gpios = <15 GPIO_ACTIVE_LOW>;
190 line-name = "sfp-mod-def0";
194 /* The MCP3021 is 100kHz clock only */
195 mikrobus_adc: mcp3021@4c {
196 compatible = "microchip,mcp3021";
200 /* Also something at 0x64 */
205 * Routed to SFP, mikrobus, and PCIe.
206 * SFP limits this to 100kHz, and requires
207 * an AT24C01A/02/04 with address pins tied
208 * low, which takes addresses 0x50 and 0x51.
209 * Mikrobus doesn't specify beyond an I2C
211 * PCIe uses ARP to assign addresses, or
214 clock-frequency = <100000>;
215 pinctrl-0 = <&clearfog_i2c1_pins>;
216 pinctrl-names = "default";
232 cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
234 pinctrl-0 = <µsom_sdhci_pins
235 &clearfog_sdhci_cd_pins>;
236 pinctrl-names = "default";
244 pinctrl-0 = <&mikro_uart_pins>;
245 pinctrl-names = "default";
250 /* CON3, nearest power. */
263 * The two PCIe units are accessible through
264 * the mini-PCIe connectors on the board.
267 /* Port 1, Lane 0. CON3, nearest power. */
268 reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>;
276 clearfog_i2c1_pins: i2c1-pins {
277 /* SFP, PCIe, mSATA, mikrobus */
278 marvell,pins = "mpp26", "mpp27";
279 marvell,function = "i2c1";
281 clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins {
282 marvell,pins = "mpp20";
283 marvell,function = "gpio";
285 mikro_pins: mikro-pins {
286 /* int: mpp22 rst: mpp29 */
287 marvell,pins = "mpp22", "mpp29";
288 marvell,function = "gpio";
290 mikro_spi_pins: mikro-spi-pins {
291 marvell,pins = "mpp43";
292 marvell,function = "spi1";
294 mikro_uart_pins: mikro-uart-pins {
295 marvell,pins = "mpp24", "mpp25";
296 marvell,function = "ua1";
302 * Add SPI CS pins for clearfog:
303 * CS0: W25Q32 (not populated on uSOM)
304 * CS1: PIC microcontroller (Pro models)
307 pinctrl-0 = <&spi1_pins &mikro_spi_pins>;
308 pinctrl-names = "default";