1 # SPDX-License-Identifier: GPL-2.0-only
3 # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
9 select ARCH_HAS_DMA_PREP_COHERENT
10 select ARCH_HAS_PTE_SPECIAL
11 select ARCH_HAS_SETUP_DMA_OPS
12 select ARCH_HAS_SYNC_DMA_FOR_CPU
13 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
14 select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC
15 select ARCH_32BIT_OFF_T
16 select BUILDTIME_EXTABLE_SORT
17 select CLONE_BACKWARDS
19 select DMA_DIRECT_REMAP
20 select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC)
21 select GENERIC_CLOCKEVENTS
22 select GENERIC_FIND_FIRST_BIT
23 # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP
24 select GENERIC_IRQ_SHOW
25 select GENERIC_PCI_IOMAP
26 select GENERIC_PENDING_IRQ if SMP
27 select GENERIC_SCHED_CLOCK
28 select GENERIC_SMP_IDLE_THREAD
30 select HAVE_ARCH_TRACEHOOK
31 select HAVE_DEBUG_STACKOVERFLOW
32 select HAVE_FUTEX_CMPXCHG if FUTEX
33 select HAVE_IOREMAP_PROT
34 select HAVE_KERNEL_GZIP
35 select HAVE_KERNEL_LZMA
37 select HAVE_KRETPROBES
38 select HAVE_MOD_ARCH_SPECIFIC
40 select HAVE_PERF_EVENTS
41 select HANDLE_DOMAIN_IRQ
43 select MODULES_USE_ELF_RELA
45 select OF_EARLY_FLATTREE
46 select PCI_SYSCALL if PCI
47 select PERF_USE_VMALLOC if ARC_CACHE_VIPT_ALIASING
49 config ARCH_HAS_CACHE_LINE_SIZE
52 config TRACE_IRQFLAGS_SUPPORT
55 config LOCKDEP_SUPPORT
58 config SCHED_OMIT_FRAME_POINTER
64 config ARCH_DISCONTIGMEM_ENABLE
67 config ARCH_FLATMEM_ENABLE
76 config GENERIC_CALIBRATE_DELAY
79 config GENERIC_HWEIGHT
82 config STACKTRACE_SUPPORT
86 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
90 menu "ARC Architecture Configuration"
92 menu "ARC Platform/SoC/Board"
94 source "arch/arc/plat-tb10x/Kconfig"
95 source "arch/arc/plat-axs10x/Kconfig"
96 #New platform adds here
97 source "arch/arc/plat-eznps/Kconfig"
98 source "arch/arc/plat-hsdk/Kconfig"
103 prompt "ARC Instruction Set"
108 select CPU_NO_EFFICIENT_FFS
110 The original ARC ISA of ARC600/700 cores
114 select ARC_TIMERS_64BIT
116 ISA for the Next Generation ARC-HS cores
120 menu "ARC CPU Configuration"
124 default ARC_CPU_770 if ISA_ARCOMPACT
125 default ARC_CPU_HS if ISA_ARCV2
133 Support for ARC750 core
139 Support for ARC770 core introduced with Rel 4.10 (Summer 2011)
140 This core has a bunch of cool new features:
141 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
142 Shared Address Spaces (for sharing TLB entries in MMU)
143 -Caches: New Prog Model, Region Flush
144 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
152 Support for ARC HS38x Cores based on ARCv2 ISA
153 The notable features are:
154 - SMP configurations of upto 4 core with coherency
155 - Optional L2 Cache and IO-Coherency
156 - Revised Interrupt Architecture (multiple priorites, reg banks,
157 auto stack switch, auto regfile save/restore)
158 - MMUv4 (PIPT dcache, Huge Pages)
160 * 64bit load/store: LDD, STD
161 * Hardware assisted divide/remainder: DIV, REM
162 * Function prologue/epilogue: ENTER_S, LEAVE_S
163 * IRQ enable/disable: CLRI, SETI
164 * pop count: FFS, FLS
165 * SETcc, BMSKN, XBFU...
169 config CPU_BIG_ENDIAN
170 bool "Enable Big Endian Mode"
172 Build kernel for Big Endian Mode of ARC CPU
175 bool "Symmetric Multi-Processing"
176 select ARC_MCIP if ISA_ARCV2
178 This enables support for systems with more than one CPU.
183 int "Maximum number of CPUs (2-4096)"
187 config ARC_SMP_HALT_ON_RESET
188 bool "Enable Halt-on-reset boot mode"
190 In SMP configuration cores can be configured as Halt-on-reset
191 or they could all start at same time. For Halt-on-reset, non
192 masters are parked until Master kicks them so they can start of
193 at designated entry point. For other case, all jump to common
194 entry point and spin wait for Master's signal.
199 bool "ARConnect Multicore IP (MCIP) Support "
203 This IP block enables SMP in ARC-HS38 cores.
204 It provides for cross-core interrupts, multi-core debug
205 hardware semaphores, shared memory,....
208 bool "Enable Cache Support"
213 config ARC_CACHE_LINE_SHIFT
214 int "Cache Line Length (as power of 2)"
218 Starting with ARC700 4.9, Cache line length is configurable,
219 This option specifies "N", with Line-len = 2 power N
220 So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
221 Linux only supports same line lengths for I and D caches.
223 config ARC_HAS_ICACHE
224 bool "Use Instruction Cache"
227 config ARC_HAS_DCACHE
228 bool "Use Data Cache"
231 config ARC_CACHE_PAGES
232 bool "Per Page Cache Control"
234 depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE
236 This can be used to over-ride the global I/D Cache Enable on a
237 per-page basis (but only for pages accessed via MMU such as
238 Kernel Virtual address or User Virtual Address)
239 TLB entries have a per-page Cache Enable Bit.
240 Note that Global I/D ENABLE + Per Page DISABLE works but corollary
241 Global DISABLE + Per Page ENABLE won't work
243 config ARC_CACHE_VIPT_ALIASING
244 bool "Support VIPT Aliasing D$"
245 depends on ARC_HAS_DCACHE && ISA_ARCOMPACT
252 Single Cycle RAMS to store Fast Path Code
255 int "ICCM Size in KB"
257 depends on ARC_HAS_ICCM
262 Single Cycle RAMS to store Fast Path Data
265 int "DCCM Size in KB"
267 depends on ARC_HAS_DCCM
270 hex "DCCM map address"
272 depends on ARC_HAS_DCCM
276 default ARC_MMU_V3 if ARC_CPU_770
277 default ARC_MMU_V2 if ARC_CPU_750D
278 default ARC_MMU_V4 if ARC_CPU_HS
290 Fixed the deficiency of v1 - possible thrashing in memcpy scenario
291 when 2 D-TLB and 1 I-TLB entries index into same 2way set.
295 depends on ARC_CPU_770
297 Introduced with ARC700 4.10: New Features
298 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
299 Shared Address Spaces (SASID)
311 prompt "MMU Page Size"
312 default ARC_PAGE_SIZE_8K
314 config ARC_PAGE_SIZE_8K
317 Choose between 8k vs 16k
319 config ARC_PAGE_SIZE_16K
321 depends on ARC_MMU_V3 || ARC_MMU_V4
323 config ARC_PAGE_SIZE_4K
325 depends on ARC_MMU_V3 || ARC_MMU_V4
330 prompt "MMU Super Page Size"
331 depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE
332 default ARC_HUGEPAGE_2M
334 config ARC_HUGEPAGE_2M
337 config ARC_HUGEPAGE_16M
343 int "Maximum NUMA Nodes (as a power of 2)"
344 default "0" if !DISCONTIGMEM
345 default "1" if DISCONTIGMEM
346 depends on NEED_MULTIPLE_NODES
348 Accessing memory beyond 1GB (with or w/o PAE) requires 2 memory
353 config ARC_COMPACT_IRQ_LEVELS
354 bool "Setup Timer IRQ as high Priority"
355 # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy
358 config ARC_FPU_SAVE_RESTORE
359 bool "Enable FPU state persistence across context switch"
361 Double Precision Floating Point unit had dedicated regs which
362 need to be saved/restored across context-switch.
363 Note that ARC FPU is overly simplistic, unlike say x86, which has
364 hardware pieces to allow software to conditionally save/restore,
365 based on actual usage of FPU by a task. Thus our implemn does
366 this for all tasks in system.
374 bool "Insn: LLOCK/SCOND (efficient atomic ops)"
376 depends on !ARC_CANT_LLSC
379 bool "Insn: SWAPE (endian-swap)"
384 config ARC_USE_UNALIGNED_MEM_ACCESS
385 bool "Enable unaligned access in HW"
387 select HAVE_EFFICIENT_UNALIGNED_ACCESS
389 The ARC HS architecture supports unaligned memory access
390 which is disabled by default. Enable unaligned access in
391 hardware and use software to use it
394 bool "Insn: 64bit LDD/STD"
396 Enable gcc to generate 64-bit load/store instructions
397 ISA mandates even/odd registers to allow encoding of two
398 dest operands with 2 possible source operands.
401 config ARC_HAS_DIV_REM
402 bool "Insn: div, divu, rem, remu"
405 config ARC_HAS_ACCL_REGS
406 bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6)"
409 Depending on the configuration, CPU can contain accumulator reg-pair
410 (also referred to as r58:r59). These can also be used by gcc as GPR so
411 kernel needs to save/restore per process
413 config ARC_IRQ_NO_AUTOSAVE
414 bool "Disable hardware autosave regfile on interrupts"
417 On HS cores, taken interrupt auto saves the regfile on stack.
418 This is programmable and can be optionally disabled in which case
419 software INTERRUPT_PROLOGUE/EPILGUE do the needed work
423 endmenu # "ARC CPU Configuration"
425 config LINUX_LINK_BASE
426 hex "Kernel link address"
429 ARC700 divides the 32 bit phy address space into two equal halves
430 -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU
431 -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel
432 Typically Linux kernel is linked at the start of untransalted addr,
433 hence the default value of 0x8zs.
434 However some customers have peripherals mapped at this addr, so
435 Linux needs to be scooted a bit.
436 If you don't know what the above means, leave this setting alone.
437 This needs to match memory start address specified in Device Tree
439 config LINUX_RAM_BASE
440 hex "RAM base address"
441 default LINUX_LINK_BASE
443 By default Linux is linked at base of RAM. However in some special
444 cases (such as HSDK), Linux can't be linked at start of DDR, hence
448 bool "High Memory Support"
449 select ARCH_DISCONTIGMEM_ENABLE
451 With ARC 2G:2G address split, only upper 2G is directly addressable by
452 kernel. Enable this to potentially allow access to rest of 2G and PAE
456 bool "Support for the 40-bit Physical Address Extension"
459 select PHYS_ADDR_T_64BIT
461 Enable access to physical memory beyond 4G, only supported on
462 ARC cores with 40 bit Physical Addressing support
464 config ARC_KVADDR_SIZE
465 int "Kernel Virtual Address Space size (MB)"
469 The kernel address space is carved out of 256MB of translated address
470 space for catering to vmalloc, modules, pkmap, fixmap. This however may
471 not suffice vmalloc requirements of a 4K CPU EZChip system. So allow
472 this to be stretched to 512 MB (by extending into the reserved
475 config ARC_CURR_IN_REG
476 bool "Dedicate Register r25 for current_task pointer"
479 This reserved Register R25 to point to Current Task in
480 kernel mode. This saves memory access for each such access
483 config ARC_EMUL_UNALIGNED
484 bool "Emulate unaligned memory access (userspace only)"
485 select SYSCTL_ARCH_UNALIGN_NO_WARN
486 select SYSCTL_ARCH_UNALIGN_ALLOW
487 depends on ISA_ARCOMPACT
489 This enables misaligned 16 & 32 bit memory access from user space.
490 Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide
491 potential bugs in code
494 int "Timer Frequency"
497 config ARC_METAWARE_HLINK
498 bool "Support for Metaware debugger assisted Host access"
500 This options allows a Linux userland apps to directly access
501 host file system (open/creat/read/write etc) with help from
502 Metaware Debugger. This can come in handy for Linux-host communication
503 when there is no real usable peripheral such as EMAC.
511 config ARC_DW2_UNWIND
512 bool "Enable DWARF specific kernel stack unwind"
516 Compiles the kernel with DWARF unwind information and can be used
517 to get stack backtraces.
519 If you say Y here the resulting kernel image will be slightly larger
520 but not slower, and it will give very useful debugging information.
521 If you don't debug the kernel, you can say N, but we may not be able
522 to solve problems without frame unwind information
524 config ARC_DBG_TLB_PARANOIA
525 bool "Paranoia Checks in Low Level TLB Handlers"
529 config ARC_BUILTIN_DTB_NAME
530 string "Built in DTB"
532 Set the name of the DTB to embed in the vmlinux binary
533 Leaving it blank selects the minimal "skeleton" dtb
535 endmenu # "ARC Architecture Configuration"
537 config FORCE_MAX_ZONEORDER
538 int "Maximum zone order"
539 default "12" if ARC_HUGEPAGE_16M
542 source "kernel/power/Kconfig"