| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * Synopsys DesignWare PCIe host controller driver |
| 4 | * |
| 5 | * Copyright (C) 2013 Samsung Electronics Co., Ltd. |
| 6 | * http://www.samsung.com |
| 7 | * |
| 8 | * Author: Jingoo Han <jg1.han@samsung.com> |
| 9 | */ |
| 10 | |
| 11 | #ifndef _PCIE_DESIGNWARE_H |
| 12 | #define _PCIE_DESIGNWARE_H |
| 13 | |
| 14 | #include <linux/bitfield.h> |
| 15 | #include <linux/dma-mapping.h> |
| 16 | #include <linux/irq.h> |
| 17 | #include <linux/msi.h> |
| 18 | #include <linux/pci.h> |
| 19 | |
| 20 | #include <linux/pci-epc.h> |
| 21 | #include <linux/pci-epf.h> |
| 22 | |
| 23 | /* Parameters for the waiting for link up routine */ |
| 24 | #define LINK_WAIT_MAX_RETRIES 10 |
| 25 | #define LINK_WAIT_USLEEP_MIN 90000 |
| 26 | #define LINK_WAIT_USLEEP_MAX 100000 |
| 27 | |
| 28 | /* Parameters for the waiting for iATU enabled routine */ |
| 29 | #define LINK_WAIT_MAX_IATU_RETRIES 5 |
| 30 | #define LINK_WAIT_IATU 9 |
| 31 | |
| 32 | /* Synopsys-specific PCIe configuration registers */ |
| 33 | #define PCIE_PORT_LINK_CONTROL 0x710 |
| 34 | #define PORT_LINK_MODE_MASK GENMASK(21, 16) |
| 35 | #define PORT_LINK_MODE(n) FIELD_PREP(PORT_LINK_MODE_MASK, n) |
| 36 | #define PORT_LINK_MODE_1_LANES PORT_LINK_MODE(0x1) |
| 37 | #define PORT_LINK_MODE_2_LANES PORT_LINK_MODE(0x3) |
| 38 | #define PORT_LINK_MODE_4_LANES PORT_LINK_MODE(0x7) |
| 39 | #define PORT_LINK_MODE_8_LANES PORT_LINK_MODE(0xf) |
| 40 | |
| 41 | #define PCIE_PORT_DEBUG0 0x728 |
| 42 | #define PORT_LOGIC_LTSSM_STATE_MASK 0x1f |
| 43 | #define PORT_LOGIC_LTSSM_STATE_L0 0x11 |
| 44 | |
| 45 | #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C |
| 46 | #define PORT_LOGIC_SPEED_CHANGE BIT(17) |
| 47 | #define PORT_LOGIC_LINK_WIDTH_MASK GENMASK(12, 8) |
| 48 | #define PORT_LOGIC_LINK_WIDTH(n) FIELD_PREP(PORT_LOGIC_LINK_WIDTH_MASK, n) |
| 49 | #define PORT_LOGIC_LINK_WIDTH_1_LANES PORT_LOGIC_LINK_WIDTH(0x1) |
| 50 | #define PORT_LOGIC_LINK_WIDTH_2_LANES PORT_LOGIC_LINK_WIDTH(0x2) |
| 51 | #define PORT_LOGIC_LINK_WIDTH_4_LANES PORT_LOGIC_LINK_WIDTH(0x4) |
| 52 | #define PORT_LOGIC_LINK_WIDTH_8_LANES PORT_LOGIC_LINK_WIDTH(0x8) |
| 53 | |
| 54 | #define PCIE_MSI_ADDR_LO 0x820 |
| 55 | #define PCIE_MSI_ADDR_HI 0x824 |
| 56 | #define PCIE_MSI_INTR0_ENABLE 0x828 |
| 57 | #define PCIE_MSI_INTR0_MASK 0x82C |
| 58 | #define PCIE_MSI_INTR0_STATUS 0x830 |
| 59 | |
| 60 | #define PCIE_ATU_VIEWPORT 0x900 |
| 61 | #define PCIE_ATU_REGION_INBOUND BIT(31) |
| 62 | #define PCIE_ATU_REGION_OUTBOUND 0 |
| 63 | #define PCIE_ATU_REGION_INDEX2 0x2 |
| 64 | #define PCIE_ATU_REGION_INDEX1 0x1 |
| 65 | #define PCIE_ATU_REGION_INDEX0 0x0 |
| 66 | #define PCIE_ATU_CR1 0x904 |
| 67 | #define PCIE_ATU_TYPE_MEM 0x0 |
| 68 | #define PCIE_ATU_TYPE_IO 0x2 |
| 69 | #define PCIE_ATU_TYPE_CFG0 0x4 |
| 70 | #define PCIE_ATU_TYPE_CFG1 0x5 |
| 71 | #define PCIE_ATU_CR2 0x908 |
| 72 | #define PCIE_ATU_ENABLE BIT(31) |
| 73 | #define PCIE_ATU_BAR_MODE_ENABLE BIT(30) |
| 74 | #define PCIE_ATU_LOWER_BASE 0x90C |
| 75 | #define PCIE_ATU_UPPER_BASE 0x910 |
| 76 | #define PCIE_ATU_LIMIT 0x914 |
| 77 | #define PCIE_ATU_LOWER_TARGET 0x918 |
| 78 | #define PCIE_ATU_BUS(x) FIELD_PREP(GENMASK(31, 24), x) |
| 79 | #define PCIE_ATU_DEV(x) FIELD_PREP(GENMASK(23, 19), x) |
| 80 | #define PCIE_ATU_FUNC(x) FIELD_PREP(GENMASK(18, 16), x) |
| 81 | #define PCIE_ATU_UPPER_TARGET 0x91C |
| 82 | |
| 83 | #define PCIE_MISC_CONTROL_1_OFF 0x8BC |
| 84 | #define PCIE_DBI_RO_WR_EN BIT(0) |
| 85 | |
| 86 | /* |
| 87 | * iATU Unroll-specific register definitions |
| 88 | * From 4.80 core version the address translation will be made by unroll |
| 89 | */ |
| 90 | #define PCIE_ATU_UNR_REGION_CTRL1 0x00 |
| 91 | #define PCIE_ATU_UNR_REGION_CTRL2 0x04 |
| 92 | #define PCIE_ATU_UNR_LOWER_BASE 0x08 |
| 93 | #define PCIE_ATU_UNR_UPPER_BASE 0x0C |
| 94 | #define PCIE_ATU_UNR_LIMIT 0x10 |
| 95 | #define PCIE_ATU_UNR_LOWER_TARGET 0x14 |
| 96 | #define PCIE_ATU_UNR_UPPER_TARGET 0x18 |
| 97 | |
| 98 | /* |
| 99 | * The default address offset between dbi_base and atu_base. Root controller |
| 100 | * drivers are not required to initialize atu_base if the offset matches this |
| 101 | * default; the driver core automatically derives atu_base from dbi_base using |
| 102 | * this offset, if atu_base not set. |
| 103 | */ |
| 104 | #define DEFAULT_DBI_ATU_OFFSET (0x3 << 20) |
| 105 | |
| 106 | /* Register address builder */ |
| 107 | #define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region) \ |
| 108 | ((region) << 9) |
| 109 | |
| 110 | #define PCIE_GET_ATU_INB_UNR_REG_OFFSET(region) \ |
| 111 | (((region) << 9) | BIT(8)) |
| 112 | |
| 113 | #define MAX_MSI_IRQS 256 |
| 114 | #define MAX_MSI_IRQS_PER_CTRL 32 |
| 115 | #define MAX_MSI_CTRLS (MAX_MSI_IRQS / MAX_MSI_IRQS_PER_CTRL) |
| 116 | #define MSI_REG_CTRL_BLOCK_SIZE 12 |
| 117 | #define MSI_DEF_NUM_VECTORS 32 |
| 118 | |
| 119 | /* Maximum number of inbound/outbound iATUs */ |
| 120 | #define MAX_IATU_IN 256 |
| 121 | #define MAX_IATU_OUT 256 |
| 122 | |
| 123 | struct pcie_port; |
| 124 | struct dw_pcie; |
| 125 | struct dw_pcie_ep; |
| 126 | |
| 127 | enum dw_pcie_region_type { |
| 128 | DW_PCIE_REGION_UNKNOWN, |
| 129 | DW_PCIE_REGION_INBOUND, |
| 130 | DW_PCIE_REGION_OUTBOUND, |
| 131 | }; |
| 132 | |
| 133 | enum dw_pcie_device_mode { |
| 134 | DW_PCIE_UNKNOWN_TYPE, |
| 135 | DW_PCIE_EP_TYPE, |
| 136 | DW_PCIE_LEG_EP_TYPE, |
| 137 | DW_PCIE_RC_TYPE, |
| 138 | }; |
| 139 | |
| 140 | struct dw_pcie_host_ops { |
| 141 | int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val); |
| 142 | int (*wr_own_conf)(struct pcie_port *pp, int where, int size, u32 val); |
| 143 | int (*rd_other_conf)(struct pcie_port *pp, struct pci_bus *bus, |
| 144 | unsigned int devfn, int where, int size, u32 *val); |
| 145 | int (*wr_other_conf)(struct pcie_port *pp, struct pci_bus *bus, |
| 146 | unsigned int devfn, int where, int size, u32 val); |
| 147 | int (*host_init)(struct pcie_port *pp); |
| 148 | void (*scan_bus)(struct pcie_port *pp); |
| 149 | void (*set_num_vectors)(struct pcie_port *pp); |
| 150 | int (*msi_host_init)(struct pcie_port *pp); |
| 151 | }; |
| 152 | |
| 153 | struct pcie_port { |
| 154 | u8 root_bus_nr; |
| 155 | u64 cfg0_base; |
| 156 | void __iomem *va_cfg0_base; |
| 157 | u32 cfg0_size; |
| 158 | u64 cfg1_base; |
| 159 | void __iomem *va_cfg1_base; |
| 160 | u32 cfg1_size; |
| 161 | resource_size_t io_base; |
| 162 | phys_addr_t io_bus_addr; |
| 163 | u32 io_size; |
| 164 | u64 mem_base; |
| 165 | phys_addr_t mem_bus_addr; |
| 166 | u32 mem_size; |
| 167 | struct resource *cfg; |
| 168 | struct resource *io; |
| 169 | struct resource *mem; |
| 170 | struct resource *busn; |
| 171 | int irq; |
| 172 | const struct dw_pcie_host_ops *ops; |
| 173 | int msi_irq; |
| 174 | struct irq_domain *irq_domain; |
| 175 | struct irq_domain *msi_domain; |
| 176 | dma_addr_t msi_data; |
| 177 | struct irq_chip *msi_irq_chip; |
| 178 | u32 num_vectors; |
| 179 | u32 irq_mask[MAX_MSI_CTRLS]; |
| 180 | raw_spinlock_t lock; |
| 181 | DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS); |
| 182 | }; |
| 183 | |
| 184 | enum dw_pcie_as_type { |
| 185 | DW_PCIE_AS_UNKNOWN, |
| 186 | DW_PCIE_AS_MEM, |
| 187 | DW_PCIE_AS_IO, |
| 188 | }; |
| 189 | |
| 190 | struct dw_pcie_ep_ops { |
| 191 | void (*ep_init)(struct dw_pcie_ep *ep); |
| 192 | int (*raise_irq)(struct dw_pcie_ep *ep, u8 func_no, |
| 193 | enum pci_epc_irq_type type, u16 interrupt_num); |
| 194 | const struct pci_epc_features* (*get_features)(struct dw_pcie_ep *ep); |
| 195 | }; |
| 196 | |
| 197 | struct dw_pcie_ep { |
| 198 | struct pci_epc *epc; |
| 199 | const struct dw_pcie_ep_ops *ops; |
| 200 | phys_addr_t phys_base; |
| 201 | size_t addr_size; |
| 202 | size_t page_size; |
| 203 | u8 bar_to_atu[6]; |
| 204 | phys_addr_t *outbound_addr; |
| 205 | unsigned long *ib_window_map; |
| 206 | unsigned long *ob_window_map; |
| 207 | u32 num_ib_windows; |
| 208 | u32 num_ob_windows; |
| 209 | void __iomem *msi_mem; |
| 210 | phys_addr_t msi_mem_phys; |
| 211 | u8 msi_cap; /* MSI capability offset */ |
| 212 | u8 msix_cap; /* MSI-X capability offset */ |
| 213 | }; |
| 214 | |
| 215 | struct dw_pcie_ops { |
| 216 | u64 (*cpu_addr_fixup)(struct dw_pcie *pcie, u64 cpu_addr); |
| 217 | u32 (*read_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg, |
| 218 | size_t size); |
| 219 | void (*write_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg, |
| 220 | size_t size, u32 val); |
| 221 | int (*link_up)(struct dw_pcie *pcie); |
| 222 | int (*start_link)(struct dw_pcie *pcie); |
| 223 | void (*stop_link)(struct dw_pcie *pcie); |
| 224 | }; |
| 225 | |
| 226 | struct dw_pcie { |
| 227 | struct device *dev; |
| 228 | void __iomem *dbi_base; |
| 229 | void __iomem *dbi_base2; |
| 230 | /* Used when iatu_unroll_enabled is true */ |
| 231 | void __iomem *atu_base; |
| 232 | u32 num_viewport; |
| 233 | u8 iatu_unroll_enabled; |
| 234 | struct pcie_port pp; |
| 235 | struct dw_pcie_ep ep; |
| 236 | const struct dw_pcie_ops *ops; |
| 237 | unsigned int version; |
| 238 | }; |
| 239 | |
| 240 | #define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp) |
| 241 | |
| 242 | #define to_dw_pcie_from_ep(endpoint) \ |
| 243 | container_of((endpoint), struct dw_pcie, ep) |
| 244 | |
| 245 | int dw_pcie_read(void __iomem *addr, int size, u32 *val); |
| 246 | int dw_pcie_write(void __iomem *addr, int size, u32 val); |
| 247 | |
| 248 | u32 __dw_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg, |
| 249 | size_t size); |
| 250 | void __dw_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg, |
| 251 | size_t size, u32 val); |
| 252 | int dw_pcie_link_up(struct dw_pcie *pci); |
| 253 | int dw_pcie_wait_for_link(struct dw_pcie *pci); |
| 254 | void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, |
| 255 | int type, u64 cpu_addr, u64 pci_addr, |
| 256 | u32 size); |
| 257 | int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int bar, |
| 258 | u64 cpu_addr, enum dw_pcie_as_type as_type); |
| 259 | void dw_pcie_disable_atu(struct dw_pcie *pci, int index, |
| 260 | enum dw_pcie_region_type type); |
| 261 | void dw_pcie_setup(struct dw_pcie *pci); |
| 262 | |
| 263 | static inline void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val) |
| 264 | { |
| 265 | __dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x4, val); |
| 266 | } |
| 267 | |
| 268 | static inline u32 dw_pcie_readl_dbi(struct dw_pcie *pci, u32 reg) |
| 269 | { |
| 270 | return __dw_pcie_read_dbi(pci, pci->dbi_base, reg, 0x4); |
| 271 | } |
| 272 | |
| 273 | static inline void dw_pcie_writew_dbi(struct dw_pcie *pci, u32 reg, u16 val) |
| 274 | { |
| 275 | __dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x2, val); |
| 276 | } |
| 277 | |
| 278 | static inline u16 dw_pcie_readw_dbi(struct dw_pcie *pci, u32 reg) |
| 279 | { |
| 280 | return __dw_pcie_read_dbi(pci, pci->dbi_base, reg, 0x2); |
| 281 | } |
| 282 | |
| 283 | static inline void dw_pcie_writeb_dbi(struct dw_pcie *pci, u32 reg, u8 val) |
| 284 | { |
| 285 | __dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x1, val); |
| 286 | } |
| 287 | |
| 288 | static inline u8 dw_pcie_readb_dbi(struct dw_pcie *pci, u32 reg) |
| 289 | { |
| 290 | return __dw_pcie_read_dbi(pci, pci->dbi_base, reg, 0x1); |
| 291 | } |
| 292 | |
| 293 | static inline void dw_pcie_writel_dbi2(struct dw_pcie *pci, u32 reg, u32 val) |
| 294 | { |
| 295 | __dw_pcie_write_dbi(pci, pci->dbi_base2, reg, 0x4, val); |
| 296 | } |
| 297 | |
| 298 | static inline u32 dw_pcie_readl_dbi2(struct dw_pcie *pci, u32 reg) |
| 299 | { |
| 300 | return __dw_pcie_read_dbi(pci, pci->dbi_base2, reg, 0x4); |
| 301 | } |
| 302 | |
| 303 | static inline void dw_pcie_writel_atu(struct dw_pcie *pci, u32 reg, u32 val) |
| 304 | { |
| 305 | __dw_pcie_write_dbi(pci, pci->atu_base, reg, 0x4, val); |
| 306 | } |
| 307 | |
| 308 | static inline u32 dw_pcie_readl_atu(struct dw_pcie *pci, u32 reg) |
| 309 | { |
| 310 | return __dw_pcie_read_dbi(pci, pci->atu_base, reg, 0x4); |
| 311 | } |
| 312 | |
| 313 | static inline void dw_pcie_dbi_ro_wr_en(struct dw_pcie *pci) |
| 314 | { |
| 315 | u32 reg; |
| 316 | u32 val; |
| 317 | |
| 318 | reg = PCIE_MISC_CONTROL_1_OFF; |
| 319 | val = dw_pcie_readl_dbi(pci, reg); |
| 320 | val |= PCIE_DBI_RO_WR_EN; |
| 321 | dw_pcie_writel_dbi(pci, reg, val); |
| 322 | } |
| 323 | |
| 324 | static inline void dw_pcie_dbi_ro_wr_dis(struct dw_pcie *pci) |
| 325 | { |
| 326 | u32 reg; |
| 327 | u32 val; |
| 328 | |
| 329 | reg = PCIE_MISC_CONTROL_1_OFF; |
| 330 | val = dw_pcie_readl_dbi(pci, reg); |
| 331 | val &= ~PCIE_DBI_RO_WR_EN; |
| 332 | dw_pcie_writel_dbi(pci, reg, val); |
| 333 | } |
| 334 | |
| 335 | #ifdef CONFIG_PCIE_DW_HOST |
| 336 | irqreturn_t dw_handle_msi_irq(struct pcie_port *pp); |
| 337 | void dw_pcie_msi_init(struct pcie_port *pp); |
| 338 | void dw_pcie_free_msi(struct pcie_port *pp); |
| 339 | void dw_pcie_setup_rc(struct pcie_port *pp); |
| 340 | int dw_pcie_host_init(struct pcie_port *pp); |
| 341 | int dw_pcie_allocate_domains(struct pcie_port *pp); |
| 342 | #else |
| 343 | static inline irqreturn_t dw_handle_msi_irq(struct pcie_port *pp) |
| 344 | { |
| 345 | return IRQ_NONE; |
| 346 | } |
| 347 | |
| 348 | static inline void dw_pcie_msi_init(struct pcie_port *pp) |
| 349 | { |
| 350 | } |
| 351 | |
| 352 | static inline void dw_pcie_free_msi(struct pcie_port *pp) |
| 353 | { |
| 354 | } |
| 355 | |
| 356 | static inline void dw_pcie_setup_rc(struct pcie_port *pp) |
| 357 | { |
| 358 | } |
| 359 | |
| 360 | static inline int dw_pcie_host_init(struct pcie_port *pp) |
| 361 | { |
| 362 | return 0; |
| 363 | } |
| 364 | |
| 365 | static inline int dw_pcie_allocate_domains(struct pcie_port *pp) |
| 366 | { |
| 367 | return 0; |
| 368 | } |
| 369 | #endif |
| 370 | |
| 371 | #ifdef CONFIG_PCIE_DW_EP |
| 372 | void dw_pcie_ep_linkup(struct dw_pcie_ep *ep); |
| 373 | int dw_pcie_ep_init(struct dw_pcie_ep *ep); |
| 374 | void dw_pcie_ep_exit(struct dw_pcie_ep *ep); |
| 375 | int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no); |
| 376 | int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no, |
| 377 | u8 interrupt_num); |
| 378 | int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no, |
| 379 | u16 interrupt_num); |
| 380 | void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar); |
| 381 | #else |
| 382 | static inline void dw_pcie_ep_linkup(struct dw_pcie_ep *ep) |
| 383 | { |
| 384 | } |
| 385 | |
| 386 | static inline int dw_pcie_ep_init(struct dw_pcie_ep *ep) |
| 387 | { |
| 388 | return 0; |
| 389 | } |
| 390 | |
| 391 | static inline void dw_pcie_ep_exit(struct dw_pcie_ep *ep) |
| 392 | { |
| 393 | } |
| 394 | |
| 395 | static inline int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no) |
| 396 | { |
| 397 | return 0; |
| 398 | } |
| 399 | |
| 400 | static inline int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no, |
| 401 | u8 interrupt_num) |
| 402 | { |
| 403 | return 0; |
| 404 | } |
| 405 | |
| 406 | static inline int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no, |
| 407 | u16 interrupt_num) |
| 408 | { |
| 409 | return 0; |
| 410 | } |
| 411 | |
| 412 | static inline void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar) |
| 413 | { |
| 414 | } |
| 415 | #endif |
| 416 | #endif /* _PCIE_DESIGNWARE_H */ |