| 1 | /* |
| 2 | * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. |
| 3 | * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. |
| 4 | * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved. |
| 5 | * |
| 6 | * This software is available to you under a choice of one of two |
| 7 | * licenses. You may choose to be licensed under the terms of the GNU |
| 8 | * General Public License (GPL) Version 2, available from the file |
| 9 | * COPYING in the main directory of this source tree, or the |
| 10 | * OpenIB.org BSD license below: |
| 11 | * |
| 12 | * Redistribution and use in source and binary forms, with or |
| 13 | * without modification, are permitted provided that the following |
| 14 | * conditions are met: |
| 15 | * |
| 16 | * - Redistributions of source code must retain the above |
| 17 | * copyright notice, this list of conditions and the following |
| 18 | * disclaimer. |
| 19 | * |
| 20 | * - Redistributions in binary form must reproduce the above |
| 21 | * copyright notice, this list of conditions and the following |
| 22 | * disclaimer in the documentation and/or other materials |
| 23 | * provided with the distribution. |
| 24 | * |
| 25 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| 26 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 27 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| 28 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS |
| 29 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN |
| 30 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
| 31 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 32 | * SOFTWARE. |
| 33 | */ |
| 34 | |
| 35 | #include <linux/etherdevice.h> |
| 36 | #include <linux/mlx4/cmd.h> |
| 37 | #include <linux/module.h> |
| 38 | #include <linux/cache.h> |
| 39 | |
| 40 | #include "fw.h" |
| 41 | #include "icm.h" |
| 42 | |
| 43 | enum { |
| 44 | MLX4_COMMAND_INTERFACE_MIN_REV = 2, |
| 45 | MLX4_COMMAND_INTERFACE_MAX_REV = 3, |
| 46 | MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3, |
| 47 | }; |
| 48 | |
| 49 | extern void __buggy_use_of_MLX4_GET(void); |
| 50 | extern void __buggy_use_of_MLX4_PUT(void); |
| 51 | |
| 52 | static bool enable_qos; |
| 53 | module_param(enable_qos, bool, 0444); |
| 54 | MODULE_PARM_DESC(enable_qos, "Enable Enhanced QoS support (default: off)"); |
| 55 | |
| 56 | #define MLX4_GET(dest, source, offset) \ |
| 57 | do { \ |
| 58 | void *__p = (char *) (source) + (offset); \ |
| 59 | u64 val; \ |
| 60 | switch (sizeof (dest)) { \ |
| 61 | case 1: (dest) = *(u8 *) __p; break; \ |
| 62 | case 2: (dest) = be16_to_cpup(__p); break; \ |
| 63 | case 4: (dest) = be32_to_cpup(__p); break; \ |
| 64 | case 8: val = get_unaligned((u64 *)__p); \ |
| 65 | (dest) = be64_to_cpu(val); break; \ |
| 66 | default: __buggy_use_of_MLX4_GET(); \ |
| 67 | } \ |
| 68 | } while (0) |
| 69 | |
| 70 | #define MLX4_PUT(dest, source, offset) \ |
| 71 | do { \ |
| 72 | void *__d = ((char *) (dest) + (offset)); \ |
| 73 | switch (sizeof(source)) { \ |
| 74 | case 1: *(u8 *) __d = (source); break; \ |
| 75 | case 2: *(__be16 *) __d = cpu_to_be16(source); break; \ |
| 76 | case 4: *(__be32 *) __d = cpu_to_be32(source); break; \ |
| 77 | case 8: *(__be64 *) __d = cpu_to_be64(source); break; \ |
| 78 | default: __buggy_use_of_MLX4_PUT(); \ |
| 79 | } \ |
| 80 | } while (0) |
| 81 | |
| 82 | static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags) |
| 83 | { |
| 84 | static const char *fname[] = { |
| 85 | [ 0] = "RC transport", |
| 86 | [ 1] = "UC transport", |
| 87 | [ 2] = "UD transport", |
| 88 | [ 3] = "XRC transport", |
| 89 | [ 6] = "SRQ support", |
| 90 | [ 7] = "IPoIB checksum offload", |
| 91 | [ 8] = "P_Key violation counter", |
| 92 | [ 9] = "Q_Key violation counter", |
| 93 | [12] = "Dual Port Different Protocol (DPDP) support", |
| 94 | [15] = "Big LSO headers", |
| 95 | [16] = "MW support", |
| 96 | [17] = "APM support", |
| 97 | [18] = "Atomic ops support", |
| 98 | [19] = "Raw multicast support", |
| 99 | [20] = "Address vector port checking support", |
| 100 | [21] = "UD multicast support", |
| 101 | [30] = "IBoE support", |
| 102 | [32] = "Unicast loopback support", |
| 103 | [34] = "FCS header control", |
| 104 | [37] = "Wake On LAN (port1) support", |
| 105 | [38] = "Wake On LAN (port2) support", |
| 106 | [40] = "UDP RSS support", |
| 107 | [41] = "Unicast VEP steering support", |
| 108 | [42] = "Multicast VEP steering support", |
| 109 | [48] = "Counters support", |
| 110 | [52] = "RSS IP fragments support", |
| 111 | [53] = "Port ETS Scheduler support", |
| 112 | [55] = "Port link type sensing support", |
| 113 | [59] = "Port management change event support", |
| 114 | [61] = "64 byte EQE support", |
| 115 | [62] = "64 byte CQE support", |
| 116 | }; |
| 117 | int i; |
| 118 | |
| 119 | mlx4_dbg(dev, "DEV_CAP flags:\n"); |
| 120 | for (i = 0; i < ARRAY_SIZE(fname); ++i) |
| 121 | if (fname[i] && (flags & (1LL << i))) |
| 122 | mlx4_dbg(dev, " %s\n", fname[i]); |
| 123 | } |
| 124 | |
| 125 | static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags) |
| 126 | { |
| 127 | static const char * const fname[] = { |
| 128 | [0] = "RSS support", |
| 129 | [1] = "RSS Toeplitz Hash Function support", |
| 130 | [2] = "RSS XOR Hash Function support", |
| 131 | [3] = "Device managed flow steering support", |
| 132 | [4] = "Automatic MAC reassignment support", |
| 133 | [5] = "Time stamping support", |
| 134 | [6] = "VST (control vlan insertion/stripping) support", |
| 135 | [7] = "FSM (MAC anti-spoofing) support", |
| 136 | [8] = "Dynamic QP updates support", |
| 137 | [9] = "Device managed flow steering IPoIB support", |
| 138 | [10] = "TCP/IP offloads/flow-steering for VXLAN support", |
| 139 | [11] = "MAD DEMUX (Secure-Host) support", |
| 140 | [12] = "Large cache line (>64B) CQE stride support", |
| 141 | [13] = "Large cache line (>64B) EQE stride support", |
| 142 | [14] = "Ethernet protocol control support", |
| 143 | [15] = "Ethernet Backplane autoneg support", |
| 144 | [16] = "CONFIG DEV support", |
| 145 | [17] = "Asymmetric EQs support", |
| 146 | [18] = "More than 80 VFs support", |
| 147 | [19] = "Performance optimized for limited rule configuration flow steering support", |
| 148 | [20] = "Recoverable error events support", |
| 149 | [21] = "Port Remap support", |
| 150 | [22] = "QCN support", |
| 151 | [23] = "QP rate limiting support", |
| 152 | [24] = "Ethernet Flow control statistics support", |
| 153 | [25] = "Granular QoS per VF support", |
| 154 | [26] = "Port ETS Scheduler support", |
| 155 | [27] = "Port beacon support", |
| 156 | [28] = "RX-ALL support", |
| 157 | [29] = "802.1ad offload support", |
| 158 | [31] = "Modifying loopback source checks using UPDATE_QP support", |
| 159 | [32] = "Loopback source checks support", |
| 160 | [33] = "RoCEv2 support", |
| 161 | [34] = "DMFS Sniffer support (UC & MC)", |
| 162 | [35] = "QinQ VST mode support", |
| 163 | [36] = "sl to vl mapping table change event support" |
| 164 | }; |
| 165 | int i; |
| 166 | |
| 167 | for (i = 0; i < ARRAY_SIZE(fname); ++i) |
| 168 | if (fname[i] && (flags & (1LL << i))) |
| 169 | mlx4_dbg(dev, " %s\n", fname[i]); |
| 170 | } |
| 171 | |
| 172 | int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg) |
| 173 | { |
| 174 | struct mlx4_cmd_mailbox *mailbox; |
| 175 | u32 *inbox; |
| 176 | int err = 0; |
| 177 | |
| 178 | #define MOD_STAT_CFG_IN_SIZE 0x100 |
| 179 | |
| 180 | #define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002 |
| 181 | #define MOD_STAT_CFG_PG_SZ_OFFSET 0x003 |
| 182 | |
| 183 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 184 | if (IS_ERR(mailbox)) |
| 185 | return PTR_ERR(mailbox); |
| 186 | inbox = mailbox->buf; |
| 187 | |
| 188 | MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET); |
| 189 | MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET); |
| 190 | |
| 191 | err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG, |
| 192 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
| 193 | |
| 194 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 195 | return err; |
| 196 | } |
| 197 | |
| 198 | int mlx4_QUERY_FUNC(struct mlx4_dev *dev, struct mlx4_func *func, int slave) |
| 199 | { |
| 200 | struct mlx4_cmd_mailbox *mailbox; |
| 201 | u32 *outbox; |
| 202 | u8 in_modifier; |
| 203 | u8 field; |
| 204 | u16 field16; |
| 205 | int err; |
| 206 | |
| 207 | #define QUERY_FUNC_BUS_OFFSET 0x00 |
| 208 | #define QUERY_FUNC_DEVICE_OFFSET 0x01 |
| 209 | #define QUERY_FUNC_FUNCTION_OFFSET 0x01 |
| 210 | #define QUERY_FUNC_PHYSICAL_FUNCTION_OFFSET 0x03 |
| 211 | #define QUERY_FUNC_RSVD_EQS_OFFSET 0x04 |
| 212 | #define QUERY_FUNC_MAX_EQ_OFFSET 0x06 |
| 213 | #define QUERY_FUNC_RSVD_UARS_OFFSET 0x0b |
| 214 | |
| 215 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 216 | if (IS_ERR(mailbox)) |
| 217 | return PTR_ERR(mailbox); |
| 218 | outbox = mailbox->buf; |
| 219 | |
| 220 | in_modifier = slave; |
| 221 | |
| 222 | err = mlx4_cmd_box(dev, 0, mailbox->dma, in_modifier, 0, |
| 223 | MLX4_CMD_QUERY_FUNC, |
| 224 | MLX4_CMD_TIME_CLASS_A, |
| 225 | MLX4_CMD_NATIVE); |
| 226 | if (err) |
| 227 | goto out; |
| 228 | |
| 229 | MLX4_GET(field, outbox, QUERY_FUNC_BUS_OFFSET); |
| 230 | func->bus = field & 0xf; |
| 231 | MLX4_GET(field, outbox, QUERY_FUNC_DEVICE_OFFSET); |
| 232 | func->device = field & 0xf1; |
| 233 | MLX4_GET(field, outbox, QUERY_FUNC_FUNCTION_OFFSET); |
| 234 | func->function = field & 0x7; |
| 235 | MLX4_GET(field, outbox, QUERY_FUNC_PHYSICAL_FUNCTION_OFFSET); |
| 236 | func->physical_function = field & 0xf; |
| 237 | MLX4_GET(field16, outbox, QUERY_FUNC_RSVD_EQS_OFFSET); |
| 238 | func->rsvd_eqs = field16 & 0xffff; |
| 239 | MLX4_GET(field16, outbox, QUERY_FUNC_MAX_EQ_OFFSET); |
| 240 | func->max_eq = field16 & 0xffff; |
| 241 | MLX4_GET(field, outbox, QUERY_FUNC_RSVD_UARS_OFFSET); |
| 242 | func->rsvd_uars = field & 0x0f; |
| 243 | |
| 244 | mlx4_dbg(dev, "Bus: %d, Device: %d, Function: %d, Physical function: %d, Max EQs: %d, Reserved EQs: %d, Reserved UARs: %d\n", |
| 245 | func->bus, func->device, func->function, func->physical_function, |
| 246 | func->max_eq, func->rsvd_eqs, func->rsvd_uars); |
| 247 | |
| 248 | out: |
| 249 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 250 | return err; |
| 251 | } |
| 252 | |
| 253 | static int mlx4_activate_vst_qinq(struct mlx4_priv *priv, int slave, int port) |
| 254 | { |
| 255 | struct mlx4_vport_oper_state *vp_oper; |
| 256 | struct mlx4_vport_state *vp_admin; |
| 257 | int err; |
| 258 | |
| 259 | vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port]; |
| 260 | vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port]; |
| 261 | |
| 262 | if (vp_admin->default_vlan != vp_oper->state.default_vlan) { |
| 263 | err = __mlx4_register_vlan(&priv->dev, port, |
| 264 | vp_admin->default_vlan, |
| 265 | &vp_oper->vlan_idx); |
| 266 | if (err) { |
| 267 | vp_oper->vlan_idx = NO_INDX; |
| 268 | mlx4_warn(&priv->dev, |
| 269 | "No vlan resources slave %d, port %d\n", |
| 270 | slave, port); |
| 271 | return err; |
| 272 | } |
| 273 | mlx4_dbg(&priv->dev, "alloc vlan %d idx %d slave %d port %d\n", |
| 274 | (int)(vp_oper->state.default_vlan), |
| 275 | vp_oper->vlan_idx, slave, port); |
| 276 | } |
| 277 | vp_oper->state.vlan_proto = vp_admin->vlan_proto; |
| 278 | vp_oper->state.default_vlan = vp_admin->default_vlan; |
| 279 | vp_oper->state.default_qos = vp_admin->default_qos; |
| 280 | |
| 281 | return 0; |
| 282 | } |
| 283 | |
| 284 | static int mlx4_handle_vst_qinq(struct mlx4_priv *priv, int slave, int port) |
| 285 | { |
| 286 | struct mlx4_vport_oper_state *vp_oper; |
| 287 | struct mlx4_slave_state *slave_state; |
| 288 | struct mlx4_vport_state *vp_admin; |
| 289 | int err; |
| 290 | |
| 291 | vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port]; |
| 292 | vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port]; |
| 293 | slave_state = &priv->mfunc.master.slave_state[slave]; |
| 294 | |
| 295 | if ((vp_admin->vlan_proto != htons(ETH_P_8021AD)) || |
| 296 | (!slave_state->active)) |
| 297 | return 0; |
| 298 | |
| 299 | if (vp_oper->state.vlan_proto == vp_admin->vlan_proto && |
| 300 | vp_oper->state.default_vlan == vp_admin->default_vlan && |
| 301 | vp_oper->state.default_qos == vp_admin->default_qos) |
| 302 | return 0; |
| 303 | |
| 304 | if (!slave_state->vst_qinq_supported) { |
| 305 | /* Warn and revert the request to set vst QinQ mode */ |
| 306 | vp_admin->vlan_proto = vp_oper->state.vlan_proto; |
| 307 | vp_admin->default_vlan = vp_oper->state.default_vlan; |
| 308 | vp_admin->default_qos = vp_oper->state.default_qos; |
| 309 | |
| 310 | mlx4_warn(&priv->dev, |
| 311 | "Slave %d does not support VST QinQ mode\n", slave); |
| 312 | return 0; |
| 313 | } |
| 314 | |
| 315 | err = mlx4_activate_vst_qinq(priv, slave, port); |
| 316 | return err; |
| 317 | } |
| 318 | |
| 319 | int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave, |
| 320 | struct mlx4_vhcr *vhcr, |
| 321 | struct mlx4_cmd_mailbox *inbox, |
| 322 | struct mlx4_cmd_mailbox *outbox, |
| 323 | struct mlx4_cmd_info *cmd) |
| 324 | { |
| 325 | struct mlx4_priv *priv = mlx4_priv(dev); |
| 326 | u8 field, port; |
| 327 | u32 size, proxy_qp, qkey; |
| 328 | int err = 0; |
| 329 | struct mlx4_func func; |
| 330 | |
| 331 | #define QUERY_FUNC_CAP_FLAGS_OFFSET 0x0 |
| 332 | #define QUERY_FUNC_CAP_NUM_PORTS_OFFSET 0x1 |
| 333 | #define QUERY_FUNC_CAP_PF_BHVR_OFFSET 0x4 |
| 334 | #define QUERY_FUNC_CAP_FMR_OFFSET 0x8 |
| 335 | #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP 0x10 |
| 336 | #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP 0x14 |
| 337 | #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP 0x18 |
| 338 | #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP 0x20 |
| 339 | #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP 0x24 |
| 340 | #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP 0x28 |
| 341 | #define QUERY_FUNC_CAP_MAX_EQ_OFFSET 0x2c |
| 342 | #define QUERY_FUNC_CAP_RESERVED_EQ_OFFSET 0x30 |
| 343 | #define QUERY_FUNC_CAP_QP_RESD_LKEY_OFFSET 0x48 |
| 344 | |
| 345 | #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET 0x50 |
| 346 | #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET 0x54 |
| 347 | #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET 0x58 |
| 348 | #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET 0x60 |
| 349 | #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET 0x64 |
| 350 | #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET 0x68 |
| 351 | |
| 352 | #define QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET 0x6c |
| 353 | |
| 354 | #define QUERY_FUNC_CAP_FMR_FLAG 0x80 |
| 355 | #define QUERY_FUNC_CAP_FLAG_RDMA 0x40 |
| 356 | #define QUERY_FUNC_CAP_FLAG_ETH 0x80 |
| 357 | #define QUERY_FUNC_CAP_FLAG_QUOTAS 0x10 |
| 358 | #define QUERY_FUNC_CAP_FLAG_RESD_LKEY 0x08 |
| 359 | #define QUERY_FUNC_CAP_FLAG_VALID_MAILBOX 0x04 |
| 360 | |
| 361 | #define QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG (1UL << 31) |
| 362 | #define QUERY_FUNC_CAP_EXTRA_FLAGS_A0_QP_ALLOC_FLAG (1UL << 30) |
| 363 | |
| 364 | /* when opcode modifier = 1 */ |
| 365 | #define QUERY_FUNC_CAP_PHYS_PORT_OFFSET 0x3 |
| 366 | #define QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET 0x4 |
| 367 | #define QUERY_FUNC_CAP_FLAGS0_OFFSET 0x8 |
| 368 | #define QUERY_FUNC_CAP_FLAGS1_OFFSET 0xc |
| 369 | |
| 370 | #define QUERY_FUNC_CAP_QP0_TUNNEL 0x10 |
| 371 | #define QUERY_FUNC_CAP_QP0_PROXY 0x14 |
| 372 | #define QUERY_FUNC_CAP_QP1_TUNNEL 0x18 |
| 373 | #define QUERY_FUNC_CAP_QP1_PROXY 0x1c |
| 374 | #define QUERY_FUNC_CAP_PHYS_PORT_ID 0x28 |
| 375 | |
| 376 | #define QUERY_FUNC_CAP_FLAGS1_FORCE_MAC 0x40 |
| 377 | #define QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN 0x80 |
| 378 | #define QUERY_FUNC_CAP_FLAGS1_NIC_INFO 0x10 |
| 379 | #define QUERY_FUNC_CAP_VF_ENABLE_QP0 0x08 |
| 380 | |
| 381 | #define QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID 0x80 |
| 382 | #define QUERY_FUNC_CAP_PHV_BIT 0x40 |
| 383 | #define QUERY_FUNC_CAP_VLAN_OFFLOAD_DISABLE 0x20 |
| 384 | |
| 385 | #define QUERY_FUNC_CAP_SUPPORTS_VST_QINQ BIT(30) |
| 386 | #define QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS BIT(31) |
| 387 | |
| 388 | if (vhcr->op_modifier == 1) { |
| 389 | struct mlx4_active_ports actv_ports = |
| 390 | mlx4_get_active_ports(dev, slave); |
| 391 | int converted_port = mlx4_slave_convert_port( |
| 392 | dev, slave, vhcr->in_modifier); |
| 393 | struct mlx4_vport_oper_state *vp_oper; |
| 394 | |
| 395 | if (converted_port < 0) |
| 396 | return -EINVAL; |
| 397 | |
| 398 | vhcr->in_modifier = converted_port; |
| 399 | /* phys-port = logical-port */ |
| 400 | field = vhcr->in_modifier - |
| 401 | find_first_bit(actv_ports.ports, dev->caps.num_ports); |
| 402 | MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET); |
| 403 | |
| 404 | port = vhcr->in_modifier; |
| 405 | proxy_qp = dev->phys_caps.base_proxy_sqpn + 8 * slave + port - 1; |
| 406 | |
| 407 | /* Set nic_info bit to mark new fields support */ |
| 408 | field = QUERY_FUNC_CAP_FLAGS1_NIC_INFO; |
| 409 | |
| 410 | if (mlx4_vf_smi_enabled(dev, slave, port) && |
| 411 | !mlx4_get_parav_qkey(dev, proxy_qp, &qkey)) { |
| 412 | field |= QUERY_FUNC_CAP_VF_ENABLE_QP0; |
| 413 | MLX4_PUT(outbox->buf, qkey, |
| 414 | QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET); |
| 415 | } |
| 416 | MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS1_OFFSET); |
| 417 | |
| 418 | /* size is now the QP number */ |
| 419 | size = dev->phys_caps.base_tunnel_sqpn + 8 * slave + port - 1; |
| 420 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_TUNNEL); |
| 421 | |
| 422 | size += 2; |
| 423 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_TUNNEL); |
| 424 | |
| 425 | MLX4_PUT(outbox->buf, proxy_qp, QUERY_FUNC_CAP_QP0_PROXY); |
| 426 | proxy_qp += 2; |
| 427 | MLX4_PUT(outbox->buf, proxy_qp, QUERY_FUNC_CAP_QP1_PROXY); |
| 428 | |
| 429 | MLX4_PUT(outbox->buf, dev->caps.phys_port_id[vhcr->in_modifier], |
| 430 | QUERY_FUNC_CAP_PHYS_PORT_ID); |
| 431 | |
| 432 | vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port]; |
| 433 | err = mlx4_handle_vst_qinq(priv, slave, port); |
| 434 | if (err) |
| 435 | return err; |
| 436 | |
| 437 | field = 0; |
| 438 | if (dev->caps.phv_bit[port]) |
| 439 | field |= QUERY_FUNC_CAP_PHV_BIT; |
| 440 | if (vp_oper->state.vlan_proto == htons(ETH_P_8021AD)) |
| 441 | field |= QUERY_FUNC_CAP_VLAN_OFFLOAD_DISABLE; |
| 442 | MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS0_OFFSET); |
| 443 | |
| 444 | } else if (vhcr->op_modifier == 0) { |
| 445 | struct mlx4_active_ports actv_ports = |
| 446 | mlx4_get_active_ports(dev, slave); |
| 447 | struct mlx4_slave_state *slave_state = |
| 448 | &priv->mfunc.master.slave_state[slave]; |
| 449 | |
| 450 | /* enable rdma and ethernet interfaces, new quota locations, |
| 451 | * and reserved lkey |
| 452 | */ |
| 453 | field = (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA | |
| 454 | QUERY_FUNC_CAP_FLAG_QUOTAS | QUERY_FUNC_CAP_FLAG_VALID_MAILBOX | |
| 455 | QUERY_FUNC_CAP_FLAG_RESD_LKEY); |
| 456 | MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET); |
| 457 | |
| 458 | field = min( |
| 459 | bitmap_weight(actv_ports.ports, dev->caps.num_ports), |
| 460 | dev->caps.num_ports); |
| 461 | MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET); |
| 462 | |
| 463 | size = dev->caps.function_caps; /* set PF behaviours */ |
| 464 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_PF_BHVR_OFFSET); |
| 465 | |
| 466 | field = 0; /* protected FMR support not available as yet */ |
| 467 | MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FMR_OFFSET); |
| 468 | |
| 469 | size = priv->mfunc.master.res_tracker.res_alloc[RES_QP].quota[slave]; |
| 470 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET); |
| 471 | size = dev->caps.num_qps; |
| 472 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP); |
| 473 | |
| 474 | size = priv->mfunc.master.res_tracker.res_alloc[RES_SRQ].quota[slave]; |
| 475 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET); |
| 476 | size = dev->caps.num_srqs; |
| 477 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP); |
| 478 | |
| 479 | size = priv->mfunc.master.res_tracker.res_alloc[RES_CQ].quota[slave]; |
| 480 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET); |
| 481 | size = dev->caps.num_cqs; |
| 482 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP); |
| 483 | |
| 484 | if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) || |
| 485 | mlx4_QUERY_FUNC(dev, &func, slave)) { |
| 486 | size = vhcr->in_modifier & |
| 487 | QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS ? |
| 488 | dev->caps.num_eqs : |
| 489 | rounddown_pow_of_two(dev->caps.num_eqs); |
| 490 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET); |
| 491 | size = dev->caps.reserved_eqs; |
| 492 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET); |
| 493 | } else { |
| 494 | size = vhcr->in_modifier & |
| 495 | QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS ? |
| 496 | func.max_eq : |
| 497 | rounddown_pow_of_two(func.max_eq); |
| 498 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET); |
| 499 | size = func.rsvd_eqs; |
| 500 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET); |
| 501 | } |
| 502 | |
| 503 | size = priv->mfunc.master.res_tracker.res_alloc[RES_MPT].quota[slave]; |
| 504 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET); |
| 505 | size = dev->caps.num_mpts; |
| 506 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP); |
| 507 | |
| 508 | size = priv->mfunc.master.res_tracker.res_alloc[RES_MTT].quota[slave]; |
| 509 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET); |
| 510 | size = dev->caps.num_mtts; |
| 511 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP); |
| 512 | |
| 513 | size = dev->caps.num_mgms + dev->caps.num_amgms; |
| 514 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET); |
| 515 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP); |
| 516 | |
| 517 | size = QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG | |
| 518 | QUERY_FUNC_CAP_EXTRA_FLAGS_A0_QP_ALLOC_FLAG; |
| 519 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET); |
| 520 | |
| 521 | size = dev->caps.reserved_lkey + ((slave << 8) & 0xFF00); |
| 522 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_RESD_LKEY_OFFSET); |
| 523 | |
| 524 | if (vhcr->in_modifier & QUERY_FUNC_CAP_SUPPORTS_VST_QINQ) |
| 525 | slave_state->vst_qinq_supported = true; |
| 526 | |
| 527 | } else |
| 528 | err = -EINVAL; |
| 529 | |
| 530 | return err; |
| 531 | } |
| 532 | |
| 533 | int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, u8 gen_or_port, |
| 534 | struct mlx4_func_cap *func_cap) |
| 535 | { |
| 536 | struct mlx4_cmd_mailbox *mailbox; |
| 537 | u32 *outbox; |
| 538 | u8 field, op_modifier; |
| 539 | u32 size, qkey; |
| 540 | int err = 0, quotas = 0; |
| 541 | u32 in_modifier; |
| 542 | u32 slave_caps; |
| 543 | |
| 544 | op_modifier = !!gen_or_port; /* 0 = general, 1 = logical port */ |
| 545 | slave_caps = QUERY_FUNC_CAP_SUPPORTS_VST_QINQ | |
| 546 | QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS; |
| 547 | in_modifier = op_modifier ? gen_or_port : slave_caps; |
| 548 | |
| 549 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 550 | if (IS_ERR(mailbox)) |
| 551 | return PTR_ERR(mailbox); |
| 552 | |
| 553 | err = mlx4_cmd_box(dev, 0, mailbox->dma, in_modifier, op_modifier, |
| 554 | MLX4_CMD_QUERY_FUNC_CAP, |
| 555 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); |
| 556 | if (err) |
| 557 | goto out; |
| 558 | |
| 559 | outbox = mailbox->buf; |
| 560 | |
| 561 | if (!op_modifier) { |
| 562 | MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET); |
| 563 | if (!(field & (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA))) { |
| 564 | mlx4_err(dev, "The host supports neither eth nor rdma interfaces\n"); |
| 565 | err = -EPROTONOSUPPORT; |
| 566 | goto out; |
| 567 | } |
| 568 | func_cap->flags = field; |
| 569 | quotas = !!(func_cap->flags & QUERY_FUNC_CAP_FLAG_QUOTAS); |
| 570 | |
| 571 | MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET); |
| 572 | func_cap->num_ports = field; |
| 573 | |
| 574 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_PF_BHVR_OFFSET); |
| 575 | func_cap->pf_context_behaviour = size; |
| 576 | |
| 577 | if (quotas) { |
| 578 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET); |
| 579 | func_cap->qp_quota = size & 0xFFFFFF; |
| 580 | |
| 581 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET); |
| 582 | func_cap->srq_quota = size & 0xFFFFFF; |
| 583 | |
| 584 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET); |
| 585 | func_cap->cq_quota = size & 0xFFFFFF; |
| 586 | |
| 587 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET); |
| 588 | func_cap->mpt_quota = size & 0xFFFFFF; |
| 589 | |
| 590 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET); |
| 591 | func_cap->mtt_quota = size & 0xFFFFFF; |
| 592 | |
| 593 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET); |
| 594 | func_cap->mcg_quota = size & 0xFFFFFF; |
| 595 | |
| 596 | } else { |
| 597 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP); |
| 598 | func_cap->qp_quota = size & 0xFFFFFF; |
| 599 | |
| 600 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP); |
| 601 | func_cap->srq_quota = size & 0xFFFFFF; |
| 602 | |
| 603 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP); |
| 604 | func_cap->cq_quota = size & 0xFFFFFF; |
| 605 | |
| 606 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP); |
| 607 | func_cap->mpt_quota = size & 0xFFFFFF; |
| 608 | |
| 609 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP); |
| 610 | func_cap->mtt_quota = size & 0xFFFFFF; |
| 611 | |
| 612 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP); |
| 613 | func_cap->mcg_quota = size & 0xFFFFFF; |
| 614 | } |
| 615 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_MAX_EQ_OFFSET); |
| 616 | func_cap->max_eq = size & 0xFFFFFF; |
| 617 | |
| 618 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET); |
| 619 | func_cap->reserved_eq = size & 0xFFFFFF; |
| 620 | |
| 621 | if (func_cap->flags & QUERY_FUNC_CAP_FLAG_RESD_LKEY) { |
| 622 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_RESD_LKEY_OFFSET); |
| 623 | func_cap->reserved_lkey = size; |
| 624 | } else { |
| 625 | func_cap->reserved_lkey = 0; |
| 626 | } |
| 627 | |
| 628 | func_cap->extra_flags = 0; |
| 629 | |
| 630 | /* Mailbox data from 0x6c and onward should only be treated if |
| 631 | * QUERY_FUNC_CAP_FLAG_VALID_MAILBOX is set in func_cap->flags |
| 632 | */ |
| 633 | if (func_cap->flags & QUERY_FUNC_CAP_FLAG_VALID_MAILBOX) { |
| 634 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET); |
| 635 | if (size & QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG) |
| 636 | func_cap->extra_flags |= MLX4_QUERY_FUNC_FLAGS_BF_RES_QP; |
| 637 | if (size & QUERY_FUNC_CAP_EXTRA_FLAGS_A0_QP_ALLOC_FLAG) |
| 638 | func_cap->extra_flags |= MLX4_QUERY_FUNC_FLAGS_A0_RES_QP; |
| 639 | } |
| 640 | |
| 641 | goto out; |
| 642 | } |
| 643 | |
| 644 | /* logical port query */ |
| 645 | if (gen_or_port > dev->caps.num_ports) { |
| 646 | err = -EINVAL; |
| 647 | goto out; |
| 648 | } |
| 649 | |
| 650 | MLX4_GET(func_cap->flags1, outbox, QUERY_FUNC_CAP_FLAGS1_OFFSET); |
| 651 | if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_ETH) { |
| 652 | if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN) { |
| 653 | mlx4_err(dev, "VLAN is enforced on this port\n"); |
| 654 | err = -EPROTONOSUPPORT; |
| 655 | goto out; |
| 656 | } |
| 657 | |
| 658 | if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_FORCE_MAC) { |
| 659 | mlx4_err(dev, "Force mac is enabled on this port\n"); |
| 660 | err = -EPROTONOSUPPORT; |
| 661 | goto out; |
| 662 | } |
| 663 | } else if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_IB) { |
| 664 | MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS0_OFFSET); |
| 665 | if (field & QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID) { |
| 666 | mlx4_err(dev, "phy_wqe_gid is enforced on this ib port\n"); |
| 667 | err = -EPROTONOSUPPORT; |
| 668 | goto out; |
| 669 | } |
| 670 | } |
| 671 | |
| 672 | MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET); |
| 673 | func_cap->physical_port = field; |
| 674 | if (func_cap->physical_port != gen_or_port) { |
| 675 | err = -EINVAL; |
| 676 | goto out; |
| 677 | } |
| 678 | |
| 679 | if (func_cap->flags1 & QUERY_FUNC_CAP_VF_ENABLE_QP0) { |
| 680 | MLX4_GET(qkey, outbox, QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET); |
| 681 | func_cap->qp0_qkey = qkey; |
| 682 | } else { |
| 683 | func_cap->qp0_qkey = 0; |
| 684 | } |
| 685 | |
| 686 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_TUNNEL); |
| 687 | func_cap->qp0_tunnel_qpn = size & 0xFFFFFF; |
| 688 | |
| 689 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_PROXY); |
| 690 | func_cap->qp0_proxy_qpn = size & 0xFFFFFF; |
| 691 | |
| 692 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_TUNNEL); |
| 693 | func_cap->qp1_tunnel_qpn = size & 0xFFFFFF; |
| 694 | |
| 695 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_PROXY); |
| 696 | func_cap->qp1_proxy_qpn = size & 0xFFFFFF; |
| 697 | |
| 698 | if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_NIC_INFO) |
| 699 | MLX4_GET(func_cap->phys_port_id, outbox, |
| 700 | QUERY_FUNC_CAP_PHYS_PORT_ID); |
| 701 | |
| 702 | MLX4_GET(func_cap->flags0, outbox, QUERY_FUNC_CAP_FLAGS0_OFFSET); |
| 703 | |
| 704 | /* All other resources are allocated by the master, but we still report |
| 705 | * 'num' and 'reserved' capabilities as follows: |
| 706 | * - num remains the maximum resource index |
| 707 | * - 'num - reserved' is the total available objects of a resource, but |
| 708 | * resource indices may be less than 'reserved' |
| 709 | * TODO: set per-resource quotas */ |
| 710 | |
| 711 | out: |
| 712 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 713 | |
| 714 | return err; |
| 715 | } |
| 716 | |
| 717 | static void disable_unsupported_roce_caps(void *buf); |
| 718 | |
| 719 | int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) |
| 720 | { |
| 721 | struct mlx4_cmd_mailbox *mailbox; |
| 722 | u32 *outbox; |
| 723 | u8 field; |
| 724 | u32 field32, flags, ext_flags; |
| 725 | u16 size; |
| 726 | u16 stat_rate; |
| 727 | int err; |
| 728 | int i; |
| 729 | |
| 730 | #define QUERY_DEV_CAP_OUT_SIZE 0x100 |
| 731 | #define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10 |
| 732 | #define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11 |
| 733 | #define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12 |
| 734 | #define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13 |
| 735 | #define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14 |
| 736 | #define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15 |
| 737 | #define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16 |
| 738 | #define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17 |
| 739 | #define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19 |
| 740 | #define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a |
| 741 | #define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b |
| 742 | #define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d |
| 743 | #define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e |
| 744 | #define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f |
| 745 | #define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20 |
| 746 | #define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21 |
| 747 | #define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22 |
| 748 | #define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23 |
| 749 | #define QUERY_DEV_CAP_NUM_SYS_EQ_OFFSET 0x26 |
| 750 | #define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27 |
| 751 | #define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29 |
| 752 | #define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b |
| 753 | #define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d |
| 754 | #define QUERY_DEV_CAP_RSS_OFFSET 0x2e |
| 755 | #define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f |
| 756 | #define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33 |
| 757 | #define QUERY_DEV_CAP_PORT_BEACON_OFFSET 0x34 |
| 758 | #define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35 |
| 759 | #define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36 |
| 760 | #define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37 |
| 761 | #define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38 |
| 762 | #define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b |
| 763 | #define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c |
| 764 | #define QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET 0x3e |
| 765 | #define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f |
| 766 | #define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40 |
| 767 | #define QUERY_DEV_CAP_FLAGS_OFFSET 0x44 |
| 768 | #define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48 |
| 769 | #define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49 |
| 770 | #define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b |
| 771 | #define QUERY_DEV_CAP_BF_OFFSET 0x4c |
| 772 | #define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d |
| 773 | #define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e |
| 774 | #define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f |
| 775 | #define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51 |
| 776 | #define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52 |
| 777 | #define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55 |
| 778 | #define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56 |
| 779 | #define QUERY_DEV_CAP_SVLAN_BY_QP_OFFSET 0x5D |
| 780 | #define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61 |
| 781 | #define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62 |
| 782 | #define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63 |
| 783 | #define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64 |
| 784 | #define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65 |
| 785 | #define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66 |
| 786 | #define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67 |
| 787 | #define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68 |
| 788 | #define QUERY_DEV_CAP_PORT_FLOWSTATS_COUNTERS_OFFSET 0x70 |
| 789 | #define QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET 0x70 |
| 790 | #define QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET 0x74 |
| 791 | #define QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET 0x76 |
| 792 | #define QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET 0x77 |
| 793 | #define QUERY_DEV_CAP_SL2VL_EVENT_OFFSET 0x78 |
| 794 | #define QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE 0x7a |
| 795 | #define QUERY_DEV_CAP_ECN_QCN_VER_OFFSET 0x7b |
| 796 | #define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80 |
| 797 | #define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82 |
| 798 | #define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84 |
| 799 | #define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86 |
| 800 | #define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88 |
| 801 | #define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a |
| 802 | #define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c |
| 803 | #define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e |
| 804 | #define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90 |
| 805 | #define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92 |
| 806 | #define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94 |
| 807 | #define QUERY_DEV_CAP_CONFIG_DEV_OFFSET 0x94 |
| 808 | #define QUERY_DEV_CAP_PHV_EN_OFFSET 0x96 |
| 809 | #define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98 |
| 810 | #define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0 |
| 811 | #define QUERY_DEV_CAP_ETH_BACKPL_OFFSET 0x9c |
| 812 | #define QUERY_DEV_CAP_DIAG_RPRT_PER_PORT 0x9c |
| 813 | #define QUERY_DEV_CAP_FW_REASSIGN_MAC 0x9d |
| 814 | #define QUERY_DEV_CAP_VXLAN 0x9e |
| 815 | #define QUERY_DEV_CAP_MAD_DEMUX_OFFSET 0xb0 |
| 816 | #define QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_BASE_OFFSET 0xa8 |
| 817 | #define QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_RANGE_OFFSET 0xac |
| 818 | #define QUERY_DEV_CAP_QP_RATE_LIMIT_NUM_OFFSET 0xcc |
| 819 | #define QUERY_DEV_CAP_QP_RATE_LIMIT_MAX_OFFSET 0xd0 |
| 820 | #define QUERY_DEV_CAP_QP_RATE_LIMIT_MIN_OFFSET 0xd2 |
| 821 | |
| 822 | |
| 823 | dev_cap->flags2 = 0; |
| 824 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 825 | if (IS_ERR(mailbox)) |
| 826 | return PTR_ERR(mailbox); |
| 827 | outbox = mailbox->buf; |
| 828 | |
| 829 | err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP, |
| 830 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
| 831 | if (err) |
| 832 | goto out; |
| 833 | |
| 834 | if (mlx4_is_mfunc(dev)) |
| 835 | disable_unsupported_roce_caps(outbox); |
| 836 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET); |
| 837 | dev_cap->reserved_qps = 1 << (field & 0xf); |
| 838 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET); |
| 839 | dev_cap->max_qps = 1 << (field & 0x1f); |
| 840 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET); |
| 841 | dev_cap->reserved_srqs = 1 << (field >> 4); |
| 842 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET); |
| 843 | dev_cap->max_srqs = 1 << (field & 0x1f); |
| 844 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET); |
| 845 | dev_cap->max_cq_sz = 1 << field; |
| 846 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET); |
| 847 | dev_cap->reserved_cqs = 1 << (field & 0xf); |
| 848 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET); |
| 849 | dev_cap->max_cqs = 1 << (field & 0x1f); |
| 850 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET); |
| 851 | dev_cap->max_mpts = 1 << (field & 0x3f); |
| 852 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET); |
| 853 | dev_cap->reserved_eqs = 1 << (field & 0xf); |
| 854 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET); |
| 855 | dev_cap->max_eqs = 1 << (field & 0xf); |
| 856 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET); |
| 857 | dev_cap->reserved_mtts = 1 << (field >> 4); |
| 858 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET); |
| 859 | dev_cap->reserved_mrws = 1 << (field & 0xf); |
| 860 | MLX4_GET(size, outbox, QUERY_DEV_CAP_NUM_SYS_EQ_OFFSET); |
| 861 | dev_cap->num_sys_eqs = size & 0xfff; |
| 862 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET); |
| 863 | dev_cap->max_requester_per_qp = 1 << (field & 0x3f); |
| 864 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET); |
| 865 | dev_cap->max_responder_per_qp = 1 << (field & 0x3f); |
| 866 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET); |
| 867 | field &= 0x1f; |
| 868 | if (!field) |
| 869 | dev_cap->max_gso_sz = 0; |
| 870 | else |
| 871 | dev_cap->max_gso_sz = 1 << field; |
| 872 | |
| 873 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSS_OFFSET); |
| 874 | if (field & 0x20) |
| 875 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_XOR; |
| 876 | if (field & 0x10) |
| 877 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_TOP; |
| 878 | field &= 0xf; |
| 879 | if (field) { |
| 880 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS; |
| 881 | dev_cap->max_rss_tbl_sz = 1 << field; |
| 882 | } else |
| 883 | dev_cap->max_rss_tbl_sz = 0; |
| 884 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET); |
| 885 | dev_cap->max_rdma_global = 1 << (field & 0x3f); |
| 886 | MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET); |
| 887 | dev_cap->local_ca_ack_delay = field & 0x1f; |
| 888 | MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET); |
| 889 | dev_cap->num_ports = field & 0xf; |
| 890 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET); |
| 891 | dev_cap->max_msg_sz = 1 << (field & 0x1f); |
| 892 | MLX4_GET(field, outbox, QUERY_DEV_CAP_PORT_FLOWSTATS_COUNTERS_OFFSET); |
| 893 | if (field & 0x10) |
| 894 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN; |
| 895 | MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); |
| 896 | if (field & 0x80) |
| 897 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN; |
| 898 | dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f; |
| 899 | if (field & 0x20) |
| 900 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER; |
| 901 | MLX4_GET(field, outbox, QUERY_DEV_CAP_PORT_BEACON_OFFSET); |
| 902 | if (field & 0x80) |
| 903 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PORT_BEACON; |
| 904 | MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET); |
| 905 | if (field & 0x80) |
| 906 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DMFS_IPOIB; |
| 907 | MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET); |
| 908 | dev_cap->fs_max_num_qp_per_entry = field; |
| 909 | MLX4_GET(field, outbox, QUERY_DEV_CAP_SL2VL_EVENT_OFFSET); |
| 910 | if (field & (1 << 5)) |
| 911 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SL_TO_VL_CHANGE_EVENT; |
| 912 | MLX4_GET(field, outbox, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET); |
| 913 | if (field & 0x1) |
| 914 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QCN; |
| 915 | MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET); |
| 916 | dev_cap->stat_rate_support = stat_rate; |
| 917 | MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); |
| 918 | if (field & 0x80) |
| 919 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_TS; |
| 920 | MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); |
| 921 | MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET); |
| 922 | dev_cap->flags = flags | (u64)ext_flags << 32; |
| 923 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET); |
| 924 | dev_cap->reserved_uars = field >> 4; |
| 925 | MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET); |
| 926 | dev_cap->uar_size = 1 << ((field & 0x3f) + 20); |
| 927 | MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET); |
| 928 | dev_cap->min_page_sz = 1 << field; |
| 929 | |
| 930 | MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET); |
| 931 | if (field & 0x80) { |
| 932 | MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET); |
| 933 | dev_cap->bf_reg_size = 1 << (field & 0x1f); |
| 934 | MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET); |
| 935 | if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size)) |
| 936 | field = 3; |
| 937 | dev_cap->bf_regs_per_page = 1 << (field & 0x3f); |
| 938 | } else { |
| 939 | dev_cap->bf_reg_size = 0; |
| 940 | } |
| 941 | |
| 942 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET); |
| 943 | dev_cap->max_sq_sg = field; |
| 944 | MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET); |
| 945 | dev_cap->max_sq_desc_sz = size; |
| 946 | |
| 947 | MLX4_GET(field, outbox, QUERY_DEV_CAP_SVLAN_BY_QP_OFFSET); |
| 948 | if (field & 0x1) |
| 949 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SVLAN_BY_QP; |
| 950 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET); |
| 951 | dev_cap->max_qp_per_mcg = 1 << field; |
| 952 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET); |
| 953 | dev_cap->reserved_mgms = field & 0xf; |
| 954 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET); |
| 955 | dev_cap->max_mcgs = 1 << field; |
| 956 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET); |
| 957 | dev_cap->reserved_pds = field >> 4; |
| 958 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET); |
| 959 | dev_cap->max_pds = 1 << (field & 0x3f); |
| 960 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET); |
| 961 | dev_cap->reserved_xrcds = field >> 4; |
| 962 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_XRC_OFFSET); |
| 963 | dev_cap->max_xrcds = 1 << (field & 0x1f); |
| 964 | |
| 965 | MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET); |
| 966 | dev_cap->rdmarc_entry_sz = size; |
| 967 | MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET); |
| 968 | dev_cap->qpc_entry_sz = size; |
| 969 | MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET); |
| 970 | dev_cap->aux_entry_sz = size; |
| 971 | MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET); |
| 972 | dev_cap->altc_entry_sz = size; |
| 973 | MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET); |
| 974 | dev_cap->eqc_entry_sz = size; |
| 975 | MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET); |
| 976 | dev_cap->cqc_entry_sz = size; |
| 977 | MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET); |
| 978 | dev_cap->srq_entry_sz = size; |
| 979 | MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET); |
| 980 | dev_cap->cmpt_entry_sz = size; |
| 981 | MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET); |
| 982 | dev_cap->mtt_entry_sz = size; |
| 983 | MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET); |
| 984 | dev_cap->dmpt_entry_sz = size; |
| 985 | |
| 986 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET); |
| 987 | dev_cap->max_srq_sz = 1 << field; |
| 988 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET); |
| 989 | dev_cap->max_qp_sz = 1 << field; |
| 990 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET); |
| 991 | dev_cap->resize_srq = field & 1; |
| 992 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET); |
| 993 | dev_cap->max_rq_sg = field; |
| 994 | MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET); |
| 995 | dev_cap->max_rq_desc_sz = size; |
| 996 | MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE); |
| 997 | if (field & (1 << 4)) |
| 998 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QOS_VPP; |
| 999 | if (field & (1 << 5)) |
| 1000 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL; |
| 1001 | if (field & (1 << 6)) |
| 1002 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CQE_STRIDE; |
| 1003 | if (field & (1 << 7)) |
| 1004 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_EQE_STRIDE; |
| 1005 | MLX4_GET(dev_cap->bmme_flags, outbox, |
| 1006 | QUERY_DEV_CAP_BMME_FLAGS_OFFSET); |
| 1007 | if (dev_cap->bmme_flags & MLX4_FLAG_ROCE_V1_V2) |
| 1008 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ROCE_V1_V2; |
| 1009 | if (dev_cap->bmme_flags & MLX4_FLAG_PORT_REMAP) |
| 1010 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PORT_REMAP; |
| 1011 | MLX4_GET(field, outbox, QUERY_DEV_CAP_CONFIG_DEV_OFFSET); |
| 1012 | if (field & 0x20) |
| 1013 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CONFIG_DEV; |
| 1014 | if (field & (1 << 2)) |
| 1015 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_IGNORE_FCS; |
| 1016 | MLX4_GET(field, outbox, QUERY_DEV_CAP_PHV_EN_OFFSET); |
| 1017 | if (field & 0x80) |
| 1018 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PHV_EN; |
| 1019 | if (field & 0x40) |
| 1020 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN; |
| 1021 | |
| 1022 | MLX4_GET(dev_cap->reserved_lkey, outbox, |
| 1023 | QUERY_DEV_CAP_RSVD_LKEY_OFFSET); |
| 1024 | MLX4_GET(field32, outbox, QUERY_DEV_CAP_ETH_BACKPL_OFFSET); |
| 1025 | if (field32 & (1 << 0)) |
| 1026 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP; |
| 1027 | if (field32 & (1 << 7)) |
| 1028 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT; |
| 1029 | MLX4_GET(field32, outbox, QUERY_DEV_CAP_DIAG_RPRT_PER_PORT); |
| 1030 | if (field32 & (1 << 17)) |
| 1031 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT; |
| 1032 | MLX4_GET(field, outbox, QUERY_DEV_CAP_FW_REASSIGN_MAC); |
| 1033 | if (field & 1<<6) |
| 1034 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN; |
| 1035 | MLX4_GET(field, outbox, QUERY_DEV_CAP_VXLAN); |
| 1036 | if (field & 1<<3) |
| 1037 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS; |
| 1038 | if (field & (1 << 5)) |
| 1039 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETS_CFG; |
| 1040 | MLX4_GET(dev_cap->max_icm_sz, outbox, |
| 1041 | QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET); |
| 1042 | if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS) |
| 1043 | MLX4_GET(dev_cap->max_counters, outbox, |
| 1044 | QUERY_DEV_CAP_MAX_COUNTERS_OFFSET); |
| 1045 | |
| 1046 | MLX4_GET(field32, outbox, |
| 1047 | QUERY_DEV_CAP_MAD_DEMUX_OFFSET); |
| 1048 | if (field32 & (1 << 0)) |
| 1049 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_MAD_DEMUX; |
| 1050 | |
| 1051 | MLX4_GET(dev_cap->dmfs_high_rate_qpn_base, outbox, |
| 1052 | QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_BASE_OFFSET); |
| 1053 | dev_cap->dmfs_high_rate_qpn_base &= MGM_QPN_MASK; |
| 1054 | MLX4_GET(dev_cap->dmfs_high_rate_qpn_range, outbox, |
| 1055 | QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_RANGE_OFFSET); |
| 1056 | dev_cap->dmfs_high_rate_qpn_range &= MGM_QPN_MASK; |
| 1057 | |
| 1058 | MLX4_GET(size, outbox, QUERY_DEV_CAP_QP_RATE_LIMIT_NUM_OFFSET); |
| 1059 | dev_cap->rl_caps.num_rates = size; |
| 1060 | if (dev_cap->rl_caps.num_rates) { |
| 1061 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT; |
| 1062 | MLX4_GET(size, outbox, QUERY_DEV_CAP_QP_RATE_LIMIT_MAX_OFFSET); |
| 1063 | dev_cap->rl_caps.max_val = size & 0xfff; |
| 1064 | dev_cap->rl_caps.max_unit = size >> 14; |
| 1065 | MLX4_GET(size, outbox, QUERY_DEV_CAP_QP_RATE_LIMIT_MIN_OFFSET); |
| 1066 | dev_cap->rl_caps.min_val = size & 0xfff; |
| 1067 | dev_cap->rl_caps.min_unit = size >> 14; |
| 1068 | } |
| 1069 | |
| 1070 | MLX4_GET(field32, outbox, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET); |
| 1071 | if (field32 & (1 << 16)) |
| 1072 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP; |
| 1073 | if (field32 & (1 << 18)) |
| 1074 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB; |
| 1075 | if (field32 & (1 << 19)) |
| 1076 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_LB_SRC_CHK; |
| 1077 | if (field32 & (1 << 26)) |
| 1078 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VLAN_CONTROL; |
| 1079 | if (field32 & (1 << 20)) |
| 1080 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FSM; |
| 1081 | if (field32 & (1 << 21)) |
| 1082 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_80_VFS; |
| 1083 | |
| 1084 | for (i = 1; i <= dev_cap->num_ports; i++) { |
| 1085 | err = mlx4_QUERY_PORT(dev, i, dev_cap->port_cap + i); |
| 1086 | if (err) |
| 1087 | goto out; |
| 1088 | } |
| 1089 | |
| 1090 | /* |
| 1091 | * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then |
| 1092 | * we can't use any EQs whose doorbell falls on that page, |
| 1093 | * even if the EQ itself isn't reserved. |
| 1094 | */ |
| 1095 | if (dev_cap->num_sys_eqs == 0) |
| 1096 | dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4, |
| 1097 | dev_cap->reserved_eqs); |
| 1098 | else |
| 1099 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SYS_EQS; |
| 1100 | |
| 1101 | out: |
| 1102 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 1103 | return err; |
| 1104 | } |
| 1105 | |
| 1106 | void mlx4_dev_cap_dump(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) |
| 1107 | { |
| 1108 | if (dev_cap->bf_reg_size > 0) |
| 1109 | mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n", |
| 1110 | dev_cap->bf_reg_size, dev_cap->bf_regs_per_page); |
| 1111 | else |
| 1112 | mlx4_dbg(dev, "BlueFlame not available\n"); |
| 1113 | |
| 1114 | mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n", |
| 1115 | dev_cap->bmme_flags, dev_cap->reserved_lkey); |
| 1116 | mlx4_dbg(dev, "Max ICM size %lld MB\n", |
| 1117 | (unsigned long long) dev_cap->max_icm_sz >> 20); |
| 1118 | mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n", |
| 1119 | dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz); |
| 1120 | mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n", |
| 1121 | dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz); |
| 1122 | mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n", |
| 1123 | dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz); |
| 1124 | mlx4_dbg(dev, "Num sys EQs: %d, max EQs: %d, reserved EQs: %d, entry size: %d\n", |
| 1125 | dev_cap->num_sys_eqs, dev_cap->max_eqs, dev_cap->reserved_eqs, |
| 1126 | dev_cap->eqc_entry_sz); |
| 1127 | mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n", |
| 1128 | dev_cap->reserved_mrws, dev_cap->reserved_mtts); |
| 1129 | mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n", |
| 1130 | dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars); |
| 1131 | mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n", |
| 1132 | dev_cap->max_pds, dev_cap->reserved_mgms); |
| 1133 | mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n", |
| 1134 | dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz); |
| 1135 | mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n", |
| 1136 | dev_cap->local_ca_ack_delay, 128 << dev_cap->port_cap[1].ib_mtu, |
| 1137 | dev_cap->port_cap[1].max_port_width); |
| 1138 | mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n", |
| 1139 | dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg); |
| 1140 | mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n", |
| 1141 | dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg); |
| 1142 | mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz); |
| 1143 | mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters); |
| 1144 | mlx4_dbg(dev, "Max RSS Table size: %d\n", dev_cap->max_rss_tbl_sz); |
| 1145 | mlx4_dbg(dev, "DMFS high rate steer QPn base: %d\n", |
| 1146 | dev_cap->dmfs_high_rate_qpn_base); |
| 1147 | mlx4_dbg(dev, "DMFS high rate steer QPn range: %d\n", |
| 1148 | dev_cap->dmfs_high_rate_qpn_range); |
| 1149 | |
| 1150 | if (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT) { |
| 1151 | struct mlx4_rate_limit_caps *rl_caps = &dev_cap->rl_caps; |
| 1152 | |
| 1153 | mlx4_dbg(dev, "QP Rate-Limit: #rates %d, unit/val max %d/%d, min %d/%d\n", |
| 1154 | rl_caps->num_rates, rl_caps->max_unit, rl_caps->max_val, |
| 1155 | rl_caps->min_unit, rl_caps->min_val); |
| 1156 | } |
| 1157 | |
| 1158 | dump_dev_cap_flags(dev, dev_cap->flags); |
| 1159 | dump_dev_cap_flags2(dev, dev_cap->flags2); |
| 1160 | } |
| 1161 | |
| 1162 | int mlx4_QUERY_PORT(struct mlx4_dev *dev, int port, struct mlx4_port_cap *port_cap) |
| 1163 | { |
| 1164 | struct mlx4_cmd_mailbox *mailbox; |
| 1165 | u32 *outbox; |
| 1166 | u8 field; |
| 1167 | u32 field32; |
| 1168 | int err; |
| 1169 | |
| 1170 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 1171 | if (IS_ERR(mailbox)) |
| 1172 | return PTR_ERR(mailbox); |
| 1173 | outbox = mailbox->buf; |
| 1174 | |
| 1175 | if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { |
| 1176 | err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP, |
| 1177 | MLX4_CMD_TIME_CLASS_A, |
| 1178 | MLX4_CMD_NATIVE); |
| 1179 | |
| 1180 | if (err) |
| 1181 | goto out; |
| 1182 | |
| 1183 | MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET); |
| 1184 | port_cap->max_vl = field >> 4; |
| 1185 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET); |
| 1186 | port_cap->ib_mtu = field >> 4; |
| 1187 | port_cap->max_port_width = field & 0xf; |
| 1188 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET); |
| 1189 | port_cap->max_gids = 1 << (field & 0xf); |
| 1190 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET); |
| 1191 | port_cap->max_pkeys = 1 << (field & 0xf); |
| 1192 | } else { |
| 1193 | #define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00 |
| 1194 | #define QUERY_PORT_MTU_OFFSET 0x01 |
| 1195 | #define QUERY_PORT_ETH_MTU_OFFSET 0x02 |
| 1196 | #define QUERY_PORT_WIDTH_OFFSET 0x06 |
| 1197 | #define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07 |
| 1198 | #define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a |
| 1199 | #define QUERY_PORT_MAX_VL_OFFSET 0x0b |
| 1200 | #define QUERY_PORT_MAC_OFFSET 0x10 |
| 1201 | #define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18 |
| 1202 | #define QUERY_PORT_WAVELENGTH_OFFSET 0x1c |
| 1203 | #define QUERY_PORT_TRANS_CODE_OFFSET 0x20 |
| 1204 | |
| 1205 | err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0, MLX4_CMD_QUERY_PORT, |
| 1206 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); |
| 1207 | if (err) |
| 1208 | goto out; |
| 1209 | |
| 1210 | MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET); |
| 1211 | port_cap->link_state = (field & 0x80) >> 7; |
| 1212 | port_cap->supported_port_types = field & 3; |
| 1213 | port_cap->suggested_type = (field >> 3) & 1; |
| 1214 | port_cap->default_sense = (field >> 4) & 1; |
| 1215 | port_cap->dmfs_optimized_state = (field >> 5) & 1; |
| 1216 | MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET); |
| 1217 | port_cap->ib_mtu = field & 0xf; |
| 1218 | MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET); |
| 1219 | port_cap->max_port_width = field & 0xf; |
| 1220 | MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET); |
| 1221 | port_cap->max_gids = 1 << (field >> 4); |
| 1222 | port_cap->max_pkeys = 1 << (field & 0xf); |
| 1223 | MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET); |
| 1224 | port_cap->max_vl = field & 0xf; |
| 1225 | port_cap->max_tc_eth = field >> 4; |
| 1226 | MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET); |
| 1227 | port_cap->log_max_macs = field & 0xf; |
| 1228 | port_cap->log_max_vlans = field >> 4; |
| 1229 | MLX4_GET(port_cap->eth_mtu, outbox, QUERY_PORT_ETH_MTU_OFFSET); |
| 1230 | MLX4_GET(port_cap->def_mac, outbox, QUERY_PORT_MAC_OFFSET); |
| 1231 | MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET); |
| 1232 | port_cap->trans_type = field32 >> 24; |
| 1233 | port_cap->vendor_oui = field32 & 0xffffff; |
| 1234 | MLX4_GET(port_cap->wavelength, outbox, QUERY_PORT_WAVELENGTH_OFFSET); |
| 1235 | MLX4_GET(port_cap->trans_code, outbox, QUERY_PORT_TRANS_CODE_OFFSET); |
| 1236 | } |
| 1237 | |
| 1238 | out: |
| 1239 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 1240 | return err; |
| 1241 | } |
| 1242 | |
| 1243 | #define DEV_CAP_EXT_2_FLAG_PFC_COUNTERS (1 << 28) |
| 1244 | #define DEV_CAP_EXT_2_FLAG_VLAN_CONTROL (1 << 26) |
| 1245 | #define DEV_CAP_EXT_2_FLAG_80_VFS (1 << 21) |
| 1246 | #define DEV_CAP_EXT_2_FLAG_FSM (1 << 20) |
| 1247 | |
| 1248 | int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave, |
| 1249 | struct mlx4_vhcr *vhcr, |
| 1250 | struct mlx4_cmd_mailbox *inbox, |
| 1251 | struct mlx4_cmd_mailbox *outbox, |
| 1252 | struct mlx4_cmd_info *cmd) |
| 1253 | { |
| 1254 | u64 flags; |
| 1255 | int err = 0; |
| 1256 | u8 field; |
| 1257 | u16 field16; |
| 1258 | u32 bmme_flags, field32; |
| 1259 | int real_port; |
| 1260 | int slave_port; |
| 1261 | int first_port; |
| 1262 | struct mlx4_active_ports actv_ports; |
| 1263 | |
| 1264 | err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP, |
| 1265 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
| 1266 | if (err) |
| 1267 | return err; |
| 1268 | |
| 1269 | disable_unsupported_roce_caps(outbox->buf); |
| 1270 | /* add port mng change event capability and disable mw type 1 |
| 1271 | * unconditionally to slaves |
| 1272 | */ |
| 1273 | MLX4_GET(flags, outbox->buf, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); |
| 1274 | flags |= MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV; |
| 1275 | flags &= ~MLX4_DEV_CAP_FLAG_MEM_WINDOW; |
| 1276 | actv_ports = mlx4_get_active_ports(dev, slave); |
| 1277 | first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports); |
| 1278 | for (slave_port = 0, real_port = first_port; |
| 1279 | real_port < first_port + |
| 1280 | bitmap_weight(actv_ports.ports, dev->caps.num_ports); |
| 1281 | ++real_port, ++slave_port) { |
| 1282 | if (flags & (MLX4_DEV_CAP_FLAG_WOL_PORT1 << real_port)) |
| 1283 | flags |= MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port; |
| 1284 | else |
| 1285 | flags &= ~(MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port); |
| 1286 | } |
| 1287 | for (; slave_port < dev->caps.num_ports; ++slave_port) |
| 1288 | flags &= ~(MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port); |
| 1289 | |
| 1290 | /* Not exposing RSS IP fragments to guests */ |
| 1291 | flags &= ~MLX4_DEV_CAP_FLAG_RSS_IP_FRAG; |
| 1292 | MLX4_PUT(outbox->buf, flags, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); |
| 1293 | |
| 1294 | MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VL_PORT_OFFSET); |
| 1295 | field &= ~0x0F; |
| 1296 | field |= bitmap_weight(actv_ports.ports, dev->caps.num_ports) & 0x0F; |
| 1297 | MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VL_PORT_OFFSET); |
| 1298 | |
| 1299 | /* For guests, disable timestamp */ |
| 1300 | MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); |
| 1301 | field &= 0x7f; |
| 1302 | MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); |
| 1303 | |
| 1304 | /* For guests, disable vxlan tunneling and QoS support */ |
| 1305 | MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VXLAN); |
| 1306 | field &= 0xd7; |
| 1307 | MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VXLAN); |
| 1308 | |
| 1309 | /* For guests, disable port BEACON */ |
| 1310 | MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_PORT_BEACON_OFFSET); |
| 1311 | field &= 0x7f; |
| 1312 | MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_PORT_BEACON_OFFSET); |
| 1313 | |
| 1314 | /* For guests, report Blueflame disabled */ |
| 1315 | MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_BF_OFFSET); |
| 1316 | field &= 0x7f; |
| 1317 | MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_BF_OFFSET); |
| 1318 | |
| 1319 | /* For guests, disable mw type 2 and port remap*/ |
| 1320 | MLX4_GET(bmme_flags, outbox->buf, QUERY_DEV_CAP_BMME_FLAGS_OFFSET); |
| 1321 | bmme_flags &= ~MLX4_BMME_FLAG_TYPE_2_WIN; |
| 1322 | bmme_flags &= ~MLX4_FLAG_PORT_REMAP; |
| 1323 | MLX4_PUT(outbox->buf, bmme_flags, QUERY_DEV_CAP_BMME_FLAGS_OFFSET); |
| 1324 | |
| 1325 | /* turn off device-managed steering capability if not enabled */ |
| 1326 | if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) { |
| 1327 | MLX4_GET(field, outbox->buf, |
| 1328 | QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); |
| 1329 | field &= 0x7f; |
| 1330 | MLX4_PUT(outbox->buf, field, |
| 1331 | QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); |
| 1332 | } |
| 1333 | |
| 1334 | /* turn off ipoib managed steering for guests */ |
| 1335 | MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET); |
| 1336 | field &= ~0x80; |
| 1337 | MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET); |
| 1338 | |
| 1339 | /* turn off host side virt features (VST, FSM, etc) for guests */ |
| 1340 | MLX4_GET(field32, outbox->buf, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET); |
| 1341 | field32 &= ~(DEV_CAP_EXT_2_FLAG_VLAN_CONTROL | DEV_CAP_EXT_2_FLAG_80_VFS | |
| 1342 | DEV_CAP_EXT_2_FLAG_FSM | DEV_CAP_EXT_2_FLAG_PFC_COUNTERS); |
| 1343 | MLX4_PUT(outbox->buf, field32, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET); |
| 1344 | |
| 1345 | /* turn off QCN for guests */ |
| 1346 | MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET); |
| 1347 | field &= 0xfe; |
| 1348 | MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET); |
| 1349 | |
| 1350 | /* turn off QP max-rate limiting for guests */ |
| 1351 | field16 = 0; |
| 1352 | MLX4_PUT(outbox->buf, field16, QUERY_DEV_CAP_QP_RATE_LIMIT_NUM_OFFSET); |
| 1353 | |
| 1354 | /* turn off QoS per VF support for guests */ |
| 1355 | MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE); |
| 1356 | field &= 0xef; |
| 1357 | MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE); |
| 1358 | |
| 1359 | /* turn off ignore FCS feature for guests */ |
| 1360 | MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CONFIG_DEV_OFFSET); |
| 1361 | field &= 0xfb; |
| 1362 | MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CONFIG_DEV_OFFSET); |
| 1363 | |
| 1364 | return 0; |
| 1365 | } |
| 1366 | |
| 1367 | static void disable_unsupported_roce_caps(void *buf) |
| 1368 | { |
| 1369 | u32 flags; |
| 1370 | |
| 1371 | MLX4_GET(flags, buf, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); |
| 1372 | flags &= ~(1UL << 31); |
| 1373 | MLX4_PUT(buf, flags, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); |
| 1374 | MLX4_GET(flags, buf, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET); |
| 1375 | flags &= ~(1UL << 24); |
| 1376 | MLX4_PUT(buf, flags, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET); |
| 1377 | MLX4_GET(flags, buf, QUERY_DEV_CAP_BMME_FLAGS_OFFSET); |
| 1378 | flags &= ~(MLX4_FLAG_ROCE_V1_V2); |
| 1379 | MLX4_PUT(buf, flags, QUERY_DEV_CAP_BMME_FLAGS_OFFSET); |
| 1380 | } |
| 1381 | |
| 1382 | int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave, |
| 1383 | struct mlx4_vhcr *vhcr, |
| 1384 | struct mlx4_cmd_mailbox *inbox, |
| 1385 | struct mlx4_cmd_mailbox *outbox, |
| 1386 | struct mlx4_cmd_info *cmd) |
| 1387 | { |
| 1388 | struct mlx4_priv *priv = mlx4_priv(dev); |
| 1389 | u64 def_mac; |
| 1390 | u8 port_type; |
| 1391 | u16 short_field; |
| 1392 | int err; |
| 1393 | int admin_link_state; |
| 1394 | int port = mlx4_slave_convert_port(dev, slave, |
| 1395 | vhcr->in_modifier & 0xFF); |
| 1396 | |
| 1397 | #define MLX4_VF_PORT_NO_LINK_SENSE_MASK 0xE0 |
| 1398 | #define MLX4_PORT_LINK_UP_MASK 0x80 |
| 1399 | #define QUERY_PORT_CUR_MAX_PKEY_OFFSET 0x0c |
| 1400 | #define QUERY_PORT_CUR_MAX_GID_OFFSET 0x0e |
| 1401 | |
| 1402 | if (port < 0) |
| 1403 | return -EINVAL; |
| 1404 | |
| 1405 | /* Protect against untrusted guests: enforce that this is the |
| 1406 | * QUERY_PORT general query. |
| 1407 | */ |
| 1408 | if (vhcr->op_modifier || vhcr->in_modifier & ~0xFF) |
| 1409 | return -EINVAL; |
| 1410 | |
| 1411 | vhcr->in_modifier = port; |
| 1412 | |
| 1413 | err = mlx4_cmd_box(dev, 0, outbox->dma, vhcr->in_modifier, 0, |
| 1414 | MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B, |
| 1415 | MLX4_CMD_NATIVE); |
| 1416 | |
| 1417 | if (!err && dev->caps.function != slave) { |
| 1418 | def_mac = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.mac; |
| 1419 | MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET); |
| 1420 | |
| 1421 | /* get port type - currently only eth is enabled */ |
| 1422 | MLX4_GET(port_type, outbox->buf, |
| 1423 | QUERY_PORT_SUPPORTED_TYPE_OFFSET); |
| 1424 | |
| 1425 | /* No link sensing allowed */ |
| 1426 | port_type &= MLX4_VF_PORT_NO_LINK_SENSE_MASK; |
| 1427 | /* set port type to currently operating port type */ |
| 1428 | port_type |= (dev->caps.port_type[vhcr->in_modifier] & 0x3); |
| 1429 | |
| 1430 | admin_link_state = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.link_state; |
| 1431 | if (IFLA_VF_LINK_STATE_ENABLE == admin_link_state) |
| 1432 | port_type |= MLX4_PORT_LINK_UP_MASK; |
| 1433 | else if (IFLA_VF_LINK_STATE_DISABLE == admin_link_state) |
| 1434 | port_type &= ~MLX4_PORT_LINK_UP_MASK; |
| 1435 | else if (IFLA_VF_LINK_STATE_AUTO == admin_link_state && mlx4_is_bonded(dev)) { |
| 1436 | int other_port = (port == 1) ? 2 : 1; |
| 1437 | struct mlx4_port_cap port_cap; |
| 1438 | |
| 1439 | err = mlx4_QUERY_PORT(dev, other_port, &port_cap); |
| 1440 | if (err) |
| 1441 | goto out; |
| 1442 | port_type |= (port_cap.link_state << 7); |
| 1443 | } |
| 1444 | |
| 1445 | MLX4_PUT(outbox->buf, port_type, |
| 1446 | QUERY_PORT_SUPPORTED_TYPE_OFFSET); |
| 1447 | |
| 1448 | if (dev->caps.port_type[vhcr->in_modifier] == MLX4_PORT_TYPE_ETH) |
| 1449 | short_field = mlx4_get_slave_num_gids(dev, slave, port); |
| 1450 | else |
| 1451 | short_field = 1; /* slave max gids */ |
| 1452 | MLX4_PUT(outbox->buf, short_field, |
| 1453 | QUERY_PORT_CUR_MAX_GID_OFFSET); |
| 1454 | |
| 1455 | short_field = dev->caps.pkey_table_len[vhcr->in_modifier]; |
| 1456 | MLX4_PUT(outbox->buf, short_field, |
| 1457 | QUERY_PORT_CUR_MAX_PKEY_OFFSET); |
| 1458 | } |
| 1459 | out: |
| 1460 | return err; |
| 1461 | } |
| 1462 | |
| 1463 | int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port, |
| 1464 | int *gid_tbl_len, int *pkey_tbl_len) |
| 1465 | { |
| 1466 | struct mlx4_cmd_mailbox *mailbox; |
| 1467 | u32 *outbox; |
| 1468 | u16 field; |
| 1469 | int err; |
| 1470 | |
| 1471 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 1472 | if (IS_ERR(mailbox)) |
| 1473 | return PTR_ERR(mailbox); |
| 1474 | |
| 1475 | err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0, |
| 1476 | MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B, |
| 1477 | MLX4_CMD_WRAPPED); |
| 1478 | if (err) |
| 1479 | goto out; |
| 1480 | |
| 1481 | outbox = mailbox->buf; |
| 1482 | |
| 1483 | MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_GID_OFFSET); |
| 1484 | *gid_tbl_len = field; |
| 1485 | |
| 1486 | MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_PKEY_OFFSET); |
| 1487 | *pkey_tbl_len = field; |
| 1488 | |
| 1489 | out: |
| 1490 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 1491 | return err; |
| 1492 | } |
| 1493 | EXPORT_SYMBOL(mlx4_get_slave_pkey_gid_tbl_len); |
| 1494 | |
| 1495 | int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt) |
| 1496 | { |
| 1497 | struct mlx4_cmd_mailbox *mailbox; |
| 1498 | struct mlx4_icm_iter iter; |
| 1499 | __be64 *pages; |
| 1500 | int lg; |
| 1501 | int nent = 0; |
| 1502 | int i; |
| 1503 | int err = 0; |
| 1504 | int ts = 0, tc = 0; |
| 1505 | |
| 1506 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 1507 | if (IS_ERR(mailbox)) |
| 1508 | return PTR_ERR(mailbox); |
| 1509 | pages = mailbox->buf; |
| 1510 | |
| 1511 | for (mlx4_icm_first(icm, &iter); |
| 1512 | !mlx4_icm_last(&iter); |
| 1513 | mlx4_icm_next(&iter)) { |
| 1514 | /* |
| 1515 | * We have to pass pages that are aligned to their |
| 1516 | * size, so find the least significant 1 in the |
| 1517 | * address or size and use that as our log2 size. |
| 1518 | */ |
| 1519 | lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1; |
| 1520 | if (lg < MLX4_ICM_PAGE_SHIFT) { |
| 1521 | mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx)\n", |
| 1522 | MLX4_ICM_PAGE_SIZE, |
| 1523 | (unsigned long long) mlx4_icm_addr(&iter), |
| 1524 | mlx4_icm_size(&iter)); |
| 1525 | err = -EINVAL; |
| 1526 | goto out; |
| 1527 | } |
| 1528 | |
| 1529 | for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) { |
| 1530 | if (virt != -1) { |
| 1531 | pages[nent * 2] = cpu_to_be64(virt); |
| 1532 | virt += 1 << lg; |
| 1533 | } |
| 1534 | |
| 1535 | pages[nent * 2 + 1] = |
| 1536 | cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) | |
| 1537 | (lg - MLX4_ICM_PAGE_SHIFT)); |
| 1538 | ts += 1 << (lg - 10); |
| 1539 | ++tc; |
| 1540 | |
| 1541 | if (++nent == MLX4_MAILBOX_SIZE / 16) { |
| 1542 | err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, |
| 1543 | MLX4_CMD_TIME_CLASS_B, |
| 1544 | MLX4_CMD_NATIVE); |
| 1545 | if (err) |
| 1546 | goto out; |
| 1547 | nent = 0; |
| 1548 | } |
| 1549 | } |
| 1550 | } |
| 1551 | |
| 1552 | if (nent) |
| 1553 | err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, |
| 1554 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); |
| 1555 | if (err) |
| 1556 | goto out; |
| 1557 | |
| 1558 | switch (op) { |
| 1559 | case MLX4_CMD_MAP_FA: |
| 1560 | mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW\n", tc, ts); |
| 1561 | break; |
| 1562 | case MLX4_CMD_MAP_ICM_AUX: |
| 1563 | mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux\n", tc, ts); |
| 1564 | break; |
| 1565 | case MLX4_CMD_MAP_ICM: |
| 1566 | mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM\n", |
| 1567 | tc, ts, (unsigned long long) virt - (ts << 10)); |
| 1568 | break; |
| 1569 | } |
| 1570 | |
| 1571 | out: |
| 1572 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 1573 | return err; |
| 1574 | } |
| 1575 | |
| 1576 | int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm) |
| 1577 | { |
| 1578 | return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1); |
| 1579 | } |
| 1580 | |
| 1581 | int mlx4_UNMAP_FA(struct mlx4_dev *dev) |
| 1582 | { |
| 1583 | return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA, |
| 1584 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); |
| 1585 | } |
| 1586 | |
| 1587 | |
| 1588 | int mlx4_RUN_FW(struct mlx4_dev *dev) |
| 1589 | { |
| 1590 | return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW, |
| 1591 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
| 1592 | } |
| 1593 | |
| 1594 | int mlx4_QUERY_FW(struct mlx4_dev *dev) |
| 1595 | { |
| 1596 | struct mlx4_fw *fw = &mlx4_priv(dev)->fw; |
| 1597 | struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd; |
| 1598 | struct mlx4_cmd_mailbox *mailbox; |
| 1599 | u32 *outbox; |
| 1600 | int err = 0; |
| 1601 | u64 fw_ver; |
| 1602 | u16 cmd_if_rev; |
| 1603 | u8 lg; |
| 1604 | |
| 1605 | #define QUERY_FW_OUT_SIZE 0x100 |
| 1606 | #define QUERY_FW_VER_OFFSET 0x00 |
| 1607 | #define QUERY_FW_PPF_ID 0x09 |
| 1608 | #define QUERY_FW_CMD_IF_REV_OFFSET 0x0a |
| 1609 | #define QUERY_FW_MAX_CMD_OFFSET 0x0f |
| 1610 | #define QUERY_FW_ERR_START_OFFSET 0x30 |
| 1611 | #define QUERY_FW_ERR_SIZE_OFFSET 0x38 |
| 1612 | #define QUERY_FW_ERR_BAR_OFFSET 0x3c |
| 1613 | |
| 1614 | #define QUERY_FW_SIZE_OFFSET 0x00 |
| 1615 | #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20 |
| 1616 | #define QUERY_FW_CLR_INT_BAR_OFFSET 0x28 |
| 1617 | |
| 1618 | #define QUERY_FW_COMM_BASE_OFFSET 0x40 |
| 1619 | #define QUERY_FW_COMM_BAR_OFFSET 0x48 |
| 1620 | |
| 1621 | #define QUERY_FW_CLOCK_OFFSET 0x50 |
| 1622 | #define QUERY_FW_CLOCK_BAR 0x58 |
| 1623 | |
| 1624 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 1625 | if (IS_ERR(mailbox)) |
| 1626 | return PTR_ERR(mailbox); |
| 1627 | outbox = mailbox->buf; |
| 1628 | |
| 1629 | err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW, |
| 1630 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
| 1631 | if (err) |
| 1632 | goto out; |
| 1633 | |
| 1634 | MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET); |
| 1635 | /* |
| 1636 | * FW subminor version is at more significant bits than minor |
| 1637 | * version, so swap here. |
| 1638 | */ |
| 1639 | dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) | |
| 1640 | ((fw_ver & 0xffff0000ull) >> 16) | |
| 1641 | ((fw_ver & 0x0000ffffull) << 16); |
| 1642 | |
| 1643 | MLX4_GET(lg, outbox, QUERY_FW_PPF_ID); |
| 1644 | dev->caps.function = lg; |
| 1645 | |
| 1646 | if (mlx4_is_slave(dev)) |
| 1647 | goto out; |
| 1648 | |
| 1649 | |
| 1650 | MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET); |
| 1651 | if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV || |
| 1652 | cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) { |
| 1653 | mlx4_err(dev, "Installed FW has unsupported command interface revision %d\n", |
| 1654 | cmd_if_rev); |
| 1655 | mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n", |
| 1656 | (int) (dev->caps.fw_ver >> 32), |
| 1657 | (int) (dev->caps.fw_ver >> 16) & 0xffff, |
| 1658 | (int) dev->caps.fw_ver & 0xffff); |
| 1659 | mlx4_err(dev, "This driver version supports only revisions %d to %d\n", |
| 1660 | MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV); |
| 1661 | err = -ENODEV; |
| 1662 | goto out; |
| 1663 | } |
| 1664 | |
| 1665 | if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS) |
| 1666 | dev->flags |= MLX4_FLAG_OLD_PORT_CMDS; |
| 1667 | |
| 1668 | MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET); |
| 1669 | cmd->max_cmds = 1 << lg; |
| 1670 | |
| 1671 | mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n", |
| 1672 | (int) (dev->caps.fw_ver >> 32), |
| 1673 | (int) (dev->caps.fw_ver >> 16) & 0xffff, |
| 1674 | (int) dev->caps.fw_ver & 0xffff, |
| 1675 | cmd_if_rev, cmd->max_cmds); |
| 1676 | |
| 1677 | MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET); |
| 1678 | MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET); |
| 1679 | MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET); |
| 1680 | fw->catas_bar = (fw->catas_bar >> 6) * 2; |
| 1681 | |
| 1682 | mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n", |
| 1683 | (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar); |
| 1684 | |
| 1685 | MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET); |
| 1686 | MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET); |
| 1687 | MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET); |
| 1688 | fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2; |
| 1689 | |
| 1690 | MLX4_GET(fw->comm_base, outbox, QUERY_FW_COMM_BASE_OFFSET); |
| 1691 | MLX4_GET(fw->comm_bar, outbox, QUERY_FW_COMM_BAR_OFFSET); |
| 1692 | fw->comm_bar = (fw->comm_bar >> 6) * 2; |
| 1693 | mlx4_dbg(dev, "Communication vector bar:%d offset:0x%llx\n", |
| 1694 | fw->comm_bar, fw->comm_base); |
| 1695 | mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2); |
| 1696 | |
| 1697 | MLX4_GET(fw->clock_offset, outbox, QUERY_FW_CLOCK_OFFSET); |
| 1698 | MLX4_GET(fw->clock_bar, outbox, QUERY_FW_CLOCK_BAR); |
| 1699 | fw->clock_bar = (fw->clock_bar >> 6) * 2; |
| 1700 | mlx4_dbg(dev, "Internal clock bar:%d offset:0x%llx\n", |
| 1701 | fw->clock_bar, fw->clock_offset); |
| 1702 | |
| 1703 | /* |
| 1704 | * Round up number of system pages needed in case |
| 1705 | * MLX4_ICM_PAGE_SIZE < PAGE_SIZE. |
| 1706 | */ |
| 1707 | fw->fw_pages = |
| 1708 | ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >> |
| 1709 | (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT); |
| 1710 | |
| 1711 | mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n", |
| 1712 | (unsigned long long) fw->clr_int_base, fw->clr_int_bar); |
| 1713 | |
| 1714 | out: |
| 1715 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 1716 | return err; |
| 1717 | } |
| 1718 | |
| 1719 | int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave, |
| 1720 | struct mlx4_vhcr *vhcr, |
| 1721 | struct mlx4_cmd_mailbox *inbox, |
| 1722 | struct mlx4_cmd_mailbox *outbox, |
| 1723 | struct mlx4_cmd_info *cmd) |
| 1724 | { |
| 1725 | u8 *outbuf; |
| 1726 | int err; |
| 1727 | |
| 1728 | outbuf = outbox->buf; |
| 1729 | err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_FW, |
| 1730 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
| 1731 | if (err) |
| 1732 | return err; |
| 1733 | |
| 1734 | /* for slaves, set pci PPF ID to invalid and zero out everything |
| 1735 | * else except FW version */ |
| 1736 | outbuf[0] = outbuf[1] = 0; |
| 1737 | memset(&outbuf[8], 0, QUERY_FW_OUT_SIZE - 8); |
| 1738 | outbuf[QUERY_FW_PPF_ID] = MLX4_INVALID_SLAVE_ID; |
| 1739 | |
| 1740 | return 0; |
| 1741 | } |
| 1742 | |
| 1743 | static void get_board_id(void *vsd, char *board_id) |
| 1744 | { |
| 1745 | int i; |
| 1746 | |
| 1747 | #define VSD_OFFSET_SIG1 0x00 |
| 1748 | #define VSD_OFFSET_SIG2 0xde |
| 1749 | #define VSD_OFFSET_MLX_BOARD_ID 0xd0 |
| 1750 | #define VSD_OFFSET_TS_BOARD_ID 0x20 |
| 1751 | |
| 1752 | #define VSD_SIGNATURE_TOPSPIN 0x5ad |
| 1753 | |
| 1754 | memset(board_id, 0, MLX4_BOARD_ID_LEN); |
| 1755 | |
| 1756 | if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN && |
| 1757 | be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) { |
| 1758 | strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN); |
| 1759 | } else { |
| 1760 | /* |
| 1761 | * The board ID is a string but the firmware byte |
| 1762 | * swaps each 4-byte word before passing it back to |
| 1763 | * us. Therefore we need to swab it before printing. |
| 1764 | */ |
| 1765 | u32 *bid_u32 = (u32 *)board_id; |
| 1766 | |
| 1767 | for (i = 0; i < 4; ++i) { |
| 1768 | u32 *addr; |
| 1769 | u32 val; |
| 1770 | |
| 1771 | addr = (u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4); |
| 1772 | val = get_unaligned(addr); |
| 1773 | val = swab32(val); |
| 1774 | put_unaligned(val, &bid_u32[i]); |
| 1775 | } |
| 1776 | } |
| 1777 | } |
| 1778 | |
| 1779 | int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter) |
| 1780 | { |
| 1781 | struct mlx4_cmd_mailbox *mailbox; |
| 1782 | u32 *outbox; |
| 1783 | int err; |
| 1784 | |
| 1785 | #define QUERY_ADAPTER_OUT_SIZE 0x100 |
| 1786 | #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10 |
| 1787 | #define QUERY_ADAPTER_VSD_OFFSET 0x20 |
| 1788 | |
| 1789 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 1790 | if (IS_ERR(mailbox)) |
| 1791 | return PTR_ERR(mailbox); |
| 1792 | outbox = mailbox->buf; |
| 1793 | |
| 1794 | err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER, |
| 1795 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
| 1796 | if (err) |
| 1797 | goto out; |
| 1798 | |
| 1799 | MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET); |
| 1800 | |
| 1801 | get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4, |
| 1802 | adapter->board_id); |
| 1803 | |
| 1804 | out: |
| 1805 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 1806 | return err; |
| 1807 | } |
| 1808 | |
| 1809 | int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param) |
| 1810 | { |
| 1811 | struct mlx4_cmd_mailbox *mailbox; |
| 1812 | __be32 *inbox; |
| 1813 | int err; |
| 1814 | static const u8 a0_dmfs_hw_steering[] = { |
| 1815 | [MLX4_STEERING_DMFS_A0_DEFAULT] = 0, |
| 1816 | [MLX4_STEERING_DMFS_A0_DYNAMIC] = 1, |
| 1817 | [MLX4_STEERING_DMFS_A0_STATIC] = 2, |
| 1818 | [MLX4_STEERING_DMFS_A0_DISABLE] = 3 |
| 1819 | }; |
| 1820 | |
| 1821 | #define INIT_HCA_IN_SIZE 0x200 |
| 1822 | #define INIT_HCA_VERSION_OFFSET 0x000 |
| 1823 | #define INIT_HCA_VERSION 2 |
| 1824 | #define INIT_HCA_VXLAN_OFFSET 0x0c |
| 1825 | #define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e |
| 1826 | #define INIT_HCA_FLAGS_OFFSET 0x014 |
| 1827 | #define INIT_HCA_RECOVERABLE_ERROR_EVENT_OFFSET 0x018 |
| 1828 | #define INIT_HCA_QPC_OFFSET 0x020 |
| 1829 | #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10) |
| 1830 | #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17) |
| 1831 | #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28) |
| 1832 | #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f) |
| 1833 | #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30) |
| 1834 | #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37) |
| 1835 | #define INIT_HCA_EQE_CQE_OFFSETS (INIT_HCA_QPC_OFFSET + 0x38) |
| 1836 | #define INIT_HCA_EQE_CQE_STRIDE_OFFSET (INIT_HCA_QPC_OFFSET + 0x3b) |
| 1837 | #define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40) |
| 1838 | #define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50) |
| 1839 | #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60) |
| 1840 | #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67) |
| 1841 | #define INIT_HCA_NUM_SYS_EQS_OFFSET (INIT_HCA_QPC_OFFSET + 0x6a) |
| 1842 | #define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70) |
| 1843 | #define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77) |
| 1844 | #define INIT_HCA_MCAST_OFFSET 0x0c0 |
| 1845 | #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00) |
| 1846 | #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12) |
| 1847 | #define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16) |
| 1848 | #define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18) |
| 1849 | #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b) |
| 1850 | #define INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN 0x6 |
| 1851 | #define INIT_HCA_FS_PARAM_OFFSET 0x1d0 |
| 1852 | #define INIT_HCA_FS_BASE_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x00) |
| 1853 | #define INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x12) |
| 1854 | #define INIT_HCA_FS_A0_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x18) |
| 1855 | #define INIT_HCA_FS_LOG_TABLE_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x1b) |
| 1856 | #define INIT_HCA_FS_ETH_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x21) |
| 1857 | #define INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x22) |
| 1858 | #define INIT_HCA_FS_IB_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x25) |
| 1859 | #define INIT_HCA_FS_IB_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x26) |
| 1860 | #define INIT_HCA_TPT_OFFSET 0x0f0 |
| 1861 | #define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00) |
| 1862 | #define INIT_HCA_TPT_MW_OFFSET (INIT_HCA_TPT_OFFSET + 0x08) |
| 1863 | #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b) |
| 1864 | #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10) |
| 1865 | #define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18) |
| 1866 | #define INIT_HCA_UAR_OFFSET 0x120 |
| 1867 | #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a) |
| 1868 | #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b) |
| 1869 | |
| 1870 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 1871 | if (IS_ERR(mailbox)) |
| 1872 | return PTR_ERR(mailbox); |
| 1873 | inbox = mailbox->buf; |
| 1874 | |
| 1875 | *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION; |
| 1876 | |
| 1877 | *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) = |
| 1878 | ((ilog2(cache_line_size()) - 4) << 5) | (1 << 4); |
| 1879 | |
| 1880 | #if defined(__LITTLE_ENDIAN) |
| 1881 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1); |
| 1882 | #elif defined(__BIG_ENDIAN) |
| 1883 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1); |
| 1884 | #else |
| 1885 | #error Host endianness not defined |
| 1886 | #endif |
| 1887 | /* Check port for UD address vector: */ |
| 1888 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1); |
| 1889 | |
| 1890 | /* Enable IPoIB checksumming if we can: */ |
| 1891 | if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM) |
| 1892 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3); |
| 1893 | |
| 1894 | /* Enable QoS support if module parameter set */ |
| 1895 | if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG && enable_qos) |
| 1896 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2); |
| 1897 | |
| 1898 | /* enable counters */ |
| 1899 | if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS) |
| 1900 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4); |
| 1901 | |
| 1902 | /* Enable RSS spread to fragmented IP packets when supported */ |
| 1903 | if (dev->caps.flags & MLX4_DEV_CAP_FLAG_RSS_IP_FRAG) |
| 1904 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 13); |
| 1905 | |
| 1906 | /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */ |
| 1907 | if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_EQE) { |
| 1908 | *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 29); |
| 1909 | dev->caps.eqe_size = 64; |
| 1910 | dev->caps.eqe_factor = 1; |
| 1911 | } else { |
| 1912 | dev->caps.eqe_size = 32; |
| 1913 | dev->caps.eqe_factor = 0; |
| 1914 | } |
| 1915 | |
| 1916 | if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_CQE) { |
| 1917 | *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 30); |
| 1918 | dev->caps.cqe_size = 64; |
| 1919 | dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE; |
| 1920 | } else { |
| 1921 | dev->caps.cqe_size = 32; |
| 1922 | } |
| 1923 | |
| 1924 | /* CX3 is capable of extending CQEs\EQEs to strides larger than 64B */ |
| 1925 | if ((dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) && |
| 1926 | (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE)) { |
| 1927 | dev->caps.eqe_size = cache_line_size(); |
| 1928 | dev->caps.cqe_size = cache_line_size(); |
| 1929 | dev->caps.eqe_factor = 0; |
| 1930 | MLX4_PUT(inbox, (u8)((ilog2(dev->caps.eqe_size) - 5) << 4 | |
| 1931 | (ilog2(dev->caps.eqe_size) - 5)), |
| 1932 | INIT_HCA_EQE_CQE_STRIDE_OFFSET); |
| 1933 | |
| 1934 | /* User still need to know to support CQE > 32B */ |
| 1935 | dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE; |
| 1936 | } |
| 1937 | |
| 1938 | if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT) |
| 1939 | *(inbox + INIT_HCA_RECOVERABLE_ERROR_EVENT_OFFSET / 4) |= cpu_to_be32(1 << 31); |
| 1940 | |
| 1941 | /* QPC/EEC/CQC/EQC/RDMARC attributes */ |
| 1942 | |
| 1943 | MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET); |
| 1944 | MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET); |
| 1945 | MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET); |
| 1946 | MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET); |
| 1947 | MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET); |
| 1948 | MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET); |
| 1949 | MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET); |
| 1950 | MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET); |
| 1951 | MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET); |
| 1952 | MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET); |
| 1953 | MLX4_PUT(inbox, param->num_sys_eqs, INIT_HCA_NUM_SYS_EQS_OFFSET); |
| 1954 | MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET); |
| 1955 | MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET); |
| 1956 | |
| 1957 | /* steering attributes */ |
| 1958 | if (dev->caps.steering_mode == |
| 1959 | MLX4_STEERING_MODE_DEVICE_MANAGED) { |
| 1960 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= |
| 1961 | cpu_to_be32(1 << |
| 1962 | INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN); |
| 1963 | |
| 1964 | MLX4_PUT(inbox, param->mc_base, INIT_HCA_FS_BASE_OFFSET); |
| 1965 | MLX4_PUT(inbox, param->log_mc_entry_sz, |
| 1966 | INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET); |
| 1967 | MLX4_PUT(inbox, param->log_mc_table_sz, |
| 1968 | INIT_HCA_FS_LOG_TABLE_SZ_OFFSET); |
| 1969 | /* Enable Ethernet flow steering |
| 1970 | * with udp unicast and tcp unicast |
| 1971 | */ |
| 1972 | if (dev->caps.dmfs_high_steer_mode != |
| 1973 | MLX4_STEERING_DMFS_A0_STATIC) |
| 1974 | MLX4_PUT(inbox, |
| 1975 | (u8)(MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN), |
| 1976 | INIT_HCA_FS_ETH_BITS_OFFSET); |
| 1977 | MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR, |
| 1978 | INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET); |
| 1979 | /* Enable IPoIB flow steering |
| 1980 | * with udp unicast and tcp unicast |
| 1981 | */ |
| 1982 | MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN), |
| 1983 | INIT_HCA_FS_IB_BITS_OFFSET); |
| 1984 | MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR, |
| 1985 | INIT_HCA_FS_IB_NUM_ADDRS_OFFSET); |
| 1986 | |
| 1987 | if (dev->caps.dmfs_high_steer_mode != |
| 1988 | MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) |
| 1989 | MLX4_PUT(inbox, |
| 1990 | ((u8)(a0_dmfs_hw_steering[dev->caps.dmfs_high_steer_mode] |
| 1991 | << 6)), |
| 1992 | INIT_HCA_FS_A0_OFFSET); |
| 1993 | } else { |
| 1994 | MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET); |
| 1995 | MLX4_PUT(inbox, param->log_mc_entry_sz, |
| 1996 | INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET); |
| 1997 | MLX4_PUT(inbox, param->log_mc_hash_sz, |
| 1998 | INIT_HCA_LOG_MC_HASH_SZ_OFFSET); |
| 1999 | MLX4_PUT(inbox, param->log_mc_table_sz, |
| 2000 | INIT_HCA_LOG_MC_TABLE_SZ_OFFSET); |
| 2001 | if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0) |
| 2002 | MLX4_PUT(inbox, (u8) (1 << 3), |
| 2003 | INIT_HCA_UC_STEERING_OFFSET); |
| 2004 | } |
| 2005 | |
| 2006 | /* TPT attributes */ |
| 2007 | |
| 2008 | MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET); |
| 2009 | MLX4_PUT(inbox, param->mw_enabled, INIT_HCA_TPT_MW_OFFSET); |
| 2010 | MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET); |
| 2011 | MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET); |
| 2012 | MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET); |
| 2013 | |
| 2014 | /* UAR attributes */ |
| 2015 | |
| 2016 | MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET); |
| 2017 | MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET); |
| 2018 | |
| 2019 | /* set parser VXLAN attributes */ |
| 2020 | if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS) { |
| 2021 | u8 parser_params = 0; |
| 2022 | MLX4_PUT(inbox, parser_params, INIT_HCA_VXLAN_OFFSET); |
| 2023 | } |
| 2024 | |
| 2025 | err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, |
| 2026 | MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE); |
| 2027 | |
| 2028 | if (err) |
| 2029 | mlx4_err(dev, "INIT_HCA returns %d\n", err); |
| 2030 | |
| 2031 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 2032 | return err; |
| 2033 | } |
| 2034 | |
| 2035 | int mlx4_QUERY_HCA(struct mlx4_dev *dev, |
| 2036 | struct mlx4_init_hca_param *param) |
| 2037 | { |
| 2038 | struct mlx4_cmd_mailbox *mailbox; |
| 2039 | __be32 *outbox; |
| 2040 | u32 dword_field; |
| 2041 | int err; |
| 2042 | u8 byte_field; |
| 2043 | static const u8 a0_dmfs_query_hw_steering[] = { |
| 2044 | [0] = MLX4_STEERING_DMFS_A0_DEFAULT, |
| 2045 | [1] = MLX4_STEERING_DMFS_A0_DYNAMIC, |
| 2046 | [2] = MLX4_STEERING_DMFS_A0_STATIC, |
| 2047 | [3] = MLX4_STEERING_DMFS_A0_DISABLE |
| 2048 | }; |
| 2049 | |
| 2050 | #define QUERY_HCA_GLOBAL_CAPS_OFFSET 0x04 |
| 2051 | #define QUERY_HCA_CORE_CLOCK_OFFSET 0x0c |
| 2052 | |
| 2053 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 2054 | if (IS_ERR(mailbox)) |
| 2055 | return PTR_ERR(mailbox); |
| 2056 | outbox = mailbox->buf; |
| 2057 | |
| 2058 | err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, |
| 2059 | MLX4_CMD_QUERY_HCA, |
| 2060 | MLX4_CMD_TIME_CLASS_B, |
| 2061 | !mlx4_is_slave(dev)); |
| 2062 | if (err) |
| 2063 | goto out; |
| 2064 | |
| 2065 | MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET); |
| 2066 | MLX4_GET(param->hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET); |
| 2067 | |
| 2068 | /* QPC/EEC/CQC/EQC/RDMARC attributes */ |
| 2069 | |
| 2070 | MLX4_GET(param->qpc_base, outbox, INIT_HCA_QPC_BASE_OFFSET); |
| 2071 | MLX4_GET(param->log_num_qps, outbox, INIT_HCA_LOG_QP_OFFSET); |
| 2072 | MLX4_GET(param->srqc_base, outbox, INIT_HCA_SRQC_BASE_OFFSET); |
| 2073 | MLX4_GET(param->log_num_srqs, outbox, INIT_HCA_LOG_SRQ_OFFSET); |
| 2074 | MLX4_GET(param->cqc_base, outbox, INIT_HCA_CQC_BASE_OFFSET); |
| 2075 | MLX4_GET(param->log_num_cqs, outbox, INIT_HCA_LOG_CQ_OFFSET); |
| 2076 | MLX4_GET(param->altc_base, outbox, INIT_HCA_ALTC_BASE_OFFSET); |
| 2077 | MLX4_GET(param->auxc_base, outbox, INIT_HCA_AUXC_BASE_OFFSET); |
| 2078 | MLX4_GET(param->eqc_base, outbox, INIT_HCA_EQC_BASE_OFFSET); |
| 2079 | MLX4_GET(param->log_num_eqs, outbox, INIT_HCA_LOG_EQ_OFFSET); |
| 2080 | MLX4_GET(param->num_sys_eqs, outbox, INIT_HCA_NUM_SYS_EQS_OFFSET); |
| 2081 | MLX4_GET(param->rdmarc_base, outbox, INIT_HCA_RDMARC_BASE_OFFSET); |
| 2082 | MLX4_GET(param->log_rd_per_qp, outbox, INIT_HCA_LOG_RD_OFFSET); |
| 2083 | |
| 2084 | MLX4_GET(dword_field, outbox, INIT_HCA_FLAGS_OFFSET); |
| 2085 | if (dword_field & (1 << INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN)) { |
| 2086 | param->steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED; |
| 2087 | } else { |
| 2088 | MLX4_GET(byte_field, outbox, INIT_HCA_UC_STEERING_OFFSET); |
| 2089 | if (byte_field & 0x8) |
| 2090 | param->steering_mode = MLX4_STEERING_MODE_B0; |
| 2091 | else |
| 2092 | param->steering_mode = MLX4_STEERING_MODE_A0; |
| 2093 | } |
| 2094 | |
| 2095 | if (dword_field & (1 << 13)) |
| 2096 | param->rss_ip_frags = 1; |
| 2097 | |
| 2098 | /* steering attributes */ |
| 2099 | if (param->steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) { |
| 2100 | MLX4_GET(param->mc_base, outbox, INIT_HCA_FS_BASE_OFFSET); |
| 2101 | MLX4_GET(param->log_mc_entry_sz, outbox, |
| 2102 | INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET); |
| 2103 | MLX4_GET(param->log_mc_table_sz, outbox, |
| 2104 | INIT_HCA_FS_LOG_TABLE_SZ_OFFSET); |
| 2105 | MLX4_GET(byte_field, outbox, |
| 2106 | INIT_HCA_FS_A0_OFFSET); |
| 2107 | param->dmfs_high_steer_mode = |
| 2108 | a0_dmfs_query_hw_steering[(byte_field >> 6) & 3]; |
| 2109 | } else { |
| 2110 | MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET); |
| 2111 | MLX4_GET(param->log_mc_entry_sz, outbox, |
| 2112 | INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET); |
| 2113 | MLX4_GET(param->log_mc_hash_sz, outbox, |
| 2114 | INIT_HCA_LOG_MC_HASH_SZ_OFFSET); |
| 2115 | MLX4_GET(param->log_mc_table_sz, outbox, |
| 2116 | INIT_HCA_LOG_MC_TABLE_SZ_OFFSET); |
| 2117 | } |
| 2118 | |
| 2119 | /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */ |
| 2120 | MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_OFFSETS); |
| 2121 | if (byte_field & 0x20) /* 64-bytes eqe enabled */ |
| 2122 | param->dev_cap_enabled |= MLX4_DEV_CAP_64B_EQE_ENABLED; |
| 2123 | if (byte_field & 0x40) /* 64-bytes cqe enabled */ |
| 2124 | param->dev_cap_enabled |= MLX4_DEV_CAP_64B_CQE_ENABLED; |
| 2125 | |
| 2126 | /* CX3 is capable of extending CQEs\EQEs to strides larger than 64B */ |
| 2127 | MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_STRIDE_OFFSET); |
| 2128 | if (byte_field) { |
| 2129 | param->dev_cap_enabled |= MLX4_DEV_CAP_EQE_STRIDE_ENABLED; |
| 2130 | param->dev_cap_enabled |= MLX4_DEV_CAP_CQE_STRIDE_ENABLED; |
| 2131 | param->cqe_size = 1 << ((byte_field & |
| 2132 | MLX4_CQE_SIZE_MASK_STRIDE) + 5); |
| 2133 | param->eqe_size = 1 << (((byte_field & |
| 2134 | MLX4_EQE_SIZE_MASK_STRIDE) >> 4) + 5); |
| 2135 | } |
| 2136 | |
| 2137 | /* TPT attributes */ |
| 2138 | |
| 2139 | MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET); |
| 2140 | MLX4_GET(param->mw_enabled, outbox, INIT_HCA_TPT_MW_OFFSET); |
| 2141 | MLX4_GET(param->log_mpt_sz, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET); |
| 2142 | MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET); |
| 2143 | MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET); |
| 2144 | |
| 2145 | /* UAR attributes */ |
| 2146 | |
| 2147 | MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET); |
| 2148 | MLX4_GET(param->log_uar_sz, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET); |
| 2149 | |
| 2150 | /* phv_check enable */ |
| 2151 | MLX4_GET(byte_field, outbox, INIT_HCA_CACHELINE_SZ_OFFSET); |
| 2152 | if (byte_field & 0x2) |
| 2153 | param->phv_check_en = 1; |
| 2154 | out: |
| 2155 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 2156 | |
| 2157 | return err; |
| 2158 | } |
| 2159 | |
| 2160 | static int mlx4_hca_core_clock_update(struct mlx4_dev *dev) |
| 2161 | { |
| 2162 | struct mlx4_cmd_mailbox *mailbox; |
| 2163 | __be32 *outbox; |
| 2164 | int err; |
| 2165 | |
| 2166 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 2167 | if (IS_ERR(mailbox)) { |
| 2168 | mlx4_warn(dev, "hca_core_clock mailbox allocation failed\n"); |
| 2169 | return PTR_ERR(mailbox); |
| 2170 | } |
| 2171 | outbox = mailbox->buf; |
| 2172 | |
| 2173 | err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, |
| 2174 | MLX4_CMD_QUERY_HCA, |
| 2175 | MLX4_CMD_TIME_CLASS_B, |
| 2176 | !mlx4_is_slave(dev)); |
| 2177 | if (err) { |
| 2178 | mlx4_warn(dev, "hca_core_clock update failed\n"); |
| 2179 | goto out; |
| 2180 | } |
| 2181 | |
| 2182 | MLX4_GET(dev->caps.hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET); |
| 2183 | |
| 2184 | out: |
| 2185 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 2186 | |
| 2187 | return err; |
| 2188 | } |
| 2189 | |
| 2190 | /* for IB-type ports only in SRIOV mode. Checks that both proxy QP0 |
| 2191 | * and real QP0 are active, so that the paravirtualized QP0 is ready |
| 2192 | * to operate */ |
| 2193 | static int check_qp0_state(struct mlx4_dev *dev, int function, int port) |
| 2194 | { |
| 2195 | struct mlx4_priv *priv = mlx4_priv(dev); |
| 2196 | /* irrelevant if not infiniband */ |
| 2197 | if (priv->mfunc.master.qp0_state[port].proxy_qp0_active && |
| 2198 | priv->mfunc.master.qp0_state[port].qp0_active) |
| 2199 | return 1; |
| 2200 | return 0; |
| 2201 | } |
| 2202 | |
| 2203 | int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave, |
| 2204 | struct mlx4_vhcr *vhcr, |
| 2205 | struct mlx4_cmd_mailbox *inbox, |
| 2206 | struct mlx4_cmd_mailbox *outbox, |
| 2207 | struct mlx4_cmd_info *cmd) |
| 2208 | { |
| 2209 | struct mlx4_priv *priv = mlx4_priv(dev); |
| 2210 | int port = mlx4_slave_convert_port(dev, slave, vhcr->in_modifier); |
| 2211 | int err; |
| 2212 | |
| 2213 | if (port < 0) |
| 2214 | return -EINVAL; |
| 2215 | |
| 2216 | if (priv->mfunc.master.slave_state[slave].init_port_mask & (1 << port)) |
| 2217 | return 0; |
| 2218 | |
| 2219 | if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) { |
| 2220 | /* Enable port only if it was previously disabled */ |
| 2221 | if (!priv->mfunc.master.init_port_ref[port]) { |
| 2222 | err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, |
| 2223 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
| 2224 | if (err) |
| 2225 | return err; |
| 2226 | } |
| 2227 | priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); |
| 2228 | } else { |
| 2229 | if (slave == mlx4_master_func_num(dev)) { |
| 2230 | if (check_qp0_state(dev, slave, port) && |
| 2231 | !priv->mfunc.master.qp0_state[port].port_active) { |
| 2232 | err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, |
| 2233 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
| 2234 | if (err) |
| 2235 | return err; |
| 2236 | priv->mfunc.master.qp0_state[port].port_active = 1; |
| 2237 | priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); |
| 2238 | } |
| 2239 | } else |
| 2240 | priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); |
| 2241 | } |
| 2242 | ++priv->mfunc.master.init_port_ref[port]; |
| 2243 | return 0; |
| 2244 | } |
| 2245 | |
| 2246 | int mlx4_INIT_PORT(struct mlx4_dev *dev, int port) |
| 2247 | { |
| 2248 | struct mlx4_cmd_mailbox *mailbox; |
| 2249 | u32 *inbox; |
| 2250 | int err; |
| 2251 | u32 flags; |
| 2252 | u16 field; |
| 2253 | |
| 2254 | if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { |
| 2255 | #define INIT_PORT_IN_SIZE 256 |
| 2256 | #define INIT_PORT_FLAGS_OFFSET 0x00 |
| 2257 | #define INIT_PORT_FLAG_SIG (1 << 18) |
| 2258 | #define INIT_PORT_FLAG_NG (1 << 17) |
| 2259 | #define INIT_PORT_FLAG_G0 (1 << 16) |
| 2260 | #define INIT_PORT_VL_SHIFT 4 |
| 2261 | #define INIT_PORT_PORT_WIDTH_SHIFT 8 |
| 2262 | #define INIT_PORT_MTU_OFFSET 0x04 |
| 2263 | #define INIT_PORT_MAX_GID_OFFSET 0x06 |
| 2264 | #define INIT_PORT_MAX_PKEY_OFFSET 0x0a |
| 2265 | #define INIT_PORT_GUID0_OFFSET 0x10 |
| 2266 | #define INIT_PORT_NODE_GUID_OFFSET 0x18 |
| 2267 | #define INIT_PORT_SI_GUID_OFFSET 0x20 |
| 2268 | |
| 2269 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 2270 | if (IS_ERR(mailbox)) |
| 2271 | return PTR_ERR(mailbox); |
| 2272 | inbox = mailbox->buf; |
| 2273 | |
| 2274 | flags = 0; |
| 2275 | flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT; |
| 2276 | flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT; |
| 2277 | MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET); |
| 2278 | |
| 2279 | field = 128 << dev->caps.ib_mtu_cap[port]; |
| 2280 | MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET); |
| 2281 | field = dev->caps.gid_table_len[port]; |
| 2282 | MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET); |
| 2283 | field = dev->caps.pkey_table_len[port]; |
| 2284 | MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET); |
| 2285 | |
| 2286 | err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT, |
| 2287 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
| 2288 | |
| 2289 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 2290 | } else |
| 2291 | err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, |
| 2292 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); |
| 2293 | |
| 2294 | if (!err) |
| 2295 | mlx4_hca_core_clock_update(dev); |
| 2296 | |
| 2297 | return err; |
| 2298 | } |
| 2299 | EXPORT_SYMBOL_GPL(mlx4_INIT_PORT); |
| 2300 | |
| 2301 | int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave, |
| 2302 | struct mlx4_vhcr *vhcr, |
| 2303 | struct mlx4_cmd_mailbox *inbox, |
| 2304 | struct mlx4_cmd_mailbox *outbox, |
| 2305 | struct mlx4_cmd_info *cmd) |
| 2306 | { |
| 2307 | struct mlx4_priv *priv = mlx4_priv(dev); |
| 2308 | int port = mlx4_slave_convert_port(dev, slave, vhcr->in_modifier); |
| 2309 | int err; |
| 2310 | |
| 2311 | if (port < 0) |
| 2312 | return -EINVAL; |
| 2313 | |
| 2314 | if (!(priv->mfunc.master.slave_state[slave].init_port_mask & |
| 2315 | (1 << port))) |
| 2316 | return 0; |
| 2317 | |
| 2318 | if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) { |
| 2319 | if (priv->mfunc.master.init_port_ref[port] == 1) { |
| 2320 | err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, |
| 2321 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
| 2322 | if (err) |
| 2323 | return err; |
| 2324 | } |
| 2325 | priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); |
| 2326 | } else { |
| 2327 | /* infiniband port */ |
| 2328 | if (slave == mlx4_master_func_num(dev)) { |
| 2329 | if (!priv->mfunc.master.qp0_state[port].qp0_active && |
| 2330 | priv->mfunc.master.qp0_state[port].port_active) { |
| 2331 | err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, |
| 2332 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
| 2333 | if (err) |
| 2334 | return err; |
| 2335 | priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); |
| 2336 | priv->mfunc.master.qp0_state[port].port_active = 0; |
| 2337 | } |
| 2338 | } else |
| 2339 | priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); |
| 2340 | } |
| 2341 | --priv->mfunc.master.init_port_ref[port]; |
| 2342 | return 0; |
| 2343 | } |
| 2344 | |
| 2345 | int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port) |
| 2346 | { |
| 2347 | return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, |
| 2348 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); |
| 2349 | } |
| 2350 | EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT); |
| 2351 | |
| 2352 | int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic) |
| 2353 | { |
| 2354 | return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, |
| 2355 | MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE); |
| 2356 | } |
| 2357 | |
| 2358 | struct mlx4_config_dev { |
| 2359 | __be32 update_flags; |
| 2360 | __be32 rsvd1[3]; |
| 2361 | __be16 vxlan_udp_dport; |
| 2362 | __be16 rsvd2; |
| 2363 | __be16 roce_v2_entropy; |
| 2364 | __be16 roce_v2_udp_dport; |
| 2365 | __be32 roce_flags; |
| 2366 | __be32 rsvd4[25]; |
| 2367 | __be16 rsvd5; |
| 2368 | u8 rsvd6; |
| 2369 | u8 rx_checksum_val; |
| 2370 | }; |
| 2371 | |
| 2372 | #define MLX4_VXLAN_UDP_DPORT (1 << 0) |
| 2373 | #define MLX4_ROCE_V2_UDP_DPORT BIT(3) |
| 2374 | #define MLX4_DISABLE_RX_PORT BIT(18) |
| 2375 | |
| 2376 | static int mlx4_CONFIG_DEV_set(struct mlx4_dev *dev, struct mlx4_config_dev *config_dev) |
| 2377 | { |
| 2378 | int err; |
| 2379 | struct mlx4_cmd_mailbox *mailbox; |
| 2380 | |
| 2381 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 2382 | if (IS_ERR(mailbox)) |
| 2383 | return PTR_ERR(mailbox); |
| 2384 | |
| 2385 | memcpy(mailbox->buf, config_dev, sizeof(*config_dev)); |
| 2386 | |
| 2387 | err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_CONFIG_DEV, |
| 2388 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); |
| 2389 | |
| 2390 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 2391 | return err; |
| 2392 | } |
| 2393 | |
| 2394 | static int mlx4_CONFIG_DEV_get(struct mlx4_dev *dev, struct mlx4_config_dev *config_dev) |
| 2395 | { |
| 2396 | int err; |
| 2397 | struct mlx4_cmd_mailbox *mailbox; |
| 2398 | |
| 2399 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 2400 | if (IS_ERR(mailbox)) |
| 2401 | return PTR_ERR(mailbox); |
| 2402 | |
| 2403 | err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 1, MLX4_CMD_CONFIG_DEV, |
| 2404 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
| 2405 | |
| 2406 | if (!err) |
| 2407 | memcpy(config_dev, mailbox->buf, sizeof(*config_dev)); |
| 2408 | |
| 2409 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 2410 | return err; |
| 2411 | } |
| 2412 | |
| 2413 | /* Conversion between the HW values and the actual functionality. |
| 2414 | * The value represented by the array index, |
| 2415 | * and the functionality determined by the flags. |
| 2416 | */ |
| 2417 | static const u8 config_dev_csum_flags[] = { |
| 2418 | [0] = 0, |
| 2419 | [1] = MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP, |
| 2420 | [2] = MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP | |
| 2421 | MLX4_RX_CSUM_MODE_L4, |
| 2422 | [3] = MLX4_RX_CSUM_MODE_L4 | |
| 2423 | MLX4_RX_CSUM_MODE_IP_OK_IP_NON_TCP_UDP | |
| 2424 | MLX4_RX_CSUM_MODE_MULTI_VLAN |
| 2425 | }; |
| 2426 | |
| 2427 | int mlx4_config_dev_retrieval(struct mlx4_dev *dev, |
| 2428 | struct mlx4_config_dev_params *params) |
| 2429 | { |
| 2430 | struct mlx4_config_dev config_dev = {0}; |
| 2431 | int err; |
| 2432 | u8 csum_mask; |
| 2433 | |
| 2434 | #define CONFIG_DEV_RX_CSUM_MODE_MASK 0x7 |
| 2435 | #define CONFIG_DEV_RX_CSUM_MODE_PORT1_BIT_OFFSET 0 |
| 2436 | #define CONFIG_DEV_RX_CSUM_MODE_PORT2_BIT_OFFSET 4 |
| 2437 | |
| 2438 | if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_CONFIG_DEV)) |
| 2439 | return -EOPNOTSUPP; |
| 2440 | |
| 2441 | err = mlx4_CONFIG_DEV_get(dev, &config_dev); |
| 2442 | if (err) |
| 2443 | return err; |
| 2444 | |
| 2445 | csum_mask = (config_dev.rx_checksum_val >> CONFIG_DEV_RX_CSUM_MODE_PORT1_BIT_OFFSET) & |
| 2446 | CONFIG_DEV_RX_CSUM_MODE_MASK; |
| 2447 | |
| 2448 | if (csum_mask >= sizeof(config_dev_csum_flags)/sizeof(config_dev_csum_flags[0])) |
| 2449 | return -EINVAL; |
| 2450 | params->rx_csum_flags_port_1 = config_dev_csum_flags[csum_mask]; |
| 2451 | |
| 2452 | csum_mask = (config_dev.rx_checksum_val >> CONFIG_DEV_RX_CSUM_MODE_PORT2_BIT_OFFSET) & |
| 2453 | CONFIG_DEV_RX_CSUM_MODE_MASK; |
| 2454 | |
| 2455 | if (csum_mask >= sizeof(config_dev_csum_flags)/sizeof(config_dev_csum_flags[0])) |
| 2456 | return -EINVAL; |
| 2457 | params->rx_csum_flags_port_2 = config_dev_csum_flags[csum_mask]; |
| 2458 | |
| 2459 | params->vxlan_udp_dport = be16_to_cpu(config_dev.vxlan_udp_dport); |
| 2460 | |
| 2461 | return 0; |
| 2462 | } |
| 2463 | EXPORT_SYMBOL_GPL(mlx4_config_dev_retrieval); |
| 2464 | |
| 2465 | int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port) |
| 2466 | { |
| 2467 | struct mlx4_config_dev config_dev; |
| 2468 | |
| 2469 | memset(&config_dev, 0, sizeof(config_dev)); |
| 2470 | config_dev.update_flags = cpu_to_be32(MLX4_VXLAN_UDP_DPORT); |
| 2471 | config_dev.vxlan_udp_dport = udp_port; |
| 2472 | |
| 2473 | return mlx4_CONFIG_DEV_set(dev, &config_dev); |
| 2474 | } |
| 2475 | EXPORT_SYMBOL_GPL(mlx4_config_vxlan_port); |
| 2476 | |
| 2477 | #define CONFIG_DISABLE_RX_PORT BIT(15) |
| 2478 | int mlx4_disable_rx_port_check(struct mlx4_dev *dev, bool dis) |
| 2479 | { |
| 2480 | struct mlx4_config_dev config_dev; |
| 2481 | |
| 2482 | memset(&config_dev, 0, sizeof(config_dev)); |
| 2483 | config_dev.update_flags = cpu_to_be32(MLX4_DISABLE_RX_PORT); |
| 2484 | if (dis) |
| 2485 | config_dev.roce_flags = |
| 2486 | cpu_to_be32(CONFIG_DISABLE_RX_PORT); |
| 2487 | |
| 2488 | return mlx4_CONFIG_DEV_set(dev, &config_dev); |
| 2489 | } |
| 2490 | |
| 2491 | int mlx4_config_roce_v2_port(struct mlx4_dev *dev, u16 udp_port) |
| 2492 | { |
| 2493 | struct mlx4_config_dev config_dev; |
| 2494 | |
| 2495 | memset(&config_dev, 0, sizeof(config_dev)); |
| 2496 | config_dev.update_flags = cpu_to_be32(MLX4_ROCE_V2_UDP_DPORT); |
| 2497 | config_dev.roce_v2_udp_dport = cpu_to_be16(udp_port); |
| 2498 | |
| 2499 | return mlx4_CONFIG_DEV_set(dev, &config_dev); |
| 2500 | } |
| 2501 | EXPORT_SYMBOL_GPL(mlx4_config_roce_v2_port); |
| 2502 | |
| 2503 | int mlx4_virt2phy_port_map(struct mlx4_dev *dev, u32 port1, u32 port2) |
| 2504 | { |
| 2505 | struct mlx4_cmd_mailbox *mailbox; |
| 2506 | struct { |
| 2507 | __be32 v_port1; |
| 2508 | __be32 v_port2; |
| 2509 | } *v2p; |
| 2510 | int err; |
| 2511 | |
| 2512 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 2513 | if (IS_ERR(mailbox)) |
| 2514 | return -ENOMEM; |
| 2515 | |
| 2516 | v2p = mailbox->buf; |
| 2517 | v2p->v_port1 = cpu_to_be32(port1); |
| 2518 | v2p->v_port2 = cpu_to_be32(port2); |
| 2519 | |
| 2520 | err = mlx4_cmd(dev, mailbox->dma, 0, |
| 2521 | MLX4_SET_PORT_VIRT2PHY, MLX4_CMD_VIRT_PORT_MAP, |
| 2522 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); |
| 2523 | |
| 2524 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 2525 | return err; |
| 2526 | } |
| 2527 | |
| 2528 | |
| 2529 | int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages) |
| 2530 | { |
| 2531 | int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0, |
| 2532 | MLX4_CMD_SET_ICM_SIZE, |
| 2533 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
| 2534 | if (ret) |
| 2535 | return ret; |
| 2536 | |
| 2537 | /* |
| 2538 | * Round up number of system pages needed in case |
| 2539 | * MLX4_ICM_PAGE_SIZE < PAGE_SIZE. |
| 2540 | */ |
| 2541 | *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >> |
| 2542 | (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT); |
| 2543 | |
| 2544 | return 0; |
| 2545 | } |
| 2546 | |
| 2547 | int mlx4_NOP(struct mlx4_dev *dev) |
| 2548 | { |
| 2549 | /* Input modifier of 0x1f means "finish as soon as possible." */ |
| 2550 | return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, MLX4_CMD_TIME_CLASS_A, |
| 2551 | MLX4_CMD_NATIVE); |
| 2552 | } |
| 2553 | |
| 2554 | int mlx4_query_diag_counters(struct mlx4_dev *dev, u8 op_modifier, |
| 2555 | const u32 offset[], |
| 2556 | u32 value[], size_t array_len, u8 port) |
| 2557 | { |
| 2558 | struct mlx4_cmd_mailbox *mailbox; |
| 2559 | u32 *outbox; |
| 2560 | size_t i; |
| 2561 | int ret; |
| 2562 | |
| 2563 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 2564 | if (IS_ERR(mailbox)) |
| 2565 | return PTR_ERR(mailbox); |
| 2566 | |
| 2567 | outbox = mailbox->buf; |
| 2568 | |
| 2569 | ret = mlx4_cmd_box(dev, 0, mailbox->dma, port, op_modifier, |
| 2570 | MLX4_CMD_DIAG_RPRT, MLX4_CMD_TIME_CLASS_A, |
| 2571 | MLX4_CMD_NATIVE); |
| 2572 | if (ret) |
| 2573 | goto out; |
| 2574 | |
| 2575 | for (i = 0; i < array_len; i++) { |
| 2576 | if (offset[i] > MLX4_MAILBOX_SIZE) { |
| 2577 | ret = -EINVAL; |
| 2578 | goto out; |
| 2579 | } |
| 2580 | |
| 2581 | MLX4_GET(value[i], outbox, offset[i]); |
| 2582 | } |
| 2583 | |
| 2584 | out: |
| 2585 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 2586 | return ret; |
| 2587 | } |
| 2588 | EXPORT_SYMBOL(mlx4_query_diag_counters); |
| 2589 | |
| 2590 | int mlx4_get_phys_port_id(struct mlx4_dev *dev) |
| 2591 | { |
| 2592 | u8 port; |
| 2593 | u32 *outbox; |
| 2594 | struct mlx4_cmd_mailbox *mailbox; |
| 2595 | u32 in_mod; |
| 2596 | u32 guid_hi, guid_lo; |
| 2597 | int err, ret = 0; |
| 2598 | #define MOD_STAT_CFG_PORT_OFFSET 8 |
| 2599 | #define MOD_STAT_CFG_GUID_H 0X14 |
| 2600 | #define MOD_STAT_CFG_GUID_L 0X1c |
| 2601 | |
| 2602 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 2603 | if (IS_ERR(mailbox)) |
| 2604 | return PTR_ERR(mailbox); |
| 2605 | outbox = mailbox->buf; |
| 2606 | |
| 2607 | for (port = 1; port <= dev->caps.num_ports; port++) { |
| 2608 | in_mod = port << MOD_STAT_CFG_PORT_OFFSET; |
| 2609 | err = mlx4_cmd_box(dev, 0, mailbox->dma, in_mod, 0x2, |
| 2610 | MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A, |
| 2611 | MLX4_CMD_NATIVE); |
| 2612 | if (err) { |
| 2613 | mlx4_err(dev, "Fail to get port %d uplink guid\n", |
| 2614 | port); |
| 2615 | ret = err; |
| 2616 | } else { |
| 2617 | MLX4_GET(guid_hi, outbox, MOD_STAT_CFG_GUID_H); |
| 2618 | MLX4_GET(guid_lo, outbox, MOD_STAT_CFG_GUID_L); |
| 2619 | dev->caps.phys_port_id[port] = (u64)guid_lo | |
| 2620 | (u64)guid_hi << 32; |
| 2621 | } |
| 2622 | } |
| 2623 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 2624 | return ret; |
| 2625 | } |
| 2626 | |
| 2627 | #define MLX4_WOL_SETUP_MODE (5 << 28) |
| 2628 | int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port) |
| 2629 | { |
| 2630 | u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8; |
| 2631 | |
| 2632 | return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3, |
| 2633 | MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A, |
| 2634 | MLX4_CMD_NATIVE); |
| 2635 | } |
| 2636 | EXPORT_SYMBOL_GPL(mlx4_wol_read); |
| 2637 | |
| 2638 | int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port) |
| 2639 | { |
| 2640 | u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8; |
| 2641 | |
| 2642 | return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG, |
| 2643 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
| 2644 | } |
| 2645 | EXPORT_SYMBOL_GPL(mlx4_wol_write); |
| 2646 | |
| 2647 | enum { |
| 2648 | ADD_TO_MCG = 0x26, |
| 2649 | }; |
| 2650 | |
| 2651 | |
| 2652 | void mlx4_opreq_action(struct work_struct *work) |
| 2653 | { |
| 2654 | struct mlx4_priv *priv = container_of(work, struct mlx4_priv, |
| 2655 | opreq_task); |
| 2656 | struct mlx4_dev *dev = &priv->dev; |
| 2657 | int num_tasks = atomic_read(&priv->opreq_count); |
| 2658 | struct mlx4_cmd_mailbox *mailbox; |
| 2659 | struct mlx4_mgm *mgm; |
| 2660 | u32 *outbox; |
| 2661 | u32 modifier; |
| 2662 | u16 token; |
| 2663 | u16 type; |
| 2664 | int err; |
| 2665 | u32 num_qps; |
| 2666 | struct mlx4_qp qp; |
| 2667 | int i; |
| 2668 | u8 rem_mcg; |
| 2669 | u8 prot; |
| 2670 | |
| 2671 | #define GET_OP_REQ_MODIFIER_OFFSET 0x08 |
| 2672 | #define GET_OP_REQ_TOKEN_OFFSET 0x14 |
| 2673 | #define GET_OP_REQ_TYPE_OFFSET 0x1a |
| 2674 | #define GET_OP_REQ_DATA_OFFSET 0x20 |
| 2675 | |
| 2676 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 2677 | if (IS_ERR(mailbox)) { |
| 2678 | mlx4_err(dev, "Failed to allocate mailbox for GET_OP_REQ\n"); |
| 2679 | return; |
| 2680 | } |
| 2681 | outbox = mailbox->buf; |
| 2682 | |
| 2683 | while (num_tasks) { |
| 2684 | err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, |
| 2685 | MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A, |
| 2686 | MLX4_CMD_NATIVE); |
| 2687 | if (err) { |
| 2688 | mlx4_err(dev, "Failed to retrieve required operation: %d\n", |
| 2689 | err); |
| 2690 | return; |
| 2691 | } |
| 2692 | MLX4_GET(modifier, outbox, GET_OP_REQ_MODIFIER_OFFSET); |
| 2693 | MLX4_GET(token, outbox, GET_OP_REQ_TOKEN_OFFSET); |
| 2694 | MLX4_GET(type, outbox, GET_OP_REQ_TYPE_OFFSET); |
| 2695 | type &= 0xfff; |
| 2696 | |
| 2697 | switch (type) { |
| 2698 | case ADD_TO_MCG: |
| 2699 | if (dev->caps.steering_mode == |
| 2700 | MLX4_STEERING_MODE_DEVICE_MANAGED) { |
| 2701 | mlx4_warn(dev, "ADD MCG operation is not supported in DEVICE_MANAGED steering mode\n"); |
| 2702 | err = EPERM; |
| 2703 | break; |
| 2704 | } |
| 2705 | mgm = (struct mlx4_mgm *)((u8 *)(outbox) + |
| 2706 | GET_OP_REQ_DATA_OFFSET); |
| 2707 | num_qps = be32_to_cpu(mgm->members_count) & |
| 2708 | MGM_QPN_MASK; |
| 2709 | rem_mcg = ((u8 *)(&mgm->members_count))[0] & 1; |
| 2710 | prot = ((u8 *)(&mgm->members_count))[0] >> 6; |
| 2711 | |
| 2712 | for (i = 0; i < num_qps; i++) { |
| 2713 | qp.qpn = be32_to_cpu(mgm->qp[i]); |
| 2714 | if (rem_mcg) |
| 2715 | err = mlx4_multicast_detach(dev, &qp, |
| 2716 | mgm->gid, |
| 2717 | prot, 0); |
| 2718 | else |
| 2719 | err = mlx4_multicast_attach(dev, &qp, |
| 2720 | mgm->gid, |
| 2721 | mgm->gid[5] |
| 2722 | , 0, prot, |
| 2723 | NULL); |
| 2724 | if (err) |
| 2725 | break; |
| 2726 | } |
| 2727 | break; |
| 2728 | default: |
| 2729 | mlx4_warn(dev, "Bad type for required operation\n"); |
| 2730 | err = EINVAL; |
| 2731 | break; |
| 2732 | } |
| 2733 | err = mlx4_cmd(dev, 0, ((u32) err | |
| 2734 | (__force u32)cpu_to_be32(token) << 16), |
| 2735 | 1, MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A, |
| 2736 | MLX4_CMD_NATIVE); |
| 2737 | if (err) { |
| 2738 | mlx4_err(dev, "Failed to acknowledge required request: %d\n", |
| 2739 | err); |
| 2740 | goto out; |
| 2741 | } |
| 2742 | memset(outbox, 0, 0xffc); |
| 2743 | num_tasks = atomic_dec_return(&priv->opreq_count); |
| 2744 | } |
| 2745 | |
| 2746 | out: |
| 2747 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 2748 | } |
| 2749 | |
| 2750 | static int mlx4_check_smp_firewall_active(struct mlx4_dev *dev, |
| 2751 | struct mlx4_cmd_mailbox *mailbox) |
| 2752 | { |
| 2753 | #define MLX4_CMD_MAD_DEMUX_SET_ATTR_OFFSET 0x10 |
| 2754 | #define MLX4_CMD_MAD_DEMUX_GETRESP_ATTR_OFFSET 0x20 |
| 2755 | #define MLX4_CMD_MAD_DEMUX_TRAP_ATTR_OFFSET 0x40 |
| 2756 | #define MLX4_CMD_MAD_DEMUX_TRAP_REPRESS_ATTR_OFFSET 0x70 |
| 2757 | |
| 2758 | u32 set_attr_mask, getresp_attr_mask; |
| 2759 | u32 trap_attr_mask, traprepress_attr_mask; |
| 2760 | |
| 2761 | MLX4_GET(set_attr_mask, mailbox->buf, |
| 2762 | MLX4_CMD_MAD_DEMUX_SET_ATTR_OFFSET); |
| 2763 | mlx4_dbg(dev, "SMP firewall set_attribute_mask = 0x%x\n", |
| 2764 | set_attr_mask); |
| 2765 | |
| 2766 | MLX4_GET(getresp_attr_mask, mailbox->buf, |
| 2767 | MLX4_CMD_MAD_DEMUX_GETRESP_ATTR_OFFSET); |
| 2768 | mlx4_dbg(dev, "SMP firewall getresp_attribute_mask = 0x%x\n", |
| 2769 | getresp_attr_mask); |
| 2770 | |
| 2771 | MLX4_GET(trap_attr_mask, mailbox->buf, |
| 2772 | MLX4_CMD_MAD_DEMUX_TRAP_ATTR_OFFSET); |
| 2773 | mlx4_dbg(dev, "SMP firewall trap_attribute_mask = 0x%x\n", |
| 2774 | trap_attr_mask); |
| 2775 | |
| 2776 | MLX4_GET(traprepress_attr_mask, mailbox->buf, |
| 2777 | MLX4_CMD_MAD_DEMUX_TRAP_REPRESS_ATTR_OFFSET); |
| 2778 | mlx4_dbg(dev, "SMP firewall traprepress_attribute_mask = 0x%x\n", |
| 2779 | traprepress_attr_mask); |
| 2780 | |
| 2781 | if (set_attr_mask && getresp_attr_mask && trap_attr_mask && |
| 2782 | traprepress_attr_mask) |
| 2783 | return 1; |
| 2784 | |
| 2785 | return 0; |
| 2786 | } |
| 2787 | |
| 2788 | int mlx4_config_mad_demux(struct mlx4_dev *dev) |
| 2789 | { |
| 2790 | struct mlx4_cmd_mailbox *mailbox; |
| 2791 | int err; |
| 2792 | |
| 2793 | /* Check if mad_demux is supported */ |
| 2794 | if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_MAD_DEMUX)) |
| 2795 | return 0; |
| 2796 | |
| 2797 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 2798 | if (IS_ERR(mailbox)) { |
| 2799 | mlx4_warn(dev, "Failed to allocate mailbox for cmd MAD_DEMUX"); |
| 2800 | return -ENOMEM; |
| 2801 | } |
| 2802 | |
| 2803 | /* Query mad_demux to find out which MADs are handled by internal sma */ |
| 2804 | err = mlx4_cmd_box(dev, 0, mailbox->dma, 0x01 /* subn mgmt class */, |
| 2805 | MLX4_CMD_MAD_DEMUX_QUERY_RESTR, MLX4_CMD_MAD_DEMUX, |
| 2806 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); |
| 2807 | if (err) { |
| 2808 | mlx4_warn(dev, "MLX4_CMD_MAD_DEMUX: query restrictions failed (%d)\n", |
| 2809 | err); |
| 2810 | goto out; |
| 2811 | } |
| 2812 | |
| 2813 | if (mlx4_check_smp_firewall_active(dev, mailbox)) |
| 2814 | dev->flags |= MLX4_FLAG_SECURE_HOST; |
| 2815 | |
| 2816 | /* Config mad_demux to handle all MADs returned by the query above */ |
| 2817 | err = mlx4_cmd(dev, mailbox->dma, 0x01 /* subn mgmt class */, |
| 2818 | MLX4_CMD_MAD_DEMUX_CONFIG, MLX4_CMD_MAD_DEMUX, |
| 2819 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); |
| 2820 | if (err) { |
| 2821 | mlx4_warn(dev, "MLX4_CMD_MAD_DEMUX: configure failed (%d)\n", err); |
| 2822 | goto out; |
| 2823 | } |
| 2824 | |
| 2825 | if (dev->flags & MLX4_FLAG_SECURE_HOST) |
| 2826 | mlx4_warn(dev, "HCA operating in secure-host mode. SMP firewall activated.\n"); |
| 2827 | out: |
| 2828 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 2829 | return err; |
| 2830 | } |
| 2831 | |
| 2832 | /* Access Reg commands */ |
| 2833 | enum mlx4_access_reg_masks { |
| 2834 | MLX4_ACCESS_REG_STATUS_MASK = 0x7f, |
| 2835 | MLX4_ACCESS_REG_METHOD_MASK = 0x7f, |
| 2836 | MLX4_ACCESS_REG_LEN_MASK = 0x7ff |
| 2837 | }; |
| 2838 | |
| 2839 | struct mlx4_access_reg { |
| 2840 | __be16 constant1; |
| 2841 | u8 status; |
| 2842 | u8 resrvd1; |
| 2843 | __be16 reg_id; |
| 2844 | u8 method; |
| 2845 | u8 constant2; |
| 2846 | __be32 resrvd2[2]; |
| 2847 | __be16 len_const; |
| 2848 | __be16 resrvd3; |
| 2849 | #define MLX4_ACCESS_REG_HEADER_SIZE (20) |
| 2850 | u8 reg_data[MLX4_MAILBOX_SIZE-MLX4_ACCESS_REG_HEADER_SIZE]; |
| 2851 | } __attribute__((__packed__)); |
| 2852 | |
| 2853 | /** |
| 2854 | * mlx4_ACCESS_REG - Generic access reg command. |
| 2855 | * @dev: mlx4_dev. |
| 2856 | * @reg_id: register ID to access. |
| 2857 | * @method: Access method Read/Write. |
| 2858 | * @reg_len: register length to Read/Write in bytes. |
| 2859 | * @reg_data: reg_data pointer to Read/Write From/To. |
| 2860 | * |
| 2861 | * Access ConnectX registers FW command. |
| 2862 | * Returns 0 on success and copies outbox mlx4_access_reg data |
| 2863 | * field into reg_data or a negative error code. |
| 2864 | */ |
| 2865 | static int mlx4_ACCESS_REG(struct mlx4_dev *dev, u16 reg_id, |
| 2866 | enum mlx4_access_reg_method method, |
| 2867 | u16 reg_len, void *reg_data) |
| 2868 | { |
| 2869 | struct mlx4_cmd_mailbox *inbox, *outbox; |
| 2870 | struct mlx4_access_reg *inbuf, *outbuf; |
| 2871 | int err; |
| 2872 | |
| 2873 | inbox = mlx4_alloc_cmd_mailbox(dev); |
| 2874 | if (IS_ERR(inbox)) |
| 2875 | return PTR_ERR(inbox); |
| 2876 | |
| 2877 | outbox = mlx4_alloc_cmd_mailbox(dev); |
| 2878 | if (IS_ERR(outbox)) { |
| 2879 | mlx4_free_cmd_mailbox(dev, inbox); |
| 2880 | return PTR_ERR(outbox); |
| 2881 | } |
| 2882 | |
| 2883 | inbuf = inbox->buf; |
| 2884 | outbuf = outbox->buf; |
| 2885 | |
| 2886 | inbuf->constant1 = cpu_to_be16(0x1<<11 | 0x4); |
| 2887 | inbuf->constant2 = 0x1; |
| 2888 | inbuf->reg_id = cpu_to_be16(reg_id); |
| 2889 | inbuf->method = method & MLX4_ACCESS_REG_METHOD_MASK; |
| 2890 | |
| 2891 | reg_len = min(reg_len, (u16)(sizeof(inbuf->reg_data))); |
| 2892 | inbuf->len_const = |
| 2893 | cpu_to_be16(((reg_len/4 + 1) & MLX4_ACCESS_REG_LEN_MASK) | |
| 2894 | ((0x3) << 12)); |
| 2895 | |
| 2896 | memcpy(inbuf->reg_data, reg_data, reg_len); |
| 2897 | err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, 0, 0, |
| 2898 | MLX4_CMD_ACCESS_REG, MLX4_CMD_TIME_CLASS_C, |
| 2899 | MLX4_CMD_WRAPPED); |
| 2900 | if (err) |
| 2901 | goto out; |
| 2902 | |
| 2903 | if (outbuf->status & MLX4_ACCESS_REG_STATUS_MASK) { |
| 2904 | err = outbuf->status & MLX4_ACCESS_REG_STATUS_MASK; |
| 2905 | mlx4_err(dev, |
| 2906 | "MLX4_CMD_ACCESS_REG(%x) returned REG status (%x)\n", |
| 2907 | reg_id, err); |
| 2908 | goto out; |
| 2909 | } |
| 2910 | |
| 2911 | memcpy(reg_data, outbuf->reg_data, reg_len); |
| 2912 | out: |
| 2913 | mlx4_free_cmd_mailbox(dev, inbox); |
| 2914 | mlx4_free_cmd_mailbox(dev, outbox); |
| 2915 | return err; |
| 2916 | } |
| 2917 | |
| 2918 | /* ConnectX registers IDs */ |
| 2919 | enum mlx4_reg_id { |
| 2920 | MLX4_REG_ID_PTYS = 0x5004, |
| 2921 | }; |
| 2922 | |
| 2923 | /** |
| 2924 | * mlx4_ACCESS_PTYS_REG - Access PTYs (Port Type and Speed) |
| 2925 | * register |
| 2926 | * @dev: mlx4_dev. |
| 2927 | * @method: Access method Read/Write. |
| 2928 | * @ptys_reg: PTYS register data pointer. |
| 2929 | * |
| 2930 | * Access ConnectX PTYS register, to Read/Write Port Type/Speed |
| 2931 | * configuration |
| 2932 | * Returns 0 on success or a negative error code. |
| 2933 | */ |
| 2934 | int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev, |
| 2935 | enum mlx4_access_reg_method method, |
| 2936 | struct mlx4_ptys_reg *ptys_reg) |
| 2937 | { |
| 2938 | return mlx4_ACCESS_REG(dev, MLX4_REG_ID_PTYS, |
| 2939 | method, sizeof(*ptys_reg), ptys_reg); |
| 2940 | } |
| 2941 | EXPORT_SYMBOL_GPL(mlx4_ACCESS_PTYS_REG); |
| 2942 | |
| 2943 | int mlx4_ACCESS_REG_wrapper(struct mlx4_dev *dev, int slave, |
| 2944 | struct mlx4_vhcr *vhcr, |
| 2945 | struct mlx4_cmd_mailbox *inbox, |
| 2946 | struct mlx4_cmd_mailbox *outbox, |
| 2947 | struct mlx4_cmd_info *cmd) |
| 2948 | { |
| 2949 | struct mlx4_access_reg *inbuf = inbox->buf; |
| 2950 | u8 method = inbuf->method & MLX4_ACCESS_REG_METHOD_MASK; |
| 2951 | u16 reg_id = be16_to_cpu(inbuf->reg_id); |
| 2952 | |
| 2953 | if (slave != mlx4_master_func_num(dev) && |
| 2954 | method == MLX4_ACCESS_REG_WRITE) |
| 2955 | return -EPERM; |
| 2956 | |
| 2957 | if (reg_id == MLX4_REG_ID_PTYS) { |
| 2958 | struct mlx4_ptys_reg *ptys_reg = |
| 2959 | (struct mlx4_ptys_reg *)inbuf->reg_data; |
| 2960 | |
| 2961 | ptys_reg->local_port = |
| 2962 | mlx4_slave_convert_port(dev, slave, |
| 2963 | ptys_reg->local_port); |
| 2964 | } |
| 2965 | |
| 2966 | return mlx4_cmd_box(dev, inbox->dma, outbox->dma, vhcr->in_modifier, |
| 2967 | 0, MLX4_CMD_ACCESS_REG, MLX4_CMD_TIME_CLASS_C, |
| 2968 | MLX4_CMD_NATIVE); |
| 2969 | } |
| 2970 | |
| 2971 | static int mlx4_SET_PORT_phv_bit(struct mlx4_dev *dev, u8 port, u8 phv_bit) |
| 2972 | { |
| 2973 | #define SET_PORT_GEN_PHV_VALID 0x10 |
| 2974 | #define SET_PORT_GEN_PHV_EN 0x80 |
| 2975 | |
| 2976 | struct mlx4_cmd_mailbox *mailbox; |
| 2977 | struct mlx4_set_port_general_context *context; |
| 2978 | u32 in_mod; |
| 2979 | int err; |
| 2980 | |
| 2981 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 2982 | if (IS_ERR(mailbox)) |
| 2983 | return PTR_ERR(mailbox); |
| 2984 | context = mailbox->buf; |
| 2985 | |
| 2986 | context->flags2 |= SET_PORT_GEN_PHV_VALID; |
| 2987 | if (phv_bit) |
| 2988 | context->phv_en |= SET_PORT_GEN_PHV_EN; |
| 2989 | |
| 2990 | in_mod = MLX4_SET_PORT_GENERAL << 8 | port; |
| 2991 | err = mlx4_cmd(dev, mailbox->dma, in_mod, MLX4_SET_PORT_ETH_OPCODE, |
| 2992 | MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, |
| 2993 | MLX4_CMD_NATIVE); |
| 2994 | |
| 2995 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 2996 | return err; |
| 2997 | } |
| 2998 | |
| 2999 | int get_phv_bit(struct mlx4_dev *dev, u8 port, int *phv) |
| 3000 | { |
| 3001 | int err; |
| 3002 | struct mlx4_func_cap func_cap; |
| 3003 | |
| 3004 | memset(&func_cap, 0, sizeof(func_cap)); |
| 3005 | err = mlx4_QUERY_FUNC_CAP(dev, port, &func_cap); |
| 3006 | if (!err) |
| 3007 | *phv = func_cap.flags0 & QUERY_FUNC_CAP_PHV_BIT; |
| 3008 | return err; |
| 3009 | } |
| 3010 | EXPORT_SYMBOL(get_phv_bit); |
| 3011 | |
| 3012 | int set_phv_bit(struct mlx4_dev *dev, u8 port, int new_val) |
| 3013 | { |
| 3014 | int ret; |
| 3015 | |
| 3016 | if (mlx4_is_slave(dev)) |
| 3017 | return -EPERM; |
| 3018 | |
| 3019 | if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PHV_EN && |
| 3020 | !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN)) { |
| 3021 | ret = mlx4_SET_PORT_phv_bit(dev, port, new_val); |
| 3022 | if (!ret) |
| 3023 | dev->caps.phv_bit[port] = new_val; |
| 3024 | return ret; |
| 3025 | } |
| 3026 | |
| 3027 | return -EOPNOTSUPP; |
| 3028 | } |
| 3029 | EXPORT_SYMBOL(set_phv_bit); |
| 3030 | |
| 3031 | int mlx4_get_is_vlan_offload_disabled(struct mlx4_dev *dev, u8 port, |
| 3032 | bool *vlan_offload_disabled) |
| 3033 | { |
| 3034 | struct mlx4_func_cap func_cap; |
| 3035 | int err; |
| 3036 | |
| 3037 | memset(&func_cap, 0, sizeof(func_cap)); |
| 3038 | err = mlx4_QUERY_FUNC_CAP(dev, port, &func_cap); |
| 3039 | if (!err) |
| 3040 | *vlan_offload_disabled = |
| 3041 | !!(func_cap.flags0 & |
| 3042 | QUERY_FUNC_CAP_VLAN_OFFLOAD_DISABLE); |
| 3043 | return err; |
| 3044 | } |
| 3045 | EXPORT_SYMBOL(mlx4_get_is_vlan_offload_disabled); |
| 3046 | |
| 3047 | void mlx4_replace_zero_macs(struct mlx4_dev *dev) |
| 3048 | { |
| 3049 | int i; |
| 3050 | u8 mac_addr[ETH_ALEN]; |
| 3051 | |
| 3052 | dev->port_random_macs = 0; |
| 3053 | for (i = 1; i <= dev->caps.num_ports; ++i) |
| 3054 | if (!dev->caps.def_mac[i] && |
| 3055 | dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH) { |
| 3056 | eth_random_addr(mac_addr); |
| 3057 | dev->port_random_macs |= 1 << i; |
| 3058 | dev->caps.def_mac[i] = mlx4_mac_to_u64(mac_addr); |
| 3059 | } |
| 3060 | } |
| 3061 | EXPORT_SYMBOL_GPL(mlx4_replace_zero_macs); |