| 1 | /* |
| 2 | * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. |
| 3 | * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. |
| 4 | * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved. |
| 5 | * |
| 6 | * This software is available to you under a choice of one of two |
| 7 | * licenses. You may choose to be licensed under the terms of the GNU |
| 8 | * General Public License (GPL) Version 2, available from the file |
| 9 | * COPYING in the main directory of this source tree, or the |
| 10 | * OpenIB.org BSD license below: |
| 11 | * |
| 12 | * Redistribution and use in source and binary forms, with or |
| 13 | * without modification, are permitted provided that the following |
| 14 | * conditions are met: |
| 15 | * |
| 16 | * - Redistributions of source code must retain the above |
| 17 | * copyright notice, this list of conditions and the following |
| 18 | * disclaimer. |
| 19 | * |
| 20 | * - Redistributions in binary form must reproduce the above |
| 21 | * copyright notice, this list of conditions and the following |
| 22 | * disclaimer in the documentation and/or other materials |
| 23 | * provided with the distribution. |
| 24 | * |
| 25 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| 26 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 27 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| 28 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS |
| 29 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN |
| 30 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
| 31 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 32 | * SOFTWARE. |
| 33 | */ |
| 34 | |
| 35 | #include <linux/etherdevice.h> |
| 36 | #include <linux/mlx4/cmd.h> |
| 37 | #include <linux/module.h> |
| 38 | #include <linux/cache.h> |
| 39 | |
| 40 | #include "fw.h" |
| 41 | #include "icm.h" |
| 42 | |
| 43 | enum { |
| 44 | MLX4_COMMAND_INTERFACE_MIN_REV = 2, |
| 45 | MLX4_COMMAND_INTERFACE_MAX_REV = 3, |
| 46 | MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3, |
| 47 | }; |
| 48 | |
| 49 | extern void __buggy_use_of_MLX4_GET(void); |
| 50 | extern void __buggy_use_of_MLX4_PUT(void); |
| 51 | |
| 52 | static bool enable_qos; |
| 53 | module_param(enable_qos, bool, 0444); |
| 54 | MODULE_PARM_DESC(enable_qos, "Enable Quality of Service support in the HCA (default: off)"); |
| 55 | |
| 56 | #define MLX4_GET(dest, source, offset) \ |
| 57 | do { \ |
| 58 | void *__p = (char *) (source) + (offset); \ |
| 59 | switch (sizeof (dest)) { \ |
| 60 | case 1: (dest) = *(u8 *) __p; break; \ |
| 61 | case 2: (dest) = be16_to_cpup(__p); break; \ |
| 62 | case 4: (dest) = be32_to_cpup(__p); break; \ |
| 63 | case 8: (dest) = be64_to_cpup(__p); break; \ |
| 64 | default: __buggy_use_of_MLX4_GET(); \ |
| 65 | } \ |
| 66 | } while (0) |
| 67 | |
| 68 | #define MLX4_PUT(dest, source, offset) \ |
| 69 | do { \ |
| 70 | void *__d = ((char *) (dest) + (offset)); \ |
| 71 | switch (sizeof(source)) { \ |
| 72 | case 1: *(u8 *) __d = (source); break; \ |
| 73 | case 2: *(__be16 *) __d = cpu_to_be16(source); break; \ |
| 74 | case 4: *(__be32 *) __d = cpu_to_be32(source); break; \ |
| 75 | case 8: *(__be64 *) __d = cpu_to_be64(source); break; \ |
| 76 | default: __buggy_use_of_MLX4_PUT(); \ |
| 77 | } \ |
| 78 | } while (0) |
| 79 | |
| 80 | static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags) |
| 81 | { |
| 82 | static const char *fname[] = { |
| 83 | [ 0] = "RC transport", |
| 84 | [ 1] = "UC transport", |
| 85 | [ 2] = "UD transport", |
| 86 | [ 3] = "XRC transport", |
| 87 | [ 4] = "reliable multicast", |
| 88 | [ 5] = "FCoIB support", |
| 89 | [ 6] = "SRQ support", |
| 90 | [ 7] = "IPoIB checksum offload", |
| 91 | [ 8] = "P_Key violation counter", |
| 92 | [ 9] = "Q_Key violation counter", |
| 93 | [10] = "VMM", |
| 94 | [12] = "DPDP", |
| 95 | [15] = "Big LSO headers", |
| 96 | [16] = "MW support", |
| 97 | [17] = "APM support", |
| 98 | [18] = "Atomic ops support", |
| 99 | [19] = "Raw multicast support", |
| 100 | [20] = "Address vector port checking support", |
| 101 | [21] = "UD multicast support", |
| 102 | [24] = "Demand paging support", |
| 103 | [25] = "Router support", |
| 104 | [30] = "IBoE support", |
| 105 | [32] = "Unicast loopback support", |
| 106 | [34] = "FCS header control", |
| 107 | [38] = "Wake On LAN support", |
| 108 | [40] = "UDP RSS support", |
| 109 | [41] = "Unicast VEP steering support", |
| 110 | [42] = "Multicast VEP steering support", |
| 111 | [48] = "Counters support", |
| 112 | [59] = "Port management change event support", |
| 113 | [61] = "64 byte EQE support", |
| 114 | [62] = "64 byte CQE support", |
| 115 | }; |
| 116 | int i; |
| 117 | |
| 118 | mlx4_dbg(dev, "DEV_CAP flags:\n"); |
| 119 | for (i = 0; i < ARRAY_SIZE(fname); ++i) |
| 120 | if (fname[i] && (flags & (1LL << i))) |
| 121 | mlx4_dbg(dev, " %s\n", fname[i]); |
| 122 | } |
| 123 | |
| 124 | static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags) |
| 125 | { |
| 126 | static const char * const fname[] = { |
| 127 | [0] = "RSS support", |
| 128 | [1] = "RSS Toeplitz Hash Function support", |
| 129 | [2] = "RSS XOR Hash Function support", |
| 130 | [3] = "Device manage flow steering support", |
| 131 | [4] = "Automatic mac reassignment support" |
| 132 | }; |
| 133 | int i; |
| 134 | |
| 135 | for (i = 0; i < ARRAY_SIZE(fname); ++i) |
| 136 | if (fname[i] && (flags & (1LL << i))) |
| 137 | mlx4_dbg(dev, " %s\n", fname[i]); |
| 138 | } |
| 139 | |
| 140 | int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg) |
| 141 | { |
| 142 | struct mlx4_cmd_mailbox *mailbox; |
| 143 | u32 *inbox; |
| 144 | int err = 0; |
| 145 | |
| 146 | #define MOD_STAT_CFG_IN_SIZE 0x100 |
| 147 | |
| 148 | #define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002 |
| 149 | #define MOD_STAT_CFG_PG_SZ_OFFSET 0x003 |
| 150 | |
| 151 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 152 | if (IS_ERR(mailbox)) |
| 153 | return PTR_ERR(mailbox); |
| 154 | inbox = mailbox->buf; |
| 155 | |
| 156 | memset(inbox, 0, MOD_STAT_CFG_IN_SIZE); |
| 157 | |
| 158 | MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET); |
| 159 | MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET); |
| 160 | |
| 161 | err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG, |
| 162 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
| 163 | |
| 164 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 165 | return err; |
| 166 | } |
| 167 | |
| 168 | int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave, |
| 169 | struct mlx4_vhcr *vhcr, |
| 170 | struct mlx4_cmd_mailbox *inbox, |
| 171 | struct mlx4_cmd_mailbox *outbox, |
| 172 | struct mlx4_cmd_info *cmd) |
| 173 | { |
| 174 | u8 field; |
| 175 | u32 size; |
| 176 | int err = 0; |
| 177 | |
| 178 | #define QUERY_FUNC_CAP_FLAGS_OFFSET 0x0 |
| 179 | #define QUERY_FUNC_CAP_NUM_PORTS_OFFSET 0x1 |
| 180 | #define QUERY_FUNC_CAP_PF_BHVR_OFFSET 0x4 |
| 181 | #define QUERY_FUNC_CAP_FMR_OFFSET 0x8 |
| 182 | #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET 0x10 |
| 183 | #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET 0x14 |
| 184 | #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET 0x18 |
| 185 | #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET 0x20 |
| 186 | #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET 0x24 |
| 187 | #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET 0x28 |
| 188 | #define QUERY_FUNC_CAP_MAX_EQ_OFFSET 0x2c |
| 189 | #define QUERY_FUNC_CAP_RESERVED_EQ_OFFSET 0x30 |
| 190 | |
| 191 | #define QUERY_FUNC_CAP_FMR_FLAG 0x80 |
| 192 | #define QUERY_FUNC_CAP_FLAG_RDMA 0x40 |
| 193 | #define QUERY_FUNC_CAP_FLAG_ETH 0x80 |
| 194 | |
| 195 | /* when opcode modifier = 1 */ |
| 196 | #define QUERY_FUNC_CAP_PHYS_PORT_OFFSET 0x3 |
| 197 | #define QUERY_FUNC_CAP_RDMA_PROPS_OFFSET 0x8 |
| 198 | #define QUERY_FUNC_CAP_ETH_PROPS_OFFSET 0xc |
| 199 | |
| 200 | #define QUERY_FUNC_CAP_QP0_TUNNEL 0x10 |
| 201 | #define QUERY_FUNC_CAP_QP0_PROXY 0x14 |
| 202 | #define QUERY_FUNC_CAP_QP1_TUNNEL 0x18 |
| 203 | #define QUERY_FUNC_CAP_QP1_PROXY 0x1c |
| 204 | |
| 205 | #define QUERY_FUNC_CAP_ETH_PROPS_FORCE_MAC 0x40 |
| 206 | #define QUERY_FUNC_CAP_ETH_PROPS_FORCE_VLAN 0x80 |
| 207 | |
| 208 | #define QUERY_FUNC_CAP_RDMA_PROPS_FORCE_PHY_WQE_GID 0x80 |
| 209 | |
| 210 | if (vhcr->op_modifier == 1) { |
| 211 | field = 0; |
| 212 | /* ensure force vlan and force mac bits are not set */ |
| 213 | MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_ETH_PROPS_OFFSET); |
| 214 | /* ensure that phy_wqe_gid bit is not set */ |
| 215 | MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_RDMA_PROPS_OFFSET); |
| 216 | |
| 217 | field = vhcr->in_modifier; /* phys-port = logical-port */ |
| 218 | MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET); |
| 219 | |
| 220 | /* size is now the QP number */ |
| 221 | size = dev->phys_caps.base_tunnel_sqpn + 8 * slave + field - 1; |
| 222 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_TUNNEL); |
| 223 | |
| 224 | size += 2; |
| 225 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_TUNNEL); |
| 226 | |
| 227 | size = dev->phys_caps.base_proxy_sqpn + 8 * slave + field - 1; |
| 228 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_PROXY); |
| 229 | |
| 230 | size += 2; |
| 231 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_PROXY); |
| 232 | |
| 233 | } else if (vhcr->op_modifier == 0) { |
| 234 | /* enable rdma and ethernet interfaces */ |
| 235 | field = (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA); |
| 236 | MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET); |
| 237 | |
| 238 | field = dev->caps.num_ports; |
| 239 | MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET); |
| 240 | |
| 241 | size = dev->caps.function_caps; /* set PF behaviours */ |
| 242 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_PF_BHVR_OFFSET); |
| 243 | |
| 244 | field = 0; /* protected FMR support not available as yet */ |
| 245 | MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FMR_OFFSET); |
| 246 | |
| 247 | size = dev->caps.num_qps; |
| 248 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET); |
| 249 | |
| 250 | size = dev->caps.num_srqs; |
| 251 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET); |
| 252 | |
| 253 | size = dev->caps.num_cqs; |
| 254 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET); |
| 255 | |
| 256 | size = dev->caps.num_eqs; |
| 257 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET); |
| 258 | |
| 259 | size = dev->caps.reserved_eqs; |
| 260 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET); |
| 261 | |
| 262 | size = dev->caps.num_mpts; |
| 263 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET); |
| 264 | |
| 265 | size = dev->caps.num_mtts; |
| 266 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET); |
| 267 | |
| 268 | size = dev->caps.num_mgms + dev->caps.num_amgms; |
| 269 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET); |
| 270 | |
| 271 | } else |
| 272 | err = -EINVAL; |
| 273 | |
| 274 | return err; |
| 275 | } |
| 276 | |
| 277 | int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, u32 gen_or_port, |
| 278 | struct mlx4_func_cap *func_cap) |
| 279 | { |
| 280 | struct mlx4_cmd_mailbox *mailbox; |
| 281 | u32 *outbox; |
| 282 | u8 field, op_modifier; |
| 283 | u32 size; |
| 284 | int err = 0; |
| 285 | |
| 286 | op_modifier = !!gen_or_port; /* 0 = general, 1 = logical port */ |
| 287 | |
| 288 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 289 | if (IS_ERR(mailbox)) |
| 290 | return PTR_ERR(mailbox); |
| 291 | |
| 292 | err = mlx4_cmd_box(dev, 0, mailbox->dma, gen_or_port, op_modifier, |
| 293 | MLX4_CMD_QUERY_FUNC_CAP, |
| 294 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); |
| 295 | if (err) |
| 296 | goto out; |
| 297 | |
| 298 | outbox = mailbox->buf; |
| 299 | |
| 300 | if (!op_modifier) { |
| 301 | MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET); |
| 302 | if (!(field & (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA))) { |
| 303 | mlx4_err(dev, "The host supports neither eth nor rdma interfaces\n"); |
| 304 | err = -EPROTONOSUPPORT; |
| 305 | goto out; |
| 306 | } |
| 307 | func_cap->flags = field; |
| 308 | |
| 309 | MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET); |
| 310 | func_cap->num_ports = field; |
| 311 | |
| 312 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_PF_BHVR_OFFSET); |
| 313 | func_cap->pf_context_behaviour = size; |
| 314 | |
| 315 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET); |
| 316 | func_cap->qp_quota = size & 0xFFFFFF; |
| 317 | |
| 318 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET); |
| 319 | func_cap->srq_quota = size & 0xFFFFFF; |
| 320 | |
| 321 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET); |
| 322 | func_cap->cq_quota = size & 0xFFFFFF; |
| 323 | |
| 324 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_MAX_EQ_OFFSET); |
| 325 | func_cap->max_eq = size & 0xFFFFFF; |
| 326 | |
| 327 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET); |
| 328 | func_cap->reserved_eq = size & 0xFFFFFF; |
| 329 | |
| 330 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET); |
| 331 | func_cap->mpt_quota = size & 0xFFFFFF; |
| 332 | |
| 333 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET); |
| 334 | func_cap->mtt_quota = size & 0xFFFFFF; |
| 335 | |
| 336 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET); |
| 337 | func_cap->mcg_quota = size & 0xFFFFFF; |
| 338 | goto out; |
| 339 | } |
| 340 | |
| 341 | /* logical port query */ |
| 342 | if (gen_or_port > dev->caps.num_ports) { |
| 343 | err = -EINVAL; |
| 344 | goto out; |
| 345 | } |
| 346 | |
| 347 | if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_ETH) { |
| 348 | MLX4_GET(field, outbox, QUERY_FUNC_CAP_ETH_PROPS_OFFSET); |
| 349 | if (field & QUERY_FUNC_CAP_ETH_PROPS_FORCE_VLAN) { |
| 350 | mlx4_err(dev, "VLAN is enforced on this port\n"); |
| 351 | err = -EPROTONOSUPPORT; |
| 352 | goto out; |
| 353 | } |
| 354 | |
| 355 | if (field & QUERY_FUNC_CAP_ETH_PROPS_FORCE_MAC) { |
| 356 | mlx4_err(dev, "Force mac is enabled on this port\n"); |
| 357 | err = -EPROTONOSUPPORT; |
| 358 | goto out; |
| 359 | } |
| 360 | } else if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_IB) { |
| 361 | MLX4_GET(field, outbox, QUERY_FUNC_CAP_RDMA_PROPS_OFFSET); |
| 362 | if (field & QUERY_FUNC_CAP_RDMA_PROPS_FORCE_PHY_WQE_GID) { |
| 363 | mlx4_err(dev, "phy_wqe_gid is " |
| 364 | "enforced on this ib port\n"); |
| 365 | err = -EPROTONOSUPPORT; |
| 366 | goto out; |
| 367 | } |
| 368 | } |
| 369 | |
| 370 | MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET); |
| 371 | func_cap->physical_port = field; |
| 372 | if (func_cap->physical_port != gen_or_port) { |
| 373 | err = -ENOSYS; |
| 374 | goto out; |
| 375 | } |
| 376 | |
| 377 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_TUNNEL); |
| 378 | func_cap->qp0_tunnel_qpn = size & 0xFFFFFF; |
| 379 | |
| 380 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_PROXY); |
| 381 | func_cap->qp0_proxy_qpn = size & 0xFFFFFF; |
| 382 | |
| 383 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_TUNNEL); |
| 384 | func_cap->qp1_tunnel_qpn = size & 0xFFFFFF; |
| 385 | |
| 386 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_PROXY); |
| 387 | func_cap->qp1_proxy_qpn = size & 0xFFFFFF; |
| 388 | |
| 389 | /* All other resources are allocated by the master, but we still report |
| 390 | * 'num' and 'reserved' capabilities as follows: |
| 391 | * - num remains the maximum resource index |
| 392 | * - 'num - reserved' is the total available objects of a resource, but |
| 393 | * resource indices may be less than 'reserved' |
| 394 | * TODO: set per-resource quotas */ |
| 395 | |
| 396 | out: |
| 397 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 398 | |
| 399 | return err; |
| 400 | } |
| 401 | |
| 402 | int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) |
| 403 | { |
| 404 | struct mlx4_cmd_mailbox *mailbox; |
| 405 | u32 *outbox; |
| 406 | u8 field; |
| 407 | u32 field32, flags, ext_flags; |
| 408 | u16 size; |
| 409 | u16 stat_rate; |
| 410 | int err; |
| 411 | int i; |
| 412 | |
| 413 | #define QUERY_DEV_CAP_OUT_SIZE 0x100 |
| 414 | #define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10 |
| 415 | #define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11 |
| 416 | #define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12 |
| 417 | #define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13 |
| 418 | #define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14 |
| 419 | #define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15 |
| 420 | #define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16 |
| 421 | #define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17 |
| 422 | #define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19 |
| 423 | #define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a |
| 424 | #define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b |
| 425 | #define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d |
| 426 | #define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e |
| 427 | #define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f |
| 428 | #define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20 |
| 429 | #define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21 |
| 430 | #define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22 |
| 431 | #define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23 |
| 432 | #define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27 |
| 433 | #define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29 |
| 434 | #define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b |
| 435 | #define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d |
| 436 | #define QUERY_DEV_CAP_RSS_OFFSET 0x2e |
| 437 | #define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f |
| 438 | #define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33 |
| 439 | #define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35 |
| 440 | #define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36 |
| 441 | #define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37 |
| 442 | #define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38 |
| 443 | #define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b |
| 444 | #define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c |
| 445 | #define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f |
| 446 | #define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40 |
| 447 | #define QUERY_DEV_CAP_FLAGS_OFFSET 0x44 |
| 448 | #define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48 |
| 449 | #define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49 |
| 450 | #define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b |
| 451 | #define QUERY_DEV_CAP_BF_OFFSET 0x4c |
| 452 | #define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d |
| 453 | #define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e |
| 454 | #define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f |
| 455 | #define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51 |
| 456 | #define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52 |
| 457 | #define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55 |
| 458 | #define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56 |
| 459 | #define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61 |
| 460 | #define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62 |
| 461 | #define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63 |
| 462 | #define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64 |
| 463 | #define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65 |
| 464 | #define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66 |
| 465 | #define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67 |
| 466 | #define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68 |
| 467 | #define QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET 0x76 |
| 468 | #define QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET 0x77 |
| 469 | #define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80 |
| 470 | #define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82 |
| 471 | #define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84 |
| 472 | #define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86 |
| 473 | #define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88 |
| 474 | #define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a |
| 475 | #define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c |
| 476 | #define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e |
| 477 | #define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90 |
| 478 | #define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92 |
| 479 | #define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94 |
| 480 | #define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98 |
| 481 | #define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0 |
| 482 | #define QUERY_DEV_CAP_FW_REASSIGN_MAC 0x9d |
| 483 | |
| 484 | dev_cap->flags2 = 0; |
| 485 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 486 | if (IS_ERR(mailbox)) |
| 487 | return PTR_ERR(mailbox); |
| 488 | outbox = mailbox->buf; |
| 489 | |
| 490 | err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP, |
| 491 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
| 492 | if (err) |
| 493 | goto out; |
| 494 | |
| 495 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET); |
| 496 | dev_cap->reserved_qps = 1 << (field & 0xf); |
| 497 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET); |
| 498 | dev_cap->max_qps = 1 << (field & 0x1f); |
| 499 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET); |
| 500 | dev_cap->reserved_srqs = 1 << (field >> 4); |
| 501 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET); |
| 502 | dev_cap->max_srqs = 1 << (field & 0x1f); |
| 503 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET); |
| 504 | dev_cap->max_cq_sz = 1 << field; |
| 505 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET); |
| 506 | dev_cap->reserved_cqs = 1 << (field & 0xf); |
| 507 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET); |
| 508 | dev_cap->max_cqs = 1 << (field & 0x1f); |
| 509 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET); |
| 510 | dev_cap->max_mpts = 1 << (field & 0x3f); |
| 511 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET); |
| 512 | dev_cap->reserved_eqs = field & 0xf; |
| 513 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET); |
| 514 | dev_cap->max_eqs = 1 << (field & 0xf); |
| 515 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET); |
| 516 | dev_cap->reserved_mtts = 1 << (field >> 4); |
| 517 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET); |
| 518 | dev_cap->max_mrw_sz = 1 << field; |
| 519 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET); |
| 520 | dev_cap->reserved_mrws = 1 << (field & 0xf); |
| 521 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET); |
| 522 | dev_cap->max_mtt_seg = 1 << (field & 0x3f); |
| 523 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET); |
| 524 | dev_cap->max_requester_per_qp = 1 << (field & 0x3f); |
| 525 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET); |
| 526 | dev_cap->max_responder_per_qp = 1 << (field & 0x3f); |
| 527 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET); |
| 528 | field &= 0x1f; |
| 529 | if (!field) |
| 530 | dev_cap->max_gso_sz = 0; |
| 531 | else |
| 532 | dev_cap->max_gso_sz = 1 << field; |
| 533 | |
| 534 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSS_OFFSET); |
| 535 | if (field & 0x20) |
| 536 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_XOR; |
| 537 | if (field & 0x10) |
| 538 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_TOP; |
| 539 | field &= 0xf; |
| 540 | if (field) { |
| 541 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS; |
| 542 | dev_cap->max_rss_tbl_sz = 1 << field; |
| 543 | } else |
| 544 | dev_cap->max_rss_tbl_sz = 0; |
| 545 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET); |
| 546 | dev_cap->max_rdma_global = 1 << (field & 0x3f); |
| 547 | MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET); |
| 548 | dev_cap->local_ca_ack_delay = field & 0x1f; |
| 549 | MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET); |
| 550 | dev_cap->num_ports = field & 0xf; |
| 551 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET); |
| 552 | dev_cap->max_msg_sz = 1 << (field & 0x1f); |
| 553 | MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); |
| 554 | if (field & 0x80) |
| 555 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN; |
| 556 | dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f; |
| 557 | MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET); |
| 558 | dev_cap->fs_max_num_qp_per_entry = field; |
| 559 | MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET); |
| 560 | dev_cap->stat_rate_support = stat_rate; |
| 561 | MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); |
| 562 | MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET); |
| 563 | dev_cap->flags = flags | (u64)ext_flags << 32; |
| 564 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET); |
| 565 | dev_cap->reserved_uars = field >> 4; |
| 566 | MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET); |
| 567 | dev_cap->uar_size = 1 << ((field & 0x3f) + 20); |
| 568 | MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET); |
| 569 | dev_cap->min_page_sz = 1 << field; |
| 570 | |
| 571 | MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET); |
| 572 | if (field & 0x80) { |
| 573 | MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET); |
| 574 | dev_cap->bf_reg_size = 1 << (field & 0x1f); |
| 575 | MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET); |
| 576 | if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size)) |
| 577 | field = 3; |
| 578 | dev_cap->bf_regs_per_page = 1 << (field & 0x3f); |
| 579 | mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n", |
| 580 | dev_cap->bf_reg_size, dev_cap->bf_regs_per_page); |
| 581 | } else { |
| 582 | dev_cap->bf_reg_size = 0; |
| 583 | mlx4_dbg(dev, "BlueFlame not available\n"); |
| 584 | } |
| 585 | |
| 586 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET); |
| 587 | dev_cap->max_sq_sg = field; |
| 588 | MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET); |
| 589 | dev_cap->max_sq_desc_sz = size; |
| 590 | |
| 591 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET); |
| 592 | dev_cap->max_qp_per_mcg = 1 << field; |
| 593 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET); |
| 594 | dev_cap->reserved_mgms = field & 0xf; |
| 595 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET); |
| 596 | dev_cap->max_mcgs = 1 << field; |
| 597 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET); |
| 598 | dev_cap->reserved_pds = field >> 4; |
| 599 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET); |
| 600 | dev_cap->max_pds = 1 << (field & 0x3f); |
| 601 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET); |
| 602 | dev_cap->reserved_xrcds = field >> 4; |
| 603 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_XRC_OFFSET); |
| 604 | dev_cap->max_xrcds = 1 << (field & 0x1f); |
| 605 | |
| 606 | MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET); |
| 607 | dev_cap->rdmarc_entry_sz = size; |
| 608 | MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET); |
| 609 | dev_cap->qpc_entry_sz = size; |
| 610 | MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET); |
| 611 | dev_cap->aux_entry_sz = size; |
| 612 | MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET); |
| 613 | dev_cap->altc_entry_sz = size; |
| 614 | MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET); |
| 615 | dev_cap->eqc_entry_sz = size; |
| 616 | MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET); |
| 617 | dev_cap->cqc_entry_sz = size; |
| 618 | MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET); |
| 619 | dev_cap->srq_entry_sz = size; |
| 620 | MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET); |
| 621 | dev_cap->cmpt_entry_sz = size; |
| 622 | MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET); |
| 623 | dev_cap->mtt_entry_sz = size; |
| 624 | MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET); |
| 625 | dev_cap->dmpt_entry_sz = size; |
| 626 | |
| 627 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET); |
| 628 | dev_cap->max_srq_sz = 1 << field; |
| 629 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET); |
| 630 | dev_cap->max_qp_sz = 1 << field; |
| 631 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET); |
| 632 | dev_cap->resize_srq = field & 1; |
| 633 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET); |
| 634 | dev_cap->max_rq_sg = field; |
| 635 | MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET); |
| 636 | dev_cap->max_rq_desc_sz = size; |
| 637 | |
| 638 | MLX4_GET(dev_cap->bmme_flags, outbox, |
| 639 | QUERY_DEV_CAP_BMME_FLAGS_OFFSET); |
| 640 | MLX4_GET(dev_cap->reserved_lkey, outbox, |
| 641 | QUERY_DEV_CAP_RSVD_LKEY_OFFSET); |
| 642 | MLX4_GET(field, outbox, QUERY_DEV_CAP_FW_REASSIGN_MAC); |
| 643 | if (field & 1<<6) |
| 644 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAGS2_REASSIGN_MAC_EN; |
| 645 | MLX4_GET(dev_cap->max_icm_sz, outbox, |
| 646 | QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET); |
| 647 | if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS) |
| 648 | MLX4_GET(dev_cap->max_counters, outbox, |
| 649 | QUERY_DEV_CAP_MAX_COUNTERS_OFFSET); |
| 650 | |
| 651 | if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { |
| 652 | for (i = 1; i <= dev_cap->num_ports; ++i) { |
| 653 | MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET); |
| 654 | dev_cap->max_vl[i] = field >> 4; |
| 655 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET); |
| 656 | dev_cap->ib_mtu[i] = field >> 4; |
| 657 | dev_cap->max_port_width[i] = field & 0xf; |
| 658 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET); |
| 659 | dev_cap->max_gids[i] = 1 << (field & 0xf); |
| 660 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET); |
| 661 | dev_cap->max_pkeys[i] = 1 << (field & 0xf); |
| 662 | } |
| 663 | } else { |
| 664 | #define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00 |
| 665 | #define QUERY_PORT_MTU_OFFSET 0x01 |
| 666 | #define QUERY_PORT_ETH_MTU_OFFSET 0x02 |
| 667 | #define QUERY_PORT_WIDTH_OFFSET 0x06 |
| 668 | #define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07 |
| 669 | #define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a |
| 670 | #define QUERY_PORT_MAX_VL_OFFSET 0x0b |
| 671 | #define QUERY_PORT_MAC_OFFSET 0x10 |
| 672 | #define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18 |
| 673 | #define QUERY_PORT_WAVELENGTH_OFFSET 0x1c |
| 674 | #define QUERY_PORT_TRANS_CODE_OFFSET 0x20 |
| 675 | |
| 676 | for (i = 1; i <= dev_cap->num_ports; ++i) { |
| 677 | err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT, |
| 678 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); |
| 679 | if (err) |
| 680 | goto out; |
| 681 | |
| 682 | MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET); |
| 683 | dev_cap->supported_port_types[i] = field & 3; |
| 684 | dev_cap->suggested_type[i] = (field >> 3) & 1; |
| 685 | dev_cap->default_sense[i] = (field >> 4) & 1; |
| 686 | MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET); |
| 687 | dev_cap->ib_mtu[i] = field & 0xf; |
| 688 | MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET); |
| 689 | dev_cap->max_port_width[i] = field & 0xf; |
| 690 | MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET); |
| 691 | dev_cap->max_gids[i] = 1 << (field >> 4); |
| 692 | dev_cap->max_pkeys[i] = 1 << (field & 0xf); |
| 693 | MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET); |
| 694 | dev_cap->max_vl[i] = field & 0xf; |
| 695 | MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET); |
| 696 | dev_cap->log_max_macs[i] = field & 0xf; |
| 697 | dev_cap->log_max_vlans[i] = field >> 4; |
| 698 | MLX4_GET(dev_cap->eth_mtu[i], outbox, QUERY_PORT_ETH_MTU_OFFSET); |
| 699 | MLX4_GET(dev_cap->def_mac[i], outbox, QUERY_PORT_MAC_OFFSET); |
| 700 | MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET); |
| 701 | dev_cap->trans_type[i] = field32 >> 24; |
| 702 | dev_cap->vendor_oui[i] = field32 & 0xffffff; |
| 703 | MLX4_GET(dev_cap->wavelength[i], outbox, QUERY_PORT_WAVELENGTH_OFFSET); |
| 704 | MLX4_GET(dev_cap->trans_code[i], outbox, QUERY_PORT_TRANS_CODE_OFFSET); |
| 705 | } |
| 706 | } |
| 707 | |
| 708 | mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n", |
| 709 | dev_cap->bmme_flags, dev_cap->reserved_lkey); |
| 710 | |
| 711 | /* |
| 712 | * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then |
| 713 | * we can't use any EQs whose doorbell falls on that page, |
| 714 | * even if the EQ itself isn't reserved. |
| 715 | */ |
| 716 | dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4, |
| 717 | dev_cap->reserved_eqs); |
| 718 | |
| 719 | mlx4_dbg(dev, "Max ICM size %lld MB\n", |
| 720 | (unsigned long long) dev_cap->max_icm_sz >> 20); |
| 721 | mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n", |
| 722 | dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz); |
| 723 | mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n", |
| 724 | dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz); |
| 725 | mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n", |
| 726 | dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz); |
| 727 | mlx4_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n", |
| 728 | dev_cap->max_eqs, dev_cap->reserved_eqs, dev_cap->eqc_entry_sz); |
| 729 | mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n", |
| 730 | dev_cap->reserved_mrws, dev_cap->reserved_mtts); |
| 731 | mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n", |
| 732 | dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars); |
| 733 | mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n", |
| 734 | dev_cap->max_pds, dev_cap->reserved_mgms); |
| 735 | mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n", |
| 736 | dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz); |
| 737 | mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n", |
| 738 | dev_cap->local_ca_ack_delay, 128 << dev_cap->ib_mtu[1], |
| 739 | dev_cap->max_port_width[1]); |
| 740 | mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n", |
| 741 | dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg); |
| 742 | mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n", |
| 743 | dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg); |
| 744 | mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz); |
| 745 | mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters); |
| 746 | mlx4_dbg(dev, "Max RSS Table size: %d\n", dev_cap->max_rss_tbl_sz); |
| 747 | |
| 748 | dump_dev_cap_flags(dev, dev_cap->flags); |
| 749 | dump_dev_cap_flags2(dev, dev_cap->flags2); |
| 750 | |
| 751 | out: |
| 752 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 753 | return err; |
| 754 | } |
| 755 | |
| 756 | int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave, |
| 757 | struct mlx4_vhcr *vhcr, |
| 758 | struct mlx4_cmd_mailbox *inbox, |
| 759 | struct mlx4_cmd_mailbox *outbox, |
| 760 | struct mlx4_cmd_info *cmd) |
| 761 | { |
| 762 | u64 flags; |
| 763 | int err = 0; |
| 764 | u8 field; |
| 765 | u32 bmme_flags; |
| 766 | |
| 767 | err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP, |
| 768 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
| 769 | if (err) |
| 770 | return err; |
| 771 | |
| 772 | /* add port mng change event capability and disable mw type 1 |
| 773 | * unconditionally to slaves |
| 774 | */ |
| 775 | MLX4_GET(flags, outbox->buf, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); |
| 776 | flags |= MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV; |
| 777 | flags &= ~MLX4_DEV_CAP_FLAG_MEM_WINDOW; |
| 778 | MLX4_PUT(outbox->buf, flags, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); |
| 779 | |
| 780 | /* For guests, report Blueflame disabled */ |
| 781 | MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_BF_OFFSET); |
| 782 | field &= 0x7f; |
| 783 | MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_BF_OFFSET); |
| 784 | |
| 785 | /* For guests, disable mw type 2 */ |
| 786 | MLX4_GET(bmme_flags, outbox, QUERY_DEV_CAP_BMME_FLAGS_OFFSET); |
| 787 | bmme_flags &= ~MLX4_BMME_FLAG_TYPE_2_WIN; |
| 788 | MLX4_PUT(outbox->buf, bmme_flags, QUERY_DEV_CAP_BMME_FLAGS_OFFSET); |
| 789 | |
| 790 | return 0; |
| 791 | } |
| 792 | |
| 793 | int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave, |
| 794 | struct mlx4_vhcr *vhcr, |
| 795 | struct mlx4_cmd_mailbox *inbox, |
| 796 | struct mlx4_cmd_mailbox *outbox, |
| 797 | struct mlx4_cmd_info *cmd) |
| 798 | { |
| 799 | u64 def_mac; |
| 800 | u8 port_type; |
| 801 | u16 short_field; |
| 802 | int err; |
| 803 | |
| 804 | #define MLX4_VF_PORT_NO_LINK_SENSE_MASK 0xE0 |
| 805 | #define QUERY_PORT_CUR_MAX_PKEY_OFFSET 0x0c |
| 806 | #define QUERY_PORT_CUR_MAX_GID_OFFSET 0x0e |
| 807 | |
| 808 | err = mlx4_cmd_box(dev, 0, outbox->dma, vhcr->in_modifier, 0, |
| 809 | MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B, |
| 810 | MLX4_CMD_NATIVE); |
| 811 | |
| 812 | if (!err && dev->caps.function != slave) { |
| 813 | /* set slave default_mac address */ |
| 814 | MLX4_GET(def_mac, outbox->buf, QUERY_PORT_MAC_OFFSET); |
| 815 | def_mac += slave << 8; |
| 816 | MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET); |
| 817 | |
| 818 | /* get port type - currently only eth is enabled */ |
| 819 | MLX4_GET(port_type, outbox->buf, |
| 820 | QUERY_PORT_SUPPORTED_TYPE_OFFSET); |
| 821 | |
| 822 | /* No link sensing allowed */ |
| 823 | port_type &= MLX4_VF_PORT_NO_LINK_SENSE_MASK; |
| 824 | /* set port type to currently operating port type */ |
| 825 | port_type |= (dev->caps.port_type[vhcr->in_modifier] & 0x3); |
| 826 | |
| 827 | MLX4_PUT(outbox->buf, port_type, |
| 828 | QUERY_PORT_SUPPORTED_TYPE_OFFSET); |
| 829 | |
| 830 | short_field = 1; /* slave max gids */ |
| 831 | MLX4_PUT(outbox->buf, short_field, |
| 832 | QUERY_PORT_CUR_MAX_GID_OFFSET); |
| 833 | |
| 834 | short_field = dev->caps.pkey_table_len[vhcr->in_modifier]; |
| 835 | MLX4_PUT(outbox->buf, short_field, |
| 836 | QUERY_PORT_CUR_MAX_PKEY_OFFSET); |
| 837 | } |
| 838 | |
| 839 | return err; |
| 840 | } |
| 841 | |
| 842 | int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port, |
| 843 | int *gid_tbl_len, int *pkey_tbl_len) |
| 844 | { |
| 845 | struct mlx4_cmd_mailbox *mailbox; |
| 846 | u32 *outbox; |
| 847 | u16 field; |
| 848 | int err; |
| 849 | |
| 850 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 851 | if (IS_ERR(mailbox)) |
| 852 | return PTR_ERR(mailbox); |
| 853 | |
| 854 | err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0, |
| 855 | MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B, |
| 856 | MLX4_CMD_WRAPPED); |
| 857 | if (err) |
| 858 | goto out; |
| 859 | |
| 860 | outbox = mailbox->buf; |
| 861 | |
| 862 | MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_GID_OFFSET); |
| 863 | *gid_tbl_len = field; |
| 864 | |
| 865 | MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_PKEY_OFFSET); |
| 866 | *pkey_tbl_len = field; |
| 867 | |
| 868 | out: |
| 869 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 870 | return err; |
| 871 | } |
| 872 | EXPORT_SYMBOL(mlx4_get_slave_pkey_gid_tbl_len); |
| 873 | |
| 874 | int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt) |
| 875 | { |
| 876 | struct mlx4_cmd_mailbox *mailbox; |
| 877 | struct mlx4_icm_iter iter; |
| 878 | __be64 *pages; |
| 879 | int lg; |
| 880 | int nent = 0; |
| 881 | int i; |
| 882 | int err = 0; |
| 883 | int ts = 0, tc = 0; |
| 884 | |
| 885 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 886 | if (IS_ERR(mailbox)) |
| 887 | return PTR_ERR(mailbox); |
| 888 | memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE); |
| 889 | pages = mailbox->buf; |
| 890 | |
| 891 | for (mlx4_icm_first(icm, &iter); |
| 892 | !mlx4_icm_last(&iter); |
| 893 | mlx4_icm_next(&iter)) { |
| 894 | /* |
| 895 | * We have to pass pages that are aligned to their |
| 896 | * size, so find the least significant 1 in the |
| 897 | * address or size and use that as our log2 size. |
| 898 | */ |
| 899 | lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1; |
| 900 | if (lg < MLX4_ICM_PAGE_SHIFT) { |
| 901 | mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n", |
| 902 | MLX4_ICM_PAGE_SIZE, |
| 903 | (unsigned long long) mlx4_icm_addr(&iter), |
| 904 | mlx4_icm_size(&iter)); |
| 905 | err = -EINVAL; |
| 906 | goto out; |
| 907 | } |
| 908 | |
| 909 | for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) { |
| 910 | if (virt != -1) { |
| 911 | pages[nent * 2] = cpu_to_be64(virt); |
| 912 | virt += 1 << lg; |
| 913 | } |
| 914 | |
| 915 | pages[nent * 2 + 1] = |
| 916 | cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) | |
| 917 | (lg - MLX4_ICM_PAGE_SHIFT)); |
| 918 | ts += 1 << (lg - 10); |
| 919 | ++tc; |
| 920 | |
| 921 | if (++nent == MLX4_MAILBOX_SIZE / 16) { |
| 922 | err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, |
| 923 | MLX4_CMD_TIME_CLASS_B, |
| 924 | MLX4_CMD_NATIVE); |
| 925 | if (err) |
| 926 | goto out; |
| 927 | nent = 0; |
| 928 | } |
| 929 | } |
| 930 | } |
| 931 | |
| 932 | if (nent) |
| 933 | err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, |
| 934 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); |
| 935 | if (err) |
| 936 | goto out; |
| 937 | |
| 938 | switch (op) { |
| 939 | case MLX4_CMD_MAP_FA: |
| 940 | mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts); |
| 941 | break; |
| 942 | case MLX4_CMD_MAP_ICM_AUX: |
| 943 | mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts); |
| 944 | break; |
| 945 | case MLX4_CMD_MAP_ICM: |
| 946 | mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n", |
| 947 | tc, ts, (unsigned long long) virt - (ts << 10)); |
| 948 | break; |
| 949 | } |
| 950 | |
| 951 | out: |
| 952 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 953 | return err; |
| 954 | } |
| 955 | |
| 956 | int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm) |
| 957 | { |
| 958 | return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1); |
| 959 | } |
| 960 | |
| 961 | int mlx4_UNMAP_FA(struct mlx4_dev *dev) |
| 962 | { |
| 963 | return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA, |
| 964 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); |
| 965 | } |
| 966 | |
| 967 | |
| 968 | int mlx4_RUN_FW(struct mlx4_dev *dev) |
| 969 | { |
| 970 | return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW, |
| 971 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
| 972 | } |
| 973 | |
| 974 | int mlx4_QUERY_FW(struct mlx4_dev *dev) |
| 975 | { |
| 976 | struct mlx4_fw *fw = &mlx4_priv(dev)->fw; |
| 977 | struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd; |
| 978 | struct mlx4_cmd_mailbox *mailbox; |
| 979 | u32 *outbox; |
| 980 | int err = 0; |
| 981 | u64 fw_ver; |
| 982 | u16 cmd_if_rev; |
| 983 | u8 lg; |
| 984 | |
| 985 | #define QUERY_FW_OUT_SIZE 0x100 |
| 986 | #define QUERY_FW_VER_OFFSET 0x00 |
| 987 | #define QUERY_FW_PPF_ID 0x09 |
| 988 | #define QUERY_FW_CMD_IF_REV_OFFSET 0x0a |
| 989 | #define QUERY_FW_MAX_CMD_OFFSET 0x0f |
| 990 | #define QUERY_FW_ERR_START_OFFSET 0x30 |
| 991 | #define QUERY_FW_ERR_SIZE_OFFSET 0x38 |
| 992 | #define QUERY_FW_ERR_BAR_OFFSET 0x3c |
| 993 | |
| 994 | #define QUERY_FW_SIZE_OFFSET 0x00 |
| 995 | #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20 |
| 996 | #define QUERY_FW_CLR_INT_BAR_OFFSET 0x28 |
| 997 | |
| 998 | #define QUERY_FW_COMM_BASE_OFFSET 0x40 |
| 999 | #define QUERY_FW_COMM_BAR_OFFSET 0x48 |
| 1000 | |
| 1001 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 1002 | if (IS_ERR(mailbox)) |
| 1003 | return PTR_ERR(mailbox); |
| 1004 | outbox = mailbox->buf; |
| 1005 | |
| 1006 | err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW, |
| 1007 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
| 1008 | if (err) |
| 1009 | goto out; |
| 1010 | |
| 1011 | MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET); |
| 1012 | /* |
| 1013 | * FW subminor version is at more significant bits than minor |
| 1014 | * version, so swap here. |
| 1015 | */ |
| 1016 | dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) | |
| 1017 | ((fw_ver & 0xffff0000ull) >> 16) | |
| 1018 | ((fw_ver & 0x0000ffffull) << 16); |
| 1019 | |
| 1020 | MLX4_GET(lg, outbox, QUERY_FW_PPF_ID); |
| 1021 | dev->caps.function = lg; |
| 1022 | |
| 1023 | if (mlx4_is_slave(dev)) |
| 1024 | goto out; |
| 1025 | |
| 1026 | |
| 1027 | MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET); |
| 1028 | if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV || |
| 1029 | cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) { |
| 1030 | mlx4_err(dev, "Installed FW has unsupported " |
| 1031 | "command interface revision %d.\n", |
| 1032 | cmd_if_rev); |
| 1033 | mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n", |
| 1034 | (int) (dev->caps.fw_ver >> 32), |
| 1035 | (int) (dev->caps.fw_ver >> 16) & 0xffff, |
| 1036 | (int) dev->caps.fw_ver & 0xffff); |
| 1037 | mlx4_err(dev, "This driver version supports only revisions %d to %d.\n", |
| 1038 | MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV); |
| 1039 | err = -ENODEV; |
| 1040 | goto out; |
| 1041 | } |
| 1042 | |
| 1043 | if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS) |
| 1044 | dev->flags |= MLX4_FLAG_OLD_PORT_CMDS; |
| 1045 | |
| 1046 | MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET); |
| 1047 | cmd->max_cmds = 1 << lg; |
| 1048 | |
| 1049 | mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n", |
| 1050 | (int) (dev->caps.fw_ver >> 32), |
| 1051 | (int) (dev->caps.fw_ver >> 16) & 0xffff, |
| 1052 | (int) dev->caps.fw_ver & 0xffff, |
| 1053 | cmd_if_rev, cmd->max_cmds); |
| 1054 | |
| 1055 | MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET); |
| 1056 | MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET); |
| 1057 | MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET); |
| 1058 | fw->catas_bar = (fw->catas_bar >> 6) * 2; |
| 1059 | |
| 1060 | mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n", |
| 1061 | (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar); |
| 1062 | |
| 1063 | MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET); |
| 1064 | MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET); |
| 1065 | MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET); |
| 1066 | fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2; |
| 1067 | |
| 1068 | MLX4_GET(fw->comm_base, outbox, QUERY_FW_COMM_BASE_OFFSET); |
| 1069 | MLX4_GET(fw->comm_bar, outbox, QUERY_FW_COMM_BAR_OFFSET); |
| 1070 | fw->comm_bar = (fw->comm_bar >> 6) * 2; |
| 1071 | mlx4_dbg(dev, "Communication vector bar:%d offset:0x%llx\n", |
| 1072 | fw->comm_bar, fw->comm_base); |
| 1073 | mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2); |
| 1074 | |
| 1075 | /* |
| 1076 | * Round up number of system pages needed in case |
| 1077 | * MLX4_ICM_PAGE_SIZE < PAGE_SIZE. |
| 1078 | */ |
| 1079 | fw->fw_pages = |
| 1080 | ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >> |
| 1081 | (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT); |
| 1082 | |
| 1083 | mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n", |
| 1084 | (unsigned long long) fw->clr_int_base, fw->clr_int_bar); |
| 1085 | |
| 1086 | out: |
| 1087 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 1088 | return err; |
| 1089 | } |
| 1090 | |
| 1091 | int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave, |
| 1092 | struct mlx4_vhcr *vhcr, |
| 1093 | struct mlx4_cmd_mailbox *inbox, |
| 1094 | struct mlx4_cmd_mailbox *outbox, |
| 1095 | struct mlx4_cmd_info *cmd) |
| 1096 | { |
| 1097 | u8 *outbuf; |
| 1098 | int err; |
| 1099 | |
| 1100 | outbuf = outbox->buf; |
| 1101 | err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_FW, |
| 1102 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
| 1103 | if (err) |
| 1104 | return err; |
| 1105 | |
| 1106 | /* for slaves, set pci PPF ID to invalid and zero out everything |
| 1107 | * else except FW version */ |
| 1108 | outbuf[0] = outbuf[1] = 0; |
| 1109 | memset(&outbuf[8], 0, QUERY_FW_OUT_SIZE - 8); |
| 1110 | outbuf[QUERY_FW_PPF_ID] = MLX4_INVALID_SLAVE_ID; |
| 1111 | |
| 1112 | return 0; |
| 1113 | } |
| 1114 | |
| 1115 | static void get_board_id(void *vsd, char *board_id) |
| 1116 | { |
| 1117 | int i; |
| 1118 | |
| 1119 | #define VSD_OFFSET_SIG1 0x00 |
| 1120 | #define VSD_OFFSET_SIG2 0xde |
| 1121 | #define VSD_OFFSET_MLX_BOARD_ID 0xd0 |
| 1122 | #define VSD_OFFSET_TS_BOARD_ID 0x20 |
| 1123 | |
| 1124 | #define VSD_SIGNATURE_TOPSPIN 0x5ad |
| 1125 | |
| 1126 | memset(board_id, 0, MLX4_BOARD_ID_LEN); |
| 1127 | |
| 1128 | if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN && |
| 1129 | be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) { |
| 1130 | strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN); |
| 1131 | } else { |
| 1132 | /* |
| 1133 | * The board ID is a string but the firmware byte |
| 1134 | * swaps each 4-byte word before passing it back to |
| 1135 | * us. Therefore we need to swab it before printing. |
| 1136 | */ |
| 1137 | for (i = 0; i < 4; ++i) |
| 1138 | ((u32 *) board_id)[i] = |
| 1139 | swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4)); |
| 1140 | } |
| 1141 | } |
| 1142 | |
| 1143 | int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter) |
| 1144 | { |
| 1145 | struct mlx4_cmd_mailbox *mailbox; |
| 1146 | u32 *outbox; |
| 1147 | int err; |
| 1148 | |
| 1149 | #define QUERY_ADAPTER_OUT_SIZE 0x100 |
| 1150 | #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10 |
| 1151 | #define QUERY_ADAPTER_VSD_OFFSET 0x20 |
| 1152 | |
| 1153 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 1154 | if (IS_ERR(mailbox)) |
| 1155 | return PTR_ERR(mailbox); |
| 1156 | outbox = mailbox->buf; |
| 1157 | |
| 1158 | err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER, |
| 1159 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
| 1160 | if (err) |
| 1161 | goto out; |
| 1162 | |
| 1163 | MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET); |
| 1164 | |
| 1165 | get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4, |
| 1166 | adapter->board_id); |
| 1167 | |
| 1168 | out: |
| 1169 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 1170 | return err; |
| 1171 | } |
| 1172 | |
| 1173 | int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param) |
| 1174 | { |
| 1175 | struct mlx4_cmd_mailbox *mailbox; |
| 1176 | __be32 *inbox; |
| 1177 | int err; |
| 1178 | |
| 1179 | #define INIT_HCA_IN_SIZE 0x200 |
| 1180 | #define INIT_HCA_VERSION_OFFSET 0x000 |
| 1181 | #define INIT_HCA_VERSION 2 |
| 1182 | #define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e |
| 1183 | #define INIT_HCA_FLAGS_OFFSET 0x014 |
| 1184 | #define INIT_HCA_QPC_OFFSET 0x020 |
| 1185 | #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10) |
| 1186 | #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17) |
| 1187 | #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28) |
| 1188 | #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f) |
| 1189 | #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30) |
| 1190 | #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37) |
| 1191 | #define INIT_HCA_EQE_CQE_OFFSETS (INIT_HCA_QPC_OFFSET + 0x38) |
| 1192 | #define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40) |
| 1193 | #define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50) |
| 1194 | #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60) |
| 1195 | #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67) |
| 1196 | #define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70) |
| 1197 | #define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77) |
| 1198 | #define INIT_HCA_MCAST_OFFSET 0x0c0 |
| 1199 | #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00) |
| 1200 | #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12) |
| 1201 | #define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16) |
| 1202 | #define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18) |
| 1203 | #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b) |
| 1204 | #define INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN 0x6 |
| 1205 | #define INIT_HCA_FS_PARAM_OFFSET 0x1d0 |
| 1206 | #define INIT_HCA_FS_BASE_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x00) |
| 1207 | #define INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x12) |
| 1208 | #define INIT_HCA_FS_LOG_TABLE_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x1b) |
| 1209 | #define INIT_HCA_FS_ETH_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x21) |
| 1210 | #define INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x22) |
| 1211 | #define INIT_HCA_FS_IB_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x25) |
| 1212 | #define INIT_HCA_FS_IB_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x26) |
| 1213 | #define INIT_HCA_TPT_OFFSET 0x0f0 |
| 1214 | #define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00) |
| 1215 | #define INIT_HCA_TPT_MW_OFFSET (INIT_HCA_TPT_OFFSET + 0x08) |
| 1216 | #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b) |
| 1217 | #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10) |
| 1218 | #define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18) |
| 1219 | #define INIT_HCA_UAR_OFFSET 0x120 |
| 1220 | #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a) |
| 1221 | #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b) |
| 1222 | |
| 1223 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 1224 | if (IS_ERR(mailbox)) |
| 1225 | return PTR_ERR(mailbox); |
| 1226 | inbox = mailbox->buf; |
| 1227 | |
| 1228 | memset(inbox, 0, INIT_HCA_IN_SIZE); |
| 1229 | |
| 1230 | *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION; |
| 1231 | |
| 1232 | *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) = |
| 1233 | (ilog2(cache_line_size()) - 4) << 5; |
| 1234 | |
| 1235 | #if defined(__LITTLE_ENDIAN) |
| 1236 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1); |
| 1237 | #elif defined(__BIG_ENDIAN) |
| 1238 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1); |
| 1239 | #else |
| 1240 | #error Host endianness not defined |
| 1241 | #endif |
| 1242 | /* Check port for UD address vector: */ |
| 1243 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1); |
| 1244 | |
| 1245 | /* Enable IPoIB checksumming if we can: */ |
| 1246 | if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM) |
| 1247 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3); |
| 1248 | |
| 1249 | /* Enable QoS support if module parameter set */ |
| 1250 | if (enable_qos) |
| 1251 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2); |
| 1252 | |
| 1253 | /* enable counters */ |
| 1254 | if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS) |
| 1255 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4); |
| 1256 | |
| 1257 | /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */ |
| 1258 | if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_EQE) { |
| 1259 | *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 29); |
| 1260 | dev->caps.eqe_size = 64; |
| 1261 | dev->caps.eqe_factor = 1; |
| 1262 | } else { |
| 1263 | dev->caps.eqe_size = 32; |
| 1264 | dev->caps.eqe_factor = 0; |
| 1265 | } |
| 1266 | |
| 1267 | if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_CQE) { |
| 1268 | *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 30); |
| 1269 | dev->caps.cqe_size = 64; |
| 1270 | dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_64B_CQE; |
| 1271 | } else { |
| 1272 | dev->caps.cqe_size = 32; |
| 1273 | } |
| 1274 | |
| 1275 | /* QPC/EEC/CQC/EQC/RDMARC attributes */ |
| 1276 | |
| 1277 | MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET); |
| 1278 | MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET); |
| 1279 | MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET); |
| 1280 | MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET); |
| 1281 | MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET); |
| 1282 | MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET); |
| 1283 | MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET); |
| 1284 | MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET); |
| 1285 | MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET); |
| 1286 | MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET); |
| 1287 | MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET); |
| 1288 | MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET); |
| 1289 | |
| 1290 | /* steering attributes */ |
| 1291 | if (dev->caps.steering_mode == |
| 1292 | MLX4_STEERING_MODE_DEVICE_MANAGED) { |
| 1293 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= |
| 1294 | cpu_to_be32(1 << |
| 1295 | INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN); |
| 1296 | |
| 1297 | MLX4_PUT(inbox, param->mc_base, INIT_HCA_FS_BASE_OFFSET); |
| 1298 | MLX4_PUT(inbox, param->log_mc_entry_sz, |
| 1299 | INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET); |
| 1300 | MLX4_PUT(inbox, param->log_mc_table_sz, |
| 1301 | INIT_HCA_FS_LOG_TABLE_SZ_OFFSET); |
| 1302 | /* Enable Ethernet flow steering |
| 1303 | * with udp unicast and tcp unicast |
| 1304 | */ |
| 1305 | MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN), |
| 1306 | INIT_HCA_FS_ETH_BITS_OFFSET); |
| 1307 | MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR, |
| 1308 | INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET); |
| 1309 | /* Enable IPoIB flow steering |
| 1310 | * with udp unicast and tcp unicast |
| 1311 | */ |
| 1312 | MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN), |
| 1313 | INIT_HCA_FS_IB_BITS_OFFSET); |
| 1314 | MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR, |
| 1315 | INIT_HCA_FS_IB_NUM_ADDRS_OFFSET); |
| 1316 | } else { |
| 1317 | MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET); |
| 1318 | MLX4_PUT(inbox, param->log_mc_entry_sz, |
| 1319 | INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET); |
| 1320 | MLX4_PUT(inbox, param->log_mc_hash_sz, |
| 1321 | INIT_HCA_LOG_MC_HASH_SZ_OFFSET); |
| 1322 | MLX4_PUT(inbox, param->log_mc_table_sz, |
| 1323 | INIT_HCA_LOG_MC_TABLE_SZ_OFFSET); |
| 1324 | if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0) |
| 1325 | MLX4_PUT(inbox, (u8) (1 << 3), |
| 1326 | INIT_HCA_UC_STEERING_OFFSET); |
| 1327 | } |
| 1328 | |
| 1329 | /* TPT attributes */ |
| 1330 | |
| 1331 | MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET); |
| 1332 | MLX4_PUT(inbox, param->mw_enabled, INIT_HCA_TPT_MW_OFFSET); |
| 1333 | MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET); |
| 1334 | MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET); |
| 1335 | MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET); |
| 1336 | |
| 1337 | /* UAR attributes */ |
| 1338 | |
| 1339 | MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET); |
| 1340 | MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET); |
| 1341 | |
| 1342 | err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000, |
| 1343 | MLX4_CMD_NATIVE); |
| 1344 | |
| 1345 | if (err) |
| 1346 | mlx4_err(dev, "INIT_HCA returns %d\n", err); |
| 1347 | |
| 1348 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 1349 | return err; |
| 1350 | } |
| 1351 | |
| 1352 | int mlx4_QUERY_HCA(struct mlx4_dev *dev, |
| 1353 | struct mlx4_init_hca_param *param) |
| 1354 | { |
| 1355 | struct mlx4_cmd_mailbox *mailbox; |
| 1356 | __be32 *outbox; |
| 1357 | u32 dword_field; |
| 1358 | int err; |
| 1359 | u8 byte_field; |
| 1360 | |
| 1361 | #define QUERY_HCA_GLOBAL_CAPS_OFFSET 0x04 |
| 1362 | |
| 1363 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 1364 | if (IS_ERR(mailbox)) |
| 1365 | return PTR_ERR(mailbox); |
| 1366 | outbox = mailbox->buf; |
| 1367 | |
| 1368 | err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, |
| 1369 | MLX4_CMD_QUERY_HCA, |
| 1370 | MLX4_CMD_TIME_CLASS_B, |
| 1371 | !mlx4_is_slave(dev)); |
| 1372 | if (err) |
| 1373 | goto out; |
| 1374 | |
| 1375 | MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET); |
| 1376 | |
| 1377 | /* QPC/EEC/CQC/EQC/RDMARC attributes */ |
| 1378 | |
| 1379 | MLX4_GET(param->qpc_base, outbox, INIT_HCA_QPC_BASE_OFFSET); |
| 1380 | MLX4_GET(param->log_num_qps, outbox, INIT_HCA_LOG_QP_OFFSET); |
| 1381 | MLX4_GET(param->srqc_base, outbox, INIT_HCA_SRQC_BASE_OFFSET); |
| 1382 | MLX4_GET(param->log_num_srqs, outbox, INIT_HCA_LOG_SRQ_OFFSET); |
| 1383 | MLX4_GET(param->cqc_base, outbox, INIT_HCA_CQC_BASE_OFFSET); |
| 1384 | MLX4_GET(param->log_num_cqs, outbox, INIT_HCA_LOG_CQ_OFFSET); |
| 1385 | MLX4_GET(param->altc_base, outbox, INIT_HCA_ALTC_BASE_OFFSET); |
| 1386 | MLX4_GET(param->auxc_base, outbox, INIT_HCA_AUXC_BASE_OFFSET); |
| 1387 | MLX4_GET(param->eqc_base, outbox, INIT_HCA_EQC_BASE_OFFSET); |
| 1388 | MLX4_GET(param->log_num_eqs, outbox, INIT_HCA_LOG_EQ_OFFSET); |
| 1389 | MLX4_GET(param->rdmarc_base, outbox, INIT_HCA_RDMARC_BASE_OFFSET); |
| 1390 | MLX4_GET(param->log_rd_per_qp, outbox, INIT_HCA_LOG_RD_OFFSET); |
| 1391 | |
| 1392 | MLX4_GET(dword_field, outbox, INIT_HCA_FLAGS_OFFSET); |
| 1393 | if (dword_field & (1 << INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN)) { |
| 1394 | param->steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED; |
| 1395 | } else { |
| 1396 | MLX4_GET(byte_field, outbox, INIT_HCA_UC_STEERING_OFFSET); |
| 1397 | if (byte_field & 0x8) |
| 1398 | param->steering_mode = MLX4_STEERING_MODE_B0; |
| 1399 | else |
| 1400 | param->steering_mode = MLX4_STEERING_MODE_A0; |
| 1401 | } |
| 1402 | /* steering attributes */ |
| 1403 | if (param->steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) { |
| 1404 | MLX4_GET(param->mc_base, outbox, INIT_HCA_FS_BASE_OFFSET); |
| 1405 | MLX4_GET(param->log_mc_entry_sz, outbox, |
| 1406 | INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET); |
| 1407 | MLX4_GET(param->log_mc_table_sz, outbox, |
| 1408 | INIT_HCA_FS_LOG_TABLE_SZ_OFFSET); |
| 1409 | } else { |
| 1410 | MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET); |
| 1411 | MLX4_GET(param->log_mc_entry_sz, outbox, |
| 1412 | INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET); |
| 1413 | MLX4_GET(param->log_mc_hash_sz, outbox, |
| 1414 | INIT_HCA_LOG_MC_HASH_SZ_OFFSET); |
| 1415 | MLX4_GET(param->log_mc_table_sz, outbox, |
| 1416 | INIT_HCA_LOG_MC_TABLE_SZ_OFFSET); |
| 1417 | } |
| 1418 | |
| 1419 | /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */ |
| 1420 | MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_OFFSETS); |
| 1421 | if (byte_field & 0x20) /* 64-bytes eqe enabled */ |
| 1422 | param->dev_cap_enabled |= MLX4_DEV_CAP_64B_EQE_ENABLED; |
| 1423 | if (byte_field & 0x40) /* 64-bytes cqe enabled */ |
| 1424 | param->dev_cap_enabled |= MLX4_DEV_CAP_64B_CQE_ENABLED; |
| 1425 | |
| 1426 | /* TPT attributes */ |
| 1427 | |
| 1428 | MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET); |
| 1429 | MLX4_GET(param->mw_enabled, outbox, INIT_HCA_TPT_MW_OFFSET); |
| 1430 | MLX4_GET(param->log_mpt_sz, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET); |
| 1431 | MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET); |
| 1432 | MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET); |
| 1433 | |
| 1434 | /* UAR attributes */ |
| 1435 | |
| 1436 | MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET); |
| 1437 | MLX4_GET(param->log_uar_sz, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET); |
| 1438 | |
| 1439 | out: |
| 1440 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 1441 | |
| 1442 | return err; |
| 1443 | } |
| 1444 | |
| 1445 | /* for IB-type ports only in SRIOV mode. Checks that both proxy QP0 |
| 1446 | * and real QP0 are active, so that the paravirtualized QP0 is ready |
| 1447 | * to operate */ |
| 1448 | static int check_qp0_state(struct mlx4_dev *dev, int function, int port) |
| 1449 | { |
| 1450 | struct mlx4_priv *priv = mlx4_priv(dev); |
| 1451 | /* irrelevant if not infiniband */ |
| 1452 | if (priv->mfunc.master.qp0_state[port].proxy_qp0_active && |
| 1453 | priv->mfunc.master.qp0_state[port].qp0_active) |
| 1454 | return 1; |
| 1455 | return 0; |
| 1456 | } |
| 1457 | |
| 1458 | int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave, |
| 1459 | struct mlx4_vhcr *vhcr, |
| 1460 | struct mlx4_cmd_mailbox *inbox, |
| 1461 | struct mlx4_cmd_mailbox *outbox, |
| 1462 | struct mlx4_cmd_info *cmd) |
| 1463 | { |
| 1464 | struct mlx4_priv *priv = mlx4_priv(dev); |
| 1465 | int port = vhcr->in_modifier; |
| 1466 | int err; |
| 1467 | |
| 1468 | if (priv->mfunc.master.slave_state[slave].init_port_mask & (1 << port)) |
| 1469 | return 0; |
| 1470 | |
| 1471 | if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) { |
| 1472 | /* Enable port only if it was previously disabled */ |
| 1473 | if (!priv->mfunc.master.init_port_ref[port]) { |
| 1474 | err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, |
| 1475 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
| 1476 | if (err) |
| 1477 | return err; |
| 1478 | } |
| 1479 | priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); |
| 1480 | } else { |
| 1481 | if (slave == mlx4_master_func_num(dev)) { |
| 1482 | if (check_qp0_state(dev, slave, port) && |
| 1483 | !priv->mfunc.master.qp0_state[port].port_active) { |
| 1484 | err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, |
| 1485 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
| 1486 | if (err) |
| 1487 | return err; |
| 1488 | priv->mfunc.master.qp0_state[port].port_active = 1; |
| 1489 | priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); |
| 1490 | } |
| 1491 | } else |
| 1492 | priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); |
| 1493 | } |
| 1494 | ++priv->mfunc.master.init_port_ref[port]; |
| 1495 | return 0; |
| 1496 | } |
| 1497 | |
| 1498 | int mlx4_INIT_PORT(struct mlx4_dev *dev, int port) |
| 1499 | { |
| 1500 | struct mlx4_cmd_mailbox *mailbox; |
| 1501 | u32 *inbox; |
| 1502 | int err; |
| 1503 | u32 flags; |
| 1504 | u16 field; |
| 1505 | |
| 1506 | if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { |
| 1507 | #define INIT_PORT_IN_SIZE 256 |
| 1508 | #define INIT_PORT_FLAGS_OFFSET 0x00 |
| 1509 | #define INIT_PORT_FLAG_SIG (1 << 18) |
| 1510 | #define INIT_PORT_FLAG_NG (1 << 17) |
| 1511 | #define INIT_PORT_FLAG_G0 (1 << 16) |
| 1512 | #define INIT_PORT_VL_SHIFT 4 |
| 1513 | #define INIT_PORT_PORT_WIDTH_SHIFT 8 |
| 1514 | #define INIT_PORT_MTU_OFFSET 0x04 |
| 1515 | #define INIT_PORT_MAX_GID_OFFSET 0x06 |
| 1516 | #define INIT_PORT_MAX_PKEY_OFFSET 0x0a |
| 1517 | #define INIT_PORT_GUID0_OFFSET 0x10 |
| 1518 | #define INIT_PORT_NODE_GUID_OFFSET 0x18 |
| 1519 | #define INIT_PORT_SI_GUID_OFFSET 0x20 |
| 1520 | |
| 1521 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 1522 | if (IS_ERR(mailbox)) |
| 1523 | return PTR_ERR(mailbox); |
| 1524 | inbox = mailbox->buf; |
| 1525 | |
| 1526 | memset(inbox, 0, INIT_PORT_IN_SIZE); |
| 1527 | |
| 1528 | flags = 0; |
| 1529 | flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT; |
| 1530 | flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT; |
| 1531 | MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET); |
| 1532 | |
| 1533 | field = 128 << dev->caps.ib_mtu_cap[port]; |
| 1534 | MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET); |
| 1535 | field = dev->caps.gid_table_len[port]; |
| 1536 | MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET); |
| 1537 | field = dev->caps.pkey_table_len[port]; |
| 1538 | MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET); |
| 1539 | |
| 1540 | err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT, |
| 1541 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
| 1542 | |
| 1543 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 1544 | } else |
| 1545 | err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, |
| 1546 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); |
| 1547 | |
| 1548 | return err; |
| 1549 | } |
| 1550 | EXPORT_SYMBOL_GPL(mlx4_INIT_PORT); |
| 1551 | |
| 1552 | int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave, |
| 1553 | struct mlx4_vhcr *vhcr, |
| 1554 | struct mlx4_cmd_mailbox *inbox, |
| 1555 | struct mlx4_cmd_mailbox *outbox, |
| 1556 | struct mlx4_cmd_info *cmd) |
| 1557 | { |
| 1558 | struct mlx4_priv *priv = mlx4_priv(dev); |
| 1559 | int port = vhcr->in_modifier; |
| 1560 | int err; |
| 1561 | |
| 1562 | if (!(priv->mfunc.master.slave_state[slave].init_port_mask & |
| 1563 | (1 << port))) |
| 1564 | return 0; |
| 1565 | |
| 1566 | if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) { |
| 1567 | if (priv->mfunc.master.init_port_ref[port] == 1) { |
| 1568 | err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, |
| 1569 | 1000, MLX4_CMD_NATIVE); |
| 1570 | if (err) |
| 1571 | return err; |
| 1572 | } |
| 1573 | priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); |
| 1574 | } else { |
| 1575 | /* infiniband port */ |
| 1576 | if (slave == mlx4_master_func_num(dev)) { |
| 1577 | if (!priv->mfunc.master.qp0_state[port].qp0_active && |
| 1578 | priv->mfunc.master.qp0_state[port].port_active) { |
| 1579 | err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, |
| 1580 | 1000, MLX4_CMD_NATIVE); |
| 1581 | if (err) |
| 1582 | return err; |
| 1583 | priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); |
| 1584 | priv->mfunc.master.qp0_state[port].port_active = 0; |
| 1585 | } |
| 1586 | } else |
| 1587 | priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); |
| 1588 | } |
| 1589 | --priv->mfunc.master.init_port_ref[port]; |
| 1590 | return 0; |
| 1591 | } |
| 1592 | |
| 1593 | int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port) |
| 1594 | { |
| 1595 | return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000, |
| 1596 | MLX4_CMD_WRAPPED); |
| 1597 | } |
| 1598 | EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT); |
| 1599 | |
| 1600 | int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic) |
| 1601 | { |
| 1602 | return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000, |
| 1603 | MLX4_CMD_NATIVE); |
| 1604 | } |
| 1605 | |
| 1606 | int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages) |
| 1607 | { |
| 1608 | int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0, |
| 1609 | MLX4_CMD_SET_ICM_SIZE, |
| 1610 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
| 1611 | if (ret) |
| 1612 | return ret; |
| 1613 | |
| 1614 | /* |
| 1615 | * Round up number of system pages needed in case |
| 1616 | * MLX4_ICM_PAGE_SIZE < PAGE_SIZE. |
| 1617 | */ |
| 1618 | *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >> |
| 1619 | (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT); |
| 1620 | |
| 1621 | return 0; |
| 1622 | } |
| 1623 | |
| 1624 | int mlx4_NOP(struct mlx4_dev *dev) |
| 1625 | { |
| 1626 | /* Input modifier of 0x1f means "finish as soon as possible." */ |
| 1627 | return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100, MLX4_CMD_NATIVE); |
| 1628 | } |
| 1629 | |
| 1630 | #define MLX4_WOL_SETUP_MODE (5 << 28) |
| 1631 | int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port) |
| 1632 | { |
| 1633 | u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8; |
| 1634 | |
| 1635 | return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3, |
| 1636 | MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A, |
| 1637 | MLX4_CMD_NATIVE); |
| 1638 | } |
| 1639 | EXPORT_SYMBOL_GPL(mlx4_wol_read); |
| 1640 | |
| 1641 | int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port) |
| 1642 | { |
| 1643 | u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8; |
| 1644 | |
| 1645 | return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG, |
| 1646 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
| 1647 | } |
| 1648 | EXPORT_SYMBOL_GPL(mlx4_wol_write); |