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Merge branches 'acpi-resources', 'acpi-battery', 'acpi-doc' and 'acpi-pnp'
[linux-2.6-block.git] / drivers / net / ethernet / freescale / fec_main.c
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1/*
2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 *
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
10 * small packets.
11 *
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
14 *
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
17 *
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
20 *
21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
22 */
23
24#include <linux/module.h>
25#include <linux/kernel.h>
26#include <linux/string.h>
27#include <linux/ptrace.h>
28#include <linux/errno.h>
29#include <linux/ioport.h>
30#include <linux/slab.h>
31#include <linux/interrupt.h>
32#include <linux/delay.h>
33#include <linux/netdevice.h>
34#include <linux/etherdevice.h>
35#include <linux/skbuff.h>
36#include <linux/in.h>
37#include <linux/ip.h>
38#include <net/ip.h>
39#include <net/tso.h>
40#include <linux/tcp.h>
41#include <linux/udp.h>
42#include <linux/icmp.h>
43#include <linux/spinlock.h>
44#include <linux/workqueue.h>
45#include <linux/bitops.h>
46#include <linux/io.h>
47#include <linux/irq.h>
48#include <linux/clk.h>
49#include <linux/platform_device.h>
50#include <linux/phy.h>
51#include <linux/fec.h>
52#include <linux/of.h>
53#include <linux/of_device.h>
54#include <linux/of_gpio.h>
55#include <linux/of_mdio.h>
56#include <linux/of_net.h>
57#include <linux/regulator/consumer.h>
58#include <linux/if_vlan.h>
59#include <linux/pinctrl/consumer.h>
60#include <linux/prefetch.h>
61
62#include <asm/cacheflush.h>
63
64#include "fec.h"
65
66static void set_multicast_list(struct net_device *ndev);
67static void fec_enet_itr_coal_init(struct net_device *ndev);
68
69#define DRIVER_NAME "fec"
70
71#define FEC_ENET_GET_QUQUE(_x) ((_x == 0) ? 1 : ((_x == 1) ? 2 : 0))
72
73/* Pause frame feild and FIFO threshold */
74#define FEC_ENET_FCE (1 << 5)
75#define FEC_ENET_RSEM_V 0x84
76#define FEC_ENET_RSFL_V 16
77#define FEC_ENET_RAEM_V 0x8
78#define FEC_ENET_RAFL_V 0x8
79#define FEC_ENET_OPD_V 0xFFF0
80
81static struct platform_device_id fec_devtype[] = {
82 {
83 /* keep it for coldfire */
84 .name = DRIVER_NAME,
85 .driver_data = 0,
86 }, {
87 .name = "imx25-fec",
88 .driver_data = FEC_QUIRK_USE_GASKET,
89 }, {
90 .name = "imx27-fec",
91 .driver_data = 0,
92 }, {
93 .name = "imx28-fec",
94 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME |
95 FEC_QUIRK_SINGLE_MDIO,
96 }, {
97 .name = "imx6q-fec",
98 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
99 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
100 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358,
101 }, {
102 .name = "mvf600-fec",
103 .driver_data = FEC_QUIRK_ENET_MAC,
104 }, {
105 .name = "imx6sx-fec",
106 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
107 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
108 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
109 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE,
110 }, {
111 /* sentinel */
112 }
113};
114MODULE_DEVICE_TABLE(platform, fec_devtype);
115
116enum imx_fec_type {
117 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
118 IMX27_FEC, /* runs on i.mx27/35/51 */
119 IMX28_FEC,
120 IMX6Q_FEC,
121 MVF600_FEC,
122 IMX6SX_FEC,
123};
124
125static const struct of_device_id fec_dt_ids[] = {
126 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
127 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
128 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
129 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
130 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
131 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], },
132 { /* sentinel */ }
133};
134MODULE_DEVICE_TABLE(of, fec_dt_ids);
135
136static unsigned char macaddr[ETH_ALEN];
137module_param_array(macaddr, byte, NULL, 0);
138MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
139
140#if defined(CONFIG_M5272)
141/*
142 * Some hardware gets it MAC address out of local flash memory.
143 * if this is non-zero then assume it is the address to get MAC from.
144 */
145#if defined(CONFIG_NETtel)
146#define FEC_FLASHMAC 0xf0006006
147#elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
148#define FEC_FLASHMAC 0xf0006000
149#elif defined(CONFIG_CANCam)
150#define FEC_FLASHMAC 0xf0020000
151#elif defined (CONFIG_M5272C3)
152#define FEC_FLASHMAC (0xffe04000 + 4)
153#elif defined(CONFIG_MOD5272)
154#define FEC_FLASHMAC 0xffc0406b
155#else
156#define FEC_FLASHMAC 0
157#endif
158#endif /* CONFIG_M5272 */
159
160/* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
161 */
162#define PKT_MAXBUF_SIZE 1522
163#define PKT_MINBUF_SIZE 64
164#define PKT_MAXBLR_SIZE 1536
165
166/* FEC receive acceleration */
167#define FEC_RACC_IPDIS (1 << 1)
168#define FEC_RACC_PRODIS (1 << 2)
169#define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
170
171/*
172 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
173 * size bits. Other FEC hardware does not, so we need to take that into
174 * account when setting it.
175 */
176#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
177 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
178#define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
179#else
180#define OPT_FRAME_SIZE 0
181#endif
182
183/* FEC MII MMFR bits definition */
184#define FEC_MMFR_ST (1 << 30)
185#define FEC_MMFR_OP_READ (2 << 28)
186#define FEC_MMFR_OP_WRITE (1 << 28)
187#define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
188#define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
189#define FEC_MMFR_TA (2 << 16)
190#define FEC_MMFR_DATA(v) (v & 0xffff)
191/* FEC ECR bits definition */
192#define FEC_ECR_MAGICEN (1 << 2)
193#define FEC_ECR_SLEEP (1 << 3)
194
195#define FEC_MII_TIMEOUT 30000 /* us */
196
197/* Transmitter timeout */
198#define TX_TIMEOUT (2 * HZ)
199
200#define FEC_PAUSE_FLAG_AUTONEG 0x1
201#define FEC_PAUSE_FLAG_ENABLE 0x2
202#define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0)
203#define FEC_WOL_FLAG_ENABLE (0x1 << 1)
204#define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2)
205
206#define COPYBREAK_DEFAULT 256
207
208#define TSO_HEADER_SIZE 128
209/* Max number of allowed TCP segments for software TSO */
210#define FEC_MAX_TSO_SEGS 100
211#define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
212
213#define IS_TSO_HEADER(txq, addr) \
214 ((addr >= txq->tso_hdrs_dma) && \
215 (addr < txq->tso_hdrs_dma + txq->tx_ring_size * TSO_HEADER_SIZE))
216
217static int mii_cnt;
218
219static inline
220struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp,
221 struct fec_enet_private *fep,
222 int queue_id)
223{
224 struct bufdesc *new_bd = bdp + 1;
225 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp + 1;
226 struct fec_enet_priv_tx_q *txq = fep->tx_queue[queue_id];
227 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[queue_id];
228 struct bufdesc_ex *ex_base;
229 struct bufdesc *base;
230 int ring_size;
231
232 if (bdp >= txq->tx_bd_base) {
233 base = txq->tx_bd_base;
234 ring_size = txq->tx_ring_size;
235 ex_base = (struct bufdesc_ex *)txq->tx_bd_base;
236 } else {
237 base = rxq->rx_bd_base;
238 ring_size = rxq->rx_ring_size;
239 ex_base = (struct bufdesc_ex *)rxq->rx_bd_base;
240 }
241
242 if (fep->bufdesc_ex)
243 return (struct bufdesc *)((ex_new_bd >= (ex_base + ring_size)) ?
244 ex_base : ex_new_bd);
245 else
246 return (new_bd >= (base + ring_size)) ?
247 base : new_bd;
248}
249
250static inline
251struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp,
252 struct fec_enet_private *fep,
253 int queue_id)
254{
255 struct bufdesc *new_bd = bdp - 1;
256 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp - 1;
257 struct fec_enet_priv_tx_q *txq = fep->tx_queue[queue_id];
258 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[queue_id];
259 struct bufdesc_ex *ex_base;
260 struct bufdesc *base;
261 int ring_size;
262
263 if (bdp >= txq->tx_bd_base) {
264 base = txq->tx_bd_base;
265 ring_size = txq->tx_ring_size;
266 ex_base = (struct bufdesc_ex *)txq->tx_bd_base;
267 } else {
268 base = rxq->rx_bd_base;
269 ring_size = rxq->rx_ring_size;
270 ex_base = (struct bufdesc_ex *)rxq->rx_bd_base;
271 }
272
273 if (fep->bufdesc_ex)
274 return (struct bufdesc *)((ex_new_bd < ex_base) ?
275 (ex_new_bd + ring_size) : ex_new_bd);
276 else
277 return (new_bd < base) ? (new_bd + ring_size) : new_bd;
278}
279
280static int fec_enet_get_bd_index(struct bufdesc *base, struct bufdesc *bdp,
281 struct fec_enet_private *fep)
282{
283 return ((const char *)bdp - (const char *)base) / fep->bufdesc_size;
284}
285
286static int fec_enet_get_free_txdesc_num(struct fec_enet_private *fep,
287 struct fec_enet_priv_tx_q *txq)
288{
289 int entries;
290
291 entries = ((const char *)txq->dirty_tx -
292 (const char *)txq->cur_tx) / fep->bufdesc_size - 1;
293
294 return entries > 0 ? entries : entries + txq->tx_ring_size;
295}
296
297static void swap_buffer(void *bufaddr, int len)
298{
299 int i;
300 unsigned int *buf = bufaddr;
301
302 for (i = 0; i < len; i += 4, buf++)
303 swab32s(buf);
304}
305
306static void swap_buffer2(void *dst_buf, void *src_buf, int len)
307{
308 int i;
309 unsigned int *src = src_buf;
310 unsigned int *dst = dst_buf;
311
312 for (i = 0; i < len; i += 4, src++, dst++)
313 *dst = swab32p(src);
314}
315
316static void fec_dump(struct net_device *ndev)
317{
318 struct fec_enet_private *fep = netdev_priv(ndev);
319 struct bufdesc *bdp;
320 struct fec_enet_priv_tx_q *txq;
321 int index = 0;
322
323 netdev_info(ndev, "TX ring dump\n");
324 pr_info("Nr SC addr len SKB\n");
325
326 txq = fep->tx_queue[0];
327 bdp = txq->tx_bd_base;
328
329 do {
330 pr_info("%3u %c%c 0x%04x 0x%08lx %4u %p\n",
331 index,
332 bdp == txq->cur_tx ? 'S' : ' ',
333 bdp == txq->dirty_tx ? 'H' : ' ',
334 bdp->cbd_sc, bdp->cbd_bufaddr, bdp->cbd_datlen,
335 txq->tx_skbuff[index]);
336 bdp = fec_enet_get_nextdesc(bdp, fep, 0);
337 index++;
338 } while (bdp != txq->tx_bd_base);
339}
340
341static inline bool is_ipv4_pkt(struct sk_buff *skb)
342{
343 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
344}
345
346static int
347fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
348{
349 /* Only run for packets requiring a checksum. */
350 if (skb->ip_summed != CHECKSUM_PARTIAL)
351 return 0;
352
353 if (unlikely(skb_cow_head(skb, 0)))
354 return -1;
355
356 if (is_ipv4_pkt(skb))
357 ip_hdr(skb)->check = 0;
358 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
359
360 return 0;
361}
362
363static int
364fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq,
365 struct sk_buff *skb,
366 struct net_device *ndev)
367{
368 struct fec_enet_private *fep = netdev_priv(ndev);
369 struct bufdesc *bdp = txq->cur_tx;
370 struct bufdesc_ex *ebdp;
371 int nr_frags = skb_shinfo(skb)->nr_frags;
372 unsigned short queue = skb_get_queue_mapping(skb);
373 int frag, frag_len;
374 unsigned short status;
375 unsigned int estatus = 0;
376 skb_frag_t *this_frag;
377 unsigned int index;
378 void *bufaddr;
379 dma_addr_t addr;
380 int i;
381
382 for (frag = 0; frag < nr_frags; frag++) {
383 this_frag = &skb_shinfo(skb)->frags[frag];
384 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
385 ebdp = (struct bufdesc_ex *)bdp;
386
387 status = bdp->cbd_sc;
388 status &= ~BD_ENET_TX_STATS;
389 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
390 frag_len = skb_shinfo(skb)->frags[frag].size;
391
392 /* Handle the last BD specially */
393 if (frag == nr_frags - 1) {
394 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
395 if (fep->bufdesc_ex) {
396 estatus |= BD_ENET_TX_INT;
397 if (unlikely(skb_shinfo(skb)->tx_flags &
398 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
399 estatus |= BD_ENET_TX_TS;
400 }
401 }
402
403 if (fep->bufdesc_ex) {
404 if (fep->quirks & FEC_QUIRK_HAS_AVB)
405 estatus |= FEC_TX_BD_FTYPE(queue);
406 if (skb->ip_summed == CHECKSUM_PARTIAL)
407 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
408 ebdp->cbd_bdu = 0;
409 ebdp->cbd_esc = estatus;
410 }
411
412 bufaddr = page_address(this_frag->page.p) + this_frag->page_offset;
413
414 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
415 if (((unsigned long) bufaddr) & fep->tx_align ||
416 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
417 memcpy(txq->tx_bounce[index], bufaddr, frag_len);
418 bufaddr = txq->tx_bounce[index];
419
420 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
421 swap_buffer(bufaddr, frag_len);
422 }
423
424 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len,
425 DMA_TO_DEVICE);
426 if (dma_mapping_error(&fep->pdev->dev, addr)) {
427 dev_kfree_skb_any(skb);
428 if (net_ratelimit())
429 netdev_err(ndev, "Tx DMA memory map failed\n");
430 goto dma_mapping_error;
431 }
432
433 bdp->cbd_bufaddr = addr;
434 bdp->cbd_datlen = frag_len;
435 bdp->cbd_sc = status;
436 }
437
438 txq->cur_tx = bdp;
439
440 return 0;
441
442dma_mapping_error:
443 bdp = txq->cur_tx;
444 for (i = 0; i < frag; i++) {
445 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
446 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
447 bdp->cbd_datlen, DMA_TO_DEVICE);
448 }
449 return NETDEV_TX_OK;
450}
451
452static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq,
453 struct sk_buff *skb, struct net_device *ndev)
454{
455 struct fec_enet_private *fep = netdev_priv(ndev);
456 int nr_frags = skb_shinfo(skb)->nr_frags;
457 struct bufdesc *bdp, *last_bdp;
458 void *bufaddr;
459 dma_addr_t addr;
460 unsigned short status;
461 unsigned short buflen;
462 unsigned short queue;
463 unsigned int estatus = 0;
464 unsigned int index;
465 int entries_free;
466 int ret;
467
468 entries_free = fec_enet_get_free_txdesc_num(fep, txq);
469 if (entries_free < MAX_SKB_FRAGS + 1) {
470 dev_kfree_skb_any(skb);
471 if (net_ratelimit())
472 netdev_err(ndev, "NOT enough BD for SG!\n");
473 return NETDEV_TX_OK;
474 }
475
476 /* Protocol checksum off-load for TCP and UDP. */
477 if (fec_enet_clear_csum(skb, ndev)) {
478 dev_kfree_skb_any(skb);
479 return NETDEV_TX_OK;
480 }
481
482 /* Fill in a Tx ring entry */
483 bdp = txq->cur_tx;
484 status = bdp->cbd_sc;
485 status &= ~BD_ENET_TX_STATS;
486
487 /* Set buffer length and buffer pointer */
488 bufaddr = skb->data;
489 buflen = skb_headlen(skb);
490
491 queue = skb_get_queue_mapping(skb);
492 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
493 if (((unsigned long) bufaddr) & fep->tx_align ||
494 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
495 memcpy(txq->tx_bounce[index], skb->data, buflen);
496 bufaddr = txq->tx_bounce[index];
497
498 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
499 swap_buffer(bufaddr, buflen);
500 }
501
502 /* Push the data cache so the CPM does not get stale memory data. */
503 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE);
504 if (dma_mapping_error(&fep->pdev->dev, addr)) {
505 dev_kfree_skb_any(skb);
506 if (net_ratelimit())
507 netdev_err(ndev, "Tx DMA memory map failed\n");
508 return NETDEV_TX_OK;
509 }
510
511 if (nr_frags) {
512 ret = fec_enet_txq_submit_frag_skb(txq, skb, ndev);
513 if (ret)
514 return ret;
515 } else {
516 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
517 if (fep->bufdesc_ex) {
518 estatus = BD_ENET_TX_INT;
519 if (unlikely(skb_shinfo(skb)->tx_flags &
520 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
521 estatus |= BD_ENET_TX_TS;
522 }
523 }
524
525 if (fep->bufdesc_ex) {
526
527 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
528
529 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
530 fep->hwts_tx_en))
531 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
532
533 if (fep->quirks & FEC_QUIRK_HAS_AVB)
534 estatus |= FEC_TX_BD_FTYPE(queue);
535
536 if (skb->ip_summed == CHECKSUM_PARTIAL)
537 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
538
539 ebdp->cbd_bdu = 0;
540 ebdp->cbd_esc = estatus;
541 }
542
543 last_bdp = txq->cur_tx;
544 index = fec_enet_get_bd_index(txq->tx_bd_base, last_bdp, fep);
545 /* Save skb pointer */
546 txq->tx_skbuff[index] = skb;
547
548 bdp->cbd_datlen = buflen;
549 bdp->cbd_bufaddr = addr;
550
551 /* Send it on its way. Tell FEC it's ready, interrupt when done,
552 * it's the last BD of the frame, and to put the CRC on the end.
553 */
554 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC);
555 bdp->cbd_sc = status;
556
557 /* If this was the last BD in the ring, start at the beginning again. */
558 bdp = fec_enet_get_nextdesc(last_bdp, fep, queue);
559
560 skb_tx_timestamp(skb);
561
562 txq->cur_tx = bdp;
563
564 /* Trigger transmission start */
565 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue));
566
567 return 0;
568}
569
570static int
571fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb,
572 struct net_device *ndev,
573 struct bufdesc *bdp, int index, char *data,
574 int size, bool last_tcp, bool is_last)
575{
576 struct fec_enet_private *fep = netdev_priv(ndev);
577 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
578 unsigned short queue = skb_get_queue_mapping(skb);
579 unsigned short status;
580 unsigned int estatus = 0;
581 dma_addr_t addr;
582
583 status = bdp->cbd_sc;
584 status &= ~BD_ENET_TX_STATS;
585
586 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
587
588 if (((unsigned long) data) & fep->tx_align ||
589 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
590 memcpy(txq->tx_bounce[index], data, size);
591 data = txq->tx_bounce[index];
592
593 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
594 swap_buffer(data, size);
595 }
596
597 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE);
598 if (dma_mapping_error(&fep->pdev->dev, addr)) {
599 dev_kfree_skb_any(skb);
600 if (net_ratelimit())
601 netdev_err(ndev, "Tx DMA memory map failed\n");
602 return NETDEV_TX_BUSY;
603 }
604
605 bdp->cbd_datlen = size;
606 bdp->cbd_bufaddr = addr;
607
608 if (fep->bufdesc_ex) {
609 if (fep->quirks & FEC_QUIRK_HAS_AVB)
610 estatus |= FEC_TX_BD_FTYPE(queue);
611 if (skb->ip_summed == CHECKSUM_PARTIAL)
612 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
613 ebdp->cbd_bdu = 0;
614 ebdp->cbd_esc = estatus;
615 }
616
617 /* Handle the last BD specially */
618 if (last_tcp)
619 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC);
620 if (is_last) {
621 status |= BD_ENET_TX_INTR;
622 if (fep->bufdesc_ex)
623 ebdp->cbd_esc |= BD_ENET_TX_INT;
624 }
625
626 bdp->cbd_sc = status;
627
628 return 0;
629}
630
631static int
632fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq,
633 struct sk_buff *skb, struct net_device *ndev,
634 struct bufdesc *bdp, int index)
635{
636 struct fec_enet_private *fep = netdev_priv(ndev);
637 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
638 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
639 unsigned short queue = skb_get_queue_mapping(skb);
640 void *bufaddr;
641 unsigned long dmabuf;
642 unsigned short status;
643 unsigned int estatus = 0;
644
645 status = bdp->cbd_sc;
646 status &= ~BD_ENET_TX_STATS;
647 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
648
649 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
650 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE;
651 if (((unsigned long)bufaddr) & fep->tx_align ||
652 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
653 memcpy(txq->tx_bounce[index], skb->data, hdr_len);
654 bufaddr = txq->tx_bounce[index];
655
656 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
657 swap_buffer(bufaddr, hdr_len);
658
659 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr,
660 hdr_len, DMA_TO_DEVICE);
661 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) {
662 dev_kfree_skb_any(skb);
663 if (net_ratelimit())
664 netdev_err(ndev, "Tx DMA memory map failed\n");
665 return NETDEV_TX_BUSY;
666 }
667 }
668
669 bdp->cbd_bufaddr = dmabuf;
670 bdp->cbd_datlen = hdr_len;
671
672 if (fep->bufdesc_ex) {
673 if (fep->quirks & FEC_QUIRK_HAS_AVB)
674 estatus |= FEC_TX_BD_FTYPE(queue);
675 if (skb->ip_summed == CHECKSUM_PARTIAL)
676 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
677 ebdp->cbd_bdu = 0;
678 ebdp->cbd_esc = estatus;
679 }
680
681 bdp->cbd_sc = status;
682
683 return 0;
684}
685
686static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq,
687 struct sk_buff *skb,
688 struct net_device *ndev)
689{
690 struct fec_enet_private *fep = netdev_priv(ndev);
691 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
692 int total_len, data_left;
693 struct bufdesc *bdp = txq->cur_tx;
694 unsigned short queue = skb_get_queue_mapping(skb);
695 struct tso_t tso;
696 unsigned int index = 0;
697 int ret;
698
699 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(fep, txq)) {
700 dev_kfree_skb_any(skb);
701 if (net_ratelimit())
702 netdev_err(ndev, "NOT enough BD for TSO!\n");
703 return NETDEV_TX_OK;
704 }
705
706 /* Protocol checksum off-load for TCP and UDP. */
707 if (fec_enet_clear_csum(skb, ndev)) {
708 dev_kfree_skb_any(skb);
709 return NETDEV_TX_OK;
710 }
711
712 /* Initialize the TSO handler, and prepare the first payload */
713 tso_start(skb, &tso);
714
715 total_len = skb->len - hdr_len;
716 while (total_len > 0) {
717 char *hdr;
718
719 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
720 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
721 total_len -= data_left;
722
723 /* prepare packet headers: MAC + IP + TCP */
724 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
725 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
726 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index);
727 if (ret)
728 goto err_release;
729
730 while (data_left > 0) {
731 int size;
732
733 size = min_t(int, tso.size, data_left);
734 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
735 index = fec_enet_get_bd_index(txq->tx_bd_base,
736 bdp, fep);
737 ret = fec_enet_txq_put_data_tso(txq, skb, ndev,
738 bdp, index,
739 tso.data, size,
740 size == data_left,
741 total_len == 0);
742 if (ret)
743 goto err_release;
744
745 data_left -= size;
746 tso_build_data(skb, &tso, size);
747 }
748
749 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
750 }
751
752 /* Save skb pointer */
753 txq->tx_skbuff[index] = skb;
754
755 skb_tx_timestamp(skb);
756 txq->cur_tx = bdp;
757
758 /* Trigger transmission start */
759 if (!(fep->quirks & FEC_QUIRK_ERR007885) ||
760 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) ||
761 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) ||
762 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) ||
763 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)))
764 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue));
765
766 return 0;
767
768err_release:
769 /* TODO: Release all used data descriptors for TSO */
770 return ret;
771}
772
773static netdev_tx_t
774fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
775{
776 struct fec_enet_private *fep = netdev_priv(ndev);
777 int entries_free;
778 unsigned short queue;
779 struct fec_enet_priv_tx_q *txq;
780 struct netdev_queue *nq;
781 int ret;
782
783 queue = skb_get_queue_mapping(skb);
784 txq = fep->tx_queue[queue];
785 nq = netdev_get_tx_queue(ndev, queue);
786
787 if (skb_is_gso(skb))
788 ret = fec_enet_txq_submit_tso(txq, skb, ndev);
789 else
790 ret = fec_enet_txq_submit_skb(txq, skb, ndev);
791 if (ret)
792 return ret;
793
794 entries_free = fec_enet_get_free_txdesc_num(fep, txq);
795 if (entries_free <= txq->tx_stop_threshold)
796 netif_tx_stop_queue(nq);
797
798 return NETDEV_TX_OK;
799}
800
801/* Init RX & TX buffer descriptors
802 */
803static void fec_enet_bd_init(struct net_device *dev)
804{
805 struct fec_enet_private *fep = netdev_priv(dev);
806 struct fec_enet_priv_tx_q *txq;
807 struct fec_enet_priv_rx_q *rxq;
808 struct bufdesc *bdp;
809 unsigned int i;
810 unsigned int q;
811
812 for (q = 0; q < fep->num_rx_queues; q++) {
813 /* Initialize the receive buffer descriptors. */
814 rxq = fep->rx_queue[q];
815 bdp = rxq->rx_bd_base;
816
817 for (i = 0; i < rxq->rx_ring_size; i++) {
818
819 /* Initialize the BD for every fragment in the page. */
820 if (bdp->cbd_bufaddr)
821 bdp->cbd_sc = BD_ENET_RX_EMPTY;
822 else
823 bdp->cbd_sc = 0;
824 bdp = fec_enet_get_nextdesc(bdp, fep, q);
825 }
826
827 /* Set the last buffer to wrap */
828 bdp = fec_enet_get_prevdesc(bdp, fep, q);
829 bdp->cbd_sc |= BD_SC_WRAP;
830
831 rxq->cur_rx = rxq->rx_bd_base;
832 }
833
834 for (q = 0; q < fep->num_tx_queues; q++) {
835 /* ...and the same for transmit */
836 txq = fep->tx_queue[q];
837 bdp = txq->tx_bd_base;
838 txq->cur_tx = bdp;
839
840 for (i = 0; i < txq->tx_ring_size; i++) {
841 /* Initialize the BD for every fragment in the page. */
842 bdp->cbd_sc = 0;
843 if (txq->tx_skbuff[i]) {
844 dev_kfree_skb_any(txq->tx_skbuff[i]);
845 txq->tx_skbuff[i] = NULL;
846 }
847 bdp->cbd_bufaddr = 0;
848 bdp = fec_enet_get_nextdesc(bdp, fep, q);
849 }
850
851 /* Set the last buffer to wrap */
852 bdp = fec_enet_get_prevdesc(bdp, fep, q);
853 bdp->cbd_sc |= BD_SC_WRAP;
854 txq->dirty_tx = bdp;
855 }
856}
857
858static void fec_enet_active_rxring(struct net_device *ndev)
859{
860 struct fec_enet_private *fep = netdev_priv(ndev);
861 int i;
862
863 for (i = 0; i < fep->num_rx_queues; i++)
864 writel(0, fep->hwp + FEC_R_DES_ACTIVE(i));
865}
866
867static void fec_enet_enable_ring(struct net_device *ndev)
868{
869 struct fec_enet_private *fep = netdev_priv(ndev);
870 struct fec_enet_priv_tx_q *txq;
871 struct fec_enet_priv_rx_q *rxq;
872 int i;
873
874 for (i = 0; i < fep->num_rx_queues; i++) {
875 rxq = fep->rx_queue[i];
876 writel(rxq->bd_dma, fep->hwp + FEC_R_DES_START(i));
877 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i));
878
879 /* enable DMA1/2 */
880 if (i)
881 writel(RCMR_MATCHEN | RCMR_CMP(i),
882 fep->hwp + FEC_RCMR(i));
883 }
884
885 for (i = 0; i < fep->num_tx_queues; i++) {
886 txq = fep->tx_queue[i];
887 writel(txq->bd_dma, fep->hwp + FEC_X_DES_START(i));
888
889 /* enable DMA1/2 */
890 if (i)
891 writel(DMA_CLASS_EN | IDLE_SLOPE(i),
892 fep->hwp + FEC_DMA_CFG(i));
893 }
894}
895
896static void fec_enet_reset_skb(struct net_device *ndev)
897{
898 struct fec_enet_private *fep = netdev_priv(ndev);
899 struct fec_enet_priv_tx_q *txq;
900 int i, j;
901
902 for (i = 0; i < fep->num_tx_queues; i++) {
903 txq = fep->tx_queue[i];
904
905 for (j = 0; j < txq->tx_ring_size; j++) {
906 if (txq->tx_skbuff[j]) {
907 dev_kfree_skb_any(txq->tx_skbuff[j]);
908 txq->tx_skbuff[j] = NULL;
909 }
910 }
911 }
912}
913
914/*
915 * This function is called to start or restart the FEC during a link
916 * change, transmit timeout, or to reconfigure the FEC. The network
917 * packet processing for this device must be stopped before this call.
918 */
919static void
920fec_restart(struct net_device *ndev)
921{
922 struct fec_enet_private *fep = netdev_priv(ndev);
923 u32 val;
924 u32 temp_mac[2];
925 u32 rcntl = OPT_FRAME_SIZE | 0x04;
926 u32 ecntl = 0x2; /* ETHEREN */
927
928 /* Whack a reset. We should wait for this.
929 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
930 * instead of reset MAC itself.
931 */
932 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
933 writel(0, fep->hwp + FEC_ECNTRL);
934 } else {
935 writel(1, fep->hwp + FEC_ECNTRL);
936 udelay(10);
937 }
938
939 /*
940 * enet-mac reset will reset mac address registers too,
941 * so need to reconfigure it.
942 */
943 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
944 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
945 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
946 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
947 }
948
949 /* Clear any outstanding interrupt. */
950 writel(0xffffffff, fep->hwp + FEC_IEVENT);
951
952 fec_enet_bd_init(ndev);
953
954 fec_enet_enable_ring(ndev);
955
956 /* Reset tx SKB buffers. */
957 fec_enet_reset_skb(ndev);
958
959 /* Enable MII mode */
960 if (fep->full_duplex == DUPLEX_FULL) {
961 /* FD enable */
962 writel(0x04, fep->hwp + FEC_X_CNTRL);
963 } else {
964 /* No Rcv on Xmit */
965 rcntl |= 0x02;
966 writel(0x0, fep->hwp + FEC_X_CNTRL);
967 }
968
969 /* Set MII speed */
970 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
971
972#if !defined(CONFIG_M5272)
973 /* set RX checksum */
974 val = readl(fep->hwp + FEC_RACC);
975 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
976 val |= FEC_RACC_OPTIONS;
977 else
978 val &= ~FEC_RACC_OPTIONS;
979 writel(val, fep->hwp + FEC_RACC);
980#endif
981
982 /*
983 * The phy interface and speed need to get configured
984 * differently on enet-mac.
985 */
986 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
987 /* Enable flow control and length check */
988 rcntl |= 0x40000000 | 0x00000020;
989
990 /* RGMII, RMII or MII */
991 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII ||
992 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
993 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID ||
994 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
995 rcntl |= (1 << 6);
996 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
997 rcntl |= (1 << 8);
998 else
999 rcntl &= ~(1 << 8);
1000
1001 /* 1G, 100M or 10M */
1002 if (fep->phy_dev) {
1003 if (fep->phy_dev->speed == SPEED_1000)
1004 ecntl |= (1 << 5);
1005 else if (fep->phy_dev->speed == SPEED_100)
1006 rcntl &= ~(1 << 9);
1007 else
1008 rcntl |= (1 << 9);
1009 }
1010 } else {
1011#ifdef FEC_MIIGSK_ENR
1012 if (fep->quirks & FEC_QUIRK_USE_GASKET) {
1013 u32 cfgr;
1014 /* disable the gasket and wait */
1015 writel(0, fep->hwp + FEC_MIIGSK_ENR);
1016 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
1017 udelay(1);
1018
1019 /*
1020 * configure the gasket:
1021 * RMII, 50 MHz, no loopback, no echo
1022 * MII, 25 MHz, no loopback, no echo
1023 */
1024 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1025 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
1026 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10)
1027 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
1028 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
1029
1030 /* re-enable the gasket */
1031 writel(2, fep->hwp + FEC_MIIGSK_ENR);
1032 }
1033#endif
1034 }
1035
1036#if !defined(CONFIG_M5272)
1037 /* enable pause frame*/
1038 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
1039 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
1040 fep->phy_dev && fep->phy_dev->pause)) {
1041 rcntl |= FEC_ENET_FCE;
1042
1043 /* set FIFO threshold parameter to reduce overrun */
1044 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
1045 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
1046 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
1047 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
1048
1049 /* OPD */
1050 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
1051 } else {
1052 rcntl &= ~FEC_ENET_FCE;
1053 }
1054#endif /* !defined(CONFIG_M5272) */
1055
1056 writel(rcntl, fep->hwp + FEC_R_CNTRL);
1057
1058 /* Setup multicast filter. */
1059 set_multicast_list(ndev);
1060#ifndef CONFIG_M5272
1061 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
1062 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
1063#endif
1064
1065 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
1066 /* enable ENET endian swap */
1067 ecntl |= (1 << 8);
1068 /* enable ENET store and forward mode */
1069 writel(1 << 8, fep->hwp + FEC_X_WMRK);
1070 }
1071
1072 if (fep->bufdesc_ex)
1073 ecntl |= (1 << 4);
1074
1075#ifndef CONFIG_M5272
1076 /* Enable the MIB statistic event counters */
1077 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
1078#endif
1079
1080 /* And last, enable the transmit and receive processing */
1081 writel(ecntl, fep->hwp + FEC_ECNTRL);
1082 fec_enet_active_rxring(ndev);
1083
1084 if (fep->bufdesc_ex)
1085 fec_ptp_start_cyclecounter(ndev);
1086
1087 /* Enable interrupts we wish to service */
1088 if (fep->link)
1089 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1090 else
1091 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK);
1092
1093 /* Init the interrupt coalescing */
1094 fec_enet_itr_coal_init(ndev);
1095
1096}
1097
1098static void
1099fec_stop(struct net_device *ndev)
1100{
1101 struct fec_enet_private *fep = netdev_priv(ndev);
1102 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
1103 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
1104 u32 val;
1105
1106 /* We cannot expect a graceful transmit stop without link !!! */
1107 if (fep->link) {
1108 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
1109 udelay(10);
1110 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
1111 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
1112 }
1113
1114 /* Whack a reset. We should wait for this.
1115 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
1116 * instead of reset MAC itself.
1117 */
1118 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1119 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
1120 writel(0, fep->hwp + FEC_ECNTRL);
1121 } else {
1122 writel(1, fep->hwp + FEC_ECNTRL);
1123 udelay(10);
1124 }
1125 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1126 } else {
1127 writel(FEC_DEFAULT_IMASK | FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK);
1128 val = readl(fep->hwp + FEC_ECNTRL);
1129 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
1130 writel(val, fep->hwp + FEC_ECNTRL);
1131
1132 if (pdata && pdata->sleep_mode_enable)
1133 pdata->sleep_mode_enable(true);
1134 }
1135 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1136
1137 /* We have to keep ENET enabled to have MII interrupt stay working */
1138 if (fep->quirks & FEC_QUIRK_ENET_MAC &&
1139 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1140 writel(2, fep->hwp + FEC_ECNTRL);
1141 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
1142 }
1143}
1144
1145
1146static void
1147fec_timeout(struct net_device *ndev)
1148{
1149 struct fec_enet_private *fep = netdev_priv(ndev);
1150
1151 fec_dump(ndev);
1152
1153 ndev->stats.tx_errors++;
1154
1155 schedule_work(&fep->tx_timeout_work);
1156}
1157
1158static void fec_enet_timeout_work(struct work_struct *work)
1159{
1160 struct fec_enet_private *fep =
1161 container_of(work, struct fec_enet_private, tx_timeout_work);
1162 struct net_device *ndev = fep->netdev;
1163
1164 rtnl_lock();
1165 if (netif_device_present(ndev) || netif_running(ndev)) {
1166 napi_disable(&fep->napi);
1167 netif_tx_lock_bh(ndev);
1168 fec_restart(ndev);
1169 netif_wake_queue(ndev);
1170 netif_tx_unlock_bh(ndev);
1171 napi_enable(&fep->napi);
1172 }
1173 rtnl_unlock();
1174}
1175
1176static void
1177fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts,
1178 struct skb_shared_hwtstamps *hwtstamps)
1179{
1180 unsigned long flags;
1181 u64 ns;
1182
1183 spin_lock_irqsave(&fep->tmreg_lock, flags);
1184 ns = timecounter_cyc2time(&fep->tc, ts);
1185 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
1186
1187 memset(hwtstamps, 0, sizeof(*hwtstamps));
1188 hwtstamps->hwtstamp = ns_to_ktime(ns);
1189}
1190
1191static void
1192fec_enet_tx_queue(struct net_device *ndev, u16 queue_id)
1193{
1194 struct fec_enet_private *fep;
1195 struct bufdesc *bdp;
1196 unsigned short status;
1197 struct sk_buff *skb;
1198 struct fec_enet_priv_tx_q *txq;
1199 struct netdev_queue *nq;
1200 int index = 0;
1201 int entries_free;
1202
1203 fep = netdev_priv(ndev);
1204
1205 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1206
1207 txq = fep->tx_queue[queue_id];
1208 /* get next bdp of dirty_tx */
1209 nq = netdev_get_tx_queue(ndev, queue_id);
1210 bdp = txq->dirty_tx;
1211
1212 /* get next bdp of dirty_tx */
1213 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
1214
1215 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
1216
1217 /* current queue is empty */
1218 if (bdp == txq->cur_tx)
1219 break;
1220
1221 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
1222
1223 skb = txq->tx_skbuff[index];
1224 txq->tx_skbuff[index] = NULL;
1225 if (!IS_TSO_HEADER(txq, bdp->cbd_bufaddr))
1226 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1227 bdp->cbd_datlen, DMA_TO_DEVICE);
1228 bdp->cbd_bufaddr = 0;
1229 if (!skb) {
1230 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
1231 continue;
1232 }
1233
1234 /* Check for errors. */
1235 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
1236 BD_ENET_TX_RL | BD_ENET_TX_UN |
1237 BD_ENET_TX_CSL)) {
1238 ndev->stats.tx_errors++;
1239 if (status & BD_ENET_TX_HB) /* No heartbeat */
1240 ndev->stats.tx_heartbeat_errors++;
1241 if (status & BD_ENET_TX_LC) /* Late collision */
1242 ndev->stats.tx_window_errors++;
1243 if (status & BD_ENET_TX_RL) /* Retrans limit */
1244 ndev->stats.tx_aborted_errors++;
1245 if (status & BD_ENET_TX_UN) /* Underrun */
1246 ndev->stats.tx_fifo_errors++;
1247 if (status & BD_ENET_TX_CSL) /* Carrier lost */
1248 ndev->stats.tx_carrier_errors++;
1249 } else {
1250 ndev->stats.tx_packets++;
1251 ndev->stats.tx_bytes += skb->len;
1252 }
1253
1254 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
1255 fep->bufdesc_ex) {
1256 struct skb_shared_hwtstamps shhwtstamps;
1257 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1258
1259 fec_enet_hwtstamp(fep, ebdp->ts, &shhwtstamps);
1260 skb_tstamp_tx(skb, &shhwtstamps);
1261 }
1262
1263 /* Deferred means some collisions occurred during transmit,
1264 * but we eventually sent the packet OK.
1265 */
1266 if (status & BD_ENET_TX_DEF)
1267 ndev->stats.collisions++;
1268
1269 /* Free the sk buffer associated with this last transmit */
1270 dev_kfree_skb_any(skb);
1271
1272 txq->dirty_tx = bdp;
1273
1274 /* Update pointer to next buffer descriptor to be transmitted */
1275 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
1276
1277 /* Since we have freed up a buffer, the ring is no longer full
1278 */
1279 if (netif_queue_stopped(ndev)) {
1280 entries_free = fec_enet_get_free_txdesc_num(fep, txq);
1281 if (entries_free >= txq->tx_wake_threshold)
1282 netif_tx_wake_queue(nq);
1283 }
1284 }
1285
1286 /* ERR006538: Keep the transmitter going */
1287 if (bdp != txq->cur_tx &&
1288 readl(fep->hwp + FEC_X_DES_ACTIVE(queue_id)) == 0)
1289 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue_id));
1290}
1291
1292static void
1293fec_enet_tx(struct net_device *ndev)
1294{
1295 struct fec_enet_private *fep = netdev_priv(ndev);
1296 u16 queue_id;
1297 /* First process class A queue, then Class B and Best Effort queue */
1298 for_each_set_bit(queue_id, &fep->work_tx, FEC_ENET_MAX_TX_QS) {
1299 clear_bit(queue_id, &fep->work_tx);
1300 fec_enet_tx_queue(ndev, queue_id);
1301 }
1302 return;
1303}
1304
1305static int
1306fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb)
1307{
1308 struct fec_enet_private *fep = netdev_priv(ndev);
1309 int off;
1310
1311 off = ((unsigned long)skb->data) & fep->rx_align;
1312 if (off)
1313 skb_reserve(skb, fep->rx_align + 1 - off);
1314
1315 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data,
1316 FEC_ENET_RX_FRSIZE - fep->rx_align,
1317 DMA_FROM_DEVICE);
1318 if (dma_mapping_error(&fep->pdev->dev, bdp->cbd_bufaddr)) {
1319 if (net_ratelimit())
1320 netdev_err(ndev, "Rx DMA memory map failed\n");
1321 return -ENOMEM;
1322 }
1323
1324 return 0;
1325}
1326
1327static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb,
1328 struct bufdesc *bdp, u32 length, bool swap)
1329{
1330 struct fec_enet_private *fep = netdev_priv(ndev);
1331 struct sk_buff *new_skb;
1332
1333 if (length > fep->rx_copybreak)
1334 return false;
1335
1336 new_skb = netdev_alloc_skb(ndev, length);
1337 if (!new_skb)
1338 return false;
1339
1340 dma_sync_single_for_cpu(&fep->pdev->dev, bdp->cbd_bufaddr,
1341 FEC_ENET_RX_FRSIZE - fep->rx_align,
1342 DMA_FROM_DEVICE);
1343 if (!swap)
1344 memcpy(new_skb->data, (*skb)->data, length);
1345 else
1346 swap_buffer2(new_skb->data, (*skb)->data, length);
1347 *skb = new_skb;
1348
1349 return true;
1350}
1351
1352/* During a receive, the cur_rx points to the current incoming buffer.
1353 * When we update through the ring, if the next incoming buffer has
1354 * not been given to the system, we just set the empty indicator,
1355 * effectively tossing the packet.
1356 */
1357static int
1358fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id)
1359{
1360 struct fec_enet_private *fep = netdev_priv(ndev);
1361 struct fec_enet_priv_rx_q *rxq;
1362 struct bufdesc *bdp;
1363 unsigned short status;
1364 struct sk_buff *skb_new = NULL;
1365 struct sk_buff *skb;
1366 ushort pkt_len;
1367 __u8 *data;
1368 int pkt_received = 0;
1369 struct bufdesc_ex *ebdp = NULL;
1370 bool vlan_packet_rcvd = false;
1371 u16 vlan_tag;
1372 int index = 0;
1373 bool is_copybreak;
1374 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME;
1375
1376#ifdef CONFIG_M532x
1377 flush_cache_all();
1378#endif
1379 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1380 rxq = fep->rx_queue[queue_id];
1381
1382 /* First, grab all of the stats for the incoming packet.
1383 * These get messed up if we get called due to a busy condition.
1384 */
1385 bdp = rxq->cur_rx;
1386
1387 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
1388
1389 if (pkt_received >= budget)
1390 break;
1391 pkt_received++;
1392
1393 /* Since we have allocated space to hold a complete frame,
1394 * the last indicator should be set.
1395 */
1396 if ((status & BD_ENET_RX_LAST) == 0)
1397 netdev_err(ndev, "rcv is not +last\n");
1398
1399
1400 /* Check for errors. */
1401 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
1402 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
1403 ndev->stats.rx_errors++;
1404 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
1405 /* Frame too long or too short. */
1406 ndev->stats.rx_length_errors++;
1407 }
1408 if (status & BD_ENET_RX_NO) /* Frame alignment */
1409 ndev->stats.rx_frame_errors++;
1410 if (status & BD_ENET_RX_CR) /* CRC Error */
1411 ndev->stats.rx_crc_errors++;
1412 if (status & BD_ENET_RX_OV) /* FIFO overrun */
1413 ndev->stats.rx_fifo_errors++;
1414 }
1415
1416 /* Report late collisions as a frame error.
1417 * On this error, the BD is closed, but we don't know what we
1418 * have in the buffer. So, just drop this frame on the floor.
1419 */
1420 if (status & BD_ENET_RX_CL) {
1421 ndev->stats.rx_errors++;
1422 ndev->stats.rx_frame_errors++;
1423 goto rx_processing_done;
1424 }
1425
1426 /* Process the incoming frame. */
1427 ndev->stats.rx_packets++;
1428 pkt_len = bdp->cbd_datlen;
1429 ndev->stats.rx_bytes += pkt_len;
1430
1431 index = fec_enet_get_bd_index(rxq->rx_bd_base, bdp, fep);
1432 skb = rxq->rx_skbuff[index];
1433
1434 /* The packet length includes FCS, but we don't want to
1435 * include that when passing upstream as it messes up
1436 * bridging applications.
1437 */
1438 is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4,
1439 need_swap);
1440 if (!is_copybreak) {
1441 skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1442 if (unlikely(!skb_new)) {
1443 ndev->stats.rx_dropped++;
1444 goto rx_processing_done;
1445 }
1446 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1447 FEC_ENET_RX_FRSIZE - fep->rx_align,
1448 DMA_FROM_DEVICE);
1449 }
1450
1451 prefetch(skb->data - NET_IP_ALIGN);
1452 skb_put(skb, pkt_len - 4);
1453 data = skb->data;
1454 if (!is_copybreak && need_swap)
1455 swap_buffer(data, pkt_len);
1456
1457 /* Extract the enhanced buffer descriptor */
1458 ebdp = NULL;
1459 if (fep->bufdesc_ex)
1460 ebdp = (struct bufdesc_ex *)bdp;
1461
1462 /* If this is a VLAN packet remove the VLAN Tag */
1463 vlan_packet_rcvd = false;
1464 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1465 fep->bufdesc_ex && (ebdp->cbd_esc & BD_ENET_RX_VLAN)) {
1466 /* Push and remove the vlan tag */
1467 struct vlan_hdr *vlan_header =
1468 (struct vlan_hdr *) (data + ETH_HLEN);
1469 vlan_tag = ntohs(vlan_header->h_vlan_TCI);
1470
1471 vlan_packet_rcvd = true;
1472
1473 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2);
1474 skb_pull(skb, VLAN_HLEN);
1475 }
1476
1477 skb->protocol = eth_type_trans(skb, ndev);
1478
1479 /* Get receive timestamp from the skb */
1480 if (fep->hwts_rx_en && fep->bufdesc_ex)
1481 fec_enet_hwtstamp(fep, ebdp->ts,
1482 skb_hwtstamps(skb));
1483
1484 if (fep->bufdesc_ex &&
1485 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
1486 if (!(ebdp->cbd_esc & FLAG_RX_CSUM_ERROR)) {
1487 /* don't check it */
1488 skb->ip_summed = CHECKSUM_UNNECESSARY;
1489 } else {
1490 skb_checksum_none_assert(skb);
1491 }
1492 }
1493
1494 /* Handle received VLAN packets */
1495 if (vlan_packet_rcvd)
1496 __vlan_hwaccel_put_tag(skb,
1497 htons(ETH_P_8021Q),
1498 vlan_tag);
1499
1500 napi_gro_receive(&fep->napi, skb);
1501
1502 if (is_copybreak) {
1503 dma_sync_single_for_device(&fep->pdev->dev, bdp->cbd_bufaddr,
1504 FEC_ENET_RX_FRSIZE - fep->rx_align,
1505 DMA_FROM_DEVICE);
1506 } else {
1507 rxq->rx_skbuff[index] = skb_new;
1508 fec_enet_new_rxbdp(ndev, bdp, skb_new);
1509 }
1510
1511rx_processing_done:
1512 /* Clear the status flags for this buffer */
1513 status &= ~BD_ENET_RX_STATS;
1514
1515 /* Mark the buffer empty */
1516 status |= BD_ENET_RX_EMPTY;
1517 bdp->cbd_sc = status;
1518
1519 if (fep->bufdesc_ex) {
1520 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1521
1522 ebdp->cbd_esc = BD_ENET_RX_INT;
1523 ebdp->cbd_prot = 0;
1524 ebdp->cbd_bdu = 0;
1525 }
1526
1527 /* Update BD pointer to next entry */
1528 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
1529
1530 /* Doing this here will keep the FEC running while we process
1531 * incoming frames. On a heavily loaded network, we should be
1532 * able to keep up at the expense of system resources.
1533 */
1534 writel(0, fep->hwp + FEC_R_DES_ACTIVE(queue_id));
1535 }
1536 rxq->cur_rx = bdp;
1537 return pkt_received;
1538}
1539
1540static int
1541fec_enet_rx(struct net_device *ndev, int budget)
1542{
1543 int pkt_received = 0;
1544 u16 queue_id;
1545 struct fec_enet_private *fep = netdev_priv(ndev);
1546
1547 for_each_set_bit(queue_id, &fep->work_rx, FEC_ENET_MAX_RX_QS) {
1548 clear_bit(queue_id, &fep->work_rx);
1549 pkt_received += fec_enet_rx_queue(ndev,
1550 budget - pkt_received, queue_id);
1551 }
1552 return pkt_received;
1553}
1554
1555static bool
1556fec_enet_collect_events(struct fec_enet_private *fep, uint int_events)
1557{
1558 if (int_events == 0)
1559 return false;
1560
1561 if (int_events & FEC_ENET_RXF)
1562 fep->work_rx |= (1 << 2);
1563 if (int_events & FEC_ENET_RXF_1)
1564 fep->work_rx |= (1 << 0);
1565 if (int_events & FEC_ENET_RXF_2)
1566 fep->work_rx |= (1 << 1);
1567
1568 if (int_events & FEC_ENET_TXF)
1569 fep->work_tx |= (1 << 2);
1570 if (int_events & FEC_ENET_TXF_1)
1571 fep->work_tx |= (1 << 0);
1572 if (int_events & FEC_ENET_TXF_2)
1573 fep->work_tx |= (1 << 1);
1574
1575 return true;
1576}
1577
1578static irqreturn_t
1579fec_enet_interrupt(int irq, void *dev_id)
1580{
1581 struct net_device *ndev = dev_id;
1582 struct fec_enet_private *fep = netdev_priv(ndev);
1583 uint int_events;
1584 irqreturn_t ret = IRQ_NONE;
1585
1586 int_events = readl(fep->hwp + FEC_IEVENT);
1587 writel(int_events, fep->hwp + FEC_IEVENT);
1588 fec_enet_collect_events(fep, int_events);
1589
1590 if ((fep->work_tx || fep->work_rx) && fep->link) {
1591 ret = IRQ_HANDLED;
1592
1593 if (napi_schedule_prep(&fep->napi)) {
1594 /* Disable the NAPI interrupts */
1595 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK);
1596 __napi_schedule(&fep->napi);
1597 }
1598 }
1599
1600 if (int_events & FEC_ENET_MII) {
1601 ret = IRQ_HANDLED;
1602 complete(&fep->mdio_done);
1603 }
1604
1605 if (fep->ptp_clock)
1606 fec_ptp_check_pps_event(fep);
1607
1608 return ret;
1609}
1610
1611static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1612{
1613 struct net_device *ndev = napi->dev;
1614 struct fec_enet_private *fep = netdev_priv(ndev);
1615 int pkts;
1616
1617 pkts = fec_enet_rx(ndev, budget);
1618
1619 fec_enet_tx(ndev);
1620
1621 if (pkts < budget) {
1622 napi_complete(napi);
1623 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1624 }
1625 return pkts;
1626}
1627
1628/* ------------------------------------------------------------------------- */
1629static void fec_get_mac(struct net_device *ndev)
1630{
1631 struct fec_enet_private *fep = netdev_priv(ndev);
1632 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
1633 unsigned char *iap, tmpaddr[ETH_ALEN];
1634
1635 /*
1636 * try to get mac address in following order:
1637 *
1638 * 1) module parameter via kernel command line in form
1639 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1640 */
1641 iap = macaddr;
1642
1643 /*
1644 * 2) from device tree data
1645 */
1646 if (!is_valid_ether_addr(iap)) {
1647 struct device_node *np = fep->pdev->dev.of_node;
1648 if (np) {
1649 const char *mac = of_get_mac_address(np);
1650 if (mac)
1651 iap = (unsigned char *) mac;
1652 }
1653 }
1654
1655 /*
1656 * 3) from flash or fuse (via platform data)
1657 */
1658 if (!is_valid_ether_addr(iap)) {
1659#ifdef CONFIG_M5272
1660 if (FEC_FLASHMAC)
1661 iap = (unsigned char *)FEC_FLASHMAC;
1662#else
1663 if (pdata)
1664 iap = (unsigned char *)&pdata->mac;
1665#endif
1666 }
1667
1668 /*
1669 * 4) FEC mac registers set by bootloader
1670 */
1671 if (!is_valid_ether_addr(iap)) {
1672 *((__be32 *) &tmpaddr[0]) =
1673 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
1674 *((__be16 *) &tmpaddr[4]) =
1675 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
1676 iap = &tmpaddr[0];
1677 }
1678
1679 /*
1680 * 5) random mac address
1681 */
1682 if (!is_valid_ether_addr(iap)) {
1683 /* Report it and use a random ethernet address instead */
1684 netdev_err(ndev, "Invalid MAC address: %pM\n", iap);
1685 eth_hw_addr_random(ndev);
1686 netdev_info(ndev, "Using random MAC address: %pM\n",
1687 ndev->dev_addr);
1688 return;
1689 }
1690
1691 memcpy(ndev->dev_addr, iap, ETH_ALEN);
1692
1693 /* Adjust MAC if using macaddr */
1694 if (iap == macaddr)
1695 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
1696}
1697
1698/* ------------------------------------------------------------------------- */
1699
1700/*
1701 * Phy section
1702 */
1703static void fec_enet_adjust_link(struct net_device *ndev)
1704{
1705 struct fec_enet_private *fep = netdev_priv(ndev);
1706 struct phy_device *phy_dev = fep->phy_dev;
1707 int status_change = 0;
1708
1709 /* Prevent a state halted on mii error */
1710 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
1711 phy_dev->state = PHY_RESUMING;
1712 return;
1713 }
1714
1715 /*
1716 * If the netdev is down, or is going down, we're not interested
1717 * in link state events, so just mark our idea of the link as down
1718 * and ignore the event.
1719 */
1720 if (!netif_running(ndev) || !netif_device_present(ndev)) {
1721 fep->link = 0;
1722 } else if (phy_dev->link) {
1723 if (!fep->link) {
1724 fep->link = phy_dev->link;
1725 status_change = 1;
1726 }
1727
1728 if (fep->full_duplex != phy_dev->duplex) {
1729 fep->full_duplex = phy_dev->duplex;
1730 status_change = 1;
1731 }
1732
1733 if (phy_dev->speed != fep->speed) {
1734 fep->speed = phy_dev->speed;
1735 status_change = 1;
1736 }
1737
1738 /* if any of the above changed restart the FEC */
1739 if (status_change) {
1740 napi_disable(&fep->napi);
1741 netif_tx_lock_bh(ndev);
1742 fec_restart(ndev);
1743 netif_wake_queue(ndev);
1744 netif_tx_unlock_bh(ndev);
1745 napi_enable(&fep->napi);
1746 }
1747 } else {
1748 if (fep->link) {
1749 napi_disable(&fep->napi);
1750 netif_tx_lock_bh(ndev);
1751 fec_stop(ndev);
1752 netif_tx_unlock_bh(ndev);
1753 napi_enable(&fep->napi);
1754 fep->link = phy_dev->link;
1755 status_change = 1;
1756 }
1757 }
1758
1759 if (status_change)
1760 phy_print_status(phy_dev);
1761}
1762
1763static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1764{
1765 struct fec_enet_private *fep = bus->priv;
1766 unsigned long time_left;
1767
1768 fep->mii_timeout = 0;
1769 init_completion(&fep->mdio_done);
1770
1771 /* start a read op */
1772 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
1773 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1774 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1775
1776 /* wait for end of transfer */
1777 time_left = wait_for_completion_timeout(&fep->mdio_done,
1778 usecs_to_jiffies(FEC_MII_TIMEOUT));
1779 if (time_left == 0) {
1780 fep->mii_timeout = 1;
1781 netdev_err(fep->netdev, "MDIO read timeout\n");
1782 return -ETIMEDOUT;
1783 }
1784
1785 /* return value */
1786 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
1787}
1788
1789static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1790 u16 value)
1791{
1792 struct fec_enet_private *fep = bus->priv;
1793 unsigned long time_left;
1794
1795 fep->mii_timeout = 0;
1796 init_completion(&fep->mdio_done);
1797
1798 /* start a write op */
1799 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
1800 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1801 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1802 fep->hwp + FEC_MII_DATA);
1803
1804 /* wait for end of transfer */
1805 time_left = wait_for_completion_timeout(&fep->mdio_done,
1806 usecs_to_jiffies(FEC_MII_TIMEOUT));
1807 if (time_left == 0) {
1808 fep->mii_timeout = 1;
1809 netdev_err(fep->netdev, "MDIO write timeout\n");
1810 return -ETIMEDOUT;
1811 }
1812
1813 return 0;
1814}
1815
1816static int fec_enet_clk_enable(struct net_device *ndev, bool enable)
1817{
1818 struct fec_enet_private *fep = netdev_priv(ndev);
1819 int ret;
1820
1821 if (enable) {
1822 ret = clk_prepare_enable(fep->clk_ahb);
1823 if (ret)
1824 return ret;
1825 ret = clk_prepare_enable(fep->clk_ipg);
1826 if (ret)
1827 goto failed_clk_ipg;
1828 if (fep->clk_enet_out) {
1829 ret = clk_prepare_enable(fep->clk_enet_out);
1830 if (ret)
1831 goto failed_clk_enet_out;
1832 }
1833 if (fep->clk_ptp) {
1834 mutex_lock(&fep->ptp_clk_mutex);
1835 ret = clk_prepare_enable(fep->clk_ptp);
1836 if (ret) {
1837 mutex_unlock(&fep->ptp_clk_mutex);
1838 goto failed_clk_ptp;
1839 } else {
1840 fep->ptp_clk_on = true;
1841 }
1842 mutex_unlock(&fep->ptp_clk_mutex);
1843 }
1844 if (fep->clk_ref) {
1845 ret = clk_prepare_enable(fep->clk_ref);
1846 if (ret)
1847 goto failed_clk_ref;
1848 }
1849 } else {
1850 clk_disable_unprepare(fep->clk_ahb);
1851 clk_disable_unprepare(fep->clk_ipg);
1852 if (fep->clk_enet_out)
1853 clk_disable_unprepare(fep->clk_enet_out);
1854 if (fep->clk_ptp) {
1855 mutex_lock(&fep->ptp_clk_mutex);
1856 clk_disable_unprepare(fep->clk_ptp);
1857 fep->ptp_clk_on = false;
1858 mutex_unlock(&fep->ptp_clk_mutex);
1859 }
1860 if (fep->clk_ref)
1861 clk_disable_unprepare(fep->clk_ref);
1862 }
1863
1864 return 0;
1865
1866failed_clk_ref:
1867 if (fep->clk_ref)
1868 clk_disable_unprepare(fep->clk_ref);
1869failed_clk_ptp:
1870 if (fep->clk_enet_out)
1871 clk_disable_unprepare(fep->clk_enet_out);
1872failed_clk_enet_out:
1873 clk_disable_unprepare(fep->clk_ipg);
1874failed_clk_ipg:
1875 clk_disable_unprepare(fep->clk_ahb);
1876
1877 return ret;
1878}
1879
1880static int fec_enet_mii_probe(struct net_device *ndev)
1881{
1882 struct fec_enet_private *fep = netdev_priv(ndev);
1883 struct phy_device *phy_dev = NULL;
1884 char mdio_bus_id[MII_BUS_ID_SIZE];
1885 char phy_name[MII_BUS_ID_SIZE + 3];
1886 int phy_id;
1887 int dev_id = fep->dev_id;
1888
1889 fep->phy_dev = NULL;
1890
1891 if (fep->phy_node) {
1892 phy_dev = of_phy_connect(ndev, fep->phy_node,
1893 &fec_enet_adjust_link, 0,
1894 fep->phy_interface);
1895 if (!phy_dev)
1896 return -ENODEV;
1897 } else {
1898 /* check for attached phy */
1899 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
1900 if ((fep->mii_bus->phy_mask & (1 << phy_id)))
1901 continue;
1902 if (fep->mii_bus->phy_map[phy_id] == NULL)
1903 continue;
1904 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
1905 continue;
1906 if (dev_id--)
1907 continue;
1908 strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
1909 break;
1910 }
1911
1912 if (phy_id >= PHY_MAX_ADDR) {
1913 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
1914 strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
1915 phy_id = 0;
1916 }
1917
1918 snprintf(phy_name, sizeof(phy_name),
1919 PHY_ID_FMT, mdio_bus_id, phy_id);
1920 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
1921 fep->phy_interface);
1922 }
1923
1924 if (IS_ERR(phy_dev)) {
1925 netdev_err(ndev, "could not attach to PHY\n");
1926 return PTR_ERR(phy_dev);
1927 }
1928
1929 /* mask with MAC supported features */
1930 if (fep->quirks & FEC_QUIRK_HAS_GBIT) {
1931 phy_dev->supported &= PHY_GBIT_FEATURES;
1932 phy_dev->supported &= ~SUPPORTED_1000baseT_Half;
1933#if !defined(CONFIG_M5272)
1934 phy_dev->supported |= SUPPORTED_Pause;
1935#endif
1936 }
1937 else
1938 phy_dev->supported &= PHY_BASIC_FEATURES;
1939
1940 phy_dev->advertising = phy_dev->supported;
1941
1942 fep->phy_dev = phy_dev;
1943 fep->link = 0;
1944 fep->full_duplex = 0;
1945
1946 netdev_info(ndev, "Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1947 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
1948 fep->phy_dev->irq);
1949
1950 return 0;
1951}
1952
1953static int fec_enet_mii_init(struct platform_device *pdev)
1954{
1955 static struct mii_bus *fec0_mii_bus;
1956 struct net_device *ndev = platform_get_drvdata(pdev);
1957 struct fec_enet_private *fep = netdev_priv(ndev);
1958 struct device_node *node;
1959 int err = -ENXIO, i;
1960 u32 mii_speed, holdtime;
1961
1962 /*
1963 * The i.MX28 dual fec interfaces are not equal.
1964 * Here are the differences:
1965 *
1966 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1967 * - fec0 acts as the 1588 time master while fec1 is slave
1968 * - external phys can only be configured by fec0
1969 *
1970 * That is to say fec1 can not work independently. It only works
1971 * when fec0 is working. The reason behind this design is that the
1972 * second interface is added primarily for Switch mode.
1973 *
1974 * Because of the last point above, both phys are attached on fec0
1975 * mdio interface in board design, and need to be configured by
1976 * fec0 mii_bus.
1977 */
1978 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) {
1979 /* fec1 uses fec0 mii_bus */
1980 if (mii_cnt && fec0_mii_bus) {
1981 fep->mii_bus = fec0_mii_bus;
1982 mii_cnt++;
1983 return 0;
1984 }
1985 return -ENOENT;
1986 }
1987
1988 fep->mii_timeout = 0;
1989
1990 /*
1991 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
1992 *
1993 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
1994 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
1995 * Reference Manual has an error on this, and gets fixed on i.MX6Q
1996 * document.
1997 */
1998 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000);
1999 if (fep->quirks & FEC_QUIRK_ENET_MAC)
2000 mii_speed--;
2001 if (mii_speed > 63) {
2002 dev_err(&pdev->dev,
2003 "fec clock (%lu) to fast to get right mii speed\n",
2004 clk_get_rate(fep->clk_ipg));
2005 err = -EINVAL;
2006 goto err_out;
2007 }
2008
2009 /*
2010 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka
2011 * MII_SPEED) register that defines the MDIO output hold time. Earlier
2012 * versions are RAZ there, so just ignore the difference and write the
2013 * register always.
2014 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
2015 * HOLDTIME + 1 is the number of clk cycles the fec is holding the
2016 * output.
2017 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
2018 * Given that ceil(clkrate / 5000000) <= 64, the calculation for
2019 * holdtime cannot result in a value greater than 3.
2020 */
2021 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1;
2022
2023 fep->phy_speed = mii_speed << 1 | holdtime << 8;
2024
2025 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
2026
2027 fep->mii_bus = mdiobus_alloc();
2028 if (fep->mii_bus == NULL) {
2029 err = -ENOMEM;
2030 goto err_out;
2031 }
2032
2033 fep->mii_bus->name = "fec_enet_mii_bus";
2034 fep->mii_bus->read = fec_enet_mdio_read;
2035 fep->mii_bus->write = fec_enet_mdio_write;
2036 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2037 pdev->name, fep->dev_id + 1);
2038 fep->mii_bus->priv = fep;
2039 fep->mii_bus->parent = &pdev->dev;
2040
2041 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
2042 if (!fep->mii_bus->irq) {
2043 err = -ENOMEM;
2044 goto err_out_free_mdiobus;
2045 }
2046
2047 for (i = 0; i < PHY_MAX_ADDR; i++)
2048 fep->mii_bus->irq[i] = PHY_POLL;
2049
2050 node = of_get_child_by_name(pdev->dev.of_node, "mdio");
2051 if (node) {
2052 err = of_mdiobus_register(fep->mii_bus, node);
2053 of_node_put(node);
2054 } else {
2055 err = mdiobus_register(fep->mii_bus);
2056 }
2057
2058 if (err)
2059 goto err_out_free_mdio_irq;
2060
2061 mii_cnt++;
2062
2063 /* save fec0 mii_bus */
2064 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO)
2065 fec0_mii_bus = fep->mii_bus;
2066
2067 return 0;
2068
2069err_out_free_mdio_irq:
2070 kfree(fep->mii_bus->irq);
2071err_out_free_mdiobus:
2072 mdiobus_free(fep->mii_bus);
2073err_out:
2074 return err;
2075}
2076
2077static void fec_enet_mii_remove(struct fec_enet_private *fep)
2078{
2079 if (--mii_cnt == 0) {
2080 mdiobus_unregister(fep->mii_bus);
2081 kfree(fep->mii_bus->irq);
2082 mdiobus_free(fep->mii_bus);
2083 }
2084}
2085
2086static int fec_enet_get_settings(struct net_device *ndev,
2087 struct ethtool_cmd *cmd)
2088{
2089 struct fec_enet_private *fep = netdev_priv(ndev);
2090 struct phy_device *phydev = fep->phy_dev;
2091
2092 if (!phydev)
2093 return -ENODEV;
2094
2095 return phy_ethtool_gset(phydev, cmd);
2096}
2097
2098static int fec_enet_set_settings(struct net_device *ndev,
2099 struct ethtool_cmd *cmd)
2100{
2101 struct fec_enet_private *fep = netdev_priv(ndev);
2102 struct phy_device *phydev = fep->phy_dev;
2103
2104 if (!phydev)
2105 return -ENODEV;
2106
2107 return phy_ethtool_sset(phydev, cmd);
2108}
2109
2110static void fec_enet_get_drvinfo(struct net_device *ndev,
2111 struct ethtool_drvinfo *info)
2112{
2113 struct fec_enet_private *fep = netdev_priv(ndev);
2114
2115 strlcpy(info->driver, fep->pdev->dev.driver->name,
2116 sizeof(info->driver));
2117 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
2118 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
2119}
2120
2121static int fec_enet_get_ts_info(struct net_device *ndev,
2122 struct ethtool_ts_info *info)
2123{
2124 struct fec_enet_private *fep = netdev_priv(ndev);
2125
2126 if (fep->bufdesc_ex) {
2127
2128 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
2129 SOF_TIMESTAMPING_RX_SOFTWARE |
2130 SOF_TIMESTAMPING_SOFTWARE |
2131 SOF_TIMESTAMPING_TX_HARDWARE |
2132 SOF_TIMESTAMPING_RX_HARDWARE |
2133 SOF_TIMESTAMPING_RAW_HARDWARE;
2134 if (fep->ptp_clock)
2135 info->phc_index = ptp_clock_index(fep->ptp_clock);
2136 else
2137 info->phc_index = -1;
2138
2139 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
2140 (1 << HWTSTAMP_TX_ON);
2141
2142 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
2143 (1 << HWTSTAMP_FILTER_ALL);
2144 return 0;
2145 } else {
2146 return ethtool_op_get_ts_info(ndev, info);
2147 }
2148}
2149
2150#if !defined(CONFIG_M5272)
2151
2152static void fec_enet_get_pauseparam(struct net_device *ndev,
2153 struct ethtool_pauseparam *pause)
2154{
2155 struct fec_enet_private *fep = netdev_priv(ndev);
2156
2157 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
2158 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
2159 pause->rx_pause = pause->tx_pause;
2160}
2161
2162static int fec_enet_set_pauseparam(struct net_device *ndev,
2163 struct ethtool_pauseparam *pause)
2164{
2165 struct fec_enet_private *fep = netdev_priv(ndev);
2166
2167 if (!fep->phy_dev)
2168 return -ENODEV;
2169
2170 if (pause->tx_pause != pause->rx_pause) {
2171 netdev_info(ndev,
2172 "hardware only support enable/disable both tx and rx");
2173 return -EINVAL;
2174 }
2175
2176 fep->pause_flag = 0;
2177
2178 /* tx pause must be same as rx pause */
2179 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
2180 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
2181
2182 if (pause->rx_pause || pause->autoneg) {
2183 fep->phy_dev->supported |= ADVERTISED_Pause;
2184 fep->phy_dev->advertising |= ADVERTISED_Pause;
2185 } else {
2186 fep->phy_dev->supported &= ~ADVERTISED_Pause;
2187 fep->phy_dev->advertising &= ~ADVERTISED_Pause;
2188 }
2189
2190 if (pause->autoneg) {
2191 if (netif_running(ndev))
2192 fec_stop(ndev);
2193 phy_start_aneg(fep->phy_dev);
2194 }
2195 if (netif_running(ndev)) {
2196 napi_disable(&fep->napi);
2197 netif_tx_lock_bh(ndev);
2198 fec_restart(ndev);
2199 netif_wake_queue(ndev);
2200 netif_tx_unlock_bh(ndev);
2201 napi_enable(&fep->napi);
2202 }
2203
2204 return 0;
2205}
2206
2207static const struct fec_stat {
2208 char name[ETH_GSTRING_LEN];
2209 u16 offset;
2210} fec_stats[] = {
2211 /* RMON TX */
2212 { "tx_dropped", RMON_T_DROP },
2213 { "tx_packets", RMON_T_PACKETS },
2214 { "tx_broadcast", RMON_T_BC_PKT },
2215 { "tx_multicast", RMON_T_MC_PKT },
2216 { "tx_crc_errors", RMON_T_CRC_ALIGN },
2217 { "tx_undersize", RMON_T_UNDERSIZE },
2218 { "tx_oversize", RMON_T_OVERSIZE },
2219 { "tx_fragment", RMON_T_FRAG },
2220 { "tx_jabber", RMON_T_JAB },
2221 { "tx_collision", RMON_T_COL },
2222 { "tx_64byte", RMON_T_P64 },
2223 { "tx_65to127byte", RMON_T_P65TO127 },
2224 { "tx_128to255byte", RMON_T_P128TO255 },
2225 { "tx_256to511byte", RMON_T_P256TO511 },
2226 { "tx_512to1023byte", RMON_T_P512TO1023 },
2227 { "tx_1024to2047byte", RMON_T_P1024TO2047 },
2228 { "tx_GTE2048byte", RMON_T_P_GTE2048 },
2229 { "tx_octets", RMON_T_OCTETS },
2230
2231 /* IEEE TX */
2232 { "IEEE_tx_drop", IEEE_T_DROP },
2233 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
2234 { "IEEE_tx_1col", IEEE_T_1COL },
2235 { "IEEE_tx_mcol", IEEE_T_MCOL },
2236 { "IEEE_tx_def", IEEE_T_DEF },
2237 { "IEEE_tx_lcol", IEEE_T_LCOL },
2238 { "IEEE_tx_excol", IEEE_T_EXCOL },
2239 { "IEEE_tx_macerr", IEEE_T_MACERR },
2240 { "IEEE_tx_cserr", IEEE_T_CSERR },
2241 { "IEEE_tx_sqe", IEEE_T_SQE },
2242 { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
2243 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
2244
2245 /* RMON RX */
2246 { "rx_packets", RMON_R_PACKETS },
2247 { "rx_broadcast", RMON_R_BC_PKT },
2248 { "rx_multicast", RMON_R_MC_PKT },
2249 { "rx_crc_errors", RMON_R_CRC_ALIGN },
2250 { "rx_undersize", RMON_R_UNDERSIZE },
2251 { "rx_oversize", RMON_R_OVERSIZE },
2252 { "rx_fragment", RMON_R_FRAG },
2253 { "rx_jabber", RMON_R_JAB },
2254 { "rx_64byte", RMON_R_P64 },
2255 { "rx_65to127byte", RMON_R_P65TO127 },
2256 { "rx_128to255byte", RMON_R_P128TO255 },
2257 { "rx_256to511byte", RMON_R_P256TO511 },
2258 { "rx_512to1023byte", RMON_R_P512TO1023 },
2259 { "rx_1024to2047byte", RMON_R_P1024TO2047 },
2260 { "rx_GTE2048byte", RMON_R_P_GTE2048 },
2261 { "rx_octets", RMON_R_OCTETS },
2262
2263 /* IEEE RX */
2264 { "IEEE_rx_drop", IEEE_R_DROP },
2265 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
2266 { "IEEE_rx_crc", IEEE_R_CRC },
2267 { "IEEE_rx_align", IEEE_R_ALIGN },
2268 { "IEEE_rx_macerr", IEEE_R_MACERR },
2269 { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
2270 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
2271};
2272
2273static void fec_enet_get_ethtool_stats(struct net_device *dev,
2274 struct ethtool_stats *stats, u64 *data)
2275{
2276 struct fec_enet_private *fep = netdev_priv(dev);
2277 int i;
2278
2279 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2280 data[i] = readl(fep->hwp + fec_stats[i].offset);
2281}
2282
2283static void fec_enet_get_strings(struct net_device *netdev,
2284 u32 stringset, u8 *data)
2285{
2286 int i;
2287 switch (stringset) {
2288 case ETH_SS_STATS:
2289 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2290 memcpy(data + i * ETH_GSTRING_LEN,
2291 fec_stats[i].name, ETH_GSTRING_LEN);
2292 break;
2293 }
2294}
2295
2296static int fec_enet_get_sset_count(struct net_device *dev, int sset)
2297{
2298 switch (sset) {
2299 case ETH_SS_STATS:
2300 return ARRAY_SIZE(fec_stats);
2301 default:
2302 return -EOPNOTSUPP;
2303 }
2304}
2305#endif /* !defined(CONFIG_M5272) */
2306
2307static int fec_enet_nway_reset(struct net_device *dev)
2308{
2309 struct fec_enet_private *fep = netdev_priv(dev);
2310 struct phy_device *phydev = fep->phy_dev;
2311
2312 if (!phydev)
2313 return -ENODEV;
2314
2315 return genphy_restart_aneg(phydev);
2316}
2317
2318/* ITR clock source is enet system clock (clk_ahb).
2319 * TCTT unit is cycle_ns * 64 cycle
2320 * So, the ICTT value = X us / (cycle_ns * 64)
2321 */
2322static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us)
2323{
2324 struct fec_enet_private *fep = netdev_priv(ndev);
2325
2326 return us * (fep->itr_clk_rate / 64000) / 1000;
2327}
2328
2329/* Set threshold for interrupt coalescing */
2330static void fec_enet_itr_coal_set(struct net_device *ndev)
2331{
2332 struct fec_enet_private *fep = netdev_priv(ndev);
2333 int rx_itr, tx_itr;
2334
2335 if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
2336 return;
2337
2338 /* Must be greater than zero to avoid unpredictable behavior */
2339 if (!fep->rx_time_itr || !fep->rx_pkts_itr ||
2340 !fep->tx_time_itr || !fep->tx_pkts_itr)
2341 return;
2342
2343 /* Select enet system clock as Interrupt Coalescing
2344 * timer Clock Source
2345 */
2346 rx_itr = FEC_ITR_CLK_SEL;
2347 tx_itr = FEC_ITR_CLK_SEL;
2348
2349 /* set ICFT and ICTT */
2350 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr);
2351 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr));
2352 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr);
2353 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr));
2354
2355 rx_itr |= FEC_ITR_EN;
2356 tx_itr |= FEC_ITR_EN;
2357
2358 writel(tx_itr, fep->hwp + FEC_TXIC0);
2359 writel(rx_itr, fep->hwp + FEC_RXIC0);
2360 writel(tx_itr, fep->hwp + FEC_TXIC1);
2361 writel(rx_itr, fep->hwp + FEC_RXIC1);
2362 writel(tx_itr, fep->hwp + FEC_TXIC2);
2363 writel(rx_itr, fep->hwp + FEC_RXIC2);
2364}
2365
2366static int
2367fec_enet_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2368{
2369 struct fec_enet_private *fep = netdev_priv(ndev);
2370
2371 if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
2372 return -EOPNOTSUPP;
2373
2374 ec->rx_coalesce_usecs = fep->rx_time_itr;
2375 ec->rx_max_coalesced_frames = fep->rx_pkts_itr;
2376
2377 ec->tx_coalesce_usecs = fep->tx_time_itr;
2378 ec->tx_max_coalesced_frames = fep->tx_pkts_itr;
2379
2380 return 0;
2381}
2382
2383static int
2384fec_enet_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2385{
2386 struct fec_enet_private *fep = netdev_priv(ndev);
2387 unsigned int cycle;
2388
2389 if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
2390 return -EOPNOTSUPP;
2391
2392 if (ec->rx_max_coalesced_frames > 255) {
2393 pr_err("Rx coalesced frames exceed hardware limiation");
2394 return -EINVAL;
2395 }
2396
2397 if (ec->tx_max_coalesced_frames > 255) {
2398 pr_err("Tx coalesced frame exceed hardware limiation");
2399 return -EINVAL;
2400 }
2401
2402 cycle = fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr);
2403 if (cycle > 0xFFFF) {
2404 pr_err("Rx coalesed usec exceeed hardware limiation");
2405 return -EINVAL;
2406 }
2407
2408 cycle = fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr);
2409 if (cycle > 0xFFFF) {
2410 pr_err("Rx coalesed usec exceeed hardware limiation");
2411 return -EINVAL;
2412 }
2413
2414 fep->rx_time_itr = ec->rx_coalesce_usecs;
2415 fep->rx_pkts_itr = ec->rx_max_coalesced_frames;
2416
2417 fep->tx_time_itr = ec->tx_coalesce_usecs;
2418 fep->tx_pkts_itr = ec->tx_max_coalesced_frames;
2419
2420 fec_enet_itr_coal_set(ndev);
2421
2422 return 0;
2423}
2424
2425static void fec_enet_itr_coal_init(struct net_device *ndev)
2426{
2427 struct ethtool_coalesce ec;
2428
2429 ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2430 ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2431
2432 ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2433 ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2434
2435 fec_enet_set_coalesce(ndev, &ec);
2436}
2437
2438static int fec_enet_get_tunable(struct net_device *netdev,
2439 const struct ethtool_tunable *tuna,
2440 void *data)
2441{
2442 struct fec_enet_private *fep = netdev_priv(netdev);
2443 int ret = 0;
2444
2445 switch (tuna->id) {
2446 case ETHTOOL_RX_COPYBREAK:
2447 *(u32 *)data = fep->rx_copybreak;
2448 break;
2449 default:
2450 ret = -EINVAL;
2451 break;
2452 }
2453
2454 return ret;
2455}
2456
2457static int fec_enet_set_tunable(struct net_device *netdev,
2458 const struct ethtool_tunable *tuna,
2459 const void *data)
2460{
2461 struct fec_enet_private *fep = netdev_priv(netdev);
2462 int ret = 0;
2463
2464 switch (tuna->id) {
2465 case ETHTOOL_RX_COPYBREAK:
2466 fep->rx_copybreak = *(u32 *)data;
2467 break;
2468 default:
2469 ret = -EINVAL;
2470 break;
2471 }
2472
2473 return ret;
2474}
2475
2476static void
2477fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2478{
2479 struct fec_enet_private *fep = netdev_priv(ndev);
2480
2481 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) {
2482 wol->supported = WAKE_MAGIC;
2483 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0;
2484 } else {
2485 wol->supported = wol->wolopts = 0;
2486 }
2487}
2488
2489static int
2490fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2491{
2492 struct fec_enet_private *fep = netdev_priv(ndev);
2493
2494 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET))
2495 return -EINVAL;
2496
2497 if (wol->wolopts & ~WAKE_MAGIC)
2498 return -EINVAL;
2499
2500 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC);
2501 if (device_may_wakeup(&ndev->dev)) {
2502 fep->wol_flag |= FEC_WOL_FLAG_ENABLE;
2503 if (fep->irq[0] > 0)
2504 enable_irq_wake(fep->irq[0]);
2505 } else {
2506 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE);
2507 if (fep->irq[0] > 0)
2508 disable_irq_wake(fep->irq[0]);
2509 }
2510
2511 return 0;
2512}
2513
2514static const struct ethtool_ops fec_enet_ethtool_ops = {
2515 .get_settings = fec_enet_get_settings,
2516 .set_settings = fec_enet_set_settings,
2517 .get_drvinfo = fec_enet_get_drvinfo,
2518 .nway_reset = fec_enet_nway_reset,
2519 .get_link = ethtool_op_get_link,
2520 .get_coalesce = fec_enet_get_coalesce,
2521 .set_coalesce = fec_enet_set_coalesce,
2522#ifndef CONFIG_M5272
2523 .get_pauseparam = fec_enet_get_pauseparam,
2524 .set_pauseparam = fec_enet_set_pauseparam,
2525 .get_strings = fec_enet_get_strings,
2526 .get_ethtool_stats = fec_enet_get_ethtool_stats,
2527 .get_sset_count = fec_enet_get_sset_count,
2528#endif
2529 .get_ts_info = fec_enet_get_ts_info,
2530 .get_tunable = fec_enet_get_tunable,
2531 .set_tunable = fec_enet_set_tunable,
2532 .get_wol = fec_enet_get_wol,
2533 .set_wol = fec_enet_set_wol,
2534};
2535
2536static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2537{
2538 struct fec_enet_private *fep = netdev_priv(ndev);
2539 struct phy_device *phydev = fep->phy_dev;
2540
2541 if (!netif_running(ndev))
2542 return -EINVAL;
2543
2544 if (!phydev)
2545 return -ENODEV;
2546
2547 if (fep->bufdesc_ex) {
2548 if (cmd == SIOCSHWTSTAMP)
2549 return fec_ptp_set(ndev, rq);
2550 if (cmd == SIOCGHWTSTAMP)
2551 return fec_ptp_get(ndev, rq);
2552 }
2553
2554 return phy_mii_ioctl(phydev, rq, cmd);
2555}
2556
2557static void fec_enet_free_buffers(struct net_device *ndev)
2558{
2559 struct fec_enet_private *fep = netdev_priv(ndev);
2560 unsigned int i;
2561 struct sk_buff *skb;
2562 struct bufdesc *bdp;
2563 struct fec_enet_priv_tx_q *txq;
2564 struct fec_enet_priv_rx_q *rxq;
2565 unsigned int q;
2566
2567 for (q = 0; q < fep->num_rx_queues; q++) {
2568 rxq = fep->rx_queue[q];
2569 bdp = rxq->rx_bd_base;
2570 for (i = 0; i < rxq->rx_ring_size; i++) {
2571 skb = rxq->rx_skbuff[i];
2572 rxq->rx_skbuff[i] = NULL;
2573 if (skb) {
2574 dma_unmap_single(&fep->pdev->dev,
2575 bdp->cbd_bufaddr,
2576 FEC_ENET_RX_FRSIZE - fep->rx_align,
2577 DMA_FROM_DEVICE);
2578 dev_kfree_skb(skb);
2579 }
2580 bdp = fec_enet_get_nextdesc(bdp, fep, q);
2581 }
2582 }
2583
2584 for (q = 0; q < fep->num_tx_queues; q++) {
2585 txq = fep->tx_queue[q];
2586 bdp = txq->tx_bd_base;
2587 for (i = 0; i < txq->tx_ring_size; i++) {
2588 kfree(txq->tx_bounce[i]);
2589 txq->tx_bounce[i] = NULL;
2590 skb = txq->tx_skbuff[i];
2591 txq->tx_skbuff[i] = NULL;
2592 dev_kfree_skb(skb);
2593 }
2594 }
2595}
2596
2597static void fec_enet_free_queue(struct net_device *ndev)
2598{
2599 struct fec_enet_private *fep = netdev_priv(ndev);
2600 int i;
2601 struct fec_enet_priv_tx_q *txq;
2602
2603 for (i = 0; i < fep->num_tx_queues; i++)
2604 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) {
2605 txq = fep->tx_queue[i];
2606 dma_free_coherent(NULL,
2607 txq->tx_ring_size * TSO_HEADER_SIZE,
2608 txq->tso_hdrs,
2609 txq->tso_hdrs_dma);
2610 }
2611
2612 for (i = 0; i < fep->num_rx_queues; i++)
2613 kfree(fep->rx_queue[i]);
2614 for (i = 0; i < fep->num_tx_queues; i++)
2615 kfree(fep->tx_queue[i]);
2616}
2617
2618static int fec_enet_alloc_queue(struct net_device *ndev)
2619{
2620 struct fec_enet_private *fep = netdev_priv(ndev);
2621 int i;
2622 int ret = 0;
2623 struct fec_enet_priv_tx_q *txq;
2624
2625 for (i = 0; i < fep->num_tx_queues; i++) {
2626 txq = kzalloc(sizeof(*txq), GFP_KERNEL);
2627 if (!txq) {
2628 ret = -ENOMEM;
2629 goto alloc_failed;
2630 }
2631
2632 fep->tx_queue[i] = txq;
2633 txq->tx_ring_size = TX_RING_SIZE;
2634 fep->total_tx_ring_size += fep->tx_queue[i]->tx_ring_size;
2635
2636 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS;
2637 txq->tx_wake_threshold =
2638 (txq->tx_ring_size - txq->tx_stop_threshold) / 2;
2639
2640 txq->tso_hdrs = dma_alloc_coherent(NULL,
2641 txq->tx_ring_size * TSO_HEADER_SIZE,
2642 &txq->tso_hdrs_dma,
2643 GFP_KERNEL);
2644 if (!txq->tso_hdrs) {
2645 ret = -ENOMEM;
2646 goto alloc_failed;
2647 }
2648 }
2649
2650 for (i = 0; i < fep->num_rx_queues; i++) {
2651 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]),
2652 GFP_KERNEL);
2653 if (!fep->rx_queue[i]) {
2654 ret = -ENOMEM;
2655 goto alloc_failed;
2656 }
2657
2658 fep->rx_queue[i]->rx_ring_size = RX_RING_SIZE;
2659 fep->total_rx_ring_size += fep->rx_queue[i]->rx_ring_size;
2660 }
2661 return ret;
2662
2663alloc_failed:
2664 fec_enet_free_queue(ndev);
2665 return ret;
2666}
2667
2668static int
2669fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue)
2670{
2671 struct fec_enet_private *fep = netdev_priv(ndev);
2672 unsigned int i;
2673 struct sk_buff *skb;
2674 struct bufdesc *bdp;
2675 struct fec_enet_priv_rx_q *rxq;
2676
2677 rxq = fep->rx_queue[queue];
2678 bdp = rxq->rx_bd_base;
2679 for (i = 0; i < rxq->rx_ring_size; i++) {
2680 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
2681 if (!skb)
2682 goto err_alloc;
2683
2684 if (fec_enet_new_rxbdp(ndev, bdp, skb)) {
2685 dev_kfree_skb(skb);
2686 goto err_alloc;
2687 }
2688
2689 rxq->rx_skbuff[i] = skb;
2690 bdp->cbd_sc = BD_ENET_RX_EMPTY;
2691
2692 if (fep->bufdesc_ex) {
2693 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2694 ebdp->cbd_esc = BD_ENET_RX_INT;
2695 }
2696
2697 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
2698 }
2699
2700 /* Set the last buffer to wrap. */
2701 bdp = fec_enet_get_prevdesc(bdp, fep, queue);
2702 bdp->cbd_sc |= BD_SC_WRAP;
2703 return 0;
2704
2705 err_alloc:
2706 fec_enet_free_buffers(ndev);
2707 return -ENOMEM;
2708}
2709
2710static int
2711fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue)
2712{
2713 struct fec_enet_private *fep = netdev_priv(ndev);
2714 unsigned int i;
2715 struct bufdesc *bdp;
2716 struct fec_enet_priv_tx_q *txq;
2717
2718 txq = fep->tx_queue[queue];
2719 bdp = txq->tx_bd_base;
2720 for (i = 0; i < txq->tx_ring_size; i++) {
2721 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
2722 if (!txq->tx_bounce[i])
2723 goto err_alloc;
2724
2725 bdp->cbd_sc = 0;
2726 bdp->cbd_bufaddr = 0;
2727
2728 if (fep->bufdesc_ex) {
2729 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2730 ebdp->cbd_esc = BD_ENET_TX_INT;
2731 }
2732
2733 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
2734 }
2735
2736 /* Set the last buffer to wrap. */
2737 bdp = fec_enet_get_prevdesc(bdp, fep, queue);
2738 bdp->cbd_sc |= BD_SC_WRAP;
2739
2740 return 0;
2741
2742 err_alloc:
2743 fec_enet_free_buffers(ndev);
2744 return -ENOMEM;
2745}
2746
2747static int fec_enet_alloc_buffers(struct net_device *ndev)
2748{
2749 struct fec_enet_private *fep = netdev_priv(ndev);
2750 unsigned int i;
2751
2752 for (i = 0; i < fep->num_rx_queues; i++)
2753 if (fec_enet_alloc_rxq_buffers(ndev, i))
2754 return -ENOMEM;
2755
2756 for (i = 0; i < fep->num_tx_queues; i++)
2757 if (fec_enet_alloc_txq_buffers(ndev, i))
2758 return -ENOMEM;
2759 return 0;
2760}
2761
2762static int
2763fec_enet_open(struct net_device *ndev)
2764{
2765 struct fec_enet_private *fep = netdev_priv(ndev);
2766 int ret;
2767
2768 pinctrl_pm_select_default_state(&fep->pdev->dev);
2769 ret = fec_enet_clk_enable(ndev, true);
2770 if (ret)
2771 return ret;
2772
2773 /* I should reset the ring buffers here, but I don't yet know
2774 * a simple way to do that.
2775 */
2776
2777 ret = fec_enet_alloc_buffers(ndev);
2778 if (ret)
2779 goto err_enet_alloc;
2780
2781 /* Probe and connect to PHY when open the interface */
2782 ret = fec_enet_mii_probe(ndev);
2783 if (ret)
2784 goto err_enet_mii_probe;
2785
2786 fec_restart(ndev);
2787 napi_enable(&fep->napi);
2788 phy_start(fep->phy_dev);
2789 netif_tx_start_all_queues(ndev);
2790
2791 device_set_wakeup_enable(&ndev->dev, fep->wol_flag &
2792 FEC_WOL_FLAG_ENABLE);
2793
2794 return 0;
2795
2796err_enet_mii_probe:
2797 fec_enet_free_buffers(ndev);
2798err_enet_alloc:
2799 fec_enet_clk_enable(ndev, false);
2800 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2801 return ret;
2802}
2803
2804static int
2805fec_enet_close(struct net_device *ndev)
2806{
2807 struct fec_enet_private *fep = netdev_priv(ndev);
2808
2809 phy_stop(fep->phy_dev);
2810
2811 if (netif_device_present(ndev)) {
2812 napi_disable(&fep->napi);
2813 netif_tx_disable(ndev);
2814 fec_stop(ndev);
2815 }
2816
2817 phy_disconnect(fep->phy_dev);
2818 fep->phy_dev = NULL;
2819
2820 fec_enet_clk_enable(ndev, false);
2821 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2822 fec_enet_free_buffers(ndev);
2823
2824 return 0;
2825}
2826
2827/* Set or clear the multicast filter for this adaptor.
2828 * Skeleton taken from sunlance driver.
2829 * The CPM Ethernet implementation allows Multicast as well as individual
2830 * MAC address filtering. Some of the drivers check to make sure it is
2831 * a group multicast address, and discard those that are not. I guess I
2832 * will do the same for now, but just remove the test if you want
2833 * individual filtering as well (do the upper net layers want or support
2834 * this kind of feature?).
2835 */
2836
2837#define HASH_BITS 6 /* #bits in hash */
2838#define CRC32_POLY 0xEDB88320
2839
2840static void set_multicast_list(struct net_device *ndev)
2841{
2842 struct fec_enet_private *fep = netdev_priv(ndev);
2843 struct netdev_hw_addr *ha;
2844 unsigned int i, bit, data, crc, tmp;
2845 unsigned char hash;
2846
2847 if (ndev->flags & IFF_PROMISC) {
2848 tmp = readl(fep->hwp + FEC_R_CNTRL);
2849 tmp |= 0x8;
2850 writel(tmp, fep->hwp + FEC_R_CNTRL);
2851 return;
2852 }
2853
2854 tmp = readl(fep->hwp + FEC_R_CNTRL);
2855 tmp &= ~0x8;
2856 writel(tmp, fep->hwp + FEC_R_CNTRL);
2857
2858 if (ndev->flags & IFF_ALLMULTI) {
2859 /* Catch all multicast addresses, so set the
2860 * filter to all 1's
2861 */
2862 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2863 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2864
2865 return;
2866 }
2867
2868 /* Clear filter and add the addresses in hash register
2869 */
2870 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2871 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2872
2873 netdev_for_each_mc_addr(ha, ndev) {
2874 /* calculate crc32 value of mac address */
2875 crc = 0xffffffff;
2876
2877 for (i = 0; i < ndev->addr_len; i++) {
2878 data = ha->addr[i];
2879 for (bit = 0; bit < 8; bit++, data >>= 1) {
2880 crc = (crc >> 1) ^
2881 (((crc ^ data) & 1) ? CRC32_POLY : 0);
2882 }
2883 }
2884
2885 /* only upper 6 bits (HASH_BITS) are used
2886 * which point to specific bit in he hash registers
2887 */
2888 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
2889
2890 if (hash > 31) {
2891 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2892 tmp |= 1 << (hash - 32);
2893 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2894 } else {
2895 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2896 tmp |= 1 << hash;
2897 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2898 }
2899 }
2900}
2901
2902/* Set a MAC change in hardware. */
2903static int
2904fec_set_mac_address(struct net_device *ndev, void *p)
2905{
2906 struct fec_enet_private *fep = netdev_priv(ndev);
2907 struct sockaddr *addr = p;
2908
2909 if (addr) {
2910 if (!is_valid_ether_addr(addr->sa_data))
2911 return -EADDRNOTAVAIL;
2912 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
2913 }
2914
2915 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
2916 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
2917 fep->hwp + FEC_ADDR_LOW);
2918 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
2919 fep->hwp + FEC_ADDR_HIGH);
2920 return 0;
2921}
2922
2923#ifdef CONFIG_NET_POLL_CONTROLLER
2924/**
2925 * fec_poll_controller - FEC Poll controller function
2926 * @dev: The FEC network adapter
2927 *
2928 * Polled functionality used by netconsole and others in non interrupt mode
2929 *
2930 */
2931static void fec_poll_controller(struct net_device *dev)
2932{
2933 int i;
2934 struct fec_enet_private *fep = netdev_priv(dev);
2935
2936 for (i = 0; i < FEC_IRQ_NUM; i++) {
2937 if (fep->irq[i] > 0) {
2938 disable_irq(fep->irq[i]);
2939 fec_enet_interrupt(fep->irq[i], dev);
2940 enable_irq(fep->irq[i]);
2941 }
2942 }
2943}
2944#endif
2945
2946#define FEATURES_NEED_QUIESCE NETIF_F_RXCSUM
2947static inline void fec_enet_set_netdev_features(struct net_device *netdev,
2948 netdev_features_t features)
2949{
2950 struct fec_enet_private *fep = netdev_priv(netdev);
2951 netdev_features_t changed = features ^ netdev->features;
2952
2953 netdev->features = features;
2954
2955 /* Receive checksum has been changed */
2956 if (changed & NETIF_F_RXCSUM) {
2957 if (features & NETIF_F_RXCSUM)
2958 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
2959 else
2960 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
2961 }
2962}
2963
2964static int fec_set_features(struct net_device *netdev,
2965 netdev_features_t features)
2966{
2967 struct fec_enet_private *fep = netdev_priv(netdev);
2968 netdev_features_t changed = features ^ netdev->features;
2969
2970 if (netif_running(netdev) && changed & FEATURES_NEED_QUIESCE) {
2971 napi_disable(&fep->napi);
2972 netif_tx_lock_bh(netdev);
2973 fec_stop(netdev);
2974 fec_enet_set_netdev_features(netdev, features);
2975 fec_restart(netdev);
2976 netif_tx_wake_all_queues(netdev);
2977 netif_tx_unlock_bh(netdev);
2978 napi_enable(&fep->napi);
2979 } else {
2980 fec_enet_set_netdev_features(netdev, features);
2981 }
2982
2983 return 0;
2984}
2985
2986static const struct net_device_ops fec_netdev_ops = {
2987 .ndo_open = fec_enet_open,
2988 .ndo_stop = fec_enet_close,
2989 .ndo_start_xmit = fec_enet_start_xmit,
2990 .ndo_set_rx_mode = set_multicast_list,
2991 .ndo_change_mtu = eth_change_mtu,
2992 .ndo_validate_addr = eth_validate_addr,
2993 .ndo_tx_timeout = fec_timeout,
2994 .ndo_set_mac_address = fec_set_mac_address,
2995 .ndo_do_ioctl = fec_enet_ioctl,
2996#ifdef CONFIG_NET_POLL_CONTROLLER
2997 .ndo_poll_controller = fec_poll_controller,
2998#endif
2999 .ndo_set_features = fec_set_features,
3000};
3001
3002 /*
3003 * XXX: We need to clean up on failure exits here.
3004 *
3005 */
3006static int fec_enet_init(struct net_device *ndev)
3007{
3008 struct fec_enet_private *fep = netdev_priv(ndev);
3009 struct fec_enet_priv_tx_q *txq;
3010 struct fec_enet_priv_rx_q *rxq;
3011 struct bufdesc *cbd_base;
3012 dma_addr_t bd_dma;
3013 int bd_size;
3014 unsigned int i;
3015
3016#if defined(CONFIG_ARM)
3017 fep->rx_align = 0xf;
3018 fep->tx_align = 0xf;
3019#else
3020 fep->rx_align = 0x3;
3021 fep->tx_align = 0x3;
3022#endif
3023
3024 fec_enet_alloc_queue(ndev);
3025
3026 if (fep->bufdesc_ex)
3027 fep->bufdesc_size = sizeof(struct bufdesc_ex);
3028 else
3029 fep->bufdesc_size = sizeof(struct bufdesc);
3030 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) *
3031 fep->bufdesc_size;
3032
3033 /* Allocate memory for buffer descriptors. */
3034 cbd_base = dma_alloc_coherent(NULL, bd_size, &bd_dma,
3035 GFP_KERNEL);
3036 if (!cbd_base) {
3037 return -ENOMEM;
3038 }
3039
3040 memset(cbd_base, 0, bd_size);
3041
3042 /* Get the Ethernet address */
3043 fec_get_mac(ndev);
3044 /* make sure MAC we just acquired is programmed into the hw */
3045 fec_set_mac_address(ndev, NULL);
3046
3047 /* Set receive and transmit descriptor base. */
3048 for (i = 0; i < fep->num_rx_queues; i++) {
3049 rxq = fep->rx_queue[i];
3050 rxq->index = i;
3051 rxq->rx_bd_base = (struct bufdesc *)cbd_base;
3052 rxq->bd_dma = bd_dma;
3053 if (fep->bufdesc_ex) {
3054 bd_dma += sizeof(struct bufdesc_ex) * rxq->rx_ring_size;
3055 cbd_base = (struct bufdesc *)
3056 (((struct bufdesc_ex *)cbd_base) + rxq->rx_ring_size);
3057 } else {
3058 bd_dma += sizeof(struct bufdesc) * rxq->rx_ring_size;
3059 cbd_base += rxq->rx_ring_size;
3060 }
3061 }
3062
3063 for (i = 0; i < fep->num_tx_queues; i++) {
3064 txq = fep->tx_queue[i];
3065 txq->index = i;
3066 txq->tx_bd_base = (struct bufdesc *)cbd_base;
3067 txq->bd_dma = bd_dma;
3068 if (fep->bufdesc_ex) {
3069 bd_dma += sizeof(struct bufdesc_ex) * txq->tx_ring_size;
3070 cbd_base = (struct bufdesc *)
3071 (((struct bufdesc_ex *)cbd_base) + txq->tx_ring_size);
3072 } else {
3073 bd_dma += sizeof(struct bufdesc) * txq->tx_ring_size;
3074 cbd_base += txq->tx_ring_size;
3075 }
3076 }
3077
3078
3079 /* The FEC Ethernet specific entries in the device structure */
3080 ndev->watchdog_timeo = TX_TIMEOUT;
3081 ndev->netdev_ops = &fec_netdev_ops;
3082 ndev->ethtool_ops = &fec_enet_ethtool_ops;
3083
3084 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
3085 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT);
3086
3087 if (fep->quirks & FEC_QUIRK_HAS_VLAN)
3088 /* enable hw VLAN support */
3089 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3090
3091 if (fep->quirks & FEC_QUIRK_HAS_CSUM) {
3092 ndev->gso_max_segs = FEC_MAX_TSO_SEGS;
3093
3094 /* enable hw accelerator */
3095 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
3096 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO);
3097 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3098 }
3099
3100 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
3101 fep->tx_align = 0;
3102 fep->rx_align = 0x3f;
3103 }
3104
3105 ndev->hw_features = ndev->features;
3106
3107 fec_restart(ndev);
3108
3109 return 0;
3110}
3111
3112#ifdef CONFIG_OF
3113static void fec_reset_phy(struct platform_device *pdev)
3114{
3115 int err, phy_reset;
3116 int msec = 1;
3117 struct device_node *np = pdev->dev.of_node;
3118
3119 if (!np)
3120 return;
3121
3122 of_property_read_u32(np, "phy-reset-duration", &msec);
3123 /* A sane reset duration should not be longer than 1s */
3124 if (msec > 1000)
3125 msec = 1;
3126
3127 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
3128 if (!gpio_is_valid(phy_reset))
3129 return;
3130
3131 err = devm_gpio_request_one(&pdev->dev, phy_reset,
3132 GPIOF_OUT_INIT_LOW, "phy-reset");
3133 if (err) {
3134 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
3135 return;
3136 }
3137 msleep(msec);
3138 gpio_set_value(phy_reset, 1);
3139}
3140#else /* CONFIG_OF */
3141static void fec_reset_phy(struct platform_device *pdev)
3142{
3143 /*
3144 * In case of platform probe, the reset has been done
3145 * by machine code.
3146 */
3147}
3148#endif /* CONFIG_OF */
3149
3150static void
3151fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx)
3152{
3153 struct device_node *np = pdev->dev.of_node;
3154 int err;
3155
3156 *num_tx = *num_rx = 1;
3157
3158 if (!np || !of_device_is_available(np))
3159 return;
3160
3161 /* parse the num of tx and rx queues */
3162 err = of_property_read_u32(np, "fsl,num-tx-queues", num_tx);
3163 if (err)
3164 *num_tx = 1;
3165
3166 err = of_property_read_u32(np, "fsl,num-rx-queues", num_rx);
3167 if (err)
3168 *num_rx = 1;
3169
3170 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) {
3171 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n",
3172 *num_tx);
3173 *num_tx = 1;
3174 return;
3175 }
3176
3177 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) {
3178 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n",
3179 *num_rx);
3180 *num_rx = 1;
3181 return;
3182 }
3183
3184}
3185
3186static int
3187fec_probe(struct platform_device *pdev)
3188{
3189 struct fec_enet_private *fep;
3190 struct fec_platform_data *pdata;
3191 struct net_device *ndev;
3192 int i, irq, ret = 0;
3193 struct resource *r;
3194 const struct of_device_id *of_id;
3195 static int dev_id;
3196 struct device_node *np = pdev->dev.of_node, *phy_node;
3197 int num_tx_qs;
3198 int num_rx_qs;
3199
3200 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs);
3201
3202 /* Init network device */
3203 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private),
3204 num_tx_qs, num_rx_qs);
3205 if (!ndev)
3206 return -ENOMEM;
3207
3208 SET_NETDEV_DEV(ndev, &pdev->dev);
3209
3210 /* setup board info structure */
3211 fep = netdev_priv(ndev);
3212
3213 of_id = of_match_device(fec_dt_ids, &pdev->dev);
3214 if (of_id)
3215 pdev->id_entry = of_id->data;
3216 fep->quirks = pdev->id_entry->driver_data;
3217
3218 fep->netdev = ndev;
3219 fep->num_rx_queues = num_rx_qs;
3220 fep->num_tx_queues = num_tx_qs;
3221
3222#if !defined(CONFIG_M5272)
3223 /* default enable pause frame auto negotiation */
3224 if (fep->quirks & FEC_QUIRK_HAS_GBIT)
3225 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
3226#endif
3227
3228 /* Select default pin state */
3229 pinctrl_pm_select_default_state(&pdev->dev);
3230
3231 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3232 fep->hwp = devm_ioremap_resource(&pdev->dev, r);
3233 if (IS_ERR(fep->hwp)) {
3234 ret = PTR_ERR(fep->hwp);
3235 goto failed_ioremap;
3236 }
3237
3238 fep->pdev = pdev;
3239 fep->dev_id = dev_id++;
3240
3241 platform_set_drvdata(pdev, ndev);
3242
3243 if (of_get_property(np, "fsl,magic-packet", NULL))
3244 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET;
3245
3246 phy_node = of_parse_phandle(np, "phy-handle", 0);
3247 if (!phy_node && of_phy_is_fixed_link(np)) {
3248 ret = of_phy_register_fixed_link(np);
3249 if (ret < 0) {
3250 dev_err(&pdev->dev,
3251 "broken fixed-link specification\n");
3252 goto failed_phy;
3253 }
3254 phy_node = of_node_get(np);
3255 }
3256 fep->phy_node = phy_node;
3257
3258 ret = of_get_phy_mode(pdev->dev.of_node);
3259 if (ret < 0) {
3260 pdata = dev_get_platdata(&pdev->dev);
3261 if (pdata)
3262 fep->phy_interface = pdata->phy;
3263 else
3264 fep->phy_interface = PHY_INTERFACE_MODE_MII;
3265 } else {
3266 fep->phy_interface = ret;
3267 }
3268
3269 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
3270 if (IS_ERR(fep->clk_ipg)) {
3271 ret = PTR_ERR(fep->clk_ipg);
3272 goto failed_clk;
3273 }
3274
3275 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
3276 if (IS_ERR(fep->clk_ahb)) {
3277 ret = PTR_ERR(fep->clk_ahb);
3278 goto failed_clk;
3279 }
3280
3281 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb);
3282
3283 /* enet_out is optional, depends on board */
3284 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out");
3285 if (IS_ERR(fep->clk_enet_out))
3286 fep->clk_enet_out = NULL;
3287
3288 fep->ptp_clk_on = false;
3289 mutex_init(&fep->ptp_clk_mutex);
3290
3291 /* clk_ref is optional, depends on board */
3292 fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref");
3293 if (IS_ERR(fep->clk_ref))
3294 fep->clk_ref = NULL;
3295
3296 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX;
3297 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
3298 if (IS_ERR(fep->clk_ptp)) {
3299 fep->clk_ptp = NULL;
3300 fep->bufdesc_ex = false;
3301 }
3302
3303 ret = fec_enet_clk_enable(ndev, true);
3304 if (ret)
3305 goto failed_clk;
3306
3307 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy");
3308 if (!IS_ERR(fep->reg_phy)) {
3309 ret = regulator_enable(fep->reg_phy);
3310 if (ret) {
3311 dev_err(&pdev->dev,
3312 "Failed to enable phy regulator: %d\n", ret);
3313 goto failed_regulator;
3314 }
3315 } else {
3316 fep->reg_phy = NULL;
3317 }
3318
3319 fec_reset_phy(pdev);
3320
3321 if (fep->bufdesc_ex)
3322 fec_ptp_init(pdev);
3323
3324 ret = fec_enet_init(ndev);
3325 if (ret)
3326 goto failed_init;
3327
3328 for (i = 0; i < FEC_IRQ_NUM; i++) {
3329 irq = platform_get_irq(pdev, i);
3330 if (irq < 0) {
3331 if (i)
3332 break;
3333 ret = irq;
3334 goto failed_irq;
3335 }
3336 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
3337 0, pdev->name, ndev);
3338 if (ret)
3339 goto failed_irq;
3340
3341 fep->irq[i] = irq;
3342 }
3343
3344 init_completion(&fep->mdio_done);
3345 ret = fec_enet_mii_init(pdev);
3346 if (ret)
3347 goto failed_mii_init;
3348
3349 /* Carrier starts down, phylib will bring it up */
3350 netif_carrier_off(ndev);
3351 fec_enet_clk_enable(ndev, false);
3352 pinctrl_pm_select_sleep_state(&pdev->dev);
3353
3354 ret = register_netdev(ndev);
3355 if (ret)
3356 goto failed_register;
3357
3358 device_init_wakeup(&ndev->dev, fep->wol_flag &
3359 FEC_WOL_HAS_MAGIC_PACKET);
3360
3361 if (fep->bufdesc_ex && fep->ptp_clock)
3362 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
3363
3364 fep->rx_copybreak = COPYBREAK_DEFAULT;
3365 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work);
3366 return 0;
3367
3368failed_register:
3369 fec_enet_mii_remove(fep);
3370failed_mii_init:
3371failed_irq:
3372failed_init:
3373 if (fep->reg_phy)
3374 regulator_disable(fep->reg_phy);
3375failed_regulator:
3376 fec_enet_clk_enable(ndev, false);
3377failed_clk:
3378failed_phy:
3379 of_node_put(phy_node);
3380failed_ioremap:
3381 free_netdev(ndev);
3382
3383 return ret;
3384}
3385
3386static int
3387fec_drv_remove(struct platform_device *pdev)
3388{
3389 struct net_device *ndev = platform_get_drvdata(pdev);
3390 struct fec_enet_private *fep = netdev_priv(ndev);
3391
3392 cancel_delayed_work_sync(&fep->time_keep);
3393 cancel_work_sync(&fep->tx_timeout_work);
3394 unregister_netdev(ndev);
3395 fec_enet_mii_remove(fep);
3396 if (fep->reg_phy)
3397 regulator_disable(fep->reg_phy);
3398 if (fep->ptp_clock)
3399 ptp_clock_unregister(fep->ptp_clock);
3400 of_node_put(fep->phy_node);
3401 free_netdev(ndev);
3402
3403 return 0;
3404}
3405
3406static int __maybe_unused fec_suspend(struct device *dev)
3407{
3408 struct net_device *ndev = dev_get_drvdata(dev);
3409 struct fec_enet_private *fep = netdev_priv(ndev);
3410
3411 rtnl_lock();
3412 if (netif_running(ndev)) {
3413 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE)
3414 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON;
3415 phy_stop(fep->phy_dev);
3416 napi_disable(&fep->napi);
3417 netif_tx_lock_bh(ndev);
3418 netif_device_detach(ndev);
3419 netif_tx_unlock_bh(ndev);
3420 fec_stop(ndev);
3421 fec_enet_clk_enable(ndev, false);
3422 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
3423 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
3424 }
3425 rtnl_unlock();
3426
3427 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
3428 regulator_disable(fep->reg_phy);
3429
3430 /* SOC supply clock to phy, when clock is disabled, phy link down
3431 * SOC control phy regulator, when regulator is disabled, phy link down
3432 */
3433 if (fep->clk_enet_out || fep->reg_phy)
3434 fep->link = 0;
3435
3436 return 0;
3437}
3438
3439static int __maybe_unused fec_resume(struct device *dev)
3440{
3441 struct net_device *ndev = dev_get_drvdata(dev);
3442 struct fec_enet_private *fep = netdev_priv(ndev);
3443 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
3444 int ret;
3445 int val;
3446
3447 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) {
3448 ret = regulator_enable(fep->reg_phy);
3449 if (ret)
3450 return ret;
3451 }
3452
3453 rtnl_lock();
3454 if (netif_running(ndev)) {
3455 ret = fec_enet_clk_enable(ndev, true);
3456 if (ret) {
3457 rtnl_unlock();
3458 goto failed_clk;
3459 }
3460 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) {
3461 if (pdata && pdata->sleep_mode_enable)
3462 pdata->sleep_mode_enable(false);
3463 val = readl(fep->hwp + FEC_ECNTRL);
3464 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
3465 writel(val, fep->hwp + FEC_ECNTRL);
3466 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON;
3467 } else {
3468 pinctrl_pm_select_default_state(&fep->pdev->dev);
3469 }
3470 fec_restart(ndev);
3471 netif_tx_lock_bh(ndev);
3472 netif_device_attach(ndev);
3473 netif_tx_unlock_bh(ndev);
3474 napi_enable(&fep->napi);
3475 phy_start(fep->phy_dev);
3476 }
3477 rtnl_unlock();
3478
3479 return 0;
3480
3481failed_clk:
3482 if (fep->reg_phy)
3483 regulator_disable(fep->reg_phy);
3484 return ret;
3485}
3486
3487static SIMPLE_DEV_PM_OPS(fec_pm_ops, fec_suspend, fec_resume);
3488
3489static struct platform_driver fec_driver = {
3490 .driver = {
3491 .name = DRIVER_NAME,
3492 .pm = &fec_pm_ops,
3493 .of_match_table = fec_dt_ids,
3494 },
3495 .id_table = fec_devtype,
3496 .probe = fec_probe,
3497 .remove = fec_drv_remove,
3498};
3499
3500module_platform_driver(fec_driver);
3501
3502MODULE_ALIAS("platform:"DRIVER_NAME);
3503MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)