| 1 | /* |
| 2 | * x86 SMP booting functions |
| 3 | * |
| 4 | * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> |
| 5 | * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> |
| 6 | * Copyright 2001 Andi Kleen, SuSE Labs. |
| 7 | * |
| 8 | * Much of the core SMP work is based on previous work by Thomas Radke, to |
| 9 | * whom a great many thanks are extended. |
| 10 | * |
| 11 | * Thanks to Intel for making available several different Pentium, |
| 12 | * Pentium Pro and Pentium-II/Xeon MP machines. |
| 13 | * Original development of Linux SMP code supported by Caldera. |
| 14 | * |
| 15 | * This code is released under the GNU General Public License version 2 or |
| 16 | * later. |
| 17 | * |
| 18 | * Fixes |
| 19 | * Felix Koop : NR_CPUS used properly |
| 20 | * Jose Renau : Handle single CPU case. |
| 21 | * Alan Cox : By repeated request 8) - Total BogoMIPS report. |
| 22 | * Greg Wright : Fix for kernel stacks panic. |
| 23 | * Erich Boleyn : MP v1.4 and additional changes. |
| 24 | * Matthias Sattler : Changes for 2.1 kernel map. |
| 25 | * Michel Lespinasse : Changes for 2.1 kernel map. |
| 26 | * Michael Chastain : Change trampoline.S to gnu as. |
| 27 | * Alan Cox : Dumb bug: 'B' step PPro's are fine |
| 28 | * Ingo Molnar : Added APIC timers, based on code |
| 29 | * from Jose Renau |
| 30 | * Ingo Molnar : various cleanups and rewrites |
| 31 | * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. |
| 32 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs |
| 33 | * Andi Kleen : Changed for SMP boot into long mode. |
| 34 | * Martin J. Bligh : Added support for multi-quad systems |
| 35 | * Dave Jones : Report invalid combinations of Athlon CPUs. |
| 36 | * Rusty Russell : Hacked into shape for new "hotplug" boot process. |
| 37 | * Andi Kleen : Converted to new state machine. |
| 38 | * Ashok Raj : CPU hotplug support |
| 39 | * Glauber Costa : i386 and x86_64 integration |
| 40 | */ |
| 41 | |
| 42 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
| 43 | |
| 44 | #include <linux/init.h> |
| 45 | #include <linux/smp.h> |
| 46 | #include <linux/module.h> |
| 47 | #include <linux/sched.h> |
| 48 | #include <linux/percpu.h> |
| 49 | #include <linux/bootmem.h> |
| 50 | #include <linux/err.h> |
| 51 | #include <linux/nmi.h> |
| 52 | #include <linux/tboot.h> |
| 53 | #include <linux/stackprotector.h> |
| 54 | #include <linux/gfp.h> |
| 55 | #include <linux/cpuidle.h> |
| 56 | |
| 57 | #include <asm/acpi.h> |
| 58 | #include <asm/desc.h> |
| 59 | #include <asm/nmi.h> |
| 60 | #include <asm/irq.h> |
| 61 | #include <asm/idle.h> |
| 62 | #include <asm/realmode.h> |
| 63 | #include <asm/cpu.h> |
| 64 | #include <asm/numa.h> |
| 65 | #include <asm/pgtable.h> |
| 66 | #include <asm/tlbflush.h> |
| 67 | #include <asm/mtrr.h> |
| 68 | #include <asm/mwait.h> |
| 69 | #include <asm/apic.h> |
| 70 | #include <asm/io_apic.h> |
| 71 | #include <asm/fpu/internal.h> |
| 72 | #include <asm/setup.h> |
| 73 | #include <asm/uv/uv.h> |
| 74 | #include <linux/mc146818rtc.h> |
| 75 | #include <asm/i8259.h> |
| 76 | #include <asm/realmode.h> |
| 77 | #include <asm/misc.h> |
| 78 | |
| 79 | /* Number of siblings per CPU package */ |
| 80 | int smp_num_siblings = 1; |
| 81 | EXPORT_SYMBOL(smp_num_siblings); |
| 82 | |
| 83 | /* Last level cache ID of each logical CPU */ |
| 84 | DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; |
| 85 | |
| 86 | /* representing HT siblings of each logical CPU */ |
| 87 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); |
| 88 | EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); |
| 89 | |
| 90 | /* representing HT and core siblings of each logical CPU */ |
| 91 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); |
| 92 | EXPORT_PER_CPU_SYMBOL(cpu_core_map); |
| 93 | |
| 94 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map); |
| 95 | |
| 96 | /* Per CPU bogomips and other parameters */ |
| 97 | DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); |
| 98 | EXPORT_PER_CPU_SYMBOL(cpu_info); |
| 99 | |
| 100 | /* Logical package management. We might want to allocate that dynamically */ |
| 101 | static int *physical_to_logical_pkg __read_mostly; |
| 102 | static unsigned long *physical_package_map __read_mostly;; |
| 103 | static unsigned long *logical_package_map __read_mostly; |
| 104 | static unsigned int max_physical_pkg_id __read_mostly; |
| 105 | unsigned int __max_logical_packages __read_mostly; |
| 106 | EXPORT_SYMBOL(__max_logical_packages); |
| 107 | |
| 108 | static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) |
| 109 | { |
| 110 | unsigned long flags; |
| 111 | |
| 112 | spin_lock_irqsave(&rtc_lock, flags); |
| 113 | CMOS_WRITE(0xa, 0xf); |
| 114 | spin_unlock_irqrestore(&rtc_lock, flags); |
| 115 | local_flush_tlb(); |
| 116 | pr_debug("1.\n"); |
| 117 | *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = |
| 118 | start_eip >> 4; |
| 119 | pr_debug("2.\n"); |
| 120 | *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = |
| 121 | start_eip & 0xf; |
| 122 | pr_debug("3.\n"); |
| 123 | } |
| 124 | |
| 125 | static inline void smpboot_restore_warm_reset_vector(void) |
| 126 | { |
| 127 | unsigned long flags; |
| 128 | |
| 129 | /* |
| 130 | * Install writable page 0 entry to set BIOS data area. |
| 131 | */ |
| 132 | local_flush_tlb(); |
| 133 | |
| 134 | /* |
| 135 | * Paranoid: Set warm reset code and vector here back |
| 136 | * to default values. |
| 137 | */ |
| 138 | spin_lock_irqsave(&rtc_lock, flags); |
| 139 | CMOS_WRITE(0, 0xf); |
| 140 | spin_unlock_irqrestore(&rtc_lock, flags); |
| 141 | |
| 142 | *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0; |
| 143 | } |
| 144 | |
| 145 | /* |
| 146 | * Report back to the Boot Processor during boot time or to the caller processor |
| 147 | * during CPU online. |
| 148 | */ |
| 149 | static void smp_callin(void) |
| 150 | { |
| 151 | int cpuid, phys_id; |
| 152 | |
| 153 | /* |
| 154 | * If waken up by an INIT in an 82489DX configuration |
| 155 | * cpu_callout_mask guarantees we don't get here before |
| 156 | * an INIT_deassert IPI reaches our local APIC, so it is |
| 157 | * now safe to touch our local APIC. |
| 158 | */ |
| 159 | cpuid = smp_processor_id(); |
| 160 | |
| 161 | /* |
| 162 | * (This works even if the APIC is not enabled.) |
| 163 | */ |
| 164 | phys_id = read_apic_id(); |
| 165 | |
| 166 | /* |
| 167 | * the boot CPU has finished the init stage and is spinning |
| 168 | * on callin_map until we finish. We are free to set up this |
| 169 | * CPU, first the APIC. (this is probably redundant on most |
| 170 | * boards) |
| 171 | */ |
| 172 | apic_ap_setup(); |
| 173 | |
| 174 | /* |
| 175 | * Save our processor parameters. Note: this information |
| 176 | * is needed for clock calibration. |
| 177 | */ |
| 178 | smp_store_cpu_info(cpuid); |
| 179 | |
| 180 | /* |
| 181 | * Get our bogomips. |
| 182 | * Update loops_per_jiffy in cpu_data. Previous call to |
| 183 | * smp_store_cpu_info() stored a value that is close but not as |
| 184 | * accurate as the value just calculated. |
| 185 | */ |
| 186 | calibrate_delay(); |
| 187 | cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy; |
| 188 | pr_debug("Stack at about %p\n", &cpuid); |
| 189 | |
| 190 | /* |
| 191 | * This must be done before setting cpu_online_mask |
| 192 | * or calling notify_cpu_starting. |
| 193 | */ |
| 194 | set_cpu_sibling_map(raw_smp_processor_id()); |
| 195 | wmb(); |
| 196 | |
| 197 | notify_cpu_starting(cpuid); |
| 198 | |
| 199 | /* |
| 200 | * Allow the master to continue. |
| 201 | */ |
| 202 | cpumask_set_cpu(cpuid, cpu_callin_mask); |
| 203 | } |
| 204 | |
| 205 | static int cpu0_logical_apicid; |
| 206 | static int enable_start_cpu0; |
| 207 | /* |
| 208 | * Activate a secondary processor. |
| 209 | */ |
| 210 | static void notrace start_secondary(void *unused) |
| 211 | { |
| 212 | /* |
| 213 | * Don't put *anything* before cpu_init(), SMP booting is too |
| 214 | * fragile that we want to limit the things done here to the |
| 215 | * most necessary things. |
| 216 | */ |
| 217 | cpu_init(); |
| 218 | x86_cpuinit.early_percpu_clock_init(); |
| 219 | preempt_disable(); |
| 220 | smp_callin(); |
| 221 | |
| 222 | enable_start_cpu0 = 0; |
| 223 | |
| 224 | #ifdef CONFIG_X86_32 |
| 225 | /* switch away from the initial page table */ |
| 226 | load_cr3(swapper_pg_dir); |
| 227 | __flush_tlb_all(); |
| 228 | #endif |
| 229 | |
| 230 | /* otherwise gcc will move up smp_processor_id before the cpu_init */ |
| 231 | barrier(); |
| 232 | /* |
| 233 | * Check TSC synchronization with the BP: |
| 234 | */ |
| 235 | check_tsc_sync_target(); |
| 236 | |
| 237 | /* |
| 238 | * Lock vector_lock and initialize the vectors on this cpu |
| 239 | * before setting the cpu online. We must set it online with |
| 240 | * vector_lock held to prevent a concurrent setup/teardown |
| 241 | * from seeing a half valid vector space. |
| 242 | */ |
| 243 | lock_vector_lock(); |
| 244 | setup_vector_irq(smp_processor_id()); |
| 245 | set_cpu_online(smp_processor_id(), true); |
| 246 | unlock_vector_lock(); |
| 247 | cpu_set_state_online(smp_processor_id()); |
| 248 | x86_platform.nmi_init(); |
| 249 | |
| 250 | /* enable local interrupts */ |
| 251 | local_irq_enable(); |
| 252 | |
| 253 | /* to prevent fake stack check failure in clock setup */ |
| 254 | boot_init_stack_canary(); |
| 255 | |
| 256 | x86_cpuinit.setup_percpu_clockev(); |
| 257 | |
| 258 | wmb(); |
| 259 | cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); |
| 260 | } |
| 261 | |
| 262 | int topology_update_package_map(unsigned int apicid, unsigned int cpu) |
| 263 | { |
| 264 | unsigned int new, pkg = apicid >> boot_cpu_data.x86_coreid_bits; |
| 265 | |
| 266 | /* Called from early boot ? */ |
| 267 | if (!physical_package_map) |
| 268 | return 0; |
| 269 | |
| 270 | if (pkg >= max_physical_pkg_id) |
| 271 | return -EINVAL; |
| 272 | |
| 273 | /* Set the logical package id */ |
| 274 | if (test_and_set_bit(pkg, physical_package_map)) |
| 275 | goto found; |
| 276 | |
| 277 | new = find_first_zero_bit(logical_package_map, __max_logical_packages); |
| 278 | if (new >= __max_logical_packages) { |
| 279 | physical_to_logical_pkg[pkg] = -1; |
| 280 | pr_warn("APIC(%x) Package %u exceeds logical package map\n", |
| 281 | apicid, pkg); |
| 282 | return -ENOSPC; |
| 283 | } |
| 284 | set_bit(new, logical_package_map); |
| 285 | pr_info("APIC(%x) Converting physical %u to logical package %u\n", |
| 286 | apicid, pkg, new); |
| 287 | physical_to_logical_pkg[pkg] = new; |
| 288 | |
| 289 | found: |
| 290 | cpu_data(cpu).logical_proc_id = physical_to_logical_pkg[pkg]; |
| 291 | return 0; |
| 292 | } |
| 293 | |
| 294 | /** |
| 295 | * topology_phys_to_logical_pkg - Map a physical package id to a logical |
| 296 | * |
| 297 | * Returns logical package id or -1 if not found |
| 298 | */ |
| 299 | int topology_phys_to_logical_pkg(unsigned int phys_pkg) |
| 300 | { |
| 301 | if (phys_pkg >= max_physical_pkg_id) |
| 302 | return -1; |
| 303 | return physical_to_logical_pkg[phys_pkg]; |
| 304 | } |
| 305 | EXPORT_SYMBOL(topology_phys_to_logical_pkg); |
| 306 | |
| 307 | static void __init smp_init_package_map(void) |
| 308 | { |
| 309 | unsigned int ncpus, cpu; |
| 310 | size_t size; |
| 311 | |
| 312 | /* |
| 313 | * Today neither Intel nor AMD support heterogenous systems. That |
| 314 | * might change in the future.... |
| 315 | * |
| 316 | * While ideally we'd want '* smp_num_siblings' in the below @ncpus |
| 317 | * computation, this won't actually work since some Intel BIOSes |
| 318 | * report inconsistent HT data when they disable HT. |
| 319 | * |
| 320 | * In particular, they reduce the APIC-IDs to only include the cores, |
| 321 | * but leave the CPUID topology to say there are (2) siblings. |
| 322 | * This means we don't know how many threads there will be until |
| 323 | * after the APIC enumeration. |
| 324 | * |
| 325 | * By not including this we'll sometimes over-estimate the number of |
| 326 | * logical packages by the amount of !present siblings, but this is |
| 327 | * still better than MAX_LOCAL_APIC. |
| 328 | * |
| 329 | * We use total_cpus not nr_cpu_ids because nr_cpu_ids can be limited |
| 330 | * on the command line leading to a similar issue as the HT disable |
| 331 | * problem because the hyperthreads are usually enumerated after the |
| 332 | * primary cores. |
| 333 | */ |
| 334 | ncpus = boot_cpu_data.x86_max_cores; |
| 335 | if (!ncpus) { |
| 336 | pr_warn("x86_max_cores == zero !?!?"); |
| 337 | ncpus = 1; |
| 338 | } |
| 339 | |
| 340 | __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus); |
| 341 | |
| 342 | /* |
| 343 | * Possibly larger than what we need as the number of apic ids per |
| 344 | * package can be smaller than the actual used apic ids. |
| 345 | */ |
| 346 | max_physical_pkg_id = DIV_ROUND_UP(MAX_LOCAL_APIC, ncpus); |
| 347 | size = max_physical_pkg_id * sizeof(unsigned int); |
| 348 | physical_to_logical_pkg = kmalloc(size, GFP_KERNEL); |
| 349 | memset(physical_to_logical_pkg, 0xff, size); |
| 350 | size = BITS_TO_LONGS(max_physical_pkg_id) * sizeof(unsigned long); |
| 351 | physical_package_map = kzalloc(size, GFP_KERNEL); |
| 352 | size = BITS_TO_LONGS(__max_logical_packages) * sizeof(unsigned long); |
| 353 | logical_package_map = kzalloc(size, GFP_KERNEL); |
| 354 | |
| 355 | pr_info("Max logical packages: %u\n", __max_logical_packages); |
| 356 | |
| 357 | for_each_present_cpu(cpu) { |
| 358 | unsigned int apicid = apic->cpu_present_to_apicid(cpu); |
| 359 | |
| 360 | if (apicid == BAD_APICID || !apic->apic_id_valid(apicid)) |
| 361 | continue; |
| 362 | if (!topology_update_package_map(apicid, cpu)) |
| 363 | continue; |
| 364 | pr_warn("CPU %u APICId %x disabled\n", cpu, apicid); |
| 365 | per_cpu(x86_bios_cpu_apicid, cpu) = BAD_APICID; |
| 366 | set_cpu_possible(cpu, false); |
| 367 | set_cpu_present(cpu, false); |
| 368 | } |
| 369 | } |
| 370 | |
| 371 | void __init smp_store_boot_cpu_info(void) |
| 372 | { |
| 373 | int id = 0; /* CPU 0 */ |
| 374 | struct cpuinfo_x86 *c = &cpu_data(id); |
| 375 | |
| 376 | *c = boot_cpu_data; |
| 377 | c->cpu_index = id; |
| 378 | smp_init_package_map(); |
| 379 | } |
| 380 | |
| 381 | /* |
| 382 | * The bootstrap kernel entry code has set these up. Save them for |
| 383 | * a given CPU |
| 384 | */ |
| 385 | void smp_store_cpu_info(int id) |
| 386 | { |
| 387 | struct cpuinfo_x86 *c = &cpu_data(id); |
| 388 | |
| 389 | *c = boot_cpu_data; |
| 390 | c->cpu_index = id; |
| 391 | /* |
| 392 | * During boot time, CPU0 has this setup already. Save the info when |
| 393 | * bringing up AP or offlined CPU0. |
| 394 | */ |
| 395 | identify_secondary_cpu(c); |
| 396 | } |
| 397 | |
| 398 | static bool |
| 399 | topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) |
| 400 | { |
| 401 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; |
| 402 | |
| 403 | return (cpu_to_node(cpu1) == cpu_to_node(cpu2)); |
| 404 | } |
| 405 | |
| 406 | static bool |
| 407 | topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) |
| 408 | { |
| 409 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; |
| 410 | |
| 411 | return !WARN_ONCE(!topology_same_node(c, o), |
| 412 | "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " |
| 413 | "[node: %d != %d]. Ignoring dependency.\n", |
| 414 | cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); |
| 415 | } |
| 416 | |
| 417 | #define link_mask(mfunc, c1, c2) \ |
| 418 | do { \ |
| 419 | cpumask_set_cpu((c1), mfunc(c2)); \ |
| 420 | cpumask_set_cpu((c2), mfunc(c1)); \ |
| 421 | } while (0) |
| 422 | |
| 423 | static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) |
| 424 | { |
| 425 | if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { |
| 426 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; |
| 427 | |
| 428 | if (c->phys_proc_id == o->phys_proc_id && |
| 429 | per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2) && |
| 430 | c->cpu_core_id == o->cpu_core_id) |
| 431 | return topology_sane(c, o, "smt"); |
| 432 | |
| 433 | } else if (c->phys_proc_id == o->phys_proc_id && |
| 434 | c->cpu_core_id == o->cpu_core_id) { |
| 435 | return topology_sane(c, o, "smt"); |
| 436 | } |
| 437 | |
| 438 | return false; |
| 439 | } |
| 440 | |
| 441 | static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) |
| 442 | { |
| 443 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; |
| 444 | |
| 445 | if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID && |
| 446 | per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) |
| 447 | return topology_sane(c, o, "llc"); |
| 448 | |
| 449 | return false; |
| 450 | } |
| 451 | |
| 452 | /* |
| 453 | * Unlike the other levels, we do not enforce keeping a |
| 454 | * multicore group inside a NUMA node. If this happens, we will |
| 455 | * discard the MC level of the topology later. |
| 456 | */ |
| 457 | static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) |
| 458 | { |
| 459 | if (c->phys_proc_id == o->phys_proc_id) |
| 460 | return true; |
| 461 | return false; |
| 462 | } |
| 463 | |
| 464 | static struct sched_domain_topology_level numa_inside_package_topology[] = { |
| 465 | #ifdef CONFIG_SCHED_SMT |
| 466 | { cpu_smt_mask, cpu_smt_flags, SD_INIT_NAME(SMT) }, |
| 467 | #endif |
| 468 | #ifdef CONFIG_SCHED_MC |
| 469 | { cpu_coregroup_mask, cpu_core_flags, SD_INIT_NAME(MC) }, |
| 470 | #endif |
| 471 | { NULL, }, |
| 472 | }; |
| 473 | /* |
| 474 | * set_sched_topology() sets the topology internal to a CPU. The |
| 475 | * NUMA topologies are layered on top of it to build the full |
| 476 | * system topology. |
| 477 | * |
| 478 | * If NUMA nodes are observed to occur within a CPU package, this |
| 479 | * function should be called. It forces the sched domain code to |
| 480 | * only use the SMT level for the CPU portion of the topology. |
| 481 | * This essentially falls back to relying on NUMA information |
| 482 | * from the SRAT table to describe the entire system topology |
| 483 | * (except for hyperthreads). |
| 484 | */ |
| 485 | static void primarily_use_numa_for_topology(void) |
| 486 | { |
| 487 | set_sched_topology(numa_inside_package_topology); |
| 488 | } |
| 489 | |
| 490 | void set_cpu_sibling_map(int cpu) |
| 491 | { |
| 492 | bool has_smt = smp_num_siblings > 1; |
| 493 | bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1; |
| 494 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
| 495 | struct cpuinfo_x86 *o; |
| 496 | int i; |
| 497 | |
| 498 | cpumask_set_cpu(cpu, cpu_sibling_setup_mask); |
| 499 | |
| 500 | if (!has_mp) { |
| 501 | cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu)); |
| 502 | cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); |
| 503 | cpumask_set_cpu(cpu, topology_core_cpumask(cpu)); |
| 504 | c->booted_cores = 1; |
| 505 | return; |
| 506 | } |
| 507 | |
| 508 | for_each_cpu(i, cpu_sibling_setup_mask) { |
| 509 | o = &cpu_data(i); |
| 510 | |
| 511 | if ((i == cpu) || (has_smt && match_smt(c, o))) |
| 512 | link_mask(topology_sibling_cpumask, cpu, i); |
| 513 | |
| 514 | if ((i == cpu) || (has_mp && match_llc(c, o))) |
| 515 | link_mask(cpu_llc_shared_mask, cpu, i); |
| 516 | |
| 517 | } |
| 518 | |
| 519 | /* |
| 520 | * This needs a separate iteration over the cpus because we rely on all |
| 521 | * topology_sibling_cpumask links to be set-up. |
| 522 | */ |
| 523 | for_each_cpu(i, cpu_sibling_setup_mask) { |
| 524 | o = &cpu_data(i); |
| 525 | |
| 526 | if ((i == cpu) || (has_mp && match_die(c, o))) { |
| 527 | link_mask(topology_core_cpumask, cpu, i); |
| 528 | |
| 529 | /* |
| 530 | * Does this new cpu bringup a new core? |
| 531 | */ |
| 532 | if (cpumask_weight( |
| 533 | topology_sibling_cpumask(cpu)) == 1) { |
| 534 | /* |
| 535 | * for each core in package, increment |
| 536 | * the booted_cores for this new cpu |
| 537 | */ |
| 538 | if (cpumask_first( |
| 539 | topology_sibling_cpumask(i)) == i) |
| 540 | c->booted_cores++; |
| 541 | /* |
| 542 | * increment the core count for all |
| 543 | * the other cpus in this package |
| 544 | */ |
| 545 | if (i != cpu) |
| 546 | cpu_data(i).booted_cores++; |
| 547 | } else if (i != cpu && !c->booted_cores) |
| 548 | c->booted_cores = cpu_data(i).booted_cores; |
| 549 | } |
| 550 | if (match_die(c, o) && !topology_same_node(c, o)) |
| 551 | primarily_use_numa_for_topology(); |
| 552 | } |
| 553 | } |
| 554 | |
| 555 | /* maps the cpu to the sched domain representing multi-core */ |
| 556 | const struct cpumask *cpu_coregroup_mask(int cpu) |
| 557 | { |
| 558 | return cpu_llc_shared_mask(cpu); |
| 559 | } |
| 560 | |
| 561 | static void impress_friends(void) |
| 562 | { |
| 563 | int cpu; |
| 564 | unsigned long bogosum = 0; |
| 565 | /* |
| 566 | * Allow the user to impress friends. |
| 567 | */ |
| 568 | pr_debug("Before bogomips\n"); |
| 569 | for_each_possible_cpu(cpu) |
| 570 | if (cpumask_test_cpu(cpu, cpu_callout_mask)) |
| 571 | bogosum += cpu_data(cpu).loops_per_jiffy; |
| 572 | pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", |
| 573 | num_online_cpus(), |
| 574 | bogosum/(500000/HZ), |
| 575 | (bogosum/(5000/HZ))%100); |
| 576 | |
| 577 | pr_debug("Before bogocount - setting activated=1\n"); |
| 578 | } |
| 579 | |
| 580 | void __inquire_remote_apic(int apicid) |
| 581 | { |
| 582 | unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; |
| 583 | const char * const names[] = { "ID", "VERSION", "SPIV" }; |
| 584 | int timeout; |
| 585 | u32 status; |
| 586 | |
| 587 | pr_info("Inquiring remote APIC 0x%x...\n", apicid); |
| 588 | |
| 589 | for (i = 0; i < ARRAY_SIZE(regs); i++) { |
| 590 | pr_info("... APIC 0x%x %s: ", apicid, names[i]); |
| 591 | |
| 592 | /* |
| 593 | * Wait for idle. |
| 594 | */ |
| 595 | status = safe_apic_wait_icr_idle(); |
| 596 | if (status) |
| 597 | pr_cont("a previous APIC delivery may have failed\n"); |
| 598 | |
| 599 | apic_icr_write(APIC_DM_REMRD | regs[i], apicid); |
| 600 | |
| 601 | timeout = 0; |
| 602 | do { |
| 603 | udelay(100); |
| 604 | status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; |
| 605 | } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); |
| 606 | |
| 607 | switch (status) { |
| 608 | case APIC_ICR_RR_VALID: |
| 609 | status = apic_read(APIC_RRR); |
| 610 | pr_cont("%08x\n", status); |
| 611 | break; |
| 612 | default: |
| 613 | pr_cont("failed\n"); |
| 614 | } |
| 615 | } |
| 616 | } |
| 617 | |
| 618 | /* |
| 619 | * The Multiprocessor Specification 1.4 (1997) example code suggests |
| 620 | * that there should be a 10ms delay between the BSP asserting INIT |
| 621 | * and de-asserting INIT, when starting a remote processor. |
| 622 | * But that slows boot and resume on modern processors, which include |
| 623 | * many cores and don't require that delay. |
| 624 | * |
| 625 | * Cmdline "init_cpu_udelay=" is available to over-ride this delay. |
| 626 | * Modern processor families are quirked to remove the delay entirely. |
| 627 | */ |
| 628 | #define UDELAY_10MS_DEFAULT 10000 |
| 629 | |
| 630 | static unsigned int init_udelay = UINT_MAX; |
| 631 | |
| 632 | static int __init cpu_init_udelay(char *str) |
| 633 | { |
| 634 | get_option(&str, &init_udelay); |
| 635 | |
| 636 | return 0; |
| 637 | } |
| 638 | early_param("cpu_init_udelay", cpu_init_udelay); |
| 639 | |
| 640 | static void __init smp_quirk_init_udelay(void) |
| 641 | { |
| 642 | /* if cmdline changed it from default, leave it alone */ |
| 643 | if (init_udelay != UINT_MAX) |
| 644 | return; |
| 645 | |
| 646 | /* if modern processor, use no delay */ |
| 647 | if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) || |
| 648 | ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) { |
| 649 | init_udelay = 0; |
| 650 | return; |
| 651 | } |
| 652 | /* else, use legacy delay */ |
| 653 | init_udelay = UDELAY_10MS_DEFAULT; |
| 654 | } |
| 655 | |
| 656 | /* |
| 657 | * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal |
| 658 | * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this |
| 659 | * won't ... remember to clear down the APIC, etc later. |
| 660 | */ |
| 661 | int |
| 662 | wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip) |
| 663 | { |
| 664 | unsigned long send_status, accept_status = 0; |
| 665 | int maxlvt; |
| 666 | |
| 667 | /* Target chip */ |
| 668 | /* Boot on the stack */ |
| 669 | /* Kick the second */ |
| 670 | apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid); |
| 671 | |
| 672 | pr_debug("Waiting for send to finish...\n"); |
| 673 | send_status = safe_apic_wait_icr_idle(); |
| 674 | |
| 675 | /* |
| 676 | * Give the other CPU some time to accept the IPI. |
| 677 | */ |
| 678 | udelay(200); |
| 679 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { |
| 680 | maxlvt = lapic_get_maxlvt(); |
| 681 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
| 682 | apic_write(APIC_ESR, 0); |
| 683 | accept_status = (apic_read(APIC_ESR) & 0xEF); |
| 684 | } |
| 685 | pr_debug("NMI sent\n"); |
| 686 | |
| 687 | if (send_status) |
| 688 | pr_err("APIC never delivered???\n"); |
| 689 | if (accept_status) |
| 690 | pr_err("APIC delivery error (%lx)\n", accept_status); |
| 691 | |
| 692 | return (send_status | accept_status); |
| 693 | } |
| 694 | |
| 695 | static int |
| 696 | wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) |
| 697 | { |
| 698 | unsigned long send_status = 0, accept_status = 0; |
| 699 | int maxlvt, num_starts, j; |
| 700 | |
| 701 | maxlvt = lapic_get_maxlvt(); |
| 702 | |
| 703 | /* |
| 704 | * Be paranoid about clearing APIC errors. |
| 705 | */ |
| 706 | if (APIC_INTEGRATED(apic_version[phys_apicid])) { |
| 707 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
| 708 | apic_write(APIC_ESR, 0); |
| 709 | apic_read(APIC_ESR); |
| 710 | } |
| 711 | |
| 712 | pr_debug("Asserting INIT\n"); |
| 713 | |
| 714 | /* |
| 715 | * Turn INIT on target chip |
| 716 | */ |
| 717 | /* |
| 718 | * Send IPI |
| 719 | */ |
| 720 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, |
| 721 | phys_apicid); |
| 722 | |
| 723 | pr_debug("Waiting for send to finish...\n"); |
| 724 | send_status = safe_apic_wait_icr_idle(); |
| 725 | |
| 726 | udelay(init_udelay); |
| 727 | |
| 728 | pr_debug("Deasserting INIT\n"); |
| 729 | |
| 730 | /* Target chip */ |
| 731 | /* Send IPI */ |
| 732 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); |
| 733 | |
| 734 | pr_debug("Waiting for send to finish...\n"); |
| 735 | send_status = safe_apic_wait_icr_idle(); |
| 736 | |
| 737 | mb(); |
| 738 | |
| 739 | /* |
| 740 | * Should we send STARTUP IPIs ? |
| 741 | * |
| 742 | * Determine this based on the APIC version. |
| 743 | * If we don't have an integrated APIC, don't send the STARTUP IPIs. |
| 744 | */ |
| 745 | if (APIC_INTEGRATED(apic_version[phys_apicid])) |
| 746 | num_starts = 2; |
| 747 | else |
| 748 | num_starts = 0; |
| 749 | |
| 750 | /* |
| 751 | * Run STARTUP IPI loop. |
| 752 | */ |
| 753 | pr_debug("#startup loops: %d\n", num_starts); |
| 754 | |
| 755 | for (j = 1; j <= num_starts; j++) { |
| 756 | pr_debug("Sending STARTUP #%d\n", j); |
| 757 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
| 758 | apic_write(APIC_ESR, 0); |
| 759 | apic_read(APIC_ESR); |
| 760 | pr_debug("After apic_write\n"); |
| 761 | |
| 762 | /* |
| 763 | * STARTUP IPI |
| 764 | */ |
| 765 | |
| 766 | /* Target chip */ |
| 767 | /* Boot on the stack */ |
| 768 | /* Kick the second */ |
| 769 | apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), |
| 770 | phys_apicid); |
| 771 | |
| 772 | /* |
| 773 | * Give the other CPU some time to accept the IPI. |
| 774 | */ |
| 775 | if (init_udelay == 0) |
| 776 | udelay(10); |
| 777 | else |
| 778 | udelay(300); |
| 779 | |
| 780 | pr_debug("Startup point 1\n"); |
| 781 | |
| 782 | pr_debug("Waiting for send to finish...\n"); |
| 783 | send_status = safe_apic_wait_icr_idle(); |
| 784 | |
| 785 | /* |
| 786 | * Give the other CPU some time to accept the IPI. |
| 787 | */ |
| 788 | if (init_udelay == 0) |
| 789 | udelay(10); |
| 790 | else |
| 791 | udelay(200); |
| 792 | |
| 793 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
| 794 | apic_write(APIC_ESR, 0); |
| 795 | accept_status = (apic_read(APIC_ESR) & 0xEF); |
| 796 | if (send_status || accept_status) |
| 797 | break; |
| 798 | } |
| 799 | pr_debug("After Startup\n"); |
| 800 | |
| 801 | if (send_status) |
| 802 | pr_err("APIC never delivered???\n"); |
| 803 | if (accept_status) |
| 804 | pr_err("APIC delivery error (%lx)\n", accept_status); |
| 805 | |
| 806 | return (send_status | accept_status); |
| 807 | } |
| 808 | |
| 809 | void smp_announce(void) |
| 810 | { |
| 811 | int num_nodes = num_online_nodes(); |
| 812 | |
| 813 | printk(KERN_INFO "x86: Booted up %d node%s, %d CPUs\n", |
| 814 | num_nodes, (num_nodes > 1 ? "s" : ""), num_online_cpus()); |
| 815 | } |
| 816 | |
| 817 | /* reduce the number of lines printed when booting a large cpu count system */ |
| 818 | static void announce_cpu(int cpu, int apicid) |
| 819 | { |
| 820 | static int current_node = -1; |
| 821 | int node = early_cpu_to_node(cpu); |
| 822 | static int width, node_width; |
| 823 | |
| 824 | if (!width) |
| 825 | width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ |
| 826 | |
| 827 | if (!node_width) |
| 828 | node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ |
| 829 | |
| 830 | if (cpu == 1) |
| 831 | printk(KERN_INFO "x86: Booting SMP configuration:\n"); |
| 832 | |
| 833 | if (system_state == SYSTEM_BOOTING) { |
| 834 | if (node != current_node) { |
| 835 | if (current_node > (-1)) |
| 836 | pr_cont("\n"); |
| 837 | current_node = node; |
| 838 | |
| 839 | printk(KERN_INFO ".... node %*s#%d, CPUs: ", |
| 840 | node_width - num_digits(node), " ", node); |
| 841 | } |
| 842 | |
| 843 | /* Add padding for the BSP */ |
| 844 | if (cpu == 1) |
| 845 | pr_cont("%*s", width + 1, " "); |
| 846 | |
| 847 | pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); |
| 848 | |
| 849 | } else |
| 850 | pr_info("Booting Node %d Processor %d APIC 0x%x\n", |
| 851 | node, cpu, apicid); |
| 852 | } |
| 853 | |
| 854 | static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs) |
| 855 | { |
| 856 | int cpu; |
| 857 | |
| 858 | cpu = smp_processor_id(); |
| 859 | if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0) |
| 860 | return NMI_HANDLED; |
| 861 | |
| 862 | return NMI_DONE; |
| 863 | } |
| 864 | |
| 865 | /* |
| 866 | * Wake up AP by INIT, INIT, STARTUP sequence. |
| 867 | * |
| 868 | * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS |
| 869 | * boot-strap code which is not a desired behavior for waking up BSP. To |
| 870 | * void the boot-strap code, wake up CPU0 by NMI instead. |
| 871 | * |
| 872 | * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined |
| 873 | * (i.e. physically hot removed and then hot added), NMI won't wake it up. |
| 874 | * We'll change this code in the future to wake up hard offlined CPU0 if |
| 875 | * real platform and request are available. |
| 876 | */ |
| 877 | static int |
| 878 | wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid, |
| 879 | int *cpu0_nmi_registered) |
| 880 | { |
| 881 | int id; |
| 882 | int boot_error; |
| 883 | |
| 884 | preempt_disable(); |
| 885 | |
| 886 | /* |
| 887 | * Wake up AP by INIT, INIT, STARTUP sequence. |
| 888 | */ |
| 889 | if (cpu) { |
| 890 | boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); |
| 891 | goto out; |
| 892 | } |
| 893 | |
| 894 | /* |
| 895 | * Wake up BSP by nmi. |
| 896 | * |
| 897 | * Register a NMI handler to help wake up CPU0. |
| 898 | */ |
| 899 | boot_error = register_nmi_handler(NMI_LOCAL, |
| 900 | wakeup_cpu0_nmi, 0, "wake_cpu0"); |
| 901 | |
| 902 | if (!boot_error) { |
| 903 | enable_start_cpu0 = 1; |
| 904 | *cpu0_nmi_registered = 1; |
| 905 | if (apic->dest_logical == APIC_DEST_LOGICAL) |
| 906 | id = cpu0_logical_apicid; |
| 907 | else |
| 908 | id = apicid; |
| 909 | boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip); |
| 910 | } |
| 911 | |
| 912 | out: |
| 913 | preempt_enable(); |
| 914 | |
| 915 | return boot_error; |
| 916 | } |
| 917 | |
| 918 | void common_cpu_up(unsigned int cpu, struct task_struct *idle) |
| 919 | { |
| 920 | /* Just in case we booted with a single CPU. */ |
| 921 | alternatives_enable_smp(); |
| 922 | |
| 923 | per_cpu(current_task, cpu) = idle; |
| 924 | |
| 925 | #ifdef CONFIG_X86_32 |
| 926 | /* Stack for startup_32 can be just as for start_secondary onwards */ |
| 927 | irq_ctx_init(cpu); |
| 928 | per_cpu(cpu_current_top_of_stack, cpu) = |
| 929 | (unsigned long)task_stack_page(idle) + THREAD_SIZE; |
| 930 | #else |
| 931 | clear_tsk_thread_flag(idle, TIF_FORK); |
| 932 | initial_gs = per_cpu_offset(cpu); |
| 933 | #endif |
| 934 | } |
| 935 | |
| 936 | /* |
| 937 | * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad |
| 938 | * (ie clustered apic addressing mode), this is a LOGICAL apic ID. |
| 939 | * Returns zero if CPU booted OK, else error code from |
| 940 | * ->wakeup_secondary_cpu. |
| 941 | */ |
| 942 | static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle) |
| 943 | { |
| 944 | volatile u32 *trampoline_status = |
| 945 | (volatile u32 *) __va(real_mode_header->trampoline_status); |
| 946 | /* start_ip had better be page-aligned! */ |
| 947 | unsigned long start_ip = real_mode_header->trampoline_start; |
| 948 | |
| 949 | unsigned long boot_error = 0; |
| 950 | int cpu0_nmi_registered = 0; |
| 951 | unsigned long timeout; |
| 952 | |
| 953 | idle->thread.sp = (unsigned long) (((struct pt_regs *) |
| 954 | (THREAD_SIZE + task_stack_page(idle))) - 1); |
| 955 | |
| 956 | early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); |
| 957 | initial_code = (unsigned long)start_secondary; |
| 958 | stack_start = idle->thread.sp; |
| 959 | |
| 960 | /* |
| 961 | * Enable the espfix hack for this CPU |
| 962 | */ |
| 963 | #ifdef CONFIG_X86_ESPFIX64 |
| 964 | init_espfix_ap(cpu); |
| 965 | #endif |
| 966 | |
| 967 | /* So we see what's up */ |
| 968 | announce_cpu(cpu, apicid); |
| 969 | |
| 970 | /* |
| 971 | * This grunge runs the startup process for |
| 972 | * the targeted processor. |
| 973 | */ |
| 974 | |
| 975 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
| 976 | |
| 977 | pr_debug("Setting warm reset code and vector.\n"); |
| 978 | |
| 979 | smpboot_setup_warm_reset_vector(start_ip); |
| 980 | /* |
| 981 | * Be paranoid about clearing APIC errors. |
| 982 | */ |
| 983 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { |
| 984 | apic_write(APIC_ESR, 0); |
| 985 | apic_read(APIC_ESR); |
| 986 | } |
| 987 | } |
| 988 | |
| 989 | /* |
| 990 | * AP might wait on cpu_callout_mask in cpu_init() with |
| 991 | * cpu_initialized_mask set if previous attempt to online |
| 992 | * it timed-out. Clear cpu_initialized_mask so that after |
| 993 | * INIT/SIPI it could start with a clean state. |
| 994 | */ |
| 995 | cpumask_clear_cpu(cpu, cpu_initialized_mask); |
| 996 | smp_mb(); |
| 997 | |
| 998 | /* |
| 999 | * Wake up a CPU in difference cases: |
| 1000 | * - Use the method in the APIC driver if it's defined |
| 1001 | * Otherwise, |
| 1002 | * - Use an INIT boot APIC message for APs or NMI for BSP. |
| 1003 | */ |
| 1004 | if (apic->wakeup_secondary_cpu) |
| 1005 | boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); |
| 1006 | else |
| 1007 | boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid, |
| 1008 | &cpu0_nmi_registered); |
| 1009 | |
| 1010 | if (!boot_error) { |
| 1011 | /* |
| 1012 | * Wait 10s total for first sign of life from AP |
| 1013 | */ |
| 1014 | boot_error = -1; |
| 1015 | timeout = jiffies + 10*HZ; |
| 1016 | while (time_before(jiffies, timeout)) { |
| 1017 | if (cpumask_test_cpu(cpu, cpu_initialized_mask)) { |
| 1018 | /* |
| 1019 | * Tell AP to proceed with initialization |
| 1020 | */ |
| 1021 | cpumask_set_cpu(cpu, cpu_callout_mask); |
| 1022 | boot_error = 0; |
| 1023 | break; |
| 1024 | } |
| 1025 | schedule(); |
| 1026 | } |
| 1027 | } |
| 1028 | |
| 1029 | if (!boot_error) { |
| 1030 | /* |
| 1031 | * Wait till AP completes initial initialization |
| 1032 | */ |
| 1033 | while (!cpumask_test_cpu(cpu, cpu_callin_mask)) { |
| 1034 | /* |
| 1035 | * Allow other tasks to run while we wait for the |
| 1036 | * AP to come online. This also gives a chance |
| 1037 | * for the MTRR work(triggered by the AP coming online) |
| 1038 | * to be completed in the stop machine context. |
| 1039 | */ |
| 1040 | schedule(); |
| 1041 | } |
| 1042 | } |
| 1043 | |
| 1044 | /* mark "stuck" area as not stuck */ |
| 1045 | *trampoline_status = 0; |
| 1046 | |
| 1047 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
| 1048 | /* |
| 1049 | * Cleanup possible dangling ends... |
| 1050 | */ |
| 1051 | smpboot_restore_warm_reset_vector(); |
| 1052 | } |
| 1053 | /* |
| 1054 | * Clean up the nmi handler. Do this after the callin and callout sync |
| 1055 | * to avoid impact of possible long unregister time. |
| 1056 | */ |
| 1057 | if (cpu0_nmi_registered) |
| 1058 | unregister_nmi_handler(NMI_LOCAL, "wake_cpu0"); |
| 1059 | |
| 1060 | return boot_error; |
| 1061 | } |
| 1062 | |
| 1063 | int native_cpu_up(unsigned int cpu, struct task_struct *tidle) |
| 1064 | { |
| 1065 | int apicid = apic->cpu_present_to_apicid(cpu); |
| 1066 | unsigned long flags; |
| 1067 | int err; |
| 1068 | |
| 1069 | WARN_ON(irqs_disabled()); |
| 1070 | |
| 1071 | pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); |
| 1072 | |
| 1073 | if (apicid == BAD_APICID || |
| 1074 | !physid_isset(apicid, phys_cpu_present_map) || |
| 1075 | !apic->apic_id_valid(apicid)) { |
| 1076 | pr_err("%s: bad cpu %d\n", __func__, cpu); |
| 1077 | return -EINVAL; |
| 1078 | } |
| 1079 | |
| 1080 | /* |
| 1081 | * Already booted CPU? |
| 1082 | */ |
| 1083 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) { |
| 1084 | pr_debug("do_boot_cpu %d Already started\n", cpu); |
| 1085 | return -ENOSYS; |
| 1086 | } |
| 1087 | |
| 1088 | /* |
| 1089 | * Save current MTRR state in case it was changed since early boot |
| 1090 | * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: |
| 1091 | */ |
| 1092 | mtrr_save_state(); |
| 1093 | |
| 1094 | /* x86 CPUs take themselves offline, so delayed offline is OK. */ |
| 1095 | err = cpu_check_up_prepare(cpu); |
| 1096 | if (err && err != -EBUSY) |
| 1097 | return err; |
| 1098 | |
| 1099 | /* the FPU context is blank, nobody can own it */ |
| 1100 | __cpu_disable_lazy_restore(cpu); |
| 1101 | |
| 1102 | common_cpu_up(cpu, tidle); |
| 1103 | |
| 1104 | /* |
| 1105 | * We have to walk the irq descriptors to setup the vector |
| 1106 | * space for the cpu which comes online. Prevent irq |
| 1107 | * alloc/free across the bringup. |
| 1108 | */ |
| 1109 | irq_lock_sparse(); |
| 1110 | |
| 1111 | err = do_boot_cpu(apicid, cpu, tidle); |
| 1112 | |
| 1113 | if (err) { |
| 1114 | irq_unlock_sparse(); |
| 1115 | pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu); |
| 1116 | return -EIO; |
| 1117 | } |
| 1118 | |
| 1119 | /* |
| 1120 | * Check TSC synchronization with the AP (keep irqs disabled |
| 1121 | * while doing so): |
| 1122 | */ |
| 1123 | local_irq_save(flags); |
| 1124 | check_tsc_sync_source(cpu); |
| 1125 | local_irq_restore(flags); |
| 1126 | |
| 1127 | while (!cpu_online(cpu)) { |
| 1128 | cpu_relax(); |
| 1129 | touch_nmi_watchdog(); |
| 1130 | } |
| 1131 | |
| 1132 | irq_unlock_sparse(); |
| 1133 | |
| 1134 | return 0; |
| 1135 | } |
| 1136 | |
| 1137 | /** |
| 1138 | * arch_disable_smp_support() - disables SMP support for x86 at runtime |
| 1139 | */ |
| 1140 | void arch_disable_smp_support(void) |
| 1141 | { |
| 1142 | disable_ioapic_support(); |
| 1143 | } |
| 1144 | |
| 1145 | /* |
| 1146 | * Fall back to non SMP mode after errors. |
| 1147 | * |
| 1148 | * RED-PEN audit/test this more. I bet there is more state messed up here. |
| 1149 | */ |
| 1150 | static __init void disable_smp(void) |
| 1151 | { |
| 1152 | pr_info("SMP disabled\n"); |
| 1153 | |
| 1154 | disable_ioapic_support(); |
| 1155 | |
| 1156 | init_cpu_present(cpumask_of(0)); |
| 1157 | init_cpu_possible(cpumask_of(0)); |
| 1158 | |
| 1159 | if (smp_found_config) |
| 1160 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); |
| 1161 | else |
| 1162 | physid_set_mask_of_physid(0, &phys_cpu_present_map); |
| 1163 | cpumask_set_cpu(0, topology_sibling_cpumask(0)); |
| 1164 | cpumask_set_cpu(0, topology_core_cpumask(0)); |
| 1165 | } |
| 1166 | |
| 1167 | enum { |
| 1168 | SMP_OK, |
| 1169 | SMP_NO_CONFIG, |
| 1170 | SMP_NO_APIC, |
| 1171 | SMP_FORCE_UP, |
| 1172 | }; |
| 1173 | |
| 1174 | /* |
| 1175 | * Various sanity checks. |
| 1176 | */ |
| 1177 | static int __init smp_sanity_check(unsigned max_cpus) |
| 1178 | { |
| 1179 | preempt_disable(); |
| 1180 | |
| 1181 | #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) |
| 1182 | if (def_to_bigsmp && nr_cpu_ids > 8) { |
| 1183 | unsigned int cpu; |
| 1184 | unsigned nr; |
| 1185 | |
| 1186 | pr_warn("More than 8 CPUs detected - skipping them\n" |
| 1187 | "Use CONFIG_X86_BIGSMP\n"); |
| 1188 | |
| 1189 | nr = 0; |
| 1190 | for_each_present_cpu(cpu) { |
| 1191 | if (nr >= 8) |
| 1192 | set_cpu_present(cpu, false); |
| 1193 | nr++; |
| 1194 | } |
| 1195 | |
| 1196 | nr = 0; |
| 1197 | for_each_possible_cpu(cpu) { |
| 1198 | if (nr >= 8) |
| 1199 | set_cpu_possible(cpu, false); |
| 1200 | nr++; |
| 1201 | } |
| 1202 | |
| 1203 | nr_cpu_ids = 8; |
| 1204 | } |
| 1205 | #endif |
| 1206 | |
| 1207 | if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { |
| 1208 | pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n", |
| 1209 | hard_smp_processor_id()); |
| 1210 | |
| 1211 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); |
| 1212 | } |
| 1213 | |
| 1214 | /* |
| 1215 | * If we couldn't find an SMP configuration at boot time, |
| 1216 | * get out of here now! |
| 1217 | */ |
| 1218 | if (!smp_found_config && !acpi_lapic) { |
| 1219 | preempt_enable(); |
| 1220 | pr_notice("SMP motherboard not detected\n"); |
| 1221 | return SMP_NO_CONFIG; |
| 1222 | } |
| 1223 | |
| 1224 | /* |
| 1225 | * Should not be necessary because the MP table should list the boot |
| 1226 | * CPU too, but we do it for the sake of robustness anyway. |
| 1227 | */ |
| 1228 | if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { |
| 1229 | pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n", |
| 1230 | boot_cpu_physical_apicid); |
| 1231 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); |
| 1232 | } |
| 1233 | preempt_enable(); |
| 1234 | |
| 1235 | /* |
| 1236 | * If we couldn't find a local APIC, then get out of here now! |
| 1237 | */ |
| 1238 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && |
| 1239 | !boot_cpu_has(X86_FEATURE_APIC)) { |
| 1240 | if (!disable_apic) { |
| 1241 | pr_err("BIOS bug, local APIC #%d not detected!...\n", |
| 1242 | boot_cpu_physical_apicid); |
| 1243 | pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n"); |
| 1244 | } |
| 1245 | return SMP_NO_APIC; |
| 1246 | } |
| 1247 | |
| 1248 | /* |
| 1249 | * If SMP should be disabled, then really disable it! |
| 1250 | */ |
| 1251 | if (!max_cpus) { |
| 1252 | pr_info("SMP mode deactivated\n"); |
| 1253 | return SMP_FORCE_UP; |
| 1254 | } |
| 1255 | |
| 1256 | return SMP_OK; |
| 1257 | } |
| 1258 | |
| 1259 | static void __init smp_cpu_index_default(void) |
| 1260 | { |
| 1261 | int i; |
| 1262 | struct cpuinfo_x86 *c; |
| 1263 | |
| 1264 | for_each_possible_cpu(i) { |
| 1265 | c = &cpu_data(i); |
| 1266 | /* mark all to hotplug */ |
| 1267 | c->cpu_index = nr_cpu_ids; |
| 1268 | } |
| 1269 | } |
| 1270 | |
| 1271 | /* |
| 1272 | * Prepare for SMP bootup. The MP table or ACPI has been read |
| 1273 | * earlier. Just do some sanity checking here and enable APIC mode. |
| 1274 | */ |
| 1275 | void __init native_smp_prepare_cpus(unsigned int max_cpus) |
| 1276 | { |
| 1277 | unsigned int i; |
| 1278 | |
| 1279 | smp_cpu_index_default(); |
| 1280 | |
| 1281 | /* |
| 1282 | * Setup boot CPU information |
| 1283 | */ |
| 1284 | smp_store_boot_cpu_info(); /* Final full version of the data */ |
| 1285 | cpumask_copy(cpu_callin_mask, cpumask_of(0)); |
| 1286 | mb(); |
| 1287 | |
| 1288 | current_thread_info()->cpu = 0; /* needed? */ |
| 1289 | for_each_possible_cpu(i) { |
| 1290 | zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); |
| 1291 | zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); |
| 1292 | zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); |
| 1293 | } |
| 1294 | set_cpu_sibling_map(0); |
| 1295 | |
| 1296 | switch (smp_sanity_check(max_cpus)) { |
| 1297 | case SMP_NO_CONFIG: |
| 1298 | disable_smp(); |
| 1299 | if (APIC_init_uniprocessor()) |
| 1300 | pr_notice("Local APIC not detected. Using dummy APIC emulation.\n"); |
| 1301 | return; |
| 1302 | case SMP_NO_APIC: |
| 1303 | disable_smp(); |
| 1304 | return; |
| 1305 | case SMP_FORCE_UP: |
| 1306 | disable_smp(); |
| 1307 | apic_bsp_setup(false); |
| 1308 | return; |
| 1309 | case SMP_OK: |
| 1310 | break; |
| 1311 | } |
| 1312 | |
| 1313 | default_setup_apic_routing(); |
| 1314 | |
| 1315 | if (read_apic_id() != boot_cpu_physical_apicid) { |
| 1316 | panic("Boot APIC ID in local APIC unexpected (%d vs %d)", |
| 1317 | read_apic_id(), boot_cpu_physical_apicid); |
| 1318 | /* Or can we switch back to PIC here? */ |
| 1319 | } |
| 1320 | |
| 1321 | cpu0_logical_apicid = apic_bsp_setup(false); |
| 1322 | |
| 1323 | pr_info("CPU%d: ", 0); |
| 1324 | print_cpu_info(&cpu_data(0)); |
| 1325 | |
| 1326 | if (is_uv_system()) |
| 1327 | uv_system_init(); |
| 1328 | |
| 1329 | set_mtrr_aps_delayed_init(); |
| 1330 | |
| 1331 | smp_quirk_init_udelay(); |
| 1332 | } |
| 1333 | |
| 1334 | void arch_enable_nonboot_cpus_begin(void) |
| 1335 | { |
| 1336 | set_mtrr_aps_delayed_init(); |
| 1337 | } |
| 1338 | |
| 1339 | void arch_enable_nonboot_cpus_end(void) |
| 1340 | { |
| 1341 | mtrr_aps_init(); |
| 1342 | } |
| 1343 | |
| 1344 | /* |
| 1345 | * Early setup to make printk work. |
| 1346 | */ |
| 1347 | void __init native_smp_prepare_boot_cpu(void) |
| 1348 | { |
| 1349 | int me = smp_processor_id(); |
| 1350 | switch_to_new_gdt(me); |
| 1351 | /* already set me in cpu_online_mask in boot_cpu_init() */ |
| 1352 | cpumask_set_cpu(me, cpu_callout_mask); |
| 1353 | cpu_set_state_online(me); |
| 1354 | } |
| 1355 | |
| 1356 | void __init native_smp_cpus_done(unsigned int max_cpus) |
| 1357 | { |
| 1358 | pr_debug("Boot done\n"); |
| 1359 | |
| 1360 | nmi_selftest(); |
| 1361 | impress_friends(); |
| 1362 | setup_ioapic_dest(); |
| 1363 | mtrr_aps_init(); |
| 1364 | } |
| 1365 | |
| 1366 | static int __initdata setup_possible_cpus = -1; |
| 1367 | static int __init _setup_possible_cpus(char *str) |
| 1368 | { |
| 1369 | get_option(&str, &setup_possible_cpus); |
| 1370 | return 0; |
| 1371 | } |
| 1372 | early_param("possible_cpus", _setup_possible_cpus); |
| 1373 | |
| 1374 | |
| 1375 | /* |
| 1376 | * cpu_possible_mask should be static, it cannot change as cpu's |
| 1377 | * are onlined, or offlined. The reason is per-cpu data-structures |
| 1378 | * are allocated by some modules at init time, and dont expect to |
| 1379 | * do this dynamically on cpu arrival/departure. |
| 1380 | * cpu_present_mask on the other hand can change dynamically. |
| 1381 | * In case when cpu_hotplug is not compiled, then we resort to current |
| 1382 | * behaviour, which is cpu_possible == cpu_present. |
| 1383 | * - Ashok Raj |
| 1384 | * |
| 1385 | * Three ways to find out the number of additional hotplug CPUs: |
| 1386 | * - If the BIOS specified disabled CPUs in ACPI/mptables use that. |
| 1387 | * - The user can overwrite it with possible_cpus=NUM |
| 1388 | * - Otherwise don't reserve additional CPUs. |
| 1389 | * We do this because additional CPUs waste a lot of memory. |
| 1390 | * -AK |
| 1391 | */ |
| 1392 | __init void prefill_possible_map(void) |
| 1393 | { |
| 1394 | int i, possible; |
| 1395 | |
| 1396 | /* no processor from mptable or madt */ |
| 1397 | if (!num_processors) |
| 1398 | num_processors = 1; |
| 1399 | |
| 1400 | i = setup_max_cpus ?: 1; |
| 1401 | if (setup_possible_cpus == -1) { |
| 1402 | possible = num_processors; |
| 1403 | #ifdef CONFIG_HOTPLUG_CPU |
| 1404 | if (setup_max_cpus) |
| 1405 | possible += disabled_cpus; |
| 1406 | #else |
| 1407 | if (possible > i) |
| 1408 | possible = i; |
| 1409 | #endif |
| 1410 | } else |
| 1411 | possible = setup_possible_cpus; |
| 1412 | |
| 1413 | total_cpus = max_t(int, possible, num_processors + disabled_cpus); |
| 1414 | |
| 1415 | /* nr_cpu_ids could be reduced via nr_cpus= */ |
| 1416 | if (possible > nr_cpu_ids) { |
| 1417 | pr_warn("%d Processors exceeds NR_CPUS limit of %d\n", |
| 1418 | possible, nr_cpu_ids); |
| 1419 | possible = nr_cpu_ids; |
| 1420 | } |
| 1421 | |
| 1422 | #ifdef CONFIG_HOTPLUG_CPU |
| 1423 | if (!setup_max_cpus) |
| 1424 | #endif |
| 1425 | if (possible > i) { |
| 1426 | pr_warn("%d Processors exceeds max_cpus limit of %u\n", |
| 1427 | possible, setup_max_cpus); |
| 1428 | possible = i; |
| 1429 | } |
| 1430 | |
| 1431 | pr_info("Allowing %d CPUs, %d hotplug CPUs\n", |
| 1432 | possible, max_t(int, possible - num_processors, 0)); |
| 1433 | |
| 1434 | for (i = 0; i < possible; i++) |
| 1435 | set_cpu_possible(i, true); |
| 1436 | for (; i < NR_CPUS; i++) |
| 1437 | set_cpu_possible(i, false); |
| 1438 | |
| 1439 | nr_cpu_ids = possible; |
| 1440 | } |
| 1441 | |
| 1442 | #ifdef CONFIG_HOTPLUG_CPU |
| 1443 | |
| 1444 | static void remove_siblinginfo(int cpu) |
| 1445 | { |
| 1446 | int sibling; |
| 1447 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
| 1448 | |
| 1449 | for_each_cpu(sibling, topology_core_cpumask(cpu)) { |
| 1450 | cpumask_clear_cpu(cpu, topology_core_cpumask(sibling)); |
| 1451 | /*/ |
| 1452 | * last thread sibling in this cpu core going down |
| 1453 | */ |
| 1454 | if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1) |
| 1455 | cpu_data(sibling).booted_cores--; |
| 1456 | } |
| 1457 | |
| 1458 | for_each_cpu(sibling, topology_sibling_cpumask(cpu)) |
| 1459 | cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling)); |
| 1460 | for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) |
| 1461 | cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling)); |
| 1462 | cpumask_clear(cpu_llc_shared_mask(cpu)); |
| 1463 | cpumask_clear(topology_sibling_cpumask(cpu)); |
| 1464 | cpumask_clear(topology_core_cpumask(cpu)); |
| 1465 | c->phys_proc_id = 0; |
| 1466 | c->cpu_core_id = 0; |
| 1467 | cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); |
| 1468 | } |
| 1469 | |
| 1470 | static void remove_cpu_from_maps(int cpu) |
| 1471 | { |
| 1472 | set_cpu_online(cpu, false); |
| 1473 | cpumask_clear_cpu(cpu, cpu_callout_mask); |
| 1474 | cpumask_clear_cpu(cpu, cpu_callin_mask); |
| 1475 | /* was set by cpu_init() */ |
| 1476 | cpumask_clear_cpu(cpu, cpu_initialized_mask); |
| 1477 | numa_remove_cpu(cpu); |
| 1478 | } |
| 1479 | |
| 1480 | void cpu_disable_common(void) |
| 1481 | { |
| 1482 | int cpu = smp_processor_id(); |
| 1483 | |
| 1484 | remove_siblinginfo(cpu); |
| 1485 | |
| 1486 | /* It's now safe to remove this processor from the online map */ |
| 1487 | lock_vector_lock(); |
| 1488 | remove_cpu_from_maps(cpu); |
| 1489 | unlock_vector_lock(); |
| 1490 | fixup_irqs(); |
| 1491 | } |
| 1492 | |
| 1493 | int native_cpu_disable(void) |
| 1494 | { |
| 1495 | int ret; |
| 1496 | |
| 1497 | ret = check_irq_vectors_for_cpu_disable(); |
| 1498 | if (ret) |
| 1499 | return ret; |
| 1500 | |
| 1501 | clear_local_APIC(); |
| 1502 | cpu_disable_common(); |
| 1503 | |
| 1504 | return 0; |
| 1505 | } |
| 1506 | |
| 1507 | int common_cpu_die(unsigned int cpu) |
| 1508 | { |
| 1509 | int ret = 0; |
| 1510 | |
| 1511 | /* We don't do anything here: idle task is faking death itself. */ |
| 1512 | |
| 1513 | /* They ack this in play_dead() by setting CPU_DEAD */ |
| 1514 | if (cpu_wait_death(cpu, 5)) { |
| 1515 | if (system_state == SYSTEM_RUNNING) |
| 1516 | pr_info("CPU %u is now offline\n", cpu); |
| 1517 | } else { |
| 1518 | pr_err("CPU %u didn't die...\n", cpu); |
| 1519 | ret = -1; |
| 1520 | } |
| 1521 | |
| 1522 | return ret; |
| 1523 | } |
| 1524 | |
| 1525 | void native_cpu_die(unsigned int cpu) |
| 1526 | { |
| 1527 | common_cpu_die(cpu); |
| 1528 | } |
| 1529 | |
| 1530 | void play_dead_common(void) |
| 1531 | { |
| 1532 | idle_task_exit(); |
| 1533 | reset_lazy_tlbstate(); |
| 1534 | amd_e400_remove_cpu(raw_smp_processor_id()); |
| 1535 | |
| 1536 | /* Ack it */ |
| 1537 | (void)cpu_report_death(); |
| 1538 | |
| 1539 | /* |
| 1540 | * With physical CPU hotplug, we should halt the cpu |
| 1541 | */ |
| 1542 | local_irq_disable(); |
| 1543 | } |
| 1544 | |
| 1545 | static bool wakeup_cpu0(void) |
| 1546 | { |
| 1547 | if (smp_processor_id() == 0 && enable_start_cpu0) |
| 1548 | return true; |
| 1549 | |
| 1550 | return false; |
| 1551 | } |
| 1552 | |
| 1553 | /* |
| 1554 | * We need to flush the caches before going to sleep, lest we have |
| 1555 | * dirty data in our caches when we come back up. |
| 1556 | */ |
| 1557 | static inline void mwait_play_dead(void) |
| 1558 | { |
| 1559 | unsigned int eax, ebx, ecx, edx; |
| 1560 | unsigned int highest_cstate = 0; |
| 1561 | unsigned int highest_subcstate = 0; |
| 1562 | void *mwait_ptr; |
| 1563 | int i; |
| 1564 | |
| 1565 | if (!this_cpu_has(X86_FEATURE_MWAIT)) |
| 1566 | return; |
| 1567 | if (!this_cpu_has(X86_FEATURE_CLFLUSH)) |
| 1568 | return; |
| 1569 | if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) |
| 1570 | return; |
| 1571 | |
| 1572 | eax = CPUID_MWAIT_LEAF; |
| 1573 | ecx = 0; |
| 1574 | native_cpuid(&eax, &ebx, &ecx, &edx); |
| 1575 | |
| 1576 | /* |
| 1577 | * eax will be 0 if EDX enumeration is not valid. |
| 1578 | * Initialized below to cstate, sub_cstate value when EDX is valid. |
| 1579 | */ |
| 1580 | if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { |
| 1581 | eax = 0; |
| 1582 | } else { |
| 1583 | edx >>= MWAIT_SUBSTATE_SIZE; |
| 1584 | for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { |
| 1585 | if (edx & MWAIT_SUBSTATE_MASK) { |
| 1586 | highest_cstate = i; |
| 1587 | highest_subcstate = edx & MWAIT_SUBSTATE_MASK; |
| 1588 | } |
| 1589 | } |
| 1590 | eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | |
| 1591 | (highest_subcstate - 1); |
| 1592 | } |
| 1593 | |
| 1594 | /* |
| 1595 | * This should be a memory location in a cache line which is |
| 1596 | * unlikely to be touched by other processors. The actual |
| 1597 | * content is immaterial as it is not actually modified in any way. |
| 1598 | */ |
| 1599 | mwait_ptr = ¤t_thread_info()->flags; |
| 1600 | |
| 1601 | wbinvd(); |
| 1602 | |
| 1603 | while (1) { |
| 1604 | /* |
| 1605 | * The CLFLUSH is a workaround for erratum AAI65 for |
| 1606 | * the Xeon 7400 series. It's not clear it is actually |
| 1607 | * needed, but it should be harmless in either case. |
| 1608 | * The WBINVD is insufficient due to the spurious-wakeup |
| 1609 | * case where we return around the loop. |
| 1610 | */ |
| 1611 | mb(); |
| 1612 | clflush(mwait_ptr); |
| 1613 | mb(); |
| 1614 | __monitor(mwait_ptr, 0, 0); |
| 1615 | mb(); |
| 1616 | __mwait(eax, 0); |
| 1617 | /* |
| 1618 | * If NMI wants to wake up CPU0, start CPU0. |
| 1619 | */ |
| 1620 | if (wakeup_cpu0()) |
| 1621 | start_cpu0(); |
| 1622 | } |
| 1623 | } |
| 1624 | |
| 1625 | static inline void hlt_play_dead(void) |
| 1626 | { |
| 1627 | if (__this_cpu_read(cpu_info.x86) >= 4) |
| 1628 | wbinvd(); |
| 1629 | |
| 1630 | while (1) { |
| 1631 | native_halt(); |
| 1632 | /* |
| 1633 | * If NMI wants to wake up CPU0, start CPU0. |
| 1634 | */ |
| 1635 | if (wakeup_cpu0()) |
| 1636 | start_cpu0(); |
| 1637 | } |
| 1638 | } |
| 1639 | |
| 1640 | void native_play_dead(void) |
| 1641 | { |
| 1642 | play_dead_common(); |
| 1643 | tboot_shutdown(TB_SHUTDOWN_WFS); |
| 1644 | |
| 1645 | mwait_play_dead(); /* Only returns on failure */ |
| 1646 | if (cpuidle_play_dead()) |
| 1647 | hlt_play_dead(); |
| 1648 | } |
| 1649 | |
| 1650 | #else /* ... !CONFIG_HOTPLUG_CPU */ |
| 1651 | int native_cpu_disable(void) |
| 1652 | { |
| 1653 | return -ENOSYS; |
| 1654 | } |
| 1655 | |
| 1656 | void native_cpu_die(unsigned int cpu) |
| 1657 | { |
| 1658 | /* We said "no" in __cpu_disable */ |
| 1659 | BUG(); |
| 1660 | } |
| 1661 | |
| 1662 | void native_play_dead(void) |
| 1663 | { |
| 1664 | BUG(); |
| 1665 | } |
| 1666 | |
| 1667 | #endif |