| 1 | /* |
| 2 | * SH7722 Setup |
| 3 | * |
| 4 | * Copyright (C) 2006 - 2007 Paul Mundt |
| 5 | * |
| 6 | * This file is subject to the terms and conditions of the GNU General Public |
| 7 | * License. See the file "COPYING" in the main directory of this archive |
| 8 | * for more details. |
| 9 | */ |
| 10 | #include <linux/platform_device.h> |
| 11 | #include <linux/init.h> |
| 12 | #include <linux/serial.h> |
| 13 | #include <linux/mm.h> |
| 14 | #include <asm/mmzone.h> |
| 15 | #include <asm/sci.h> |
| 16 | |
| 17 | static struct plat_sci_port sci_platform_data[] = { |
| 18 | { |
| 19 | .mapbase = 0xffe00000, |
| 20 | .flags = UPF_BOOT_AUTOCONF, |
| 21 | .type = PORT_SCIF, |
| 22 | .irqs = { 80, 80, 80, 80 }, |
| 23 | }, |
| 24 | { |
| 25 | .mapbase = 0xffe10000, |
| 26 | .flags = UPF_BOOT_AUTOCONF, |
| 27 | .type = PORT_SCIF, |
| 28 | .irqs = { 81, 81, 81, 81 }, |
| 29 | }, |
| 30 | { |
| 31 | .mapbase = 0xffe20000, |
| 32 | .flags = UPF_BOOT_AUTOCONF, |
| 33 | .type = PORT_SCIF, |
| 34 | .irqs = { 82, 82, 82, 82 }, |
| 35 | }, |
| 36 | { |
| 37 | .flags = 0, |
| 38 | } |
| 39 | }; |
| 40 | |
| 41 | static struct platform_device sci_device = { |
| 42 | .name = "sh-sci", |
| 43 | .id = -1, |
| 44 | .dev = { |
| 45 | .platform_data = sci_platform_data, |
| 46 | }, |
| 47 | }; |
| 48 | |
| 49 | static struct platform_device *sh7722_devices[] __initdata = { |
| 50 | &sci_device, |
| 51 | }; |
| 52 | |
| 53 | static int __init sh7722_devices_setup(void) |
| 54 | { |
| 55 | return platform_add_devices(sh7722_devices, |
| 56 | ARRAY_SIZE(sh7722_devices)); |
| 57 | } |
| 58 | __initcall(sh7722_devices_setup); |
| 59 | |
| 60 | enum { |
| 61 | UNUSED=0, |
| 62 | |
| 63 | /* interrupt sources */ |
| 64 | IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, |
| 65 | HUDI, |
| 66 | SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI, |
| 67 | RTC_ATI, RTC_PRI, RTC_CUI, |
| 68 | DMAC0, DMAC1, DMAC2, DMAC3, |
| 69 | VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU, |
| 70 | VPU, TPU, |
| 71 | USB_USBI0, USB_USBI1, |
| 72 | DMAC4, DMAC5, DMAC_DADERR, |
| 73 | KEYSC, |
| 74 | SCIF0, SCIF1, SCIF2, SIOF0, SIOF1, SIO, |
| 75 | FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I, |
| 76 | I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI, |
| 77 | SDHI0, SDHI1, SDHI2, SDHI3, |
| 78 | CMT, TSIF, SIU, TWODG, |
| 79 | TMU0, TMU1, TMU2, |
| 80 | IRDA, JPU, LCDC, |
| 81 | |
| 82 | /* interrupt groups */ |
| 83 | |
| 84 | SIM, RTC, DMAC0123, VIOVOU, USB, DMAC45, FLCTL, I2C, SDHI, |
| 85 | }; |
| 86 | |
| 87 | static struct intc_vect vectors[] = { |
| 88 | INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), |
| 89 | INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), |
| 90 | INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), |
| 91 | INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0), |
| 92 | INTC_VECT(SIM_ERI, 0x700), INTC_VECT(SIM_RXI, 0x720), |
| 93 | INTC_VECT(SIM_TXI, 0x740), INTC_VECT(SIM_TEI, 0x760), |
| 94 | INTC_VECT(RTC_ATI, 0x780), INTC_VECT(RTC_PRI, 0x7a0), |
| 95 | INTC_VECT(RTC_CUI, 0x7c0), |
| 96 | INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820), |
| 97 | INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860), |
| 98 | INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0), |
| 99 | INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0), |
| 100 | INTC_VECT(VPU, 0x980), INTC_VECT(TPU, 0x9a0), |
| 101 | INTC_VECT(USB_USBI0, 0xa20), INTC_VECT(USB_USBI1, 0xa40), |
| 102 | INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0), |
| 103 | INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0), |
| 104 | INTC_VECT(SCIF0, 0xc00), INTC_VECT(SCIF1, 0xc20), |
| 105 | INTC_VECT(SCIF2, 0xc40), INTC_VECT(SIOF0, 0xc80), |
| 106 | INTC_VECT(SIOF1, 0xca0), INTC_VECT(SIO, 0xd00), |
| 107 | INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0), |
| 108 | INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0), |
| 109 | INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20), |
| 110 | INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60), |
| 111 | INTC_VECT(SDHI0, 0xe80), INTC_VECT(SDHI1, 0xea0), |
| 112 | INTC_VECT(SDHI2, 0xec0), INTC_VECT(SDHI3, 0xee0), |
| 113 | INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20), |
| 114 | INTC_VECT(SIU, 0xf80), INTC_VECT(TWODG, 0xfa0), |
| 115 | INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), |
| 116 | INTC_VECT(TMU2, 0x440), INTC_VECT(IRDA, 0x480), |
| 117 | INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580), |
| 118 | }; |
| 119 | |
| 120 | static struct intc_group groups[] = { |
| 121 | INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI), |
| 122 | INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI), |
| 123 | INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3), |
| 124 | INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU), |
| 125 | INTC_GROUP(USB, USB_USBI0, USB_USBI1), |
| 126 | INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR), |
| 127 | INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI, |
| 128 | FLCTL_FLTREQ0I, FLCTL_FLTREQ1I), |
| 129 | INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI), |
| 130 | INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3), |
| 131 | }; |
| 132 | |
| 133 | static struct intc_prio priorities[] = { |
| 134 | INTC_PRIO(SCIF0, 3), |
| 135 | INTC_PRIO(SCIF1, 3), |
| 136 | INTC_PRIO(SCIF2, 3), |
| 137 | INTC_PRIO(TMU0, 2), |
| 138 | INTC_PRIO(TMU1, 2), |
| 139 | }; |
| 140 | |
| 141 | static struct intc_mask_reg mask_registers[] = { |
| 142 | { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */ |
| 143 | { } }, |
| 144 | { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ |
| 145 | { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } }, |
| 146 | { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */ |
| 147 | { 0, 0, 0, VPU, } }, |
| 148 | { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */ |
| 149 | { SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } }, |
| 150 | { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */ |
| 151 | { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } }, |
| 152 | { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */ |
| 153 | { KEYSC, DMAC_DADERR, DMAC5, DMAC4, 0, SCIF2, SCIF1, SCIF0 } }, |
| 154 | { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */ |
| 155 | { 0, 0, 0, SIO, 0, 0, SIOF1, SIOF0 } }, |
| 156 | { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */ |
| 157 | { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI, |
| 158 | FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } }, |
| 159 | { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ |
| 160 | { SDHI3, SDHI2, SDHI1, SDHI0, 0, 0, TWODG, SIU } }, |
| 161 | { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ |
| 162 | { 0, 0, 0, CMT, 0, USB_USBI1, USB_USBI0, } }, |
| 163 | { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */ |
| 164 | { } }, |
| 165 | { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */ |
| 166 | { 0, RTC_CUI, RTC_PRI, RTC_ATI, 0, TPU, 0, TSIF } }, |
| 167 | { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */ |
| 168 | { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, |
| 169 | }; |
| 170 | |
| 171 | static struct intc_prio_reg prio_registers[] = { |
| 172 | { 0xa4080000, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, IRDA } }, |
| 173 | { 0xa4080004, 16, 4, /* IPRB */ { JPU, LCDC, SIM } }, |
| 174 | { 0xa4080008, 16, 4, /* IPRC */ { } }, |
| 175 | { 0xa408000c, 16, 4, /* IPRD */ { } }, |
| 176 | { 0xa4080010, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, 0, VPU } }, |
| 177 | { 0xa4080014, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } }, |
| 178 | { 0xa4080018, 16, 4, /* IPRG */ { SCIF0, SCIF1, SCIF2 } }, |
| 179 | { 0xa408001c, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C } }, |
| 180 | { 0xa4080020, 16, 4, /* IPRI */ { SIO, 0, TSIF, RTC } }, |
| 181 | { 0xa4080024, 16, 4, /* IPRJ */ { 0, 0, SIU } }, |
| 182 | { 0xa4080028, 16, 4, /* IPRK */ { 0, 0, 0, SDHI } }, |
| 183 | { 0xa408002c, 16, 4, /* IPRL */ { TWODG, 0, TPU } }, |
| 184 | { 0xa4140010, 32, 4, /* INTPRI00 */ |
| 185 | { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, |
| 186 | }; |
| 187 | |
| 188 | static struct intc_sense_reg sense_registers[] = { |
| 189 | { 0xa414001c, 16, 2, /* ICR1 */ |
| 190 | { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, |
| 191 | }; |
| 192 | |
| 193 | static DECLARE_INTC_DESC(intc_desc, "sh7722", vectors, groups, priorities, |
| 194 | mask_registers, prio_registers, sense_registers); |
| 195 | |
| 196 | void __init plat_irq_setup(void) |
| 197 | { |
| 198 | register_intc_controller(&intc_desc); |
| 199 | } |
| 200 | |
| 201 | void __init plat_mem_setup(void) |
| 202 | { |
| 203 | /* Register the URAM space as Node 1 */ |
| 204 | setup_bootmem_node(1, 0x055f0000, 0x05610000); |
| 205 | } |