| 1 | * Freescale Enhanced Secure Digital Host Controller (eSDHC) for i.MX |
| 2 | |
| 3 | The Enhanced Secure Digital Host Controller on Freescale i.MX family |
| 4 | provides an interface for MMC, SD, and SDIO types of memory cards. |
| 5 | |
| 6 | This file documents differences between the core properties described |
| 7 | by mmc.txt and the properties used by the sdhci-esdhc-imx driver. |
| 8 | |
| 9 | Required properties: |
| 10 | - compatible : Should be "fsl,<chip>-esdhc", the supported chips include |
| 11 | "fsl,imx25-esdhc" |
| 12 | "fsl,imx35-esdhc" |
| 13 | "fsl,imx51-esdhc" |
| 14 | "fsl,imx53-esdhc" |
| 15 | "fsl,imx6q-usdhc" |
| 16 | "fsl,imx6sl-usdhc" |
| 17 | "fsl,imx6sx-usdhc" |
| 18 | |
| 19 | Optional properties: |
| 20 | - fsl,wp-controller : Indicate to use controller internal write protection |
| 21 | - fsl,delay-line : Specify the number of delay cells for override mode. |
| 22 | This is used to set the clock delay for DLL(Delay Line) on override mode |
| 23 | to select a proper data sampling window in case the clock quality is not good |
| 24 | due to signal path is too long on the board. Please refer to eSDHC/uSDHC |
| 25 | chapter, DLL (Delay Line) section in RM for details. |
| 26 | - voltage-ranges : Specify the voltage range in case there are software |
| 27 | transparent level shifters on the outputs of the controller. Two cells are |
| 28 | required, first cell specifies minimum slot voltage (mV), second cell |
| 29 | specifies maximum slot voltage (mV). Several ranges could be specified. |
| 30 | |
| 31 | Examples: |
| 32 | |
| 33 | esdhc@70004000 { |
| 34 | compatible = "fsl,imx51-esdhc"; |
| 35 | reg = <0x70004000 0x4000>; |
| 36 | interrupts = <1>; |
| 37 | fsl,wp-controller; |
| 38 | }; |
| 39 | |
| 40 | esdhc@70008000 { |
| 41 | compatible = "fsl,imx51-esdhc"; |
| 42 | reg = <0x70008000 0x4000>; |
| 43 | interrupts = <2>; |
| 44 | cd-gpios = <&gpio1 6 0>; /* GPIO1_6 */ |
| 45 | wp-gpios = <&gpio1 5 0>; /* GPIO1_5 */ |
| 46 | }; |