Commit | Line | Data |
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1a89dd91 MZ |
1 | /* |
2 | * Copyright (C) 2012 ARM Ltd. | |
3 | * Author: Marc Zyngier <marc.zyngier@arm.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
17 | */ | |
18 | ||
01ac5e34 | 19 | #include <linux/cpu.h> |
1a89dd91 MZ |
20 | #include <linux/kvm.h> |
21 | #include <linux/kvm_host.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/io.h> | |
01ac5e34 MZ |
24 | #include <linux/of.h> |
25 | #include <linux/of_address.h> | |
26 | #include <linux/of_irq.h> | |
2a2f3e26 | 27 | #include <linux/uaccess.h> |
01ac5e34 MZ |
28 | |
29 | #include <linux/irqchip/arm-gic.h> | |
30 | ||
1a89dd91 | 31 | #include <asm/kvm_emulate.h> |
01ac5e34 MZ |
32 | #include <asm/kvm_arm.h> |
33 | #include <asm/kvm_mmu.h> | |
1a89dd91 | 34 | |
b47ef92a MZ |
35 | /* |
36 | * How the whole thing works (courtesy of Christoffer Dall): | |
37 | * | |
38 | * - At any time, the dist->irq_pending_on_cpu is the oracle that knows if | |
7e362919 CD |
39 | * something is pending on the CPU interface. |
40 | * - Interrupts that are pending on the distributor are stored on the | |
41 | * vgic.irq_pending vgic bitmap (this bitmap is updated by both user land | |
42 | * ioctls and guest mmio ops, and other in-kernel peripherals such as the | |
43 | * arch. timers). | |
b47ef92a MZ |
44 | * - Every time the bitmap changes, the irq_pending_on_cpu oracle is |
45 | * recalculated | |
46 | * - To calculate the oracle, we need info for each cpu from | |
47 | * compute_pending_for_cpu, which considers: | |
227844f5 CD |
48 | * - PPI: dist->irq_pending & dist->irq_enable |
49 | * - SPI: dist->irq_pending & dist->irq_enable & dist->irq_spi_target | |
7e362919 | 50 | * - irq_spi_target is a 'formatted' version of the GICD_ITARGETSRn |
b47ef92a MZ |
51 | * registers, stored on each vcpu. We only keep one bit of |
52 | * information per interrupt, making sure that only one vcpu can | |
53 | * accept the interrupt. | |
7e362919 | 54 | * - If any of the above state changes, we must recalculate the oracle. |
b47ef92a MZ |
55 | * - The same is true when injecting an interrupt, except that we only |
56 | * consider a single interrupt at a time. The irq_spi_cpu array | |
57 | * contains the target CPU for each SPI. | |
58 | * | |
59 | * The handling of level interrupts adds some extra complexity. We | |
60 | * need to track when the interrupt has been EOIed, so we can sample | |
61 | * the 'line' again. This is achieved as such: | |
62 | * | |
63 | * - When a level interrupt is moved onto a vcpu, the corresponding | |
dbf20f9d | 64 | * bit in irq_queued is set. As long as this bit is set, the line |
b47ef92a MZ |
65 | * will be ignored for further interrupts. The interrupt is injected |
66 | * into the vcpu with the GICH_LR_EOI bit set (generate a | |
67 | * maintenance interrupt on EOI). | |
68 | * - When the interrupt is EOIed, the maintenance interrupt fires, | |
dbf20f9d | 69 | * and clears the corresponding bit in irq_queued. This allows the |
b47ef92a | 70 | * interrupt line to be sampled again. |
faa1b46c CD |
71 | * - Note that level-triggered interrupts can also be set to pending from |
72 | * writes to GICD_ISPENDRn and lowering the external input line does not | |
73 | * cause the interrupt to become inactive in such a situation. | |
74 | * Conversely, writes to GICD_ICPENDRn do not cause the interrupt to become | |
75 | * inactive as long as the external input line is held high. | |
b47ef92a MZ |
76 | */ |
77 | ||
83215812 | 78 | #include "vgic.h" |
330690cd | 79 | |
a1fcb44e | 80 | static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu); |
8d5c6b06 | 81 | static void vgic_retire_lr(int lr_nr, int irq, struct kvm_vcpu *vcpu); |
8d5c6b06 MZ |
82 | static struct vgic_lr vgic_get_lr(const struct kvm_vcpu *vcpu, int lr); |
83 | static void vgic_set_lr(struct kvm_vcpu *vcpu, int lr, struct vgic_lr lr_desc); | |
01ac5e34 | 84 | |
8f186d52 MZ |
85 | static const struct vgic_ops *vgic_ops; |
86 | static const struct vgic_params *vgic; | |
b47ef92a | 87 | |
b26e5fda AP |
88 | static void add_sgi_source(struct kvm_vcpu *vcpu, int irq, int source) |
89 | { | |
90 | vcpu->kvm->arch.vgic.vm_ops.add_sgi_source(vcpu, irq, source); | |
91 | } | |
92 | ||
93 | static bool queue_sgi(struct kvm_vcpu *vcpu, int irq) | |
94 | { | |
95 | return vcpu->kvm->arch.vgic.vm_ops.queue_sgi(vcpu, irq); | |
96 | } | |
97 | ||
98 | int kvm_vgic_map_resources(struct kvm *kvm) | |
99 | { | |
100 | return kvm->arch.vgic.vm_ops.map_resources(kvm, vgic); | |
101 | } | |
102 | ||
9662fb48 | 103 | /* |
c1bfb577 MZ |
104 | * struct vgic_bitmap contains a bitmap made of unsigned longs, but |
105 | * extracts u32s out of them. | |
9662fb48 VK |
106 | * |
107 | * This does not work on 64-bit BE systems, because the bitmap access | |
108 | * will store two consecutive 32-bit words with the higher-addressed | |
109 | * register's bits at the lower index and the lower-addressed register's | |
110 | * bits at the higher index. | |
111 | * | |
112 | * Therefore, swizzle the register index when accessing the 32-bit word | |
113 | * registers to access the right register's value. | |
114 | */ | |
115 | #if defined(CONFIG_CPU_BIG_ENDIAN) && BITS_PER_LONG == 64 | |
116 | #define REG_OFFSET_SWIZZLE 1 | |
117 | #else | |
118 | #define REG_OFFSET_SWIZZLE 0 | |
119 | #endif | |
b47ef92a | 120 | |
c1bfb577 MZ |
121 | static int vgic_init_bitmap(struct vgic_bitmap *b, int nr_cpus, int nr_irqs) |
122 | { | |
123 | int nr_longs; | |
124 | ||
125 | nr_longs = nr_cpus + BITS_TO_LONGS(nr_irqs - VGIC_NR_PRIVATE_IRQS); | |
126 | ||
127 | b->private = kzalloc(sizeof(unsigned long) * nr_longs, GFP_KERNEL); | |
128 | if (!b->private) | |
129 | return -ENOMEM; | |
130 | ||
131 | b->shared = b->private + nr_cpus; | |
132 | ||
133 | return 0; | |
134 | } | |
135 | ||
136 | static void vgic_free_bitmap(struct vgic_bitmap *b) | |
137 | { | |
138 | kfree(b->private); | |
139 | b->private = NULL; | |
140 | b->shared = NULL; | |
141 | } | |
142 | ||
2df36a5d CD |
143 | /* |
144 | * Call this function to convert a u64 value to an unsigned long * bitmask | |
145 | * in a way that works on both 32-bit and 64-bit LE and BE platforms. | |
146 | * | |
147 | * Warning: Calling this function may modify *val. | |
148 | */ | |
149 | static unsigned long *u64_to_bitmask(u64 *val) | |
150 | { | |
151 | #if defined(CONFIG_CPU_BIG_ENDIAN) && BITS_PER_LONG == 32 | |
152 | *val = (*val >> 32) | (*val << 32); | |
153 | #endif | |
154 | return (unsigned long *)val; | |
155 | } | |
156 | ||
83215812 | 157 | u32 *vgic_bitmap_get_reg(struct vgic_bitmap *x, int cpuid, u32 offset) |
b47ef92a MZ |
158 | { |
159 | offset >>= 2; | |
160 | if (!offset) | |
c1bfb577 | 161 | return (u32 *)(x->private + cpuid) + REG_OFFSET_SWIZZLE; |
b47ef92a | 162 | else |
c1bfb577 | 163 | return (u32 *)(x->shared) + ((offset - 1) ^ REG_OFFSET_SWIZZLE); |
b47ef92a MZ |
164 | } |
165 | ||
166 | static int vgic_bitmap_get_irq_val(struct vgic_bitmap *x, | |
167 | int cpuid, int irq) | |
168 | { | |
169 | if (irq < VGIC_NR_PRIVATE_IRQS) | |
c1bfb577 | 170 | return test_bit(irq, x->private + cpuid); |
b47ef92a | 171 | |
c1bfb577 | 172 | return test_bit(irq - VGIC_NR_PRIVATE_IRQS, x->shared); |
b47ef92a MZ |
173 | } |
174 | ||
83215812 AP |
175 | void vgic_bitmap_set_irq_val(struct vgic_bitmap *x, int cpuid, |
176 | int irq, int val) | |
b47ef92a MZ |
177 | { |
178 | unsigned long *reg; | |
179 | ||
180 | if (irq < VGIC_NR_PRIVATE_IRQS) { | |
c1bfb577 | 181 | reg = x->private + cpuid; |
b47ef92a | 182 | } else { |
c1bfb577 | 183 | reg = x->shared; |
b47ef92a MZ |
184 | irq -= VGIC_NR_PRIVATE_IRQS; |
185 | } | |
186 | ||
187 | if (val) | |
188 | set_bit(irq, reg); | |
189 | else | |
190 | clear_bit(irq, reg); | |
191 | } | |
192 | ||
193 | static unsigned long *vgic_bitmap_get_cpu_map(struct vgic_bitmap *x, int cpuid) | |
194 | { | |
c1bfb577 | 195 | return x->private + cpuid; |
b47ef92a MZ |
196 | } |
197 | ||
83215812 | 198 | unsigned long *vgic_bitmap_get_shared_map(struct vgic_bitmap *x) |
b47ef92a | 199 | { |
c1bfb577 MZ |
200 | return x->shared; |
201 | } | |
202 | ||
203 | static int vgic_init_bytemap(struct vgic_bytemap *x, int nr_cpus, int nr_irqs) | |
204 | { | |
205 | int size; | |
206 | ||
207 | size = nr_cpus * VGIC_NR_PRIVATE_IRQS; | |
208 | size += nr_irqs - VGIC_NR_PRIVATE_IRQS; | |
209 | ||
210 | x->private = kzalloc(size, GFP_KERNEL); | |
211 | if (!x->private) | |
212 | return -ENOMEM; | |
213 | ||
214 | x->shared = x->private + nr_cpus * VGIC_NR_PRIVATE_IRQS / sizeof(u32); | |
215 | return 0; | |
216 | } | |
217 | ||
218 | static void vgic_free_bytemap(struct vgic_bytemap *b) | |
219 | { | |
220 | kfree(b->private); | |
221 | b->private = NULL; | |
222 | b->shared = NULL; | |
b47ef92a MZ |
223 | } |
224 | ||
83215812 | 225 | u32 *vgic_bytemap_get_reg(struct vgic_bytemap *x, int cpuid, u32 offset) |
b47ef92a | 226 | { |
c1bfb577 MZ |
227 | u32 *reg; |
228 | ||
229 | if (offset < VGIC_NR_PRIVATE_IRQS) { | |
230 | reg = x->private; | |
231 | offset += cpuid * VGIC_NR_PRIVATE_IRQS; | |
232 | } else { | |
233 | reg = x->shared; | |
234 | offset -= VGIC_NR_PRIVATE_IRQS; | |
235 | } | |
236 | ||
237 | return reg + (offset / sizeof(u32)); | |
b47ef92a MZ |
238 | } |
239 | ||
240 | #define VGIC_CFG_LEVEL 0 | |
241 | #define VGIC_CFG_EDGE 1 | |
242 | ||
243 | static bool vgic_irq_is_edge(struct kvm_vcpu *vcpu, int irq) | |
244 | { | |
245 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
246 | int irq_val; | |
247 | ||
248 | irq_val = vgic_bitmap_get_irq_val(&dist->irq_cfg, vcpu->vcpu_id, irq); | |
249 | return irq_val == VGIC_CFG_EDGE; | |
250 | } | |
251 | ||
252 | static int vgic_irq_is_enabled(struct kvm_vcpu *vcpu, int irq) | |
253 | { | |
254 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
255 | ||
256 | return vgic_bitmap_get_irq_val(&dist->irq_enabled, vcpu->vcpu_id, irq); | |
257 | } | |
258 | ||
dbf20f9d | 259 | static int vgic_irq_is_queued(struct kvm_vcpu *vcpu, int irq) |
9d949dce MZ |
260 | { |
261 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
262 | ||
dbf20f9d | 263 | return vgic_bitmap_get_irq_val(&dist->irq_queued, vcpu->vcpu_id, irq); |
9d949dce MZ |
264 | } |
265 | ||
dbf20f9d | 266 | static void vgic_irq_set_queued(struct kvm_vcpu *vcpu, int irq) |
9d949dce MZ |
267 | { |
268 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
269 | ||
dbf20f9d | 270 | vgic_bitmap_set_irq_val(&dist->irq_queued, vcpu->vcpu_id, irq, 1); |
9d949dce MZ |
271 | } |
272 | ||
dbf20f9d | 273 | static void vgic_irq_clear_queued(struct kvm_vcpu *vcpu, int irq) |
9d949dce MZ |
274 | { |
275 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
276 | ||
dbf20f9d | 277 | vgic_bitmap_set_irq_val(&dist->irq_queued, vcpu->vcpu_id, irq, 0); |
9d949dce MZ |
278 | } |
279 | ||
faa1b46c CD |
280 | static int vgic_dist_irq_get_level(struct kvm_vcpu *vcpu, int irq) |
281 | { | |
282 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
283 | ||
284 | return vgic_bitmap_get_irq_val(&dist->irq_level, vcpu->vcpu_id, irq); | |
285 | } | |
286 | ||
287 | static void vgic_dist_irq_set_level(struct kvm_vcpu *vcpu, int irq) | |
288 | { | |
289 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
290 | ||
291 | vgic_bitmap_set_irq_val(&dist->irq_level, vcpu->vcpu_id, irq, 1); | |
292 | } | |
293 | ||
294 | static void vgic_dist_irq_clear_level(struct kvm_vcpu *vcpu, int irq) | |
295 | { | |
296 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
297 | ||
298 | vgic_bitmap_set_irq_val(&dist->irq_level, vcpu->vcpu_id, irq, 0); | |
299 | } | |
300 | ||
301 | static int vgic_dist_irq_soft_pend(struct kvm_vcpu *vcpu, int irq) | |
302 | { | |
303 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
304 | ||
305 | return vgic_bitmap_get_irq_val(&dist->irq_soft_pend, vcpu->vcpu_id, irq); | |
306 | } | |
307 | ||
308 | static void vgic_dist_irq_clear_soft_pend(struct kvm_vcpu *vcpu, int irq) | |
309 | { | |
310 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
311 | ||
312 | vgic_bitmap_set_irq_val(&dist->irq_soft_pend, vcpu->vcpu_id, irq, 0); | |
313 | } | |
314 | ||
9d949dce MZ |
315 | static int vgic_dist_irq_is_pending(struct kvm_vcpu *vcpu, int irq) |
316 | { | |
317 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
318 | ||
227844f5 | 319 | return vgic_bitmap_get_irq_val(&dist->irq_pending, vcpu->vcpu_id, irq); |
9d949dce MZ |
320 | } |
321 | ||
83215812 | 322 | void vgic_dist_irq_set_pending(struct kvm_vcpu *vcpu, int irq) |
b47ef92a MZ |
323 | { |
324 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
325 | ||
227844f5 | 326 | vgic_bitmap_set_irq_val(&dist->irq_pending, vcpu->vcpu_id, irq, 1); |
b47ef92a MZ |
327 | } |
328 | ||
83215812 | 329 | void vgic_dist_irq_clear_pending(struct kvm_vcpu *vcpu, int irq) |
b47ef92a MZ |
330 | { |
331 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
332 | ||
227844f5 | 333 | vgic_bitmap_set_irq_val(&dist->irq_pending, vcpu->vcpu_id, irq, 0); |
b47ef92a MZ |
334 | } |
335 | ||
336 | static void vgic_cpu_irq_set(struct kvm_vcpu *vcpu, int irq) | |
337 | { | |
338 | if (irq < VGIC_NR_PRIVATE_IRQS) | |
339 | set_bit(irq, vcpu->arch.vgic_cpu.pending_percpu); | |
340 | else | |
341 | set_bit(irq - VGIC_NR_PRIVATE_IRQS, | |
342 | vcpu->arch.vgic_cpu.pending_shared); | |
343 | } | |
344 | ||
83215812 | 345 | void vgic_cpu_irq_clear(struct kvm_vcpu *vcpu, int irq) |
b47ef92a MZ |
346 | { |
347 | if (irq < VGIC_NR_PRIVATE_IRQS) | |
348 | clear_bit(irq, vcpu->arch.vgic_cpu.pending_percpu); | |
349 | else | |
350 | clear_bit(irq - VGIC_NR_PRIVATE_IRQS, | |
351 | vcpu->arch.vgic_cpu.pending_shared); | |
352 | } | |
353 | ||
dbf20f9d CD |
354 | static bool vgic_can_sample_irq(struct kvm_vcpu *vcpu, int irq) |
355 | { | |
356 | return vgic_irq_is_edge(vcpu, irq) || !vgic_irq_is_queued(vcpu, irq); | |
357 | } | |
358 | ||
1a89dd91 MZ |
359 | /** |
360 | * vgic_reg_access - access vgic register | |
361 | * @mmio: pointer to the data describing the mmio access | |
362 | * @reg: pointer to the virtual backing of vgic distributor data | |
363 | * @offset: least significant 2 bits used for word offset | |
364 | * @mode: ACCESS_ mode (see defines above) | |
365 | * | |
366 | * Helper to make vgic register access easier using one of the access | |
367 | * modes defined for vgic register access | |
368 | * (read,raz,write-ignored,setbit,clearbit,write) | |
369 | */ | |
83215812 AP |
370 | void vgic_reg_access(struct kvm_exit_mmio *mmio, u32 *reg, |
371 | phys_addr_t offset, int mode) | |
1a89dd91 MZ |
372 | { |
373 | int word_offset = (offset & 3) * 8; | |
374 | u32 mask = (1UL << (mmio->len * 8)) - 1; | |
375 | u32 regval; | |
376 | ||
377 | /* | |
378 | * Any alignment fault should have been delivered to the guest | |
379 | * directly (ARM ARM B3.12.7 "Prioritization of aborts"). | |
380 | */ | |
381 | ||
382 | if (reg) { | |
383 | regval = *reg; | |
384 | } else { | |
385 | BUG_ON(mode != (ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED)); | |
386 | regval = 0; | |
387 | } | |
388 | ||
389 | if (mmio->is_write) { | |
390 | u32 data = mmio_data_read(mmio, mask) << word_offset; | |
391 | switch (ACCESS_WRITE_MASK(mode)) { | |
392 | case ACCESS_WRITE_IGNORED: | |
393 | return; | |
394 | ||
395 | case ACCESS_WRITE_SETBIT: | |
396 | regval |= data; | |
397 | break; | |
398 | ||
399 | case ACCESS_WRITE_CLEARBIT: | |
400 | regval &= ~data; | |
401 | break; | |
402 | ||
403 | case ACCESS_WRITE_VALUE: | |
404 | regval = (regval & ~(mask << word_offset)) | data; | |
405 | break; | |
406 | } | |
407 | *reg = regval; | |
408 | } else { | |
409 | switch (ACCESS_READ_MASK(mode)) { | |
410 | case ACCESS_READ_RAZ: | |
411 | regval = 0; | |
412 | /* fall through */ | |
413 | ||
414 | case ACCESS_READ_VALUE: | |
415 | mmio_data_write(mmio, mask, regval >> word_offset); | |
416 | } | |
417 | } | |
418 | } | |
419 | ||
83215812 AP |
420 | bool handle_mmio_raz_wi(struct kvm_vcpu *vcpu, struct kvm_exit_mmio *mmio, |
421 | phys_addr_t offset) | |
b47ef92a MZ |
422 | { |
423 | vgic_reg_access(mmio, NULL, offset, | |
424 | ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED); | |
425 | return false; | |
426 | } | |
427 | ||
83215812 AP |
428 | bool vgic_handle_enable_reg(struct kvm *kvm, struct kvm_exit_mmio *mmio, |
429 | phys_addr_t offset, int vcpu_id, int access) | |
b47ef92a | 430 | { |
d97f683d AP |
431 | u32 *reg; |
432 | int mode = ACCESS_READ_VALUE | access; | |
433 | struct kvm_vcpu *target_vcpu = kvm_get_vcpu(kvm, vcpu_id); | |
434 | ||
435 | reg = vgic_bitmap_get_reg(&kvm->arch.vgic.irq_enabled, vcpu_id, offset); | |
436 | vgic_reg_access(mmio, reg, offset, mode); | |
b47ef92a | 437 | if (mmio->is_write) { |
d97f683d AP |
438 | if (access & ACCESS_WRITE_CLEARBIT) { |
439 | if (offset < 4) /* Force SGI enabled */ | |
440 | *reg |= 0xffff; | |
441 | vgic_retire_disabled_irqs(target_vcpu); | |
442 | } | |
443 | vgic_update_state(kvm); | |
b47ef92a MZ |
444 | return true; |
445 | } | |
446 | ||
447 | return false; | |
448 | } | |
449 | ||
83215812 AP |
450 | bool vgic_handle_set_pending_reg(struct kvm *kvm, |
451 | struct kvm_exit_mmio *mmio, | |
452 | phys_addr_t offset, int vcpu_id) | |
b47ef92a | 453 | { |
9da48b55 | 454 | u32 *reg, orig; |
faa1b46c | 455 | u32 level_mask; |
d97f683d AP |
456 | int mode = ACCESS_READ_VALUE | ACCESS_WRITE_SETBIT; |
457 | struct vgic_dist *dist = &kvm->arch.vgic; | |
faa1b46c | 458 | |
d97f683d | 459 | reg = vgic_bitmap_get_reg(&dist->irq_cfg, vcpu_id, offset); |
faa1b46c CD |
460 | level_mask = (~(*reg)); |
461 | ||
462 | /* Mark both level and edge triggered irqs as pending */ | |
d97f683d | 463 | reg = vgic_bitmap_get_reg(&dist->irq_pending, vcpu_id, offset); |
9da48b55 | 464 | orig = *reg; |
d97f683d | 465 | vgic_reg_access(mmio, reg, offset, mode); |
faa1b46c | 466 | |
b47ef92a | 467 | if (mmio->is_write) { |
faa1b46c CD |
468 | /* Set the soft-pending flag only for level-triggered irqs */ |
469 | reg = vgic_bitmap_get_reg(&dist->irq_soft_pend, | |
d97f683d AP |
470 | vcpu_id, offset); |
471 | vgic_reg_access(mmio, reg, offset, mode); | |
faa1b46c CD |
472 | *reg &= level_mask; |
473 | ||
9da48b55 CD |
474 | /* Ignore writes to SGIs */ |
475 | if (offset < 2) { | |
476 | *reg &= ~0xffff; | |
477 | *reg |= orig & 0xffff; | |
478 | } | |
479 | ||
d97f683d | 480 | vgic_update_state(kvm); |
b47ef92a MZ |
481 | return true; |
482 | } | |
483 | ||
484 | return false; | |
485 | } | |
486 | ||
83215812 AP |
487 | bool vgic_handle_clear_pending_reg(struct kvm *kvm, |
488 | struct kvm_exit_mmio *mmio, | |
489 | phys_addr_t offset, int vcpu_id) | |
b47ef92a | 490 | { |
faa1b46c | 491 | u32 *level_active; |
9da48b55 | 492 | u32 *reg, orig; |
d97f683d AP |
493 | int mode = ACCESS_READ_VALUE | ACCESS_WRITE_CLEARBIT; |
494 | struct vgic_dist *dist = &kvm->arch.vgic; | |
faa1b46c | 495 | |
d97f683d | 496 | reg = vgic_bitmap_get_reg(&dist->irq_pending, vcpu_id, offset); |
9da48b55 | 497 | orig = *reg; |
d97f683d | 498 | vgic_reg_access(mmio, reg, offset, mode); |
b47ef92a | 499 | if (mmio->is_write) { |
faa1b46c CD |
500 | /* Re-set level triggered level-active interrupts */ |
501 | level_active = vgic_bitmap_get_reg(&dist->irq_level, | |
d97f683d AP |
502 | vcpu_id, offset); |
503 | reg = vgic_bitmap_get_reg(&dist->irq_pending, vcpu_id, offset); | |
faa1b46c CD |
504 | *reg |= *level_active; |
505 | ||
9da48b55 CD |
506 | /* Ignore writes to SGIs */ |
507 | if (offset < 2) { | |
508 | *reg &= ~0xffff; | |
509 | *reg |= orig & 0xffff; | |
510 | } | |
511 | ||
faa1b46c CD |
512 | /* Clear soft-pending flags */ |
513 | reg = vgic_bitmap_get_reg(&dist->irq_soft_pend, | |
d97f683d AP |
514 | vcpu_id, offset); |
515 | vgic_reg_access(mmio, reg, offset, mode); | |
faa1b46c | 516 | |
d97f683d | 517 | vgic_update_state(kvm); |
b47ef92a MZ |
518 | return true; |
519 | } | |
b47ef92a MZ |
520 | return false; |
521 | } | |
522 | ||
b47ef92a MZ |
523 | static u32 vgic_cfg_expand(u16 val) |
524 | { | |
525 | u32 res = 0; | |
526 | int i; | |
527 | ||
528 | /* | |
529 | * Turn a 16bit value like abcd...mnop into a 32bit word | |
530 | * a0b0c0d0...m0n0o0p0, which is what the HW cfg register is. | |
531 | */ | |
532 | for (i = 0; i < 16; i++) | |
533 | res |= ((val >> i) & VGIC_CFG_EDGE) << (2 * i + 1); | |
534 | ||
535 | return res; | |
536 | } | |
537 | ||
538 | static u16 vgic_cfg_compress(u32 val) | |
539 | { | |
540 | u16 res = 0; | |
541 | int i; | |
542 | ||
543 | /* | |
544 | * Turn a 32bit word a0b0c0d0...m0n0o0p0 into 16bit value like | |
545 | * abcd...mnop which is what we really care about. | |
546 | */ | |
547 | for (i = 0; i < 16; i++) | |
548 | res |= ((val >> (i * 2 + 1)) & VGIC_CFG_EDGE) << i; | |
549 | ||
550 | return res; | |
551 | } | |
552 | ||
553 | /* | |
554 | * The distributor uses 2 bits per IRQ for the CFG register, but the | |
555 | * LSB is always 0. As such, we only keep the upper bit, and use the | |
556 | * two above functions to compress/expand the bits | |
557 | */ | |
83215812 AP |
558 | bool vgic_handle_cfg_reg(u32 *reg, struct kvm_exit_mmio *mmio, |
559 | phys_addr_t offset) | |
b47ef92a MZ |
560 | { |
561 | u32 val; | |
6545eae3 | 562 | |
f2ae85b2 | 563 | if (offset & 4) |
b47ef92a MZ |
564 | val = *reg >> 16; |
565 | else | |
566 | val = *reg & 0xffff; | |
567 | ||
568 | val = vgic_cfg_expand(val); | |
569 | vgic_reg_access(mmio, &val, offset, | |
570 | ACCESS_READ_VALUE | ACCESS_WRITE_VALUE); | |
571 | if (mmio->is_write) { | |
f2ae85b2 | 572 | if (offset < 8) { |
b47ef92a MZ |
573 | *reg = ~0U; /* Force PPIs/SGIs to 1 */ |
574 | return false; | |
575 | } | |
576 | ||
577 | val = vgic_cfg_compress(val); | |
f2ae85b2 | 578 | if (offset & 4) { |
b47ef92a MZ |
579 | *reg &= 0xffff; |
580 | *reg |= val << 16; | |
581 | } else { | |
582 | *reg &= 0xffff << 16; | |
583 | *reg |= val; | |
584 | } | |
585 | } | |
586 | ||
587 | return false; | |
588 | } | |
589 | ||
cbd333a4 CD |
590 | /** |
591 | * vgic_unqueue_irqs - move pending IRQs from LRs to the distributor | |
592 | * @vgic_cpu: Pointer to the vgic_cpu struct holding the LRs | |
593 | * | |
594 | * Move any pending IRQs that have already been assigned to LRs back to the | |
595 | * emulated distributor state so that the complete emulated state can be read | |
596 | * from the main emulation structures without investigating the LRs. | |
597 | * | |
598 | * Note that IRQs in the active state in the LRs get their pending state moved | |
599 | * to the distributor but the active state stays in the LRs, because we don't | |
600 | * track the active state on the distributor side. | |
601 | */ | |
83215812 | 602 | void vgic_unqueue_irqs(struct kvm_vcpu *vcpu) |
cbd333a4 | 603 | { |
cbd333a4 | 604 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; |
8d5c6b06 | 605 | int i; |
cbd333a4 CD |
606 | |
607 | for_each_set_bit(i, vgic_cpu->lr_used, vgic_cpu->nr_lr) { | |
8d5c6b06 | 608 | struct vgic_lr lr = vgic_get_lr(vcpu, i); |
cbd333a4 CD |
609 | |
610 | /* | |
611 | * There are three options for the state bits: | |
612 | * | |
613 | * 01: pending | |
614 | * 10: active | |
615 | * 11: pending and active | |
616 | * | |
617 | * If the LR holds only an active interrupt (not pending) then | |
618 | * just leave it alone. | |
619 | */ | |
8d5c6b06 | 620 | if ((lr.state & LR_STATE_MASK) == LR_STATE_ACTIVE) |
cbd333a4 CD |
621 | continue; |
622 | ||
623 | /* | |
624 | * Reestablish the pending state on the distributor and the | |
625 | * CPU interface. It may have already been pending, but that | |
626 | * is fine, then we are only setting a few bits that were | |
627 | * already set. | |
628 | */ | |
227844f5 | 629 | vgic_dist_irq_set_pending(vcpu, lr.irq); |
8d5c6b06 | 630 | if (lr.irq < VGIC_NR_SGIS) |
b26e5fda | 631 | add_sgi_source(vcpu, lr.irq, lr.source); |
8d5c6b06 MZ |
632 | lr.state &= ~LR_STATE_PENDING; |
633 | vgic_set_lr(vcpu, i, lr); | |
cbd333a4 CD |
634 | |
635 | /* | |
636 | * If there's no state left on the LR (it could still be | |
637 | * active), then the LR does not hold any useful info and can | |
638 | * be marked as free for other use. | |
639 | */ | |
cced50c9 | 640 | if (!(lr.state & LR_STATE_MASK)) { |
8d5c6b06 | 641 | vgic_retire_lr(i, lr.irq, vcpu); |
cced50c9 CD |
642 | vgic_irq_clear_queued(vcpu, lr.irq); |
643 | } | |
cbd333a4 CD |
644 | |
645 | /* Finally update the VGIC state. */ | |
646 | vgic_update_state(vcpu->kvm); | |
647 | } | |
648 | } | |
649 | ||
83215812 AP |
650 | const |
651 | struct kvm_mmio_range *vgic_find_range(const struct kvm_mmio_range *ranges, | |
1a89dd91 | 652 | struct kvm_exit_mmio *mmio, |
1006e8cb | 653 | phys_addr_t offset) |
1a89dd91 | 654 | { |
83215812 | 655 | const struct kvm_mmio_range *r = ranges; |
1a89dd91 MZ |
656 | |
657 | while (r->len) { | |
1006e8cb CD |
658 | if (offset >= r->base && |
659 | (offset + mmio->len) <= (r->base + r->len)) | |
1a89dd91 MZ |
660 | return r; |
661 | r++; | |
662 | } | |
663 | ||
664 | return NULL; | |
665 | } | |
666 | ||
c3c91836 | 667 | static bool vgic_validate_access(const struct vgic_dist *dist, |
83215812 | 668 | const struct kvm_mmio_range *range, |
c3c91836 MZ |
669 | unsigned long offset) |
670 | { | |
671 | int irq; | |
672 | ||
673 | if (!range->bits_per_irq) | |
674 | return true; /* Not an irq-based access */ | |
675 | ||
676 | irq = offset * 8 / range->bits_per_irq; | |
677 | if (irq >= dist->nr_irqs) | |
678 | return false; | |
679 | ||
680 | return true; | |
681 | } | |
682 | ||
05bc8aaf AP |
683 | /* |
684 | * Call the respective handler function for the given range. | |
685 | * We split up any 64 bit accesses into two consecutive 32 bit | |
686 | * handler calls and merge the result afterwards. | |
687 | * We do this in a little endian fashion regardless of the host's | |
688 | * or guest's endianness, because the GIC is always LE and the rest of | |
689 | * the code (vgic_reg_access) also puts it in a LE fashion already. | |
690 | * At this point we have already identified the handle function, so | |
691 | * range points to that one entry and offset is relative to this. | |
692 | */ | |
693 | static bool call_range_handler(struct kvm_vcpu *vcpu, | |
694 | struct kvm_exit_mmio *mmio, | |
695 | unsigned long offset, | |
83215812 | 696 | const struct kvm_mmio_range *range) |
05bc8aaf AP |
697 | { |
698 | u32 *data32 = (void *)mmio->data; | |
699 | struct kvm_exit_mmio mmio32; | |
700 | bool ret; | |
701 | ||
702 | if (likely(mmio->len <= 4)) | |
703 | return range->handle_mmio(vcpu, mmio, offset); | |
704 | ||
705 | /* | |
706 | * Any access bigger than 4 bytes (that we currently handle in KVM) | |
707 | * is actually 8 bytes long, caused by a 64-bit access | |
708 | */ | |
709 | ||
710 | mmio32.len = 4; | |
711 | mmio32.is_write = mmio->is_write; | |
9fedf146 | 712 | mmio32.private = mmio->private; |
05bc8aaf AP |
713 | |
714 | mmio32.phys_addr = mmio->phys_addr + 4; | |
715 | if (mmio->is_write) | |
716 | *(u32 *)mmio32.data = data32[1]; | |
717 | ret = range->handle_mmio(vcpu, &mmio32, offset + 4); | |
718 | if (!mmio->is_write) | |
719 | data32[1] = *(u32 *)mmio32.data; | |
720 | ||
721 | mmio32.phys_addr = mmio->phys_addr; | |
722 | if (mmio->is_write) | |
723 | *(u32 *)mmio32.data = data32[0]; | |
724 | ret |= range->handle_mmio(vcpu, &mmio32, offset); | |
725 | if (!mmio->is_write) | |
726 | data32[0] = *(u32 *)mmio32.data; | |
727 | ||
728 | return ret; | |
729 | } | |
730 | ||
1a89dd91 | 731 | /** |
96415257 | 732 | * vgic_handle_mmio_range - handle an in-kernel MMIO access |
1a89dd91 MZ |
733 | * @vcpu: pointer to the vcpu performing the access |
734 | * @run: pointer to the kvm_run structure | |
735 | * @mmio: pointer to the data describing the access | |
96415257 AP |
736 | * @ranges: array of MMIO ranges in a given region |
737 | * @mmio_base: base address of that region | |
1a89dd91 | 738 | * |
96415257 | 739 | * returns true if the MMIO access could be performed |
1a89dd91 | 740 | */ |
83215812 | 741 | bool vgic_handle_mmio_range(struct kvm_vcpu *vcpu, struct kvm_run *run, |
96415257 | 742 | struct kvm_exit_mmio *mmio, |
83215812 | 743 | const struct kvm_mmio_range *ranges, |
96415257 | 744 | unsigned long mmio_base) |
1a89dd91 | 745 | { |
83215812 | 746 | const struct kvm_mmio_range *range; |
b47ef92a | 747 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
b47ef92a MZ |
748 | bool updated_state; |
749 | unsigned long offset; | |
750 | ||
96415257 | 751 | offset = mmio->phys_addr - mmio_base; |
83215812 | 752 | range = vgic_find_range(ranges, mmio, offset); |
b47ef92a MZ |
753 | if (unlikely(!range || !range->handle_mmio)) { |
754 | pr_warn("Unhandled access %d %08llx %d\n", | |
755 | mmio->is_write, mmio->phys_addr, mmio->len); | |
756 | return false; | |
757 | } | |
758 | ||
759 | spin_lock(&vcpu->kvm->arch.vgic.lock); | |
96415257 | 760 | offset -= range->base; |
c3c91836 | 761 | if (vgic_validate_access(dist, range, offset)) { |
05bc8aaf | 762 | updated_state = call_range_handler(vcpu, mmio, offset, range); |
c3c91836 | 763 | } else { |
05bc8aaf AP |
764 | if (!mmio->is_write) |
765 | memset(mmio->data, 0, mmio->len); | |
c3c91836 MZ |
766 | updated_state = false; |
767 | } | |
b47ef92a MZ |
768 | spin_unlock(&vcpu->kvm->arch.vgic.lock); |
769 | kvm_prepare_mmio(run, mmio); | |
770 | kvm_handle_mmio_return(vcpu, run); | |
771 | ||
5863c2ce MZ |
772 | if (updated_state) |
773 | vgic_kick_vcpus(vcpu->kvm); | |
774 | ||
b47ef92a MZ |
775 | return true; |
776 | } | |
777 | ||
96415257 AP |
778 | /** |
779 | * vgic_handle_mmio - handle an in-kernel MMIO access for the GIC emulation | |
780 | * @vcpu: pointer to the vcpu performing the access | |
781 | * @run: pointer to the kvm_run structure | |
782 | * @mmio: pointer to the data describing the access | |
783 | * | |
784 | * returns true if the MMIO access has been performed in kernel space, | |
785 | * and false if it needs to be emulated in user space. | |
b26e5fda | 786 | * Calls the actual handling routine for the selected VGIC model. |
96415257 AP |
787 | */ |
788 | bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run, | |
789 | struct kvm_exit_mmio *mmio) | |
790 | { | |
791 | if (!irqchip_in_kernel(vcpu->kvm)) | |
792 | return false; | |
793 | ||
b26e5fda AP |
794 | /* |
795 | * This will currently call either vgic_v2_handle_mmio() or | |
796 | * vgic_v3_handle_mmio(), which in turn will call | |
797 | * vgic_handle_mmio_range() defined above. | |
798 | */ | |
799 | return vcpu->kvm->arch.vgic.vm_ops.handle_mmio(vcpu, run, mmio); | |
96415257 AP |
800 | } |
801 | ||
fb65ab63 MZ |
802 | static int vgic_nr_shared_irqs(struct vgic_dist *dist) |
803 | { | |
804 | return dist->nr_irqs - VGIC_NR_PRIVATE_IRQS; | |
805 | } | |
806 | ||
b47ef92a MZ |
807 | static int compute_pending_for_cpu(struct kvm_vcpu *vcpu) |
808 | { | |
9d949dce MZ |
809 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
810 | unsigned long *pending, *enabled, *pend_percpu, *pend_shared; | |
811 | unsigned long pending_private, pending_shared; | |
fb65ab63 | 812 | int nr_shared = vgic_nr_shared_irqs(dist); |
9d949dce MZ |
813 | int vcpu_id; |
814 | ||
815 | vcpu_id = vcpu->vcpu_id; | |
816 | pend_percpu = vcpu->arch.vgic_cpu.pending_percpu; | |
817 | pend_shared = vcpu->arch.vgic_cpu.pending_shared; | |
818 | ||
227844f5 | 819 | pending = vgic_bitmap_get_cpu_map(&dist->irq_pending, vcpu_id); |
9d949dce MZ |
820 | enabled = vgic_bitmap_get_cpu_map(&dist->irq_enabled, vcpu_id); |
821 | bitmap_and(pend_percpu, pending, enabled, VGIC_NR_PRIVATE_IRQS); | |
822 | ||
227844f5 | 823 | pending = vgic_bitmap_get_shared_map(&dist->irq_pending); |
9d949dce | 824 | enabled = vgic_bitmap_get_shared_map(&dist->irq_enabled); |
fb65ab63 | 825 | bitmap_and(pend_shared, pending, enabled, nr_shared); |
9d949dce MZ |
826 | bitmap_and(pend_shared, pend_shared, |
827 | vgic_bitmap_get_shared_map(&dist->irq_spi_target[vcpu_id]), | |
fb65ab63 | 828 | nr_shared); |
9d949dce MZ |
829 | |
830 | pending_private = find_first_bit(pend_percpu, VGIC_NR_PRIVATE_IRQS); | |
fb65ab63 | 831 | pending_shared = find_first_bit(pend_shared, nr_shared); |
9d949dce | 832 | return (pending_private < VGIC_NR_PRIVATE_IRQS || |
fb65ab63 | 833 | pending_shared < vgic_nr_shared_irqs(dist)); |
b47ef92a MZ |
834 | } |
835 | ||
836 | /* | |
837 | * Update the interrupt state and determine which CPUs have pending | |
838 | * interrupts. Must be called with distributor lock held. | |
839 | */ | |
83215812 | 840 | void vgic_update_state(struct kvm *kvm) |
b47ef92a MZ |
841 | { |
842 | struct vgic_dist *dist = &kvm->arch.vgic; | |
843 | struct kvm_vcpu *vcpu; | |
844 | int c; | |
845 | ||
846 | if (!dist->enabled) { | |
c1bfb577 | 847 | set_bit(0, dist->irq_pending_on_cpu); |
b47ef92a MZ |
848 | return; |
849 | } | |
850 | ||
851 | kvm_for_each_vcpu(c, vcpu, kvm) { | |
852 | if (compute_pending_for_cpu(vcpu)) { | |
853 | pr_debug("CPU%d has pending interrupts\n", c); | |
c1bfb577 | 854 | set_bit(c, dist->irq_pending_on_cpu); |
b47ef92a MZ |
855 | } |
856 | } | |
1a89dd91 | 857 | } |
330690cd | 858 | |
8d5c6b06 MZ |
859 | static struct vgic_lr vgic_get_lr(const struct kvm_vcpu *vcpu, int lr) |
860 | { | |
8f186d52 | 861 | return vgic_ops->get_lr(vcpu, lr); |
8d5c6b06 MZ |
862 | } |
863 | ||
864 | static void vgic_set_lr(struct kvm_vcpu *vcpu, int lr, | |
865 | struct vgic_lr vlr) | |
866 | { | |
8f186d52 | 867 | vgic_ops->set_lr(vcpu, lr, vlr); |
8d5c6b06 MZ |
868 | } |
869 | ||
69bb2c9f MZ |
870 | static void vgic_sync_lr_elrsr(struct kvm_vcpu *vcpu, int lr, |
871 | struct vgic_lr vlr) | |
872 | { | |
8f186d52 | 873 | vgic_ops->sync_lr_elrsr(vcpu, lr, vlr); |
69bb2c9f MZ |
874 | } |
875 | ||
876 | static inline u64 vgic_get_elrsr(struct kvm_vcpu *vcpu) | |
877 | { | |
8f186d52 | 878 | return vgic_ops->get_elrsr(vcpu); |
69bb2c9f MZ |
879 | } |
880 | ||
8d6a0313 MZ |
881 | static inline u64 vgic_get_eisr(struct kvm_vcpu *vcpu) |
882 | { | |
8f186d52 | 883 | return vgic_ops->get_eisr(vcpu); |
8d6a0313 MZ |
884 | } |
885 | ||
495dd859 MZ |
886 | static inline u32 vgic_get_interrupt_status(struct kvm_vcpu *vcpu) |
887 | { | |
8f186d52 | 888 | return vgic_ops->get_interrupt_status(vcpu); |
495dd859 MZ |
889 | } |
890 | ||
909d9b50 MZ |
891 | static inline void vgic_enable_underflow(struct kvm_vcpu *vcpu) |
892 | { | |
8f186d52 | 893 | vgic_ops->enable_underflow(vcpu); |
909d9b50 MZ |
894 | } |
895 | ||
896 | static inline void vgic_disable_underflow(struct kvm_vcpu *vcpu) | |
897 | { | |
8f186d52 | 898 | vgic_ops->disable_underflow(vcpu); |
909d9b50 MZ |
899 | } |
900 | ||
83215812 | 901 | void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr) |
beee38b9 | 902 | { |
8f186d52 | 903 | vgic_ops->get_vmcr(vcpu, vmcr); |
beee38b9 MZ |
904 | } |
905 | ||
83215812 | 906 | void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr) |
beee38b9 | 907 | { |
8f186d52 | 908 | vgic_ops->set_vmcr(vcpu, vmcr); |
beee38b9 MZ |
909 | } |
910 | ||
da8dafd1 MZ |
911 | static inline void vgic_enable(struct kvm_vcpu *vcpu) |
912 | { | |
8f186d52 | 913 | vgic_ops->enable(vcpu); |
da8dafd1 MZ |
914 | } |
915 | ||
8d5c6b06 MZ |
916 | static void vgic_retire_lr(int lr_nr, int irq, struct kvm_vcpu *vcpu) |
917 | { | |
918 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
919 | struct vgic_lr vlr = vgic_get_lr(vcpu, lr_nr); | |
920 | ||
921 | vlr.state = 0; | |
922 | vgic_set_lr(vcpu, lr_nr, vlr); | |
923 | clear_bit(lr_nr, vgic_cpu->lr_used); | |
924 | vgic_cpu->vgic_irq_lr_map[irq] = LR_EMPTY; | |
925 | } | |
a1fcb44e MZ |
926 | |
927 | /* | |
928 | * An interrupt may have been disabled after being made pending on the | |
929 | * CPU interface (the classic case is a timer running while we're | |
930 | * rebooting the guest - the interrupt would kick as soon as the CPU | |
931 | * interface gets enabled, with deadly consequences). | |
932 | * | |
933 | * The solution is to examine already active LRs, and check the | |
934 | * interrupt is still enabled. If not, just retire it. | |
935 | */ | |
936 | static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu) | |
937 | { | |
938 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
939 | int lr; | |
940 | ||
8f186d52 | 941 | for_each_set_bit(lr, vgic_cpu->lr_used, vgic->nr_lr) { |
8d5c6b06 | 942 | struct vgic_lr vlr = vgic_get_lr(vcpu, lr); |
a1fcb44e | 943 | |
8d5c6b06 MZ |
944 | if (!vgic_irq_is_enabled(vcpu, vlr.irq)) { |
945 | vgic_retire_lr(lr, vlr.irq, vcpu); | |
dbf20f9d CD |
946 | if (vgic_irq_is_queued(vcpu, vlr.irq)) |
947 | vgic_irq_clear_queued(vcpu, vlr.irq); | |
a1fcb44e MZ |
948 | } |
949 | } | |
950 | } | |
951 | ||
9d949dce MZ |
952 | /* |
953 | * Queue an interrupt to a CPU virtual interface. Return true on success, | |
954 | * or false if it wasn't possible to queue it. | |
1d916229 | 955 | * sgi_source must be zero for any non-SGI interrupts. |
9d949dce | 956 | */ |
83215812 | 957 | bool vgic_queue_irq(struct kvm_vcpu *vcpu, u8 sgi_source_id, int irq) |
9d949dce MZ |
958 | { |
959 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
5fb66da6 | 960 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
8d5c6b06 | 961 | struct vgic_lr vlr; |
9d949dce MZ |
962 | int lr; |
963 | ||
964 | /* Sanitize the input... */ | |
965 | BUG_ON(sgi_source_id & ~7); | |
966 | BUG_ON(sgi_source_id && irq >= VGIC_NR_SGIS); | |
5fb66da6 | 967 | BUG_ON(irq >= dist->nr_irqs); |
9d949dce MZ |
968 | |
969 | kvm_debug("Queue IRQ%d\n", irq); | |
970 | ||
971 | lr = vgic_cpu->vgic_irq_lr_map[irq]; | |
972 | ||
973 | /* Do we have an active interrupt for the same CPUID? */ | |
8d5c6b06 MZ |
974 | if (lr != LR_EMPTY) { |
975 | vlr = vgic_get_lr(vcpu, lr); | |
976 | if (vlr.source == sgi_source_id) { | |
977 | kvm_debug("LR%d piggyback for IRQ%d\n", lr, vlr.irq); | |
978 | BUG_ON(!test_bit(lr, vgic_cpu->lr_used)); | |
979 | vlr.state |= LR_STATE_PENDING; | |
980 | vgic_set_lr(vcpu, lr, vlr); | |
981 | return true; | |
982 | } | |
9d949dce MZ |
983 | } |
984 | ||
985 | /* Try to use another LR for this interrupt */ | |
986 | lr = find_first_zero_bit((unsigned long *)vgic_cpu->lr_used, | |
8f186d52 MZ |
987 | vgic->nr_lr); |
988 | if (lr >= vgic->nr_lr) | |
9d949dce MZ |
989 | return false; |
990 | ||
991 | kvm_debug("LR%d allocated for IRQ%d %x\n", lr, irq, sgi_source_id); | |
9d949dce MZ |
992 | vgic_cpu->vgic_irq_lr_map[irq] = lr; |
993 | set_bit(lr, vgic_cpu->lr_used); | |
994 | ||
8d5c6b06 MZ |
995 | vlr.irq = irq; |
996 | vlr.source = sgi_source_id; | |
997 | vlr.state = LR_STATE_PENDING; | |
9d949dce | 998 | if (!vgic_irq_is_edge(vcpu, irq)) |
8d5c6b06 MZ |
999 | vlr.state |= LR_EOI_INT; |
1000 | ||
1001 | vgic_set_lr(vcpu, lr, vlr); | |
9d949dce MZ |
1002 | |
1003 | return true; | |
1004 | } | |
1005 | ||
9d949dce MZ |
1006 | static bool vgic_queue_hwirq(struct kvm_vcpu *vcpu, int irq) |
1007 | { | |
dbf20f9d | 1008 | if (!vgic_can_sample_irq(vcpu, irq)) |
9d949dce MZ |
1009 | return true; /* level interrupt, already queued */ |
1010 | ||
1011 | if (vgic_queue_irq(vcpu, 0, irq)) { | |
1012 | if (vgic_irq_is_edge(vcpu, irq)) { | |
227844f5 | 1013 | vgic_dist_irq_clear_pending(vcpu, irq); |
9d949dce MZ |
1014 | vgic_cpu_irq_clear(vcpu, irq); |
1015 | } else { | |
dbf20f9d | 1016 | vgic_irq_set_queued(vcpu, irq); |
9d949dce MZ |
1017 | } |
1018 | ||
1019 | return true; | |
1020 | } | |
1021 | ||
1022 | return false; | |
1023 | } | |
1024 | ||
1025 | /* | |
1026 | * Fill the list registers with pending interrupts before running the | |
1027 | * guest. | |
1028 | */ | |
1029 | static void __kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) | |
1030 | { | |
1031 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
1032 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
1033 | int i, vcpu_id; | |
1034 | int overflow = 0; | |
1035 | ||
1036 | vcpu_id = vcpu->vcpu_id; | |
1037 | ||
1038 | /* | |
1039 | * We may not have any pending interrupt, or the interrupts | |
1040 | * may have been serviced from another vcpu. In all cases, | |
1041 | * move along. | |
1042 | */ | |
1043 | if (!kvm_vgic_vcpu_pending_irq(vcpu)) { | |
1044 | pr_debug("CPU%d has no pending interrupt\n", vcpu_id); | |
1045 | goto epilog; | |
1046 | } | |
1047 | ||
1048 | /* SGIs */ | |
1049 | for_each_set_bit(i, vgic_cpu->pending_percpu, VGIC_NR_SGIS) { | |
b26e5fda | 1050 | if (!queue_sgi(vcpu, i)) |
9d949dce MZ |
1051 | overflow = 1; |
1052 | } | |
1053 | ||
1054 | /* PPIs */ | |
1055 | for_each_set_bit_from(i, vgic_cpu->pending_percpu, VGIC_NR_PRIVATE_IRQS) { | |
1056 | if (!vgic_queue_hwirq(vcpu, i)) | |
1057 | overflow = 1; | |
1058 | } | |
1059 | ||
1060 | /* SPIs */ | |
fb65ab63 | 1061 | for_each_set_bit(i, vgic_cpu->pending_shared, vgic_nr_shared_irqs(dist)) { |
9d949dce MZ |
1062 | if (!vgic_queue_hwirq(vcpu, i + VGIC_NR_PRIVATE_IRQS)) |
1063 | overflow = 1; | |
1064 | } | |
1065 | ||
1066 | epilog: | |
1067 | if (overflow) { | |
909d9b50 | 1068 | vgic_enable_underflow(vcpu); |
9d949dce | 1069 | } else { |
909d9b50 | 1070 | vgic_disable_underflow(vcpu); |
9d949dce MZ |
1071 | /* |
1072 | * We're about to run this VCPU, and we've consumed | |
1073 | * everything the distributor had in store for | |
1074 | * us. Claim we don't have anything pending. We'll | |
1075 | * adjust that if needed while exiting. | |
1076 | */ | |
c1bfb577 | 1077 | clear_bit(vcpu_id, dist->irq_pending_on_cpu); |
9d949dce MZ |
1078 | } |
1079 | } | |
1080 | ||
1081 | static bool vgic_process_maintenance(struct kvm_vcpu *vcpu) | |
1082 | { | |
495dd859 | 1083 | u32 status = vgic_get_interrupt_status(vcpu); |
9d949dce MZ |
1084 | bool level_pending = false; |
1085 | ||
495dd859 | 1086 | kvm_debug("STATUS = %08x\n", status); |
9d949dce | 1087 | |
495dd859 | 1088 | if (status & INT_STATUS_EOI) { |
9d949dce MZ |
1089 | /* |
1090 | * Some level interrupts have been EOIed. Clear their | |
1091 | * active bit. | |
1092 | */ | |
8d6a0313 | 1093 | u64 eisr = vgic_get_eisr(vcpu); |
2df36a5d | 1094 | unsigned long *eisr_ptr = u64_to_bitmask(&eisr); |
8d5c6b06 | 1095 | int lr; |
9d949dce | 1096 | |
8f186d52 | 1097 | for_each_set_bit(lr, eisr_ptr, vgic->nr_lr) { |
8d5c6b06 | 1098 | struct vgic_lr vlr = vgic_get_lr(vcpu, lr); |
faa1b46c | 1099 | WARN_ON(vgic_irq_is_edge(vcpu, vlr.irq)); |
9d949dce | 1100 | |
dbf20f9d | 1101 | vgic_irq_clear_queued(vcpu, vlr.irq); |
8d5c6b06 MZ |
1102 | WARN_ON(vlr.state & LR_STATE_MASK); |
1103 | vlr.state = 0; | |
1104 | vgic_set_lr(vcpu, lr, vlr); | |
9d949dce | 1105 | |
faa1b46c CD |
1106 | /* |
1107 | * If the IRQ was EOIed it was also ACKed and we we | |
1108 | * therefore assume we can clear the soft pending | |
1109 | * state (should it had been set) for this interrupt. | |
1110 | * | |
1111 | * Note: if the IRQ soft pending state was set after | |
1112 | * the IRQ was acked, it actually shouldn't be | |
1113 | * cleared, but we have no way of knowing that unless | |
1114 | * we start trapping ACKs when the soft-pending state | |
1115 | * is set. | |
1116 | */ | |
1117 | vgic_dist_irq_clear_soft_pend(vcpu, vlr.irq); | |
1118 | ||
9d949dce | 1119 | /* Any additional pending interrupt? */ |
faa1b46c | 1120 | if (vgic_dist_irq_get_level(vcpu, vlr.irq)) { |
8d5c6b06 | 1121 | vgic_cpu_irq_set(vcpu, vlr.irq); |
9d949dce MZ |
1122 | level_pending = true; |
1123 | } else { | |
faa1b46c | 1124 | vgic_dist_irq_clear_pending(vcpu, vlr.irq); |
8d5c6b06 | 1125 | vgic_cpu_irq_clear(vcpu, vlr.irq); |
9d949dce | 1126 | } |
75da01e1 MZ |
1127 | |
1128 | /* | |
1129 | * Despite being EOIed, the LR may not have | |
1130 | * been marked as empty. | |
1131 | */ | |
69bb2c9f | 1132 | vgic_sync_lr_elrsr(vcpu, lr, vlr); |
9d949dce MZ |
1133 | } |
1134 | } | |
1135 | ||
495dd859 | 1136 | if (status & INT_STATUS_UNDERFLOW) |
909d9b50 | 1137 | vgic_disable_underflow(vcpu); |
9d949dce MZ |
1138 | |
1139 | return level_pending; | |
1140 | } | |
1141 | ||
1142 | /* | |
33c83cb3 MZ |
1143 | * Sync back the VGIC state after a guest run. The distributor lock is |
1144 | * needed so we don't get preempted in the middle of the state processing. | |
9d949dce MZ |
1145 | */ |
1146 | static void __kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) | |
1147 | { | |
1148 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
1149 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
69bb2c9f MZ |
1150 | u64 elrsr; |
1151 | unsigned long *elrsr_ptr; | |
9d949dce MZ |
1152 | int lr, pending; |
1153 | bool level_pending; | |
1154 | ||
1155 | level_pending = vgic_process_maintenance(vcpu); | |
69bb2c9f | 1156 | elrsr = vgic_get_elrsr(vcpu); |
2df36a5d | 1157 | elrsr_ptr = u64_to_bitmask(&elrsr); |
9d949dce MZ |
1158 | |
1159 | /* Clear mappings for empty LRs */ | |
8f186d52 | 1160 | for_each_set_bit(lr, elrsr_ptr, vgic->nr_lr) { |
8d5c6b06 | 1161 | struct vgic_lr vlr; |
9d949dce MZ |
1162 | |
1163 | if (!test_and_clear_bit(lr, vgic_cpu->lr_used)) | |
1164 | continue; | |
1165 | ||
8d5c6b06 | 1166 | vlr = vgic_get_lr(vcpu, lr); |
9d949dce | 1167 | |
5fb66da6 | 1168 | BUG_ON(vlr.irq >= dist->nr_irqs); |
8d5c6b06 | 1169 | vgic_cpu->vgic_irq_lr_map[vlr.irq] = LR_EMPTY; |
9d949dce MZ |
1170 | } |
1171 | ||
1172 | /* Check if we still have something up our sleeve... */ | |
8f186d52 MZ |
1173 | pending = find_first_zero_bit(elrsr_ptr, vgic->nr_lr); |
1174 | if (level_pending || pending < vgic->nr_lr) | |
c1bfb577 | 1175 | set_bit(vcpu->vcpu_id, dist->irq_pending_on_cpu); |
9d949dce MZ |
1176 | } |
1177 | ||
1178 | void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) | |
1179 | { | |
1180 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
1181 | ||
1182 | if (!irqchip_in_kernel(vcpu->kvm)) | |
1183 | return; | |
1184 | ||
1185 | spin_lock(&dist->lock); | |
1186 | __kvm_vgic_flush_hwstate(vcpu); | |
1187 | spin_unlock(&dist->lock); | |
1188 | } | |
1189 | ||
1190 | void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) | |
1191 | { | |
33c83cb3 MZ |
1192 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
1193 | ||
9d949dce MZ |
1194 | if (!irqchip_in_kernel(vcpu->kvm)) |
1195 | return; | |
1196 | ||
33c83cb3 | 1197 | spin_lock(&dist->lock); |
9d949dce | 1198 | __kvm_vgic_sync_hwstate(vcpu); |
33c83cb3 | 1199 | spin_unlock(&dist->lock); |
9d949dce MZ |
1200 | } |
1201 | ||
1202 | int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu) | |
1203 | { | |
1204 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
1205 | ||
1206 | if (!irqchip_in_kernel(vcpu->kvm)) | |
1207 | return 0; | |
1208 | ||
c1bfb577 | 1209 | return test_bit(vcpu->vcpu_id, dist->irq_pending_on_cpu); |
9d949dce MZ |
1210 | } |
1211 | ||
83215812 | 1212 | void vgic_kick_vcpus(struct kvm *kvm) |
5863c2ce MZ |
1213 | { |
1214 | struct kvm_vcpu *vcpu; | |
1215 | int c; | |
1216 | ||
1217 | /* | |
1218 | * We've injected an interrupt, time to find out who deserves | |
1219 | * a good kick... | |
1220 | */ | |
1221 | kvm_for_each_vcpu(c, vcpu, kvm) { | |
1222 | if (kvm_vgic_vcpu_pending_irq(vcpu)) | |
1223 | kvm_vcpu_kick(vcpu); | |
1224 | } | |
1225 | } | |
1226 | ||
1227 | static int vgic_validate_injection(struct kvm_vcpu *vcpu, int irq, int level) | |
1228 | { | |
227844f5 | 1229 | int edge_triggered = vgic_irq_is_edge(vcpu, irq); |
5863c2ce MZ |
1230 | |
1231 | /* | |
1232 | * Only inject an interrupt if: | |
1233 | * - edge triggered and we have a rising edge | |
1234 | * - level triggered and we change level | |
1235 | */ | |
faa1b46c CD |
1236 | if (edge_triggered) { |
1237 | int state = vgic_dist_irq_is_pending(vcpu, irq); | |
5863c2ce | 1238 | return level > state; |
faa1b46c CD |
1239 | } else { |
1240 | int state = vgic_dist_irq_get_level(vcpu, irq); | |
5863c2ce | 1241 | return level != state; |
faa1b46c | 1242 | } |
5863c2ce MZ |
1243 | } |
1244 | ||
016ed39c | 1245 | static int vgic_update_irq_pending(struct kvm *kvm, int cpuid, |
5863c2ce MZ |
1246 | unsigned int irq_num, bool level) |
1247 | { | |
1248 | struct vgic_dist *dist = &kvm->arch.vgic; | |
1249 | struct kvm_vcpu *vcpu; | |
227844f5 | 1250 | int edge_triggered, level_triggered; |
5863c2ce | 1251 | int enabled; |
a0675c25 | 1252 | bool ret = true, can_inject = true; |
5863c2ce MZ |
1253 | |
1254 | spin_lock(&dist->lock); | |
1255 | ||
1256 | vcpu = kvm_get_vcpu(kvm, cpuid); | |
227844f5 CD |
1257 | edge_triggered = vgic_irq_is_edge(vcpu, irq_num); |
1258 | level_triggered = !edge_triggered; | |
5863c2ce MZ |
1259 | |
1260 | if (!vgic_validate_injection(vcpu, irq_num, level)) { | |
1261 | ret = false; | |
1262 | goto out; | |
1263 | } | |
1264 | ||
1265 | if (irq_num >= VGIC_NR_PRIVATE_IRQS) { | |
1266 | cpuid = dist->irq_spi_cpu[irq_num - VGIC_NR_PRIVATE_IRQS]; | |
a0675c25 AP |
1267 | if (cpuid == VCPU_NOT_ALLOCATED) { |
1268 | /* Pretend we use CPU0, and prevent injection */ | |
1269 | cpuid = 0; | |
1270 | can_inject = false; | |
1271 | } | |
5863c2ce MZ |
1272 | vcpu = kvm_get_vcpu(kvm, cpuid); |
1273 | } | |
1274 | ||
1275 | kvm_debug("Inject IRQ%d level %d CPU%d\n", irq_num, level, cpuid); | |
1276 | ||
faa1b46c CD |
1277 | if (level) { |
1278 | if (level_triggered) | |
1279 | vgic_dist_irq_set_level(vcpu, irq_num); | |
227844f5 | 1280 | vgic_dist_irq_set_pending(vcpu, irq_num); |
faa1b46c CD |
1281 | } else { |
1282 | if (level_triggered) { | |
1283 | vgic_dist_irq_clear_level(vcpu, irq_num); | |
1284 | if (!vgic_dist_irq_soft_pend(vcpu, irq_num)) | |
1285 | vgic_dist_irq_clear_pending(vcpu, irq_num); | |
faa1b46c | 1286 | } |
7d39f9e3 | 1287 | |
1288 | ret = false; | |
1289 | goto out; | |
faa1b46c | 1290 | } |
5863c2ce MZ |
1291 | |
1292 | enabled = vgic_irq_is_enabled(vcpu, irq_num); | |
1293 | ||
a0675c25 | 1294 | if (!enabled || !can_inject) { |
5863c2ce MZ |
1295 | ret = false; |
1296 | goto out; | |
1297 | } | |
1298 | ||
dbf20f9d | 1299 | if (!vgic_can_sample_irq(vcpu, irq_num)) { |
5863c2ce MZ |
1300 | /* |
1301 | * Level interrupt in progress, will be picked up | |
1302 | * when EOId. | |
1303 | */ | |
1304 | ret = false; | |
1305 | goto out; | |
1306 | } | |
1307 | ||
1308 | if (level) { | |
1309 | vgic_cpu_irq_set(vcpu, irq_num); | |
c1bfb577 | 1310 | set_bit(cpuid, dist->irq_pending_on_cpu); |
5863c2ce MZ |
1311 | } |
1312 | ||
1313 | out: | |
1314 | spin_unlock(&dist->lock); | |
1315 | ||
016ed39c | 1316 | return ret ? cpuid : -EINVAL; |
5863c2ce MZ |
1317 | } |
1318 | ||
1319 | /** | |
1320 | * kvm_vgic_inject_irq - Inject an IRQ from a device to the vgic | |
1321 | * @kvm: The VM structure pointer | |
1322 | * @cpuid: The CPU for PPIs | |
1323 | * @irq_num: The IRQ number that is assigned to the device | |
1324 | * @level: Edge-triggered: true: to trigger the interrupt | |
1325 | * false: to ignore the call | |
1326 | * Level-sensitive true: activates an interrupt | |
1327 | * false: deactivates an interrupt | |
1328 | * | |
1329 | * The GIC is not concerned with devices being active-LOW or active-HIGH for | |
1330 | * level-sensitive interrupts. You can think of the level parameter as 1 | |
1331 | * being HIGH and 0 being LOW and all devices being active-HIGH. | |
1332 | */ | |
1333 | int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num, | |
1334 | bool level) | |
1335 | { | |
ca7d9c82 | 1336 | int ret = 0; |
016ed39c | 1337 | int vcpu_id; |
5863c2ce | 1338 | |
ca7d9c82 | 1339 | if (unlikely(!vgic_initialized(kvm))) { |
59892136 AP |
1340 | /* |
1341 | * We only provide the automatic initialization of the VGIC | |
1342 | * for the legacy case of a GICv2. Any other type must | |
1343 | * be explicitly initialized once setup with the respective | |
1344 | * KVM device call. | |
1345 | */ | |
1346 | if (kvm->arch.vgic.vgic_model != KVM_DEV_TYPE_ARM_VGIC_V2) { | |
1347 | ret = -EBUSY; | |
1348 | goto out; | |
1349 | } | |
ca7d9c82 CD |
1350 | mutex_lock(&kvm->lock); |
1351 | ret = vgic_init(kvm); | |
1352 | mutex_unlock(&kvm->lock); | |
1353 | ||
1354 | if (ret) | |
1355 | goto out; | |
016ed39c | 1356 | } |
5863c2ce | 1357 | |
ca7d9c82 CD |
1358 | vcpu_id = vgic_update_irq_pending(kvm, cpuid, irq_num, level); |
1359 | if (vcpu_id >= 0) { | |
1360 | /* kick the specified vcpu */ | |
1361 | kvm_vcpu_kick(kvm_get_vcpu(kvm, vcpu_id)); | |
1362 | } | |
1363 | ||
1364 | out: | |
1365 | return ret; | |
5863c2ce MZ |
1366 | } |
1367 | ||
01ac5e34 MZ |
1368 | static irqreturn_t vgic_maintenance_handler(int irq, void *data) |
1369 | { | |
1370 | /* | |
1371 | * We cannot rely on the vgic maintenance interrupt to be | |
1372 | * delivered synchronously. This means we can only use it to | |
1373 | * exit the VM, and we perform the handling of EOIed | |
1374 | * interrupts on the exit path (see vgic_process_maintenance). | |
1375 | */ | |
1376 | return IRQ_HANDLED; | |
1377 | } | |
1378 | ||
c1bfb577 MZ |
1379 | void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu) |
1380 | { | |
1381 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
1382 | ||
1383 | kfree(vgic_cpu->pending_shared); | |
1384 | kfree(vgic_cpu->vgic_irq_lr_map); | |
1385 | vgic_cpu->pending_shared = NULL; | |
1386 | vgic_cpu->vgic_irq_lr_map = NULL; | |
1387 | } | |
1388 | ||
1389 | static int vgic_vcpu_init_maps(struct kvm_vcpu *vcpu, int nr_irqs) | |
1390 | { | |
1391 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
1392 | ||
1393 | int sz = (nr_irqs - VGIC_NR_PRIVATE_IRQS) / 8; | |
1394 | vgic_cpu->pending_shared = kzalloc(sz, GFP_KERNEL); | |
6d3cfbe2 | 1395 | vgic_cpu->vgic_irq_lr_map = kmalloc(nr_irqs, GFP_KERNEL); |
c1bfb577 MZ |
1396 | |
1397 | if (!vgic_cpu->pending_shared || !vgic_cpu->vgic_irq_lr_map) { | |
1398 | kvm_vgic_vcpu_destroy(vcpu); | |
1399 | return -ENOMEM; | |
1400 | } | |
1401 | ||
6d3cfbe2 | 1402 | memset(vgic_cpu->vgic_irq_lr_map, LR_EMPTY, nr_irqs); |
01ac5e34 MZ |
1403 | |
1404 | /* | |
ca85f623 MZ |
1405 | * Store the number of LRs per vcpu, so we don't have to go |
1406 | * all the way to the distributor structure to find out. Only | |
1407 | * assembly code should use this one. | |
01ac5e34 | 1408 | */ |
8f186d52 | 1409 | vgic_cpu->nr_lr = vgic->nr_lr; |
01ac5e34 | 1410 | |
6d3cfbe2 | 1411 | return 0; |
01ac5e34 MZ |
1412 | } |
1413 | ||
3caa2d8c AP |
1414 | /** |
1415 | * kvm_vgic_get_max_vcpus - Get the maximum number of VCPUs allowed by HW | |
1416 | * | |
1417 | * The host's GIC naturally limits the maximum amount of VCPUs a guest | |
1418 | * can use. | |
1419 | */ | |
1420 | int kvm_vgic_get_max_vcpus(void) | |
1421 | { | |
1422 | return vgic->max_gic_vcpus; | |
1423 | } | |
1424 | ||
c1bfb577 MZ |
1425 | void kvm_vgic_destroy(struct kvm *kvm) |
1426 | { | |
1427 | struct vgic_dist *dist = &kvm->arch.vgic; | |
1428 | struct kvm_vcpu *vcpu; | |
1429 | int i; | |
1430 | ||
1431 | kvm_for_each_vcpu(i, vcpu, kvm) | |
1432 | kvm_vgic_vcpu_destroy(vcpu); | |
1433 | ||
1434 | vgic_free_bitmap(&dist->irq_enabled); | |
1435 | vgic_free_bitmap(&dist->irq_level); | |
1436 | vgic_free_bitmap(&dist->irq_pending); | |
1437 | vgic_free_bitmap(&dist->irq_soft_pend); | |
1438 | vgic_free_bitmap(&dist->irq_queued); | |
1439 | vgic_free_bitmap(&dist->irq_cfg); | |
1440 | vgic_free_bytemap(&dist->irq_priority); | |
1441 | if (dist->irq_spi_target) { | |
1442 | for (i = 0; i < dist->nr_cpus; i++) | |
1443 | vgic_free_bitmap(&dist->irq_spi_target[i]); | |
1444 | } | |
1445 | kfree(dist->irq_sgi_sources); | |
1446 | kfree(dist->irq_spi_cpu); | |
a0675c25 | 1447 | kfree(dist->irq_spi_mpidr); |
c1bfb577 MZ |
1448 | kfree(dist->irq_spi_target); |
1449 | kfree(dist->irq_pending_on_cpu); | |
1450 | dist->irq_sgi_sources = NULL; | |
1451 | dist->irq_spi_cpu = NULL; | |
1452 | dist->irq_spi_target = NULL; | |
1453 | dist->irq_pending_on_cpu = NULL; | |
1f57be28 | 1454 | dist->nr_cpus = 0; |
c1bfb577 MZ |
1455 | } |
1456 | ||
1457 | /* | |
1458 | * Allocate and initialize the various data structures. Must be called | |
1459 | * with kvm->lock held! | |
1460 | */ | |
83215812 | 1461 | int vgic_init(struct kvm *kvm) |
c1bfb577 MZ |
1462 | { |
1463 | struct vgic_dist *dist = &kvm->arch.vgic; | |
1464 | struct kvm_vcpu *vcpu; | |
1465 | int nr_cpus, nr_irqs; | |
6d3cfbe2 | 1466 | int ret, i, vcpu_id; |
c1bfb577 | 1467 | |
1f57be28 | 1468 | if (vgic_initialized(kvm)) |
4956f2bc MZ |
1469 | return 0; |
1470 | ||
1471 | nr_cpus = dist->nr_cpus = atomic_read(&kvm->online_vcpus); | |
1472 | if (!nr_cpus) /* No vcpus? Can't be good... */ | |
66b030e4 | 1473 | return -ENODEV; |
5fb66da6 | 1474 | |
4956f2bc MZ |
1475 | /* |
1476 | * If nobody configured the number of interrupts, use the | |
1477 | * legacy one. | |
1478 | */ | |
5fb66da6 MZ |
1479 | if (!dist->nr_irqs) |
1480 | dist->nr_irqs = VGIC_NR_IRQS_LEGACY; | |
1481 | ||
1482 | nr_irqs = dist->nr_irqs; | |
c1bfb577 MZ |
1483 | |
1484 | ret = vgic_init_bitmap(&dist->irq_enabled, nr_cpus, nr_irqs); | |
1485 | ret |= vgic_init_bitmap(&dist->irq_level, nr_cpus, nr_irqs); | |
1486 | ret |= vgic_init_bitmap(&dist->irq_pending, nr_cpus, nr_irqs); | |
1487 | ret |= vgic_init_bitmap(&dist->irq_soft_pend, nr_cpus, nr_irqs); | |
1488 | ret |= vgic_init_bitmap(&dist->irq_queued, nr_cpus, nr_irqs); | |
1489 | ret |= vgic_init_bitmap(&dist->irq_cfg, nr_cpus, nr_irqs); | |
1490 | ret |= vgic_init_bytemap(&dist->irq_priority, nr_cpus, nr_irqs); | |
1491 | ||
1492 | if (ret) | |
1493 | goto out; | |
1494 | ||
1495 | dist->irq_sgi_sources = kzalloc(nr_cpus * VGIC_NR_SGIS, GFP_KERNEL); | |
1496 | dist->irq_spi_cpu = kzalloc(nr_irqs - VGIC_NR_PRIVATE_IRQS, GFP_KERNEL); | |
1497 | dist->irq_spi_target = kzalloc(sizeof(*dist->irq_spi_target) * nr_cpus, | |
1498 | GFP_KERNEL); | |
1499 | dist->irq_pending_on_cpu = kzalloc(BITS_TO_LONGS(nr_cpus) * sizeof(long), | |
1500 | GFP_KERNEL); | |
1501 | if (!dist->irq_sgi_sources || | |
1502 | !dist->irq_spi_cpu || | |
1503 | !dist->irq_spi_target || | |
1504 | !dist->irq_pending_on_cpu) { | |
1505 | ret = -ENOMEM; | |
1506 | goto out; | |
1507 | } | |
1508 | ||
1509 | for (i = 0; i < nr_cpus; i++) | |
1510 | ret |= vgic_init_bitmap(&dist->irq_spi_target[i], | |
1511 | nr_cpus, nr_irqs); | |
1512 | ||
1513 | if (ret) | |
1514 | goto out; | |
1515 | ||
b26e5fda AP |
1516 | ret = kvm->arch.vgic.vm_ops.init_model(kvm); |
1517 | if (ret) | |
1518 | goto out; | |
6d3cfbe2 PM |
1519 | |
1520 | kvm_for_each_vcpu(vcpu_id, vcpu, kvm) { | |
c1bfb577 MZ |
1521 | ret = vgic_vcpu_init_maps(vcpu, nr_irqs); |
1522 | if (ret) { | |
1523 | kvm_err("VGIC: Failed to allocate vcpu memory\n"); | |
1524 | break; | |
1525 | } | |
c1bfb577 | 1526 | |
6d3cfbe2 PM |
1527 | for (i = 0; i < dist->nr_irqs; i++) { |
1528 | if (i < VGIC_NR_PPIS) | |
1529 | vgic_bitmap_set_irq_val(&dist->irq_enabled, | |
1530 | vcpu->vcpu_id, i, 1); | |
1531 | if (i < VGIC_NR_PRIVATE_IRQS) | |
1532 | vgic_bitmap_set_irq_val(&dist->irq_cfg, | |
1533 | vcpu->vcpu_id, i, | |
1534 | VGIC_CFG_EDGE); | |
1535 | } | |
1536 | ||
1537 | vgic_enable(vcpu); | |
1538 | } | |
4956f2bc | 1539 | |
c1bfb577 MZ |
1540 | out: |
1541 | if (ret) | |
1542 | kvm_vgic_destroy(kvm); | |
1543 | ||
1544 | return ret; | |
1545 | } | |
1546 | ||
b26e5fda AP |
1547 | static int init_vgic_model(struct kvm *kvm, int type) |
1548 | { | |
1549 | switch (type) { | |
1550 | case KVM_DEV_TYPE_ARM_VGIC_V2: | |
1551 | vgic_v2_init_emulation(kvm); | |
1552 | break; | |
b5d84ff6 AP |
1553 | #ifdef CONFIG_ARM_GIC_V3 |
1554 | case KVM_DEV_TYPE_ARM_VGIC_V3: | |
1555 | vgic_v3_init_emulation(kvm); | |
1556 | break; | |
1557 | #endif | |
b26e5fda AP |
1558 | default: |
1559 | return -ENODEV; | |
1560 | } | |
1561 | ||
3caa2d8c AP |
1562 | if (atomic_read(&kvm->online_vcpus) > kvm->arch.max_vcpus) |
1563 | return -E2BIG; | |
1564 | ||
b26e5fda AP |
1565 | return 0; |
1566 | } | |
1567 | ||
59892136 | 1568 | int kvm_vgic_create(struct kvm *kvm, u32 type) |
01ac5e34 | 1569 | { |
6b50f540 | 1570 | int i, vcpu_lock_idx = -1, ret; |
7330672b | 1571 | struct kvm_vcpu *vcpu; |
01ac5e34 MZ |
1572 | |
1573 | mutex_lock(&kvm->lock); | |
1574 | ||
4ce7ebdf | 1575 | if (irqchip_in_kernel(kvm)) { |
01ac5e34 MZ |
1576 | ret = -EEXIST; |
1577 | goto out; | |
1578 | } | |
1579 | ||
b5d84ff6 AP |
1580 | /* |
1581 | * This function is also called by the KVM_CREATE_IRQCHIP handler, | |
1582 | * which had no chance yet to check the availability of the GICv2 | |
1583 | * emulation. So check this here again. KVM_CREATE_DEVICE does | |
1584 | * the proper checks already. | |
1585 | */ | |
1586 | if (type == KVM_DEV_TYPE_ARM_VGIC_V2 && !vgic->can_emulate_gicv2) | |
1587 | return -ENODEV; | |
1588 | ||
7330672b CD |
1589 | /* |
1590 | * Any time a vcpu is run, vcpu_load is called which tries to grab the | |
1591 | * vcpu->mutex. By grabbing the vcpu->mutex of all VCPUs we ensure | |
1592 | * that no other VCPUs are run while we create the vgic. | |
1593 | */ | |
6b50f540 | 1594 | ret = -EBUSY; |
7330672b CD |
1595 | kvm_for_each_vcpu(i, vcpu, kvm) { |
1596 | if (!mutex_trylock(&vcpu->mutex)) | |
1597 | goto out_unlock; | |
1598 | vcpu_lock_idx = i; | |
1599 | } | |
1600 | ||
1601 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
6b50f540 | 1602 | if (vcpu->arch.has_run_once) |
7330672b | 1603 | goto out_unlock; |
7330672b | 1604 | } |
6b50f540 | 1605 | ret = 0; |
7330672b | 1606 | |
b26e5fda AP |
1607 | ret = init_vgic_model(kvm, type); |
1608 | if (ret) | |
1609 | goto out_unlock; | |
1610 | ||
01ac5e34 | 1611 | spin_lock_init(&kvm->arch.vgic.lock); |
f982cf4e | 1612 | kvm->arch.vgic.in_kernel = true; |
59892136 | 1613 | kvm->arch.vgic.vgic_model = type; |
8f186d52 | 1614 | kvm->arch.vgic.vctrl_base = vgic->vctrl_base; |
01ac5e34 MZ |
1615 | kvm->arch.vgic.vgic_dist_base = VGIC_ADDR_UNDEF; |
1616 | kvm->arch.vgic.vgic_cpu_base = VGIC_ADDR_UNDEF; | |
a0675c25 | 1617 | kvm->arch.vgic.vgic_redist_base = VGIC_ADDR_UNDEF; |
01ac5e34 | 1618 | |
7330672b CD |
1619 | out_unlock: |
1620 | for (; vcpu_lock_idx >= 0; vcpu_lock_idx--) { | |
1621 | vcpu = kvm_get_vcpu(kvm, vcpu_lock_idx); | |
1622 | mutex_unlock(&vcpu->mutex); | |
1623 | } | |
1624 | ||
01ac5e34 MZ |
1625 | out: |
1626 | mutex_unlock(&kvm->lock); | |
1627 | return ret; | |
1628 | } | |
1629 | ||
1fa451bc | 1630 | static int vgic_ioaddr_overlap(struct kvm *kvm) |
330690cd CD |
1631 | { |
1632 | phys_addr_t dist = kvm->arch.vgic.vgic_dist_base; | |
1633 | phys_addr_t cpu = kvm->arch.vgic.vgic_cpu_base; | |
1634 | ||
1635 | if (IS_VGIC_ADDR_UNDEF(dist) || IS_VGIC_ADDR_UNDEF(cpu)) | |
1636 | return 0; | |
1637 | if ((dist <= cpu && dist + KVM_VGIC_V2_DIST_SIZE > cpu) || | |
1638 | (cpu <= dist && cpu + KVM_VGIC_V2_CPU_SIZE > dist)) | |
1639 | return -EBUSY; | |
1640 | return 0; | |
1641 | } | |
1642 | ||
1643 | static int vgic_ioaddr_assign(struct kvm *kvm, phys_addr_t *ioaddr, | |
1644 | phys_addr_t addr, phys_addr_t size) | |
1645 | { | |
1646 | int ret; | |
1647 | ||
ce01e4e8 CD |
1648 | if (addr & ~KVM_PHYS_MASK) |
1649 | return -E2BIG; | |
1650 | ||
1651 | if (addr & (SZ_4K - 1)) | |
1652 | return -EINVAL; | |
1653 | ||
330690cd CD |
1654 | if (!IS_VGIC_ADDR_UNDEF(*ioaddr)) |
1655 | return -EEXIST; | |
1656 | if (addr + size < addr) | |
1657 | return -EINVAL; | |
1658 | ||
30c21170 | 1659 | *ioaddr = addr; |
330690cd CD |
1660 | ret = vgic_ioaddr_overlap(kvm); |
1661 | if (ret) | |
30c21170 HW |
1662 | *ioaddr = VGIC_ADDR_UNDEF; |
1663 | ||
330690cd CD |
1664 | return ret; |
1665 | } | |
1666 | ||
ce01e4e8 CD |
1667 | /** |
1668 | * kvm_vgic_addr - set or get vgic VM base addresses | |
1669 | * @kvm: pointer to the vm struct | |
ac3d3735 | 1670 | * @type: the VGIC addr type, one of KVM_VGIC_V[23]_ADDR_TYPE_XXX |
ce01e4e8 CD |
1671 | * @addr: pointer to address value |
1672 | * @write: if true set the address in the VM address space, if false read the | |
1673 | * address | |
1674 | * | |
1675 | * Set or get the vgic base addresses for the distributor and the virtual CPU | |
1676 | * interface in the VM physical address space. These addresses are properties | |
1677 | * of the emulated core/SoC and therefore user space initially knows this | |
1678 | * information. | |
1679 | */ | |
1680 | int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write) | |
330690cd CD |
1681 | { |
1682 | int r = 0; | |
1683 | struct vgic_dist *vgic = &kvm->arch.vgic; | |
ac3d3735 AP |
1684 | int type_needed; |
1685 | phys_addr_t *addr_ptr, block_size; | |
4fa96afd | 1686 | phys_addr_t alignment; |
330690cd | 1687 | |
330690cd CD |
1688 | mutex_lock(&kvm->lock); |
1689 | switch (type) { | |
1690 | case KVM_VGIC_V2_ADDR_TYPE_DIST: | |
ac3d3735 AP |
1691 | type_needed = KVM_DEV_TYPE_ARM_VGIC_V2; |
1692 | addr_ptr = &vgic->vgic_dist_base; | |
1693 | block_size = KVM_VGIC_V2_DIST_SIZE; | |
4fa96afd | 1694 | alignment = SZ_4K; |
330690cd CD |
1695 | break; |
1696 | case KVM_VGIC_V2_ADDR_TYPE_CPU: | |
ac3d3735 AP |
1697 | type_needed = KVM_DEV_TYPE_ARM_VGIC_V2; |
1698 | addr_ptr = &vgic->vgic_cpu_base; | |
1699 | block_size = KVM_VGIC_V2_CPU_SIZE; | |
4fa96afd | 1700 | alignment = SZ_4K; |
330690cd | 1701 | break; |
ac3d3735 AP |
1702 | #ifdef CONFIG_ARM_GIC_V3 |
1703 | case KVM_VGIC_V3_ADDR_TYPE_DIST: | |
1704 | type_needed = KVM_DEV_TYPE_ARM_VGIC_V3; | |
1705 | addr_ptr = &vgic->vgic_dist_base; | |
1706 | block_size = KVM_VGIC_V3_DIST_SIZE; | |
4fa96afd | 1707 | alignment = SZ_64K; |
ac3d3735 AP |
1708 | break; |
1709 | case KVM_VGIC_V3_ADDR_TYPE_REDIST: | |
1710 | type_needed = KVM_DEV_TYPE_ARM_VGIC_V3; | |
1711 | addr_ptr = &vgic->vgic_redist_base; | |
1712 | block_size = KVM_VGIC_V3_REDIST_SIZE; | |
4fa96afd | 1713 | alignment = SZ_64K; |
ac3d3735 AP |
1714 | break; |
1715 | #endif | |
330690cd CD |
1716 | default: |
1717 | r = -ENODEV; | |
ac3d3735 AP |
1718 | goto out; |
1719 | } | |
1720 | ||
1721 | if (vgic->vgic_model != type_needed) { | |
1722 | r = -ENODEV; | |
1723 | goto out; | |
330690cd CD |
1724 | } |
1725 | ||
4fa96afd AP |
1726 | if (write) { |
1727 | if (!IS_ALIGNED(*addr, alignment)) | |
1728 | r = -EINVAL; | |
1729 | else | |
1730 | r = vgic_ioaddr_assign(kvm, addr_ptr, *addr, | |
1731 | block_size); | |
1732 | } else { | |
ac3d3735 | 1733 | *addr = *addr_ptr; |
4fa96afd | 1734 | } |
ac3d3735 AP |
1735 | |
1736 | out: | |
330690cd CD |
1737 | mutex_unlock(&kvm->lock); |
1738 | return r; | |
1739 | } | |
7330672b | 1740 | |
83215812 | 1741 | int vgic_set_common_attr(struct kvm_device *dev, struct kvm_device_attr *attr) |
7330672b | 1742 | { |
ce01e4e8 CD |
1743 | int r; |
1744 | ||
1745 | switch (attr->group) { | |
1746 | case KVM_DEV_ARM_VGIC_GRP_ADDR: { | |
1747 | u64 __user *uaddr = (u64 __user *)(long)attr->addr; | |
1748 | u64 addr; | |
1749 | unsigned long type = (unsigned long)attr->attr; | |
1750 | ||
1751 | if (copy_from_user(&addr, uaddr, sizeof(addr))) | |
1752 | return -EFAULT; | |
1753 | ||
1754 | r = kvm_vgic_addr(dev->kvm, type, &addr, true); | |
1755 | return (r == -ENODEV) ? -ENXIO : r; | |
1756 | } | |
a98f26f1 MZ |
1757 | case KVM_DEV_ARM_VGIC_GRP_NR_IRQS: { |
1758 | u32 __user *uaddr = (u32 __user *)(long)attr->addr; | |
1759 | u32 val; | |
1760 | int ret = 0; | |
1761 | ||
1762 | if (get_user(val, uaddr)) | |
1763 | return -EFAULT; | |
1764 | ||
1765 | /* | |
1766 | * We require: | |
1767 | * - at least 32 SPIs on top of the 16 SGIs and 16 PPIs | |
1768 | * - at most 1024 interrupts | |
1769 | * - a multiple of 32 interrupts | |
1770 | */ | |
1771 | if (val < (VGIC_NR_PRIVATE_IRQS + 32) || | |
1772 | val > VGIC_MAX_IRQS || | |
1773 | (val & 31)) | |
1774 | return -EINVAL; | |
1775 | ||
1776 | mutex_lock(&dev->kvm->lock); | |
1777 | ||
c52edf5f | 1778 | if (vgic_ready(dev->kvm) || dev->kvm->arch.vgic.nr_irqs) |
a98f26f1 MZ |
1779 | ret = -EBUSY; |
1780 | else | |
1781 | dev->kvm->arch.vgic.nr_irqs = val; | |
1782 | ||
1783 | mutex_unlock(&dev->kvm->lock); | |
1784 | ||
1785 | return ret; | |
1786 | } | |
065c0034 EA |
1787 | case KVM_DEV_ARM_VGIC_GRP_CTRL: { |
1788 | switch (attr->attr) { | |
1789 | case KVM_DEV_ARM_VGIC_CTRL_INIT: | |
1790 | r = vgic_init(dev->kvm); | |
1791 | return r; | |
1792 | } | |
1793 | break; | |
1794 | } | |
ce01e4e8 CD |
1795 | } |
1796 | ||
7330672b CD |
1797 | return -ENXIO; |
1798 | } | |
1799 | ||
83215812 | 1800 | int vgic_get_common_attr(struct kvm_device *dev, struct kvm_device_attr *attr) |
7330672b | 1801 | { |
ce01e4e8 CD |
1802 | int r = -ENXIO; |
1803 | ||
1804 | switch (attr->group) { | |
1805 | case KVM_DEV_ARM_VGIC_GRP_ADDR: { | |
1806 | u64 __user *uaddr = (u64 __user *)(long)attr->addr; | |
1807 | u64 addr; | |
1808 | unsigned long type = (unsigned long)attr->attr; | |
1809 | ||
1810 | r = kvm_vgic_addr(dev->kvm, type, &addr, false); | |
1811 | if (r) | |
1812 | return (r == -ENODEV) ? -ENXIO : r; | |
1813 | ||
1814 | if (copy_to_user(uaddr, &addr, sizeof(addr))) | |
1815 | return -EFAULT; | |
c07a0191 CD |
1816 | break; |
1817 | } | |
b60da146 AP |
1818 | case KVM_DEV_ARM_VGIC_GRP_NR_IRQS: { |
1819 | u32 __user *uaddr = (u32 __user *)(long)attr->addr; | |
1820 | ||
1821 | r = put_user(dev->kvm->arch.vgic.nr_irqs, uaddr); | |
1822 | break; | |
1823 | } | |
1824 | ||
1825 | } | |
1826 | ||
1827 | return r; | |
1828 | } | |
1829 | ||
83215812 | 1830 | int vgic_has_attr_regs(const struct kvm_mmio_range *ranges, phys_addr_t offset) |
c07a0191 CD |
1831 | { |
1832 | struct kvm_exit_mmio dev_attr_mmio; | |
1833 | ||
1834 | dev_attr_mmio.len = 4; | |
83215812 | 1835 | if (vgic_find_range(ranges, &dev_attr_mmio, offset)) |
c07a0191 CD |
1836 | return 0; |
1837 | else | |
1838 | return -ENXIO; | |
1839 | } | |
1840 | ||
c06a841b WD |
1841 | static void vgic_init_maintenance_interrupt(void *info) |
1842 | { | |
1843 | enable_percpu_irq(vgic->maint_irq, 0); | |
1844 | } | |
1845 | ||
1846 | static int vgic_cpu_notify(struct notifier_block *self, | |
1847 | unsigned long action, void *cpu) | |
1848 | { | |
1849 | switch (action) { | |
1850 | case CPU_STARTING: | |
1851 | case CPU_STARTING_FROZEN: | |
1852 | vgic_init_maintenance_interrupt(NULL); | |
1853 | break; | |
1854 | case CPU_DYING: | |
1855 | case CPU_DYING_FROZEN: | |
1856 | disable_percpu_irq(vgic->maint_irq); | |
1857 | break; | |
1858 | } | |
1859 | ||
1860 | return NOTIFY_OK; | |
1861 | } | |
1862 | ||
1863 | static struct notifier_block vgic_cpu_nb = { | |
1864 | .notifier_call = vgic_cpu_notify, | |
1865 | }; | |
1866 | ||
1867 | static const struct of_device_id vgic_ids[] = { | |
1868 | { .compatible = "arm,cortex-a15-gic", .data = vgic_v2_probe, }, | |
1869 | { .compatible = "arm,gic-v3", .data = vgic_v3_probe, }, | |
1870 | {}, | |
1871 | }; | |
1872 | ||
1873 | int kvm_vgic_hyp_init(void) | |
1874 | { | |
1875 | const struct of_device_id *matched_id; | |
a875dafc CD |
1876 | const int (*vgic_probe)(struct device_node *,const struct vgic_ops **, |
1877 | const struct vgic_params **); | |
c06a841b WD |
1878 | struct device_node *vgic_node; |
1879 | int ret; | |
1880 | ||
1881 | vgic_node = of_find_matching_node_and_match(NULL, | |
1882 | vgic_ids, &matched_id); | |
1883 | if (!vgic_node) { | |
1884 | kvm_err("error: no compatible GIC node found\n"); | |
1885 | return -ENODEV; | |
1886 | } | |
1887 | ||
1888 | vgic_probe = matched_id->data; | |
1889 | ret = vgic_probe(vgic_node, &vgic_ops, &vgic); | |
1890 | if (ret) | |
1891 | return ret; | |
1892 | ||
1893 | ret = request_percpu_irq(vgic->maint_irq, vgic_maintenance_handler, | |
1894 | "vgic", kvm_get_running_vcpus()); | |
1895 | if (ret) { | |
1896 | kvm_err("Cannot register interrupt %d\n", vgic->maint_irq); | |
1897 | return ret; | |
1898 | } | |
1899 | ||
1900 | ret = __register_cpu_notifier(&vgic_cpu_nb); | |
1901 | if (ret) { | |
1902 | kvm_err("Cannot register vgic CPU notifier\n"); | |
1903 | goto out_free_irq; | |
1904 | } | |
1905 | ||
1906 | /* Callback into for arch code for setup */ | |
1907 | vgic_arch_setup(vgic); | |
1908 | ||
1909 | on_each_cpu(vgic_init_maintenance_interrupt, NULL, 1); | |
1910 | ||
ea2f83a7 | 1911 | return 0; |
c06a841b WD |
1912 | |
1913 | out_free_irq: | |
1914 | free_percpu_irq(vgic->maint_irq, kvm_get_running_vcpus()); | |
1915 | return ret; | |
1916 | } |