[linux-2.6-block.git] / virt / kvm / arm / vgic-v3.c

/*
 * Copyright (C) 2013 ARM Limited, All Rights Reserved.
 * Author: Marc Zyngier <marc.zyngier@arm.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/cpu.h>
#include <linux/kvm.h>
#include <linux/kvm_host.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>

#include <linux/irqchip/arm-gic-v3.h>

#include <asm/kvm_emulate.h>
#include <asm/kvm_arm.h>
#include <asm/kvm_asm.h>
#include <asm/kvm_mmu.h>

/* These are for GICv2 emulation only */
#define GICH_LR_VIRTUALID		(0x3ffUL << 0)
#define GICH_LR_PHYSID_CPUID_SHIFT	(10)
#define GICH_LR_PHYSID_CPUID		(7UL << GICH_LR_PHYSID_CPUID_SHIFT)
#define ICH_LR_VIRTUALID_MASK		(BIT_ULL(32) - 1)

static u32 ich_vtr_el2;

static struct vgic_lr vgic_v3_get_lr(const struct kvm_vcpu *vcpu, int lr)
{
	struct vgic_lr lr_desc;
	u64 val = vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr];

	if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3)
		lr_desc.irq = val & ICH_LR_VIRTUALID_MASK;
	else
		lr_desc.irq = val & GICH_LR_VIRTUALID;

	lr_desc.source = 0;
	if (lr_desc.irq <= 15 &&
	    vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V2)
		lr_desc.source = (val >> GICH_LR_PHYSID_CPUID_SHIFT) & 0x7;

	lr_desc.state = 0;

	if (val & ICH_LR_PENDING_BIT)
		lr_desc.state |= LR_STATE_PENDING;
	if (val & ICH_LR_ACTIVE_BIT)
		lr_desc.state |= LR_STATE_ACTIVE;
	if (val & ICH_LR_EOI)
		lr_desc.state |= LR_EOI_INT;
	if (val & ICH_LR_HW) {
		lr_desc.state |= LR_HW;
		lr_desc.hwirq = (val >> ICH_LR_PHYS_ID_SHIFT) & GENMASK(9, 0);
	}

	return lr_desc;
}

static void vgic_v3_set_lr(struct kvm_vcpu *vcpu, int lr,
			   struct vgic_lr lr_desc)
{
	u64 lr_val;

	lr_val = lr_desc.irq;

	/*
	 * Currently all guest IRQs are Group1, as Group0 would result
	 * in a FIQ in the guest, which it wouldn't expect.
	 * Eventually we want to make this configurable, so we may revisit
	 * this in the future.
	 */
	switch (vcpu->kvm->arch.vgic.vgic_model) {
	case KVM_DEV_TYPE_ARM_VGIC_V3:
		lr_val |= ICH_LR_GROUP;
		break;
	case  KVM_DEV_TYPE_ARM_VGIC_V2:
		if (lr_desc.irq < VGIC_NR_SGIS)
			lr_val |= (u32)lr_desc.source << GICH_LR_PHYSID_CPUID_SHIFT;
		break;
	default:
		BUG();
	}

	if (lr_desc.state & LR_STATE_PENDING)
		lr_val |= ICH_LR_PENDING_BIT;
	if (lr_desc.state & LR_STATE_ACTIVE)
		lr_val |= ICH_LR_ACTIVE_BIT;
	if (lr_desc.state & LR_EOI_INT)
		lr_val |= ICH_LR_EOI;
	if (lr_desc.state & LR_HW) {
		lr_val |= ICH_LR_HW;
		lr_val |= ((u64)lr_desc.hwirq) << ICH_LR_PHYS_ID_SHIFT;
	}

	vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = lr_val;

	if (!(lr_desc.state & LR_STATE_MASK))
		vcpu->arch.vgic_cpu.vgic_v3.vgic_elrsr |= (1U << lr);
	else
		vcpu->arch.vgic_cpu.vgic_v3.vgic_elrsr &= ~(1U << lr);
}

static u64 vgic_v3_get_elrsr(const struct kvm_vcpu *vcpu)
{
	return vcpu->arch.vgic_cpu.vgic_v3.vgic_elrsr;
}

static u64 vgic_v3_get_eisr(const struct kvm_vcpu *vcpu)
{
	return vcpu->arch.vgic_cpu.vgic_v3.vgic_eisr;
}

static void vgic_v3_clear_eisr(struct kvm_vcpu *vcpu)
{
	vcpu->arch.vgic_cpu.vgic_v3.vgic_eisr = 0;
}

static u32 vgic_v3_get_interrupt_status(const struct kvm_vcpu *vcpu)
{
	u32 misr = vcpu->arch.vgic_cpu.vgic_v3.vgic_misr;
	u32 ret = 0;

	if (misr & ICH_MISR_EOI)
		ret |= INT_STATUS_EOI;
	if (misr & ICH_MISR_U)
		ret |= INT_STATUS_UNDERFLOW;

	return ret;
}

static void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
{
	u32 vmcr = vcpu->arch.vgic_cpu.vgic_v3.vgic_vmcr;

	vmcrp->ctlr = (vmcr & ICH_VMCR_CTLR_MASK) >> ICH_VMCR_CTLR_SHIFT;
	vmcrp->abpr = (vmcr & ICH_VMCR_BPR1_MASK) >> ICH_VMCR_BPR1_SHIFT;
	vmcrp->bpr  = (vmcr & ICH_VMCR_BPR0_MASK) >> ICH_VMCR_BPR0_SHIFT;
	vmcrp->pmr  = (vmcr & ICH_VMCR_PMR_MASK) >> ICH_VMCR_PMR_SHIFT;
}

static void vgic_v3_enable_underflow(struct kvm_vcpu *vcpu)
{
	vcpu->arch.vgic_cpu.vgic_v3.vgic_hcr |= ICH_HCR_UIE;
}

static void vgic_v3_disable_underflow(struct kvm_vcpu *vcpu)
{
	vcpu->arch.vgic_cpu.vgic_v3.vgic_hcr &= ~ICH_HCR_UIE;
}

static void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
{
	u32 vmcr;

	vmcr  = (vmcrp->ctlr << ICH_VMCR_CTLR_SHIFT) & ICH_VMCR_CTLR_MASK;
	vmcr |= (vmcrp->abpr << ICH_VMCR_BPR1_SHIFT) & ICH_VMCR_BPR1_MASK;
	vmcr |= (vmcrp->bpr << ICH_VMCR_BPR0_SHIFT) & ICH_VMCR_BPR0_MASK;
	vmcr |= (vmcrp->pmr << ICH_VMCR_PMR_SHIFT) & ICH_VMCR_PMR_MASK;

	vcpu->arch.vgic_cpu.vgic_v3.vgic_vmcr = vmcr;
}

static void vgic_v3_enable(struct kvm_vcpu *vcpu)
{
	struct vgic_v3_cpu_if *vgic_v3 = &vcpu->arch.vgic_cpu.vgic_v3;

	/*
	 * By forcing VMCR to zero, the GIC will restore the binary
	 * points to their reset values. Anything else resets to zero
	 * anyway.
	 */
	vgic_v3->vgic_vmcr = 0;
	vgic_v3->vgic_elrsr = ~0;

	/*
	 * If we are emulating a GICv3, we do it in an non-GICv2-compatible
	 * way, so we force SRE to 1 to demonstrate this to the guest.
	 * This goes with the spec allowing the value to be RAO/WI.
	 */
	if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3)
		vgic_v3->vgic_sre = ICC_SRE_EL1_SRE;
	else
		vgic_v3->vgic_sre = 0;

	/* Get the show on the road... */
	vgic_v3->vgic_hcr = ICH_HCR_EN;
}

static const struct vgic_ops vgic_v3_ops = {
	.get_lr			= vgic_v3_get_lr,
	.set_lr			= vgic_v3_set_lr,
	.get_elrsr		= vgic_v3_get_elrsr,
	.get_eisr		= vgic_v3_get_eisr,
	.clear_eisr		= vgic_v3_clear_eisr,
	.get_interrupt_status	= vgic_v3_get_interrupt_status,
	.enable_underflow	= vgic_v3_enable_underflow,
	.disable_underflow	= vgic_v3_disable_underflow,
	.get_vmcr		= vgic_v3_get_vmcr,
	.set_vmcr		= vgic_v3_set_vmcr,
	.enable			= vgic_v3_enable,
};

static struct vgic_params vgic_v3_params;

static void vgic_cpu_init_lrs(void *params)
{
	kvm_call_hyp(__vgic_v3_init_lrs);
}

/**
 * vgic_v3_probe - probe for a GICv3 compatible interrupt controller in DT
 * @node:	pointer to the DT node
 * @ops: 	address of a pointer to the GICv3 operations
 * @params:	address of a pointer to HW-specific parameters
 *
 * Returns 0 if a GICv3 has been found, with the low level operations
 * in *ops and the HW parameters in *params. Returns an error code
 * otherwise.
 */
int vgic_v3_probe(struct device_node *vgic_node,
		  const struct vgic_ops **ops,
		  const struct vgic_params **params)
{
	int ret = 0;
	u32 gicv_idx;
	struct resource vcpu_res;
	struct vgic_params *vgic = &vgic_v3_params;

	vgic->maint_irq = irq_of_parse_and_map(vgic_node, 0);
	if (!vgic->maint_irq) {
		kvm_err("error getting vgic maintenance irq from DT\n");
		ret = -ENXIO;
		goto out;
	}

	ich_vtr_el2 = kvm_call_hyp(__vgic_v3_get_ich_vtr_el2);

	/*
	 * The ListRegs field is 5 bits, but there is a architectural
	 * maximum of 16 list registers. Just ignore bit 4...
	 */
	vgic->nr_lr = (ich_vtr_el2 & 0xf) + 1;
	vgic->can_emulate_gicv2 = false;

	if (of_property_read_u32(vgic_node, "#redistributor-regions", &gicv_idx))
		gicv_idx = 1;

	gicv_idx += 3; /* Also skip GICD, GICC, GICH */
	if (of_address_to_resource(vgic_node, gicv_idx, &vcpu_res)) {
		kvm_info("GICv3: no GICV resource entry\n");
		vgic->vcpu_base = 0;
	} else if (!PAGE_ALIGNED(vcpu_res.start)) {
		pr_warn("GICV physical address 0x%llx not page aligned\n",
			(unsigned long long)vcpu_res.start);
		vgic->vcpu_base = 0;
	} else if (!PAGE_ALIGNED(resource_size(&vcpu_res))) {
		pr_warn("GICV size 0x%llx not a multiple of page size 0x%lx\n",
			(unsigned long long)resource_size(&vcpu_res),
			PAGE_SIZE);
		vgic->vcpu_base = 0;
	} else {
		vgic->vcpu_base = vcpu_res.start;
		vgic->can_emulate_gicv2 = true;
		kvm_register_device_ops(&kvm_arm_vgic_v2_ops,
					KVM_DEV_TYPE_ARM_VGIC_V2);
	}
	if (vgic->vcpu_base == 0)
		kvm_info("disabling GICv2 emulation\n");
	kvm_register_device_ops(&kvm_arm_vgic_v3_ops, KVM_DEV_TYPE_ARM_VGIC_V3);

	vgic->vctrl_base = NULL;
	vgic->type = VGIC_V3;
	vgic->max_gic_vcpus = VGIC_V3_MAX_CPUS;

	kvm_info("%s@%llx IRQ%d\n", vgic_node->name,
		 vcpu_res.start, vgic->maint_irq);

	on_each_cpu(vgic_cpu_init_lrs, vgic, 1);

	*ops = &vgic_v3_ops;
	*params = vgic;

out:
	of_node_put(vgic_node);
	return ret;
}
Commit	Line	Data
b2fb1c0d MZ	1	/*
	2	* Copyright (C) 2013 ARM Limited, All Rights Reserved.
	3	* Author: Marc Zyngier <marc.zyngier@arm.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	16	*/
	17
	18	#include <linux/cpu.h>
	19	#include <linux/kvm.h>
	20	#include <linux/kvm_host.h>
	21	#include <linux/interrupt.h>
	22	#include <linux/io.h>
	23	#include <linux/of.h>
	24	#include <linux/of_address.h>
	25	#include <linux/of_irq.h>
	26
	27	#include <linux/irqchip/arm-gic-v3.h>
	28
	29	#include <asm/kvm_emulate.h>
	30	#include <asm/kvm_arm.h>
9d8415d6	31	#include <asm/kvm_asm.h>
b2fb1c0d MZ	32	#include <asm/kvm_mmu.h>
	33
	34	/* These are for GICv2 emulation only */
	35	#define GICH_LR_VIRTUALID (0x3ffUL << 0)
	36	#define GICH_LR_PHYSID_CPUID_SHIFT (10)
	37	#define GICH_LR_PHYSID_CPUID (7UL << GICH_LR_PHYSID_CPUID_SHIFT)
b5d84ff6	38	#define ICH_LR_VIRTUALID_MASK (BIT_ULL(32) - 1)
b2fb1c0d	39
b2fb1c0d MZ	40	static u32 ich_vtr_el2;
	41
	42	static struct vgic_lr vgic_v3_get_lr(const struct kvm_vcpu *vcpu, int lr)
	43	{
	44	struct vgic_lr lr_desc;
1b8e83c0	45	u64 val = vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr];
b2fb1c0d	46
b5d84ff6 AP	47	if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3)
b5d84ff6 AP	48	lr_desc.irq = val & ICH_LR_VIRTUALID_MASK;
b2fb1c0d	49	else
b5d84ff6 AP	50	lr_desc.irq = val & GICH_LR_VIRTUALID;
	51
	52	lr_desc.source = 0;
	53	if (lr_desc.irq <= 15 &&
	54	vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V2)
	55	lr_desc.source = (val >> GICH_LR_PHYSID_CPUID_SHIFT) & 0x7;
	56
	57	lr_desc.state = 0;
b2fb1c0d MZ	58
	59	if (val & ICH_LR_PENDING_BIT)
	60	lr_desc.state \|= LR_STATE_PENDING;
	61	if (val & ICH_LR_ACTIVE_BIT)
	62	lr_desc.state \|= LR_STATE_ACTIVE;
	63	if (val & ICH_LR_EOI)
	64	lr_desc.state \|= LR_EOI_INT;
fb182cf8 MZ	65	if (val & ICH_LR_HW) {
	66	lr_desc.state \|= LR_HW;
	67	lr_desc.hwirq = (val >> ICH_LR_PHYS_ID_SHIFT) & GENMASK(9, 0);
	68	}
b2fb1c0d MZ	69
	70	return lr_desc;
	71	}
	72
	73	static void vgic_v3_set_lr(struct kvm_vcpu *vcpu, int lr,
	74	struct vgic_lr lr_desc)
	75	{
b5d84ff6 AP	76	u64 lr_val;
	77
	78	lr_val = lr_desc.irq;
	79
	80	/*
	81	* Currently all guest IRQs are Group1, as Group0 would result
	82	* in a FIQ in the guest, which it wouldn't expect.
	83	* Eventually we want to make this configurable, so we may revisit
	84	* this in the future.
	85	*/
fb182cf8 MZ	86	switch (vcpu->kvm->arch.vgic.vgic_model) {
fb182cf8 MZ	87	case KVM_DEV_TYPE_ARM_VGIC_V3:
b5d84ff6	88	lr_val \|= ICH_LR_GROUP;
fb182cf8 MZ	89	break;
	90	case KVM_DEV_TYPE_ARM_VGIC_V2:
	91	if (lr_desc.irq < VGIC_NR_SGIS)
	92	lr_val \|= (u32)lr_desc.source << GICH_LR_PHYSID_CPUID_SHIFT;
	93	break;
	94	default:
	95	BUG();
	96	}
b2fb1c0d MZ	97
	98	if (lr_desc.state & LR_STATE_PENDING)
	99	lr_val \|= ICH_LR_PENDING_BIT;
	100	if (lr_desc.state & LR_STATE_ACTIVE)
	101	lr_val \|= ICH_LR_ACTIVE_BIT;
	102	if (lr_desc.state & LR_EOI_INT)
	103	lr_val \|= ICH_LR_EOI;
fb182cf8 MZ	104	if (lr_desc.state & LR_HW) {
	105	lr_val \|= ICH_LR_HW;
	106	lr_val \|= ((u64)lr_desc.hwirq) << ICH_LR_PHYS_ID_SHIFT;
	107	}
b2fb1c0d	108
1b8e83c0	109	vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = lr_val;
b2fb1c0d	110
b2fb1c0d MZ	111	if (!(lr_desc.state & LR_STATE_MASK))
b2fb1c0d MZ	112	vcpu->arch.vgic_cpu.vgic_v3.vgic_elrsr \|= (1U << lr);
ae705930 CD	113	else
ae705930 CD	114	vcpu->arch.vgic_cpu.vgic_v3.vgic_elrsr &= ~(1U << lr);
b2fb1c0d MZ	115	}
	116
	117	static u64 vgic_v3_get_elrsr(const struct kvm_vcpu *vcpu)
	118	{
	119	return vcpu->arch.vgic_cpu.vgic_v3.vgic_elrsr;
	120	}
	121
	122	static u64 vgic_v3_get_eisr(const struct kvm_vcpu *vcpu)
	123	{
	124	return vcpu->arch.vgic_cpu.vgic_v3.vgic_eisr;
	125	}
	126
ae705930 CD	127	static void vgic_v3_clear_eisr(struct kvm_vcpu *vcpu)
	128	{
	129	vcpu->arch.vgic_cpu.vgic_v3.vgic_eisr = 0;
	130	}
	131
b2fb1c0d MZ	132	static u32 vgic_v3_get_interrupt_status(const struct kvm_vcpu *vcpu)
	133	{
	134	u32 misr = vcpu->arch.vgic_cpu.vgic_v3.vgic_misr;
	135	u32 ret = 0;
	136
	137	if (misr & ICH_MISR_EOI)
	138	ret \|= INT_STATUS_EOI;
	139	if (misr & ICH_MISR_U)
	140	ret \|= INT_STATUS_UNDERFLOW;
	141
	142	return ret;
	143	}
	144
	145	static void vgic_v3_get_vmcr(struct kvm_vcpu vcpu, struct vgic_vmcr vmcrp)
	146	{
	147	u32 vmcr = vcpu->arch.vgic_cpu.vgic_v3.vgic_vmcr;
	148
	149	vmcrp->ctlr = (vmcr & ICH_VMCR_CTLR_MASK) >> ICH_VMCR_CTLR_SHIFT;
	150	vmcrp->abpr = (vmcr & ICH_VMCR_BPR1_MASK) >> ICH_VMCR_BPR1_SHIFT;
	151	vmcrp->bpr = (vmcr & ICH_VMCR_BPR0_MASK) >> ICH_VMCR_BPR0_SHIFT;
	152	vmcrp->pmr = (vmcr & ICH_VMCR_PMR_MASK) >> ICH_VMCR_PMR_SHIFT;
	153	}
	154
	155	static void vgic_v3_enable_underflow(struct kvm_vcpu *vcpu)
	156	{
	157	vcpu->arch.vgic_cpu.vgic_v3.vgic_hcr \|= ICH_HCR_UIE;
	158	}
	159
	160	static void vgic_v3_disable_underflow(struct kvm_vcpu *vcpu)
	161	{
	162	vcpu->arch.vgic_cpu.vgic_v3.vgic_hcr &= ~ICH_HCR_UIE;
	163	}
	164
	165	static void vgic_v3_set_vmcr(struct kvm_vcpu vcpu, struct vgic_vmcr vmcrp)
	166	{
	167	u32 vmcr;
	168
	169	vmcr = (vmcrp->ctlr << ICH_VMCR_CTLR_SHIFT) & ICH_VMCR_CTLR_MASK;
	170	vmcr \|= (vmcrp->abpr << ICH_VMCR_BPR1_SHIFT) & ICH_VMCR_BPR1_MASK;
	171	vmcr \|= (vmcrp->bpr << ICH_VMCR_BPR0_SHIFT) & ICH_VMCR_BPR0_MASK;
	172	vmcr \|= (vmcrp->pmr << ICH_VMCR_PMR_SHIFT) & ICH_VMCR_PMR_MASK;
	173
	174	vcpu->arch.vgic_cpu.vgic_v3.vgic_vmcr = vmcr;
	175	}
	176
	177	static void vgic_v3_enable(struct kvm_vcpu *vcpu)
	178	{
2f5fa41a AP	179	struct vgic_v3_cpu_if *vgic_v3 = &vcpu->arch.vgic_cpu.vgic_v3;
2f5fa41a AP	180
b2fb1c0d MZ	181	/*
	182	* By forcing VMCR to zero, the GIC will restore the binary
	183	* points to their reset values. Anything else resets to zero
	184	* anyway.
	185	*/
2f5fa41a	186	vgic_v3->vgic_vmcr = 0;
c4cd4c16	187	vgic_v3->vgic_elrsr = ~0;
2f5fa41a	188
b5d84ff6 AP	189	/*
	190	* If we are emulating a GICv3, we do it in an non-GICv2-compatible
	191	* way, so we force SRE to 1 to demonstrate this to the guest.
	192	* This goes with the spec allowing the value to be RAO/WI.
	193	*/
	194	if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3)
	195	vgic_v3->vgic_sre = ICC_SRE_EL1_SRE;
	196	else
	197	vgic_v3->vgic_sre = 0;
b2fb1c0d MZ	198
b2fb1c0d MZ	199	/* Get the show on the road... */
2f5fa41a	200	vgic_v3->vgic_hcr = ICH_HCR_EN;
b2fb1c0d MZ	201	}
	202
	203	static const struct vgic_ops vgic_v3_ops = {
	204	.get_lr = vgic_v3_get_lr,
	205	.set_lr = vgic_v3_set_lr,
b2fb1c0d MZ	206	.get_elrsr = vgic_v3_get_elrsr,
b2fb1c0d MZ	207	.get_eisr = vgic_v3_get_eisr,
ae705930	208	.clear_eisr = vgic_v3_clear_eisr,
b2fb1c0d MZ	209	.get_interrupt_status = vgic_v3_get_interrupt_status,
	210	.enable_underflow = vgic_v3_enable_underflow,
	211	.disable_underflow = vgic_v3_disable_underflow,
	212	.get_vmcr = vgic_v3_get_vmcr,
	213	.set_vmcr = vgic_v3_set_vmcr,
	214	.enable = vgic_v3_enable,
	215	};
	216
	217	static struct vgic_params vgic_v3_params;
	218
0d98d00b MZ	219	static void vgic_cpu_init_lrs(void *params)
	220	{
	221	kvm_call_hyp(__vgic_v3_init_lrs);
	222	}
	223
b2fb1c0d MZ	224	/**
	225	* vgic_v3_probe - probe for a GICv3 compatible interrupt controller in DT
	226	* @node: pointer to the DT node
	227	* @ops: address of a pointer to the GICv3 operations
	228	* @params: address of a pointer to HW-specific parameters
	229	*
	230	* Returns 0 if a GICv3 has been found, with the low level operations
	231	* in ops and the HW parameters in params. Returns an error code
	232	* otherwise.
	233	*/
	234	int vgic_v3_probe(struct device_node *vgic_node,
	235	const struct vgic_ops **ops,
	236	const struct vgic_params **params)
	237	{
	238	int ret = 0;
	239	u32 gicv_idx;
	240	struct resource vcpu_res;
	241	struct vgic_params *vgic = &vgic_v3_params;
	242
	243	vgic->maint_irq = irq_of_parse_and_map(vgic_node, 0);
	244	if (!vgic->maint_irq) {
	245	kvm_err("error getting vgic maintenance irq from DT\n");
	246	ret = -ENXIO;
	247	goto out;
	248	}
	249
	250	ich_vtr_el2 = kvm_call_hyp(__vgic_v3_get_ich_vtr_el2);
	251
	252	/*
	253	* The ListRegs field is 5 bits, but there is a architectural
	254	* maximum of 16 list registers. Just ignore bit 4...
	255	*/
	256	vgic->nr_lr = (ich_vtr_el2 & 0xf) + 1;
b5d84ff6	257	vgic->can_emulate_gicv2 = false;
b2fb1c0d MZ	258
	259	if (of_property_read_u32(vgic_node, "#redistributor-regions", &gicv_idx))
	260	gicv_idx = 1;
	261
	262	gicv_idx += 3; /* Also skip GICD, GICC, GICH */
	263	if (of_address_to_resource(vgic_node, gicv_idx, &vcpu_res)) {
b5d84ff6 AP	264	kvm_info("GICv3: no GICV resource entry\n");
	265	vgic->vcpu_base = 0;
	266	} else if (!PAGE_ALIGNED(vcpu_res.start)) {
	267	pr_warn("GICV physical address 0x%llx not page aligned\n",
fb3ec679	268	(unsigned long long)vcpu_res.start);
b5d84ff6 AP	269	vgic->vcpu_base = 0;
	270	} else if (!PAGE_ALIGNED(resource_size(&vcpu_res))) {
	271	pr_warn("GICV size 0x%llx not a multiple of page size 0x%lx\n",
fb3ec679 MZ	272	(unsigned long long)resource_size(&vcpu_res),
fb3ec679 MZ	273	PAGE_SIZE);
b5d84ff6 AP	274	vgic->vcpu_base = 0;
	275	} else {
	276	vgic->vcpu_base = vcpu_res.start;
	277	vgic->can_emulate_gicv2 = true;
	278	kvm_register_device_ops(&kvm_arm_vgic_v2_ops,
	279	KVM_DEV_TYPE_ARM_VGIC_V2);
fb3ec679	280	}
b5d84ff6 AP	281	if (vgic->vcpu_base == 0)
	282	kvm_info("disabling GICv2 emulation\n");
	283	kvm_register_device_ops(&kvm_arm_vgic_v3_ops, KVM_DEV_TYPE_ARM_VGIC_V3);
fb3ec679	284
b2fb1c0d MZ	285	vgic->vctrl_base = NULL;
b2fb1c0d MZ	286	vgic->type = VGIC_V3;
ef748917	287	vgic->max_gic_vcpus = VGIC_V3_MAX_CPUS;
b2fb1c0d MZ	288
	289	kvm_info("%s@%llx IRQ%d\n", vgic_node->name,
	290	vcpu_res.start, vgic->maint_irq);
	291
0d98d00b MZ	292	on_each_cpu(vgic_cpu_init_lrs, vgic, 1);
0d98d00b MZ	293
b2fb1c0d MZ	294	*ops = &vgic_v3_ops;
	295	*params = vgic;
	296
	297	out:
	298	of_node_put(vgic_node);
	299	return ret;
	300	}