[linux-2.6-block.git] / sound / soc / sof / intel / hda.c

// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
//
// This file is provided under a dual BSD/GPLv2 license.  When using or
// redistributing this file, you may do so under either license.
//
// Copyright(c) 2018 Intel Corporation. All rights reserved.
//
// Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
//	    Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
//	    Rander Wang <rander.wang@intel.com>
//          Keyon Jie <yang.jie@linux.intel.com>
//

/*
 * Hardware interface for generic Intel audio DSP HDA IP
 */

#include <sound/hdaudio_ext.h>
#include <sound/hda_register.h>

#include <linux/module.h>
#include <sound/sof.h>
#include <sound/sof/xtensa.h>
#include "../ops.h"
#include "hda.h"

#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
#include <sound/soc-acpi-intel-match.h>
#endif

/* platform specific devices */
#include "shim.h"

#define IS_CFL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa348)
#define IS_CNL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9dc8)

/*
 * Debug
 */

struct hda_dsp_msg_code {
	u32 code;
	const char *msg;
};

static const struct hda_dsp_msg_code hda_dsp_rom_msg[] = {
	{HDA_DSP_ROM_FW_MANIFEST_LOADED, "status: manifest loaded"},
	{HDA_DSP_ROM_FW_FW_LOADED, "status: fw loaded"},
	{HDA_DSP_ROM_FW_ENTERED, "status: fw entered"},
	{HDA_DSP_ROM_CSE_ERROR, "error: cse error"},
	{HDA_DSP_ROM_CSE_WRONG_RESPONSE, "error: cse wrong response"},
	{HDA_DSP_ROM_IMR_TO_SMALL, "error: IMR too small"},
	{HDA_DSP_ROM_BASE_FW_NOT_FOUND, "error: base fw not found"},
	{HDA_DSP_ROM_CSE_VALIDATION_FAILED, "error: signature verification failed"},
	{HDA_DSP_ROM_IPC_FATAL_ERROR, "error: ipc fatal error"},
	{HDA_DSP_ROM_L2_CACHE_ERROR, "error: L2 cache error"},
	{HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL, "error: load offset too small"},
	{HDA_DSP_ROM_API_PTR_INVALID, "error: API ptr invalid"},
	{HDA_DSP_ROM_BASEFW_INCOMPAT, "error: base fw incompatible"},
	{HDA_DSP_ROM_UNHANDLED_INTERRUPT, "error: unhandled interrupt"},
	{HDA_DSP_ROM_MEMORY_HOLE_ECC, "error: ECC memory hole"},
	{HDA_DSP_ROM_KERNEL_EXCEPTION, "error: kernel exception"},
	{HDA_DSP_ROM_USER_EXCEPTION, "error: user exception"},
	{HDA_DSP_ROM_UNEXPECTED_RESET, "error: unexpected reset"},
	{HDA_DSP_ROM_NULL_FW_ENTRY,	"error: null FW entry point"},
};

static void hda_dsp_get_status_skl(struct snd_sof_dev *sdev)
{
	u32 status;
	int i;

	status = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
				  HDA_ADSP_FW_STATUS_SKL);

	for (i = 0; i < ARRAY_SIZE(hda_dsp_rom_msg); i++) {
		if (status == hda_dsp_rom_msg[i].code) {
			dev_err(sdev->dev, "%s - code %8.8x\n",
				hda_dsp_rom_msg[i].msg, status);
			return;
		}
	}

	/* not for us, must be generic sof message */
	dev_dbg(sdev->dev, "unknown ROM status value %8.8x\n", status);
}

static void hda_dsp_get_status(struct snd_sof_dev *sdev)
{
	u32 status;
	int i;

	status = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
				  HDA_DSP_SRAM_REG_ROM_STATUS);

	for (i = 0; i < ARRAY_SIZE(hda_dsp_rom_msg); i++) {
		if (status == hda_dsp_rom_msg[i].code) {
			dev_err(sdev->dev, "%s - code %8.8x\n",
				hda_dsp_rom_msg[i].msg, status);
			return;
		}
	}

	/* not for us, must be generic sof message */
	dev_dbg(sdev->dev, "unknown ROM status value %8.8x\n", status);
}

static void hda_dsp_get_registers(struct snd_sof_dev *sdev,
				  struct sof_ipc_dsp_oops_xtensa *xoops,
				  struct sof_ipc_panic_info *panic_info,
				  u32 *stack, size_t stack_words)
{
	u32 offset = sdev->dsp_oops_offset;

	/* first read registers */
	sof_mailbox_read(sdev, offset, xoops, sizeof(*xoops));

	/* note: variable AR register array is not read */

	/* then get panic info */
	offset += xoops->arch_hdr.totalsize;
	sof_block_read(sdev, sdev->mmio_bar, offset,
		       panic_info, sizeof(*panic_info));

	/* then get the stack */
	offset += sizeof(*panic_info);
	sof_block_read(sdev, sdev->mmio_bar, offset, stack,
		       stack_words * sizeof(u32));
}

void hda_dsp_dump_skl(struct snd_sof_dev *sdev, u32 flags)
{
	struct sof_ipc_dsp_oops_xtensa xoops;
	struct sof_ipc_panic_info panic_info;
	u32 stack[HDA_DSP_STACK_DUMP_SIZE];
	u32 status, panic;

	/* try APL specific status message types first */
	hda_dsp_get_status_skl(sdev);

	/* now try generic SOF status messages */
	status = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
				  HDA_ADSP_ERROR_CODE_SKL);

	/*TODO: Check: there is no define in spec, but it is used in the code*/
	panic = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
				 HDA_ADSP_ERROR_CODE_SKL + 0x4);

	if (sdev->boot_complete) {
		hda_dsp_get_registers(sdev, &xoops, &panic_info, stack,
				      HDA_DSP_STACK_DUMP_SIZE);
		snd_sof_get_status(sdev, status, panic, &xoops, &panic_info,
				   stack, HDA_DSP_STACK_DUMP_SIZE);
	} else {
		dev_err(sdev->dev, "error: status = 0x%8.8x panic = 0x%8.8x\n",
			status, panic);
		hda_dsp_get_status_skl(sdev);
	}
}

void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags)
{
	struct sof_ipc_dsp_oops_xtensa xoops;
	struct sof_ipc_panic_info panic_info;
	u32 stack[HDA_DSP_STACK_DUMP_SIZE];
	u32 status, panic;

	/* try APL specific status message types first */
	hda_dsp_get_status(sdev);

	/* now try generic SOF status messages */
	status = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
				  HDA_DSP_SRAM_REG_FW_STATUS);
	panic = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_SRAM_REG_FW_TRACEP);

	if (sdev->boot_complete) {
		hda_dsp_get_registers(sdev, &xoops, &panic_info, stack,
				      HDA_DSP_STACK_DUMP_SIZE);
		snd_sof_get_status(sdev, status, panic, &xoops, &panic_info,
				   stack, HDA_DSP_STACK_DUMP_SIZE);
	} else {
		dev_err(sdev->dev, "error: status = 0x%8.8x panic = 0x%8.8x\n",
			status, panic);
		hda_dsp_get_status(sdev);
	}
}

void hda_ipc_irq_dump(struct snd_sof_dev *sdev)
{
	struct hdac_bus *bus = sof_to_bus(sdev);
	u32 adspis;
	u32 intsts;
	u32 intctl;
	u32 ppsts;
	u8 rirbsts;

	/* read key IRQ stats and config registers */
	adspis = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIS);
	intsts = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS);
	intctl = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL);
	ppsts = snd_sof_dsp_read(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPSTS);
	rirbsts = snd_hdac_chip_readb(bus, RIRBSTS);

	dev_err(sdev->dev,
		"error: hda irq intsts 0x%8.8x intlctl 0x%8.8x rirb %2.2x\n",
		intsts, intctl, rirbsts);
	dev_err(sdev->dev,
		"error: dsp irq ppsts 0x%8.8x adspis 0x%8.8x\n",
		ppsts, adspis);
}

void hda_ipc_dump(struct snd_sof_dev *sdev)
{
	u32 hipcie;
	u32 hipct;
	u32 hipcctl;

	hda_ipc_irq_dump(sdev);

	/* read IPC status */
	hipcie = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCIE);
	hipct = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCT);
	hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCCTL);

	/* dump the IPC regs */
	/* TODO: parse the raw msg */
	dev_err(sdev->dev,
		"error: host status 0x%8.8x dsp status 0x%8.8x mask 0x%8.8x\n",
		hipcie, hipct, hipcctl);
}

static int hda_init(struct snd_sof_dev *sdev)
{
	struct hda_bus *hbus;
	struct hdac_bus *bus;
	struct pci_dev *pci = to_pci_dev(sdev->dev);
	int ret;

	hbus = sof_to_hbus(sdev);
	bus = sof_to_bus(sdev);

	/* HDA bus init */
	sof_hda_bus_init(bus, &pci->dev);

	/* Workaround for a communication error on CFL (bko#199007) and CNL */
	if (IS_CFL(pci) || IS_CNL(pci))
		bus->polling_mode = 1;

	bus->use_posbuf = 1;
	bus->bdl_pos_adj = 0;

	mutex_init(&hbus->prepare_mutex);
	hbus->pci = pci;
	hbus->mixer_assigned = -1;
	hbus->modelname = "sofbus";

	/* initialise hdac bus */
	bus->addr = pci_resource_start(pci, 0);
#if IS_ENABLED(CONFIG_PCI)
	bus->remap_addr = pci_ioremap_bar(pci, 0);
#endif
	if (!bus->remap_addr) {
		dev_err(bus->dev, "error: ioremap error\n");
		return -ENXIO;
	}

	/* HDA base */
	sdev->bar[HDA_DSP_HDA_BAR] = bus->remap_addr;

	/* get controller capabilities */
	ret = hda_dsp_ctrl_get_caps(sdev);
	if (ret < 0)
		dev_err(sdev->dev, "error: get caps error\n");

	return ret;
}

#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)

static const char *fixup_tplg_name(struct snd_sof_dev *sdev,
				   const char *sof_tplg_filename)
{
	const char *tplg_filename = NULL;
	char *filename;
	char *split_ext;

	filename = devm_kstrdup(sdev->dev, sof_tplg_filename, GFP_KERNEL);
	if (!filename)
		return NULL;

	/* this assumes a .tplg extension */
	split_ext = strsep(&filename, ".");
	if (split_ext) {
		tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL,
					       "%s-idisp.tplg", split_ext);
		if (!tplg_filename)
			return NULL;
	}
	return tplg_filename;
}

#endif

static int hda_init_caps(struct snd_sof_dev *sdev)
{
	struct hdac_bus *bus = sof_to_bus(sdev);
#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
	struct hdac_ext_link *hlink;
	struct snd_soc_acpi_mach_params *mach_params;
	struct snd_soc_acpi_mach *hda_mach;
	struct snd_sof_pdata *pdata = sdev->pdata;
	struct snd_soc_acpi_mach *mach;
	const char *tplg_filename;
	int codec_num = 0;
	int i;
#endif
	int ret = 0;

	device_disable_async_suspend(bus->dev);

	/* check if dsp is there */
	if (bus->ppcap)
		dev_dbg(sdev->dev, "PP capability, will probe DSP later.\n");

	ret = hda_dsp_ctrl_init_chip(sdev, true);
	if (ret < 0) {
		dev_err(bus->dev, "error: init chip failed with ret: %d\n",
			ret);
		return ret;
	}

#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
	if (bus->mlcap)
		snd_hdac_ext_bus_get_ml_capabilities(bus);

	/* init i915 and HDMI codecs */
	ret = hda_codec_i915_init(sdev);
	if (ret < 0) {
		dev_err(sdev->dev, "error: no HDMI audio devices found\n");
		return ret;
	}

	/* codec detection */
	if (!bus->codec_mask) {
		dev_info(bus->dev, "no hda codecs found!\n");
	} else {
		dev_info(bus->dev, "hda codecs found, mask %lx\n",
			 bus->codec_mask);

		for (i = 0; i < HDA_MAX_CODECS; i++) {
			if (bus->codec_mask & (1 << i))
				codec_num++;
		}

		/*
		 * If no machine driver is found, then:
		 *
		 * hda machine driver is used if :
		 * 1. there is one HDMI codec and one external HDAudio codec
		 * 2. only HDMI codec
		 */
		if (!pdata->machine && codec_num <= 2 &&
		    HDA_IDISP_CODEC(bus->codec_mask)) {
			hda_mach = snd_soc_acpi_intel_hda_machines;
			pdata->machine = hda_mach;

			/* topology: use the info from hda_machines */
			pdata->tplg_filename =
				hda_mach->sof_tplg_filename;

			/* firmware: pick the first in machine list */
			mach = pdata->desc->machines;
			pdata->fw_filename = mach->sof_fw_filename;

			dev_info(bus->dev, "using HDA machine driver %s now\n",
				 hda_mach->drv_name);

			/* fixup topology file for HDMI only platforms */
			if (codec_num == 1) {
				/* use local variable for readability */
				tplg_filename = pdata->tplg_filename;
				tplg_filename = fixup_tplg_name(sdev, tplg_filename);
				if (!tplg_filename) {
					hda_codec_i915_exit(sdev);
					return ret;
				}
				pdata->tplg_filename = tplg_filename;
			}
		}
	}

	/* used by hda machine driver to create dai links */
	if (pdata->machine) {
		mach_params = (struct snd_soc_acpi_mach_params *)
			&pdata->machine->mach_params;
		mach_params->codec_mask = bus->codec_mask;
		mach_params->platform = dev_name(sdev->dev);
	}

	/* create codec instances */
	hda_codec_probe_bus(sdev);

	hda_codec_i915_put(sdev);

	/*
	 * we are done probing so decrement link counts
	 */
	list_for_each_entry(hlink, &bus->hlink_list, list)
		snd_hdac_ext_bus_link_put(bus, hlink);
#endif
	return 0;
}

static const struct sof_intel_dsp_desc
	*get_chip_info(struct snd_sof_pdata *pdata)
{
	const struct sof_dev_desc *desc = pdata->desc;
	const struct sof_intel_dsp_desc *chip_info;

	chip_info = desc->chip_info;

	return chip_info;
}

int hda_dsp_probe(struct snd_sof_dev *sdev)
{
	struct pci_dev *pci = to_pci_dev(sdev->dev);
	struct sof_intel_hda_dev *hdev;
	struct hdac_bus *bus;
	const struct sof_intel_dsp_desc *chip;
	int ret = 0;

	/*
	 * detect DSP by checking class/subclass/prog-id information
	 * class=04 subclass 03 prog-if 00: no DSP, legacy driver is required
	 * class=04 subclass 01 prog-if 00: DSP is present
	 *   (and may be required e.g. for DMIC or SSP support)
	 * class=04 subclass 03 prog-if 80: either of DSP or legacy mode works
	 */
	if (pci->class == 0x040300) {
		dev_err(sdev->dev, "error: the DSP is not enabled on this platform, aborting probe\n");
		return -ENODEV;
	} else if (pci->class != 0x040100 && pci->class != 0x040380) {
		dev_err(sdev->dev, "error: unknown PCI class/subclass/prog-if 0x%06x found, aborting probe\n", pci->class);
		return -ENODEV;
	}
	dev_info(sdev->dev, "DSP detected with PCI class/subclass/prog-if 0x%06x\n", pci->class);

	chip = get_chip_info(sdev->pdata);
	if (!chip) {
		dev_err(sdev->dev, "error: no such device supported, chip id:%x\n",
			pci->device);
		ret = -EIO;
		goto err;
	}

	hdev = devm_kzalloc(sdev->dev, sizeof(*hdev), GFP_KERNEL);
	if (!hdev)
		return -ENOMEM;
	sdev->pdata->hw_pdata = hdev;
	hdev->desc = chip;

	hdev->dmic_dev = platform_device_register_data(sdev->dev, "dmic-codec",
						       PLATFORM_DEVID_NONE,
						       NULL, 0);
	if (IS_ERR(hdev->dmic_dev)) {
		dev_err(sdev->dev, "error: failed to create DMIC device\n");
		return PTR_ERR(hdev->dmic_dev);
	}

	/*
	 * use position update IPC if either it is forced
	 * or we don't have other choice
	 */
#if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_FORCE_IPC_POSITION)
	hdev->no_ipc_position = 0;
#else
	hdev->no_ipc_position = sof_ops(sdev)->pcm_pointer ? 1 : 0;
#endif

	/* set up HDA base */
	bus = sof_to_bus(sdev);
	ret = hda_init(sdev);
	if (ret < 0)
		goto hdac_bus_unmap;

	/* DSP base */
#if IS_ENABLED(CONFIG_PCI)
	sdev->bar[HDA_DSP_BAR] = pci_ioremap_bar(pci, HDA_DSP_BAR);
#endif
	if (!sdev->bar[HDA_DSP_BAR]) {
		dev_err(sdev->dev, "error: ioremap error\n");
		ret = -ENXIO;
		goto hdac_bus_unmap;
	}

	sdev->mmio_bar = HDA_DSP_BAR;
	sdev->mailbox_bar = HDA_DSP_BAR;

	/* allow 64bit DMA address if supported by H/W */
	if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(64))) {
		dev_dbg(sdev->dev, "DMA mask is 64 bit\n");
		dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(64));
	} else {
		dev_dbg(sdev->dev, "DMA mask is 32 bit\n");
		dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
		dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
	}

	/* init streams */
	ret = hda_dsp_stream_init(sdev);
	if (ret < 0) {
		dev_err(sdev->dev, "error: failed to init streams\n");
		/*
		 * not all errors are due to memory issues, but trying
		 * to free everything does not harm
		 */
		goto free_streams;
	}

	/*
	 * register our IRQ
	 * let's try to enable msi firstly
	 * if it fails, use legacy interrupt mode
	 * TODO: support interrupt mode selection with kernel parameter
	 *       support msi multiple vectors
	 */
	ret = pci_alloc_irq_vectors(pci, 1, 1, PCI_IRQ_MSI);
	if (ret < 0) {
		dev_info(sdev->dev, "use legacy interrupt mode\n");
		/*
		 * in IO-APIC mode, hda->irq and ipc_irq are using the same
		 * irq number of pci->irq
		 */
		hdev->irq = pci->irq;
		sdev->ipc_irq = pci->irq;
		sdev->msi_enabled = 0;
	} else {
		dev_info(sdev->dev, "use msi interrupt mode\n");
		hdev->irq = pci_irq_vector(pci, 0);
		/* ipc irq number is the same of hda irq */
		sdev->ipc_irq = hdev->irq;
		sdev->msi_enabled = 1;
	}

	dev_dbg(sdev->dev, "using HDA IRQ %d\n", hdev->irq);
	ret = request_threaded_irq(hdev->irq, hda_dsp_stream_interrupt,
				   hda_dsp_stream_threaded_handler,
				   IRQF_SHARED, "AudioHDA", bus);
	if (ret < 0) {
		dev_err(sdev->dev, "error: failed to register HDA IRQ %d\n",
			hdev->irq);
		goto free_irq_vector;
	}

	dev_dbg(sdev->dev, "using IPC IRQ %d\n", sdev->ipc_irq);
	ret = request_threaded_irq(sdev->ipc_irq, hda_dsp_ipc_irq_handler,
				   sof_ops(sdev)->irq_thread, IRQF_SHARED,
				   "AudioDSP", sdev);
	if (ret < 0) {
		dev_err(sdev->dev, "error: failed to register IPC IRQ %d\n",
			sdev->ipc_irq);
		goto free_hda_irq;
	}

	pci_set_master(pci);
	synchronize_irq(pci->irq);

	/*
	 * clear TCSEL to clear playback on some HD Audio
	 * codecs. PCI TCSEL is defined in the Intel manuals.
	 */
	snd_sof_pci_update_bits(sdev, PCI_TCSEL, 0x07, 0);

	/* init HDA capabilities */
	ret = hda_init_caps(sdev);
	if (ret < 0)
		goto free_ipc_irq;

	/* enable ppcap interrupt */
	hda_dsp_ctrl_ppcap_enable(sdev, true);
	hda_dsp_ctrl_ppcap_int_enable(sdev, true);

	/* initialize waitq for code loading */
	init_waitqueue_head(&sdev->waitq);

	/* set default mailbox offset for FW ready message */
	sdev->dsp_box.offset = HDA_DSP_MBOX_UPLINK_OFFSET;

	return 0;

free_ipc_irq:
	free_irq(sdev->ipc_irq, sdev);
free_hda_irq:
	free_irq(hdev->irq, bus);
free_irq_vector:
	if (sdev->msi_enabled)
		pci_free_irq_vectors(pci);
free_streams:
	hda_dsp_stream_free(sdev);
/* dsp_unmap: not currently used */
	iounmap(sdev->bar[HDA_DSP_BAR]);
hdac_bus_unmap:
	iounmap(bus->remap_addr);
err:
	return ret;
}

int hda_dsp_remove(struct snd_sof_dev *sdev)
{
	struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
	struct hdac_bus *bus = sof_to_bus(sdev);
	struct pci_dev *pci = to_pci_dev(sdev->dev);
	const struct sof_intel_dsp_desc *chip = hda->desc;

#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
	/* codec removal, invoke bus_device_remove */
	snd_hdac_ext_bus_device_remove(bus);
#endif

	if (!IS_ERR_OR_NULL(hda->dmic_dev))
		platform_device_unregister(hda->dmic_dev);

	/* disable DSP IRQ */
	snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
				SOF_HDA_PPCTL_PIE, 0);

	/* disable CIE and GIE interrupts */
	snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
				SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_GLOBAL_EN, 0);

	/* disable cores */
	if (chip)
		hda_dsp_core_reset_power_down(sdev, chip->cores_mask);

	/* disable DSP */
	snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
				SOF_HDA_PPCTL_GPROCEN, 0);

	free_irq(sdev->ipc_irq, sdev);
	free_irq(hda->irq, bus);
	if (sdev->msi_enabled)
		pci_free_irq_vectors(pci);

	hda_dsp_stream_free(sdev);
#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
	snd_hdac_link_free_all(bus);
#endif

	iounmap(sdev->bar[HDA_DSP_BAR]);
	iounmap(bus->remap_addr);

#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
	snd_hdac_ext_bus_exit(bus);
#endif
	hda_codec_i915_exit(sdev);

	return 0;
}

MODULE_LICENSE("Dual BSD/GPL");
Commit	Line	Data
dd96daca LG	1	// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
	2	//
	3	// This file is provided under a dual BSD/GPLv2 license. When using or
	4	// redistributing this file, you may do so under either license.
	5	//
	6	// Copyright(c) 2018 Intel Corporation. All rights reserved.
	7	//
	8	// Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
	9	// Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
	10	// Rander Wang <rander.wang@intel.com>
	11	// Keyon Jie <yang.jie@linux.intel.com>
	12	//
	13
	14	/*
	15	* Hardware interface for generic Intel audio DSP HDA IP
	16	*/
	17
dd96daca	18	#include <sound/hdaudio_ext.h>
f1fd9d0e KV	19	#include <sound/hda_register.h>
f1fd9d0e KV	20
dd96daca	21	#include <linux/module.h>
dd96daca LG	22	#include <sound/sof.h>
	23	#include <sound/sof/xtensa.h>
	24	#include "../ops.h"
	25	#include "hda.h"
dd96daca LG	26
	27	#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
	28	#include <sound/soc-acpi-intel-match.h>
	29	#endif
	30
	31	/* platform specific devices */
	32	#include "shim.h"
	33
64ca9d9f BL	34	#define IS_CFL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa348)
	35	#define IS_CNL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9dc8)
	36
dd96daca LG	37	/*
	38	* Debug
	39	*/
	40
	41	struct hda_dsp_msg_code {
	42	u32 code;
	43	const char *msg;
	44	};
	45
	46	static const struct hda_dsp_msg_code hda_dsp_rom_msg[] = {
	47	{HDA_DSP_ROM_FW_MANIFEST_LOADED, "status: manifest loaded"},
	48	{HDA_DSP_ROM_FW_FW_LOADED, "status: fw loaded"},
	49	{HDA_DSP_ROM_FW_ENTERED, "status: fw entered"},
	50	{HDA_DSP_ROM_CSE_ERROR, "error: cse error"},
	51	{HDA_DSP_ROM_CSE_WRONG_RESPONSE, "error: cse wrong response"},
	52	{HDA_DSP_ROM_IMR_TO_SMALL, "error: IMR too small"},
	53	{HDA_DSP_ROM_BASE_FW_NOT_FOUND, "error: base fw not found"},
	54	{HDA_DSP_ROM_CSE_VALIDATION_FAILED, "error: signature verification failed"},
	55	{HDA_DSP_ROM_IPC_FATAL_ERROR, "error: ipc fatal error"},
	56	{HDA_DSP_ROM_L2_CACHE_ERROR, "error: L2 cache error"},
	57	{HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL, "error: load offset too small"},
	58	{HDA_DSP_ROM_API_PTR_INVALID, "error: API ptr invalid"},
07f80454	59	{HDA_DSP_ROM_BASEFW_INCOMPAT, "error: base fw incompatible"},
dd96daca LG	60	{HDA_DSP_ROM_UNHANDLED_INTERRUPT, "error: unhandled interrupt"},
	61	{HDA_DSP_ROM_MEMORY_HOLE_ECC, "error: ECC memory hole"},
	62	{HDA_DSP_ROM_KERNEL_EXCEPTION, "error: kernel exception"},
	63	{HDA_DSP_ROM_USER_EXCEPTION, "error: user exception"},
	64	{HDA_DSP_ROM_UNEXPECTED_RESET, "error: unexpected reset"},
	65	{HDA_DSP_ROM_NULL_FW_ENTRY, "error: null FW entry point"},
	66	};
	67
	68	static void hda_dsp_get_status_skl(struct snd_sof_dev *sdev)
	69	{
	70	u32 status;
	71	int i;
	72
	73	status = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
	74	HDA_ADSP_FW_STATUS_SKL);
	75
	76	for (i = 0; i < ARRAY_SIZE(hda_dsp_rom_msg); i++) {
	77	if (status == hda_dsp_rom_msg[i].code) {
	78	dev_err(sdev->dev, "%s - code %8.8x\n",
	79	hda_dsp_rom_msg[i].msg, status);
	80	return;
	81	}
	82	}
	83
	84	/* not for us, must be generic sof message */
	85	dev_dbg(sdev->dev, "unknown ROM status value %8.8x\n", status);
	86	}
	87
	88	static void hda_dsp_get_status(struct snd_sof_dev *sdev)
	89	{
	90	u32 status;
	91	int i;
	92
	93	status = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
	94	HDA_DSP_SRAM_REG_ROM_STATUS);
	95
	96	for (i = 0; i < ARRAY_SIZE(hda_dsp_rom_msg); i++) {
	97	if (status == hda_dsp_rom_msg[i].code) {
	98	dev_err(sdev->dev, "%s - code %8.8x\n",
	99	hda_dsp_rom_msg[i].msg, status);
	100	return;
	101	}
	102	}
	103
	104	/* not for us, must be generic sof message */
	105	dev_dbg(sdev->dev, "unknown ROM status value %8.8x\n", status);
	106	}
	107
	108	static void hda_dsp_get_registers(struct snd_sof_dev *sdev,
	109	struct sof_ipc_dsp_oops_xtensa *xoops,
	110	struct sof_ipc_panic_info *panic_info,
	111	u32 *stack, size_t stack_words)
	112	{
14104eb6 KV	113	u32 offset = sdev->dsp_oops_offset;
14104eb6 KV	114
dd96daca	115	/* first read registers */
14104eb6 KV	116	sof_mailbox_read(sdev, offset, xoops, sizeof(*xoops));
	117
	118	/* note: variable AR register array is not read */
dd96daca LG	119
dd96daca LG	120	/* then get panic info */
14104eb6 KV	121	offset += xoops->arch_hdr.totalsize;
	122	sof_block_read(sdev, sdev->mmio_bar, offset,
	123	panic_info, sizeof(*panic_info));
dd96daca LG	124
dd96daca LG	125	/* then get the stack */
14104eb6 KV	126	offset += sizeof(*panic_info);
14104eb6 KV	127	sof_block_read(sdev, sdev->mmio_bar, offset, stack,
dd96daca LG	128	stack_words * sizeof(u32));
	129	}
	130
	131	void hda_dsp_dump_skl(struct snd_sof_dev *sdev, u32 flags)
	132	{
	133	struct sof_ipc_dsp_oops_xtensa xoops;
	134	struct sof_ipc_panic_info panic_info;
	135	u32 stack[HDA_DSP_STACK_DUMP_SIZE];
	136	u32 status, panic;
	137
	138	/* try APL specific status message types first */
	139	hda_dsp_get_status_skl(sdev);
	140
	141	/* now try generic SOF status messages */
	142	status = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
	143	HDA_ADSP_ERROR_CODE_SKL);
	144
	145	/TODO: Check: there is no define in spec, but it is used in the code/
	146	panic = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
	147	HDA_ADSP_ERROR_CODE_SKL + 0x4);
	148
	149	if (sdev->boot_complete) {
	150	hda_dsp_get_registers(sdev, &xoops, &panic_info, stack,
	151	HDA_DSP_STACK_DUMP_SIZE);
	152	snd_sof_get_status(sdev, status, panic, &xoops, &panic_info,
	153	stack, HDA_DSP_STACK_DUMP_SIZE);
	154	} else {
	155	dev_err(sdev->dev, "error: status = 0x%8.8x panic = 0x%8.8x\n",
	156	status, panic);
	157	hda_dsp_get_status_skl(sdev);
	158	}
	159	}
	160
	161	void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags)
	162	{
	163	struct sof_ipc_dsp_oops_xtensa xoops;
	164	struct sof_ipc_panic_info panic_info;
	165	u32 stack[HDA_DSP_STACK_DUMP_SIZE];
	166	u32 status, panic;
	167
	168	/* try APL specific status message types first */
	169	hda_dsp_get_status(sdev);
	170
	171	/* now try generic SOF status messages */
	172	status = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
	173	HDA_DSP_SRAM_REG_FW_STATUS);
	174	panic = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_SRAM_REG_FW_TRACEP);
	175
	176	if (sdev->boot_complete) {
	177	hda_dsp_get_registers(sdev, &xoops, &panic_info, stack,
	178	HDA_DSP_STACK_DUMP_SIZE);
	179	snd_sof_get_status(sdev, status, panic, &xoops, &panic_info,
	180	stack, HDA_DSP_STACK_DUMP_SIZE);
	181	} else {
	182	dev_err(sdev->dev, "error: status = 0x%8.8x panic = 0x%8.8x\n",
	183	status, panic);
	184	hda_dsp_get_status(sdev);
	185	}
	186	}
	187
f1fd9d0e KV	188	void hda_ipc_irq_dump(struct snd_sof_dev *sdev)
	189	{
	190	struct hdac_bus *bus = sof_to_bus(sdev);
	191	u32 adspis;
	192	u32 intsts;
	193	u32 intctl;
	194	u32 ppsts;
	195	u8 rirbsts;
	196
	197	/* read key IRQ stats and config registers */
	198	adspis = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIS);
	199	intsts = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS);
	200	intctl = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL);
	201	ppsts = snd_sof_dsp_read(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPSTS);
	202	rirbsts = snd_hdac_chip_readb(bus, RIRBSTS);
	203
	204	dev_err(sdev->dev,
	205	"error: hda irq intsts 0x%8.8x intlctl 0x%8.8x rirb %2.2x\n",
	206	intsts, intctl, rirbsts);
	207	dev_err(sdev->dev,
	208	"error: dsp irq ppsts 0x%8.8x adspis 0x%8.8x\n",
	209	ppsts, adspis);
	210	}
	211
f3da49f0 PX	212	void hda_ipc_dump(struct snd_sof_dev *sdev)
	213	{
	214	u32 hipcie;
	215	u32 hipct;
	216	u32 hipcctl;
	217
f1fd9d0e KV	218	hda_ipc_irq_dump(sdev);
f1fd9d0e KV	219
f3da49f0 PX	220	/* read IPC status */
	221	hipcie = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCIE);
	222	hipct = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCT);
	223	hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCCTL);
	224
	225	/* dump the IPC regs */
	226	/* TODO: parse the raw msg */
	227	dev_err(sdev->dev,
	228	"error: host status 0x%8.8x dsp status 0x%8.8x mask 0x%8.8x\n",
	229	hipcie, hipct, hipcctl);
	230	}
	231
dd96daca LG	232	static int hda_init(struct snd_sof_dev *sdev)
	233	{
	234	struct hda_bus *hbus;
	235	struct hdac_bus *bus;
dd96daca LG	236	struct pci_dev *pci = to_pci_dev(sdev->dev);
	237	int ret;
	238
	239	hbus = sof_to_hbus(sdev);
	240	bus = sof_to_bus(sdev);
	241
	242	/* HDA bus init */
d4ff1b39	243	sof_hda_bus_init(bus, &pci->dev);
64ca9d9f BL	244
	245	/* Workaround for a communication error on CFL (bko#199007) and CNL */
	246	if (IS_CFL(pci) \|\| IS_CNL(pci))
	247	bus->polling_mode = 1;
	248
dd96daca LG	249	bus->use_posbuf = 1;
	250	bus->bdl_pos_adj = 0;
	251
	252	mutex_init(&hbus->prepare_mutex);
	253	hbus->pci = pci;
	254	hbus->mixer_assigned = -1;
	255	hbus->modelname = "sofbus";
	256
	257	/* initialise hdac bus */
	258	bus->addr = pci_resource_start(pci, 0);
ad169f9f	259	#if IS_ENABLED(CONFIG_PCI)
dd96daca	260	bus->remap_addr = pci_ioremap_bar(pci, 0);
ad169f9f	261	#endif
dd96daca LG	262	if (!bus->remap_addr) {
	263	dev_err(bus->dev, "error: ioremap error\n");
	264	return -ENXIO;
	265	}
	266
	267	/* HDA base */
	268	sdev->bar[HDA_DSP_HDA_BAR] = bus->remap_addr;
	269
	270	/* get controller capabilities */
	271	ret = hda_dsp_ctrl_get_caps(sdev);
	272	if (ret < 0)
	273	dev_err(sdev->dev, "error: get caps error\n");
	274
	275	return ret;
	276	}
	277
	278	#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
	279
	280	static const char fixup_tplg_name(struct snd_sof_dev sdev,
	281	const char *sof_tplg_filename)
	282	{
	283	const char *tplg_filename = NULL;
	284	char *filename;
	285	char *split_ext;
	286
	287	filename = devm_kstrdup(sdev->dev, sof_tplg_filename, GFP_KERNEL);
	288	if (!filename)
	289	return NULL;
	290
	291	/* this assumes a .tplg extension */
	292	split_ext = strsep(&filename, ".");
	293	if (split_ext) {
	294	tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL,
	295	"%s-idisp.tplg", split_ext);
	296	if (!tplg_filename)
	297	return NULL;
	298	}
	299	return tplg_filename;
	300	}
	301
be1b577d ZY	302	#endif
be1b577d ZY	303
dd96daca LG	304	static int hda_init_caps(struct snd_sof_dev *sdev)
	305	{
	306	struct hdac_bus *bus = sof_to_bus(sdev);
be1b577d	307	#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
dd96daca LG	308	struct hdac_ext_link *hlink;
	309	struct snd_soc_acpi_mach_params *mach_params;
	310	struct snd_soc_acpi_mach *hda_mach;
	311	struct snd_sof_pdata *pdata = sdev->pdata;
	312	struct snd_soc_acpi_mach *mach;
	313	const char *tplg_filename;
	314	int codec_num = 0;
dd96daca	315	int i;
be1b577d ZY	316	#endif
be1b577d ZY	317	int ret = 0;
dd96daca LG	318
	319	device_disable_async_suspend(bus->dev);
	320
	321	/* check if dsp is there */
	322	if (bus->ppcap)
	323	dev_dbg(sdev->dev, "PP capability, will probe DSP later.\n");
	324
be1b577d ZY	325	ret = hda_dsp_ctrl_init_chip(sdev, true);
	326	if (ret < 0) {
	327	dev_err(bus->dev, "error: init chip failed with ret: %d\n",
	328	ret);
	329	return ret;
	330	}
	331
	332	#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
dd96daca LG	333	if (bus->mlcap)
	334	snd_hdac_ext_bus_get_ml_capabilities(bus);
	335
	336	/* init i915 and HDMI codecs */
	337	ret = hda_codec_i915_init(sdev);
	338	if (ret < 0) {
	339	dev_err(sdev->dev, "error: no HDMI audio devices found\n");
	340	return ret;
	341	}
	342
dd96daca LG	343	/* codec detection */
	344	if (!bus->codec_mask) {
	345	dev_info(bus->dev, "no hda codecs found!\n");
	346	} else {
	347	dev_info(bus->dev, "hda codecs found, mask %lx\n",
	348	bus->codec_mask);
	349
	350	for (i = 0; i < HDA_MAX_CODECS; i++) {
	351	if (bus->codec_mask & (1 << i))
	352	codec_num++;
	353	}
	354
	355	/*
	356	* If no machine driver is found, then:
	357	*
	358	* hda machine driver is used if :
	359	* 1. there is one HDMI codec and one external HDAudio codec
	360	* 2. only HDMI codec
	361	*/
	362	if (!pdata->machine && codec_num <= 2 &&
	363	HDA_IDISP_CODEC(bus->codec_mask)) {
	364	hda_mach = snd_soc_acpi_intel_hda_machines;
	365	pdata->machine = hda_mach;
	366
	367	/* topology: use the info from hda_machines */
	368	pdata->tplg_filename =
	369	hda_mach->sof_tplg_filename;
	370
	371	/* firmware: pick the first in machine list */
	372	mach = pdata->desc->machines;
	373	pdata->fw_filename = mach->sof_fw_filename;
	374
	375	dev_info(bus->dev, "using HDA machine driver %s now\n",
	376	hda_mach->drv_name);
	377
	378	/* fixup topology file for HDMI only platforms */
	379	if (codec_num == 1) {
	380	/* use local variable for readability */
	381	tplg_filename = pdata->tplg_filename;
	382	tplg_filename = fixup_tplg_name(sdev, tplg_filename);
be1b577d ZY	383	if (!tplg_filename) {
	384	hda_codec_i915_exit(sdev);
	385	return ret;
	386	}
dd96daca LG	387	pdata->tplg_filename = tplg_filename;
	388	}
	389	}
	390	}
	391
	392	/* used by hda machine driver to create dai links */
	393	if (pdata->machine) {
	394	mach_params = (struct snd_soc_acpi_mach_params *)
	395	&pdata->machine->mach_params;
	396	mach_params->codec_mask = bus->codec_mask;
	397	mach_params->platform = dev_name(sdev->dev);
	398	}
	399
	400	/* create codec instances */
	401	hda_codec_probe_bus(sdev);
	402
	403	hda_codec_i915_put(sdev);
	404
	405	/*
	406	* we are done probing so decrement link counts
	407	*/
	408	list_for_each_entry(hlink, &bus->hlink_list, list)
	409	snd_hdac_ext_bus_link_put(bus, hlink);
be1b577d	410	#endif
dd96daca LG	411	return 0;
	412	}
	413
dd96daca LG	414	static const struct sof_intel_dsp_desc
	415	get_chip_info(struct snd_sof_pdata pdata)
	416	{
	417	const struct sof_dev_desc *desc = pdata->desc;
	418	const struct sof_intel_dsp_desc *chip_info;
	419
	420	chip_info = desc->chip_info;
	421
	422	return chip_info;
	423	}
	424
	425	int hda_dsp_probe(struct snd_sof_dev *sdev)
	426	{
	427	struct pci_dev *pci = to_pci_dev(sdev->dev);
	428	struct sof_intel_hda_dev *hdev;
	429	struct hdac_bus *bus;
dd96daca	430	const struct sof_intel_dsp_desc *chip;
be1b577d	431	int ret = 0;
dd96daca LG	432
	433	/*
	434	* detect DSP by checking class/subclass/prog-id information
	435	* class=04 subclass 03 prog-if 00: no DSP, legacy driver is required
	436	* class=04 subclass 01 prog-if 00: DSP is present
	437	* (and may be required e.g. for DMIC or SSP support)
	438	* class=04 subclass 03 prog-if 80: either of DSP or legacy mode works
	439	*/
	440	if (pci->class == 0x040300) {
	441	dev_err(sdev->dev, "error: the DSP is not enabled on this platform, aborting probe\n");
	442	return -ENODEV;
	443	} else if (pci->class != 0x040100 && pci->class != 0x040380) {
	444	dev_err(sdev->dev, "error: unknown PCI class/subclass/prog-if 0x%06x found, aborting probe\n", pci->class);
	445	return -ENODEV;
	446	}
	447	dev_info(sdev->dev, "DSP detected with PCI class/subclass/prog-if 0x%06x\n", pci->class);
	448
	449	chip = get_chip_info(sdev->pdata);
	450	if (!chip) {
	451	dev_err(sdev->dev, "error: no such device supported, chip id:%x\n",
	452	pci->device);
	453	ret = -EIO;
	454	goto err;
	455	}
	456
	457	hdev = devm_kzalloc(sdev->dev, sizeof(*hdev), GFP_KERNEL);
	458	if (!hdev)
	459	return -ENOMEM;
	460	sdev->pdata->hw_pdata = hdev;
	461	hdev->desc = chip;
	462
	463	hdev->dmic_dev = platform_device_register_data(sdev->dev, "dmic-codec",
	464	PLATFORM_DEVID_NONE,
	465	NULL, 0);
	466	if (IS_ERR(hdev->dmic_dev)) {
	467	dev_err(sdev->dev, "error: failed to create DMIC device\n");
	468	return PTR_ERR(hdev->dmic_dev);
	469	}
	470
	471	/*
	472	* use position update IPC if either it is forced
	473	* or we don't have other choice
	474	*/
	475	#if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_FORCE_IPC_POSITION)
	476	hdev->no_ipc_position = 0;
	477	#else
	478	hdev->no_ipc_position = sof_ops(sdev)->pcm_pointer ? 1 : 0;
	479	#endif
	480
	481	/* set up HDA base */
	482	bus = sof_to_bus(sdev);
	483	ret = hda_init(sdev);
	484	if (ret < 0)
	485	goto hdac_bus_unmap;
	486
	487	/* DSP base */
ad169f9f	488	#if IS_ENABLED(CONFIG_PCI)
dd96daca	489	sdev->bar[HDA_DSP_BAR] = pci_ioremap_bar(pci, HDA_DSP_BAR);
ad169f9f	490	#endif
dd96daca LG	491	if (!sdev->bar[HDA_DSP_BAR]) {
	492	dev_err(sdev->dev, "error: ioremap error\n");
	493	ret = -ENXIO;
	494	goto hdac_bus_unmap;
	495	}
	496
	497	sdev->mmio_bar = HDA_DSP_BAR;
	498	sdev->mailbox_bar = HDA_DSP_BAR;
	499
	500	/* allow 64bit DMA address if supported by H/W */
	501	if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(64))) {
	502	dev_dbg(sdev->dev, "DMA mask is 64 bit\n");
	503	dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(64));
	504	} else {
	505	dev_dbg(sdev->dev, "DMA mask is 32 bit\n");
	506	dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
	507	dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
	508	}
	509
	510	/* init streams */
	511	ret = hda_dsp_stream_init(sdev);
	512	if (ret < 0) {
	513	dev_err(sdev->dev, "error: failed to init streams\n");
	514	/*
	515	* not all errors are due to memory issues, but trying
	516	* to free everything does not harm
	517	*/
	518	goto free_streams;
	519	}
	520
	521	/*
	522	* register our IRQ
	523	* let's try to enable msi firstly
	524	* if it fails, use legacy interrupt mode
	525	* TODO: support interrupt mode selection with kernel parameter
	526	* support msi multiple vectors
	527	*/
	528	ret = pci_alloc_irq_vectors(pci, 1, 1, PCI_IRQ_MSI);
	529	if (ret < 0) {
	530	dev_info(sdev->dev, "use legacy interrupt mode\n");
	531	/*
	532	* in IO-APIC mode, hda->irq and ipc_irq are using the same
	533	* irq number of pci->irq
	534	*/
	535	hdev->irq = pci->irq;
	536	sdev->ipc_irq = pci->irq;
	537	sdev->msi_enabled = 0;
	538	} else {
	539	dev_info(sdev->dev, "use msi interrupt mode\n");
	540	hdev->irq = pci_irq_vector(pci, 0);
	541	/* ipc irq number is the same of hda irq */
	542	sdev->ipc_irq = hdev->irq;
	543	sdev->msi_enabled = 1;
	544	}
	545
	546	dev_dbg(sdev->dev, "using HDA IRQ %d\n", hdev->irq);
	547	ret = request_threaded_irq(hdev->irq, hda_dsp_stream_interrupt,
	548	hda_dsp_stream_threaded_handler,
	549	IRQF_SHARED, "AudioHDA", bus);
	550	if (ret < 0) {
	551	dev_err(sdev->dev, "error: failed to register HDA IRQ %d\n",
	552	hdev->irq);
	553	goto free_irq_vector;
	554	}
555
556	dev_dbg(sdev->dev, "using IPC IRQ %d\n", sdev->ipc_irq);
557	ret = request_threaded_irq(sdev->ipc_irq, hda_dsp_ipc_irq_handler,
558	sof_ops(sdev)->irq_thread, IRQF_SHARED,
559	"AudioDSP", sdev);
560	if (ret < 0) {
561	dev_err(sdev->dev, "error: failed to register IPC IRQ %d\n",
562	sdev->ipc_irq);
563	goto free_hda_irq;
564	}
565
566	pci_set_master(pci);
567	synchronize_irq(pci->irq);
568
569	/*
570	* clear TCSEL to clear playback on some HD Audio
571	* codecs. PCI TCSEL is defined in the Intel manuals.
572	*/
573	snd_sof_pci_update_bits(sdev, PCI_TCSEL, 0x07, 0);
574
575	/* init HDA capabilities */
576	ret = hda_init_caps(sdev);
577	if (ret < 0)
578	goto free_ipc_irq;
579
1f5253b0 ZY	580	/* enable ppcap interrupt */
	581	hda_dsp_ctrl_ppcap_enable(sdev, true);
	582	hda_dsp_ctrl_ppcap_int_enable(sdev, true);
dd96daca LG	583
	584	/* initialize waitq for code loading */
	585	init_waitqueue_head(&sdev->waitq);
	586
	587	/* set default mailbox offset for FW ready message */
	588	sdev->dsp_box.offset = HDA_DSP_MBOX_UPLINK_OFFSET;
	589
	590	return 0;
	591
	592	free_ipc_irq:
	593	free_irq(sdev->ipc_irq, sdev);
	594	free_hda_irq:
	595	free_irq(hdev->irq, bus);
	596	free_irq_vector:
	597	if (sdev->msi_enabled)
	598	pci_free_irq_vectors(pci);
	599	free_streams:
	600	hda_dsp_stream_free(sdev);
	601	/* dsp_unmap: not currently used */
	602	iounmap(sdev->bar[HDA_DSP_BAR]);
	603	hdac_bus_unmap:
	604	iounmap(bus->remap_addr);
	605	err:
	606	return ret;
	607	}
	608
	609	int hda_dsp_remove(struct snd_sof_dev *sdev)
	610	{
	611	struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
	612	struct hdac_bus *bus = sof_to_bus(sdev);
	613	struct pci_dev *pci = to_pci_dev(sdev->dev);
	614	const struct sof_intel_dsp_desc *chip = hda->desc;
	615
	616	#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
	617	/* codec removal, invoke bus_device_remove */
	618	snd_hdac_ext_bus_device_remove(bus);
	619	#endif
	620
	621	if (!IS_ERR_OR_NULL(hda->dmic_dev))
	622	platform_device_unregister(hda->dmic_dev);
	623
	624	/* disable DSP IRQ */
	625	snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
	626	SOF_HDA_PPCTL_PIE, 0);
	627
	628	/* disable CIE and GIE interrupts */
	629	snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
	630	SOF_HDA_INT_CTRL_EN \| SOF_HDA_INT_GLOBAL_EN, 0);
	631
	632	/* disable cores */
	633	if (chip)
	634	hda_dsp_core_reset_power_down(sdev, chip->cores_mask);
	635
	636	/* disable DSP */
	637	snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
	638	SOF_HDA_PPCTL_GPROCEN, 0);
	639
	640	free_irq(sdev->ipc_irq, sdev);
	641	free_irq(hda->irq, bus);
	642	if (sdev->msi_enabled)
	643	pci_free_irq_vectors(pci);
	644
	645	hda_dsp_stream_free(sdev);
	646	#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
647	snd_hdac_link_free_all(bus);
648	#endif
649
650	iounmap(sdev->bar[HDA_DSP_BAR]);
651	iounmap(bus->remap_addr);
652
653	#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
654	snd_hdac_ext_bus_exit(bus);
655	#endif
656	hda_codec_i915_exit(sdev);
657
658	return 0;
659	}
660
661	MODULE_LICENSE("Dual BSD/GPL");