[linux-2.6-block.git] / sound / soc / samsung / s3c24xx-i2s.c

/*
 * s3c24xx-i2s.c  --  ALSA Soc Audio Layer
 *
 * (c) 2006 Wolfson Microelectronics PLC.
 * Graeme Gregory graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
 *
 * Copyright 2004-2005 Simtec Electronics
 *	http://armlinux.simtec.co.uk/
 *	Ben Dooks <ben@simtec.co.uk>
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 */

#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/module.h>

#include <sound/soc.h>
#include <sound/pcm_params.h>

#include <mach/dma.h>
#include <mach/gpio-samsung.h>
#include <plat/gpio-cfg.h>
#include "regs-iis.h"

#include "dma.h"
#include "s3c24xx-i2s.h"

static struct s3c_dma_client s3c24xx_dma_client_out = {
	.name = "I2S PCM Stereo out"
};

static struct s3c_dma_client s3c24xx_dma_client_in = {
	.name = "I2S PCM Stereo in"
};

static struct s3c_dma_params s3c24xx_i2s_pcm_stereo_out = {
	.client		= &s3c24xx_dma_client_out,
	.channel	= DMACH_I2S_OUT,
	.dma_addr	= S3C2410_PA_IIS + S3C2410_IISFIFO,
	.dma_size	= 2,
};

static struct s3c_dma_params s3c24xx_i2s_pcm_stereo_in = {
	.client		= &s3c24xx_dma_client_in,
	.channel	= DMACH_I2S_IN,
	.dma_addr	= S3C2410_PA_IIS + S3C2410_IISFIFO,
	.dma_size	= 2,
};

struct s3c24xx_i2s_info {
	void __iomem	*regs;
	struct clk	*iis_clk;
	u32		iiscon;
	u32		iismod;
	u32		iisfcon;
	u32		iispsr;
};
static struct s3c24xx_i2s_info s3c24xx_i2s;

static void s3c24xx_snd_txctrl(int on)
{
	u32 iisfcon;
	u32 iiscon;
	u32 iismod;

	pr_debug("Entered %s\n", __func__);

	iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
	iiscon  = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
	iismod  = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);

	pr_debug("r: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);

	if (on) {
		iisfcon |= S3C2410_IISFCON_TXDMA | S3C2410_IISFCON_TXENABLE;
		iiscon  |= S3C2410_IISCON_TXDMAEN | S3C2410_IISCON_IISEN;
		iiscon  &= ~S3C2410_IISCON_TXIDLE;
		iismod  |= S3C2410_IISMOD_TXMODE;

		writel(iismod,  s3c24xx_i2s.regs + S3C2410_IISMOD);
		writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
		writel(iiscon,  s3c24xx_i2s.regs + S3C2410_IISCON);
	} else {
		/* note, we have to disable the FIFOs otherwise bad things
		 * seem to happen when the DMA stops. According to the
		 * Samsung supplied kernel, this should allow the DMA
		 * engine and FIFOs to reset. If this isn't allowed, the
		 * DMA engine will simply freeze randomly.
		 */

		iisfcon &= ~S3C2410_IISFCON_TXENABLE;
		iisfcon &= ~S3C2410_IISFCON_TXDMA;
		iiscon  |=  S3C2410_IISCON_TXIDLE;
		iiscon  &= ~S3C2410_IISCON_TXDMAEN;
		iismod  &= ~S3C2410_IISMOD_TXMODE;

		writel(iiscon,  s3c24xx_i2s.regs + S3C2410_IISCON);
		writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
		writel(iismod,  s3c24xx_i2s.regs + S3C2410_IISMOD);
	}

	pr_debug("w: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
}

static void s3c24xx_snd_rxctrl(int on)
{
	u32 iisfcon;
	u32 iiscon;
	u32 iismod;

	pr_debug("Entered %s\n", __func__);

	iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
	iiscon  = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
	iismod  = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);

	pr_debug("r: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);

	if (on) {
		iisfcon |= S3C2410_IISFCON_RXDMA | S3C2410_IISFCON_RXENABLE;
		iiscon  |= S3C2410_IISCON_RXDMAEN | S3C2410_IISCON_IISEN;
		iiscon  &= ~S3C2410_IISCON_RXIDLE;
		iismod  |= S3C2410_IISMOD_RXMODE;

		writel(iismod,  s3c24xx_i2s.regs + S3C2410_IISMOD);
		writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
		writel(iiscon,  s3c24xx_i2s.regs + S3C2410_IISCON);
	} else {
		/* note, we have to disable the FIFOs otherwise bad things
		 * seem to happen when the DMA stops. According to the
		 * Samsung supplied kernel, this should allow the DMA
		 * engine and FIFOs to reset. If this isn't allowed, the
		 * DMA engine will simply freeze randomly.
		 */

		iisfcon &= ~S3C2410_IISFCON_RXENABLE;
		iisfcon &= ~S3C2410_IISFCON_RXDMA;
		iiscon  |= S3C2410_IISCON_RXIDLE;
		iiscon  &= ~S3C2410_IISCON_RXDMAEN;
		iismod  &= ~S3C2410_IISMOD_RXMODE;

		writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
		writel(iiscon,  s3c24xx_i2s.regs + S3C2410_IISCON);
		writel(iismod,  s3c24xx_i2s.regs + S3C2410_IISMOD);
	}

	pr_debug("w: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
}

/*
 * Wait for the LR signal to allow synchronisation to the L/R clock
 * from the codec. May only be needed for slave mode.
 */
static int s3c24xx_snd_lrsync(void)
{
	u32 iiscon;
	int timeout = 50; /* 5ms */

	pr_debug("Entered %s\n", __func__);

	while (1) {
		iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
		if (iiscon & S3C2410_IISCON_LRINDEX)
			break;

		if (!timeout--)
			return -ETIMEDOUT;
		udelay(100);
	}

	return 0;
}

/*
 * Check whether CPU is the master or slave
 */
static inline int s3c24xx_snd_is_clkmaster(void)
{
	pr_debug("Entered %s\n", __func__);

	return (readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & S3C2410_IISMOD_SLAVE) ? 0:1;
}

/*
 * Set S3C24xx I2S DAI format
 */
static int s3c24xx_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
		unsigned int fmt)
{
	u32 iismod;

	pr_debug("Entered %s\n", __func__);

	iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
	pr_debug("hw_params r: IISMOD: %x \n", iismod);

	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBM_CFM:
		iismod |= S3C2410_IISMOD_SLAVE;
		break;
	case SND_SOC_DAIFMT_CBS_CFS:
		iismod &= ~S3C2410_IISMOD_SLAVE;
		break;
	default:
		return -EINVAL;
	}

	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_LEFT_J:
		iismod |= S3C2410_IISMOD_MSB;
		break;
	case SND_SOC_DAIFMT_I2S:
		iismod &= ~S3C2410_IISMOD_MSB;
		break;
	default:
		return -EINVAL;
	}

	writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
	pr_debug("hw_params w: IISMOD: %x \n", iismod);
	return 0;
}

static int s3c24xx_i2s_hw_params(struct snd_pcm_substream *substream,
				 struct snd_pcm_hw_params *params,
				 struct snd_soc_dai *dai)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct s3c_dma_params *dma_data;
	u32 iismod;

	pr_debug("Entered %s\n", __func__);

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
		dma_data = &s3c24xx_i2s_pcm_stereo_out;
	else
		dma_data = &s3c24xx_i2s_pcm_stereo_in;

	snd_soc_dai_set_dma_data(rtd->cpu_dai, substream, dma_data);

	/* Working copies of register */
	iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
	pr_debug("hw_params r: IISMOD: %x\n", iismod);

	switch (params_format(params)) {
	case SNDRV_PCM_FORMAT_S8:
		iismod &= ~S3C2410_IISMOD_16BIT;
		dma_data->dma_size = 1;
		break;
	case SNDRV_PCM_FORMAT_S16_LE:
		iismod |= S3C2410_IISMOD_16BIT;
		dma_data->dma_size = 2;
		break;
	default:
		return -EINVAL;
	}

	writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
	pr_debug("hw_params w: IISMOD: %x\n", iismod);
	return 0;
}

static int s3c24xx_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
			       struct snd_soc_dai *dai)
{
	int ret = 0;
	struct s3c_dma_params *dma_data =
		snd_soc_dai_get_dma_data(dai, substream);

	pr_debug("Entered %s\n", __func__);

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_RESUME:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
		if (!s3c24xx_snd_is_clkmaster()) {
			ret = s3c24xx_snd_lrsync();
			if (ret)
				goto exit_err;
		}

		if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
			s3c24xx_snd_rxctrl(1);
		else
			s3c24xx_snd_txctrl(1);

		s3c2410_dma_ctrl(dma_data->channel, S3C2410_DMAOP_STARTED);
		break;
	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_SUSPEND:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
		if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
			s3c24xx_snd_rxctrl(0);
		else
			s3c24xx_snd_txctrl(0);
		break;
	default:
		ret = -EINVAL;
		break;
	}

exit_err:
	return ret;
}

/*
 * Set S3C24xx Clock source
 */
static int s3c24xx_i2s_set_sysclk(struct snd_soc_dai *cpu_dai,
	int clk_id, unsigned int freq, int dir)
{
	u32 iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);

	pr_debug("Entered %s\n", __func__);

	iismod &= ~S3C2440_IISMOD_MPLL;

	switch (clk_id) {
	case S3C24XX_CLKSRC_PCLK:
		break;
	case S3C24XX_CLKSRC_MPLL:
		iismod |= S3C2440_IISMOD_MPLL;
		break;
	default:
		return -EINVAL;
	}

	writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
	return 0;
}

/*
 * Set S3C24xx Clock dividers
 */
static int s3c24xx_i2s_set_clkdiv(struct snd_soc_dai *cpu_dai,
	int div_id, int div)
{
	u32 reg;

	pr_debug("Entered %s\n", __func__);

	switch (div_id) {
	case S3C24XX_DIV_BCLK:
		reg = readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & ~S3C2410_IISMOD_FS_MASK;
		writel(reg | div, s3c24xx_i2s.regs + S3C2410_IISMOD);
		break;
	case S3C24XX_DIV_MCLK:
		reg = readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & ~(S3C2410_IISMOD_384FS);
		writel(reg | div, s3c24xx_i2s.regs + S3C2410_IISMOD);
		break;
	case S3C24XX_DIV_PRESCALER:
		writel(div, s3c24xx_i2s.regs + S3C2410_IISPSR);
		reg = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
		writel(reg | S3C2410_IISCON_PSCEN, s3c24xx_i2s.regs + S3C2410_IISCON);
		break;
	default:
		return -EINVAL;
	}

	return 0;
}

/*
 * To avoid duplicating clock code, allow machine driver to
 * get the clockrate from here.
 */
u32 s3c24xx_i2s_get_clockrate(void)
{
	return clk_get_rate(s3c24xx_i2s.iis_clk);
}
EXPORT_SYMBOL_GPL(s3c24xx_i2s_get_clockrate);

static int s3c24xx_i2s_probe(struct snd_soc_dai *dai)
{
	pr_debug("Entered %s\n", __func__);

	s3c24xx_i2s.regs = ioremap(S3C2410_PA_IIS, 0x100);
	if (s3c24xx_i2s.regs == NULL)
		return -ENXIO;

	s3c24xx_i2s.iis_clk = clk_get(dai->dev, "iis");
	if (IS_ERR(s3c24xx_i2s.iis_clk)) {
		pr_err("failed to get iis_clock\n");
		iounmap(s3c24xx_i2s.regs);
		return PTR_ERR(s3c24xx_i2s.iis_clk);
	}
	clk_enable(s3c24xx_i2s.iis_clk);

	/* Configure the I2S pins (GPE0...GPE4) in correct mode */
	s3c_gpio_cfgall_range(S3C2410_GPE(0), 5, S3C_GPIO_SFN(2),
			      S3C_GPIO_PULL_NONE);

	writel(S3C2410_IISCON_IISEN, s3c24xx_i2s.regs + S3C2410_IISCON);

	s3c24xx_snd_txctrl(0);
	s3c24xx_snd_rxctrl(0);

	return 0;
}

#ifdef CONFIG_PM
static int s3c24xx_i2s_suspend(struct snd_soc_dai *cpu_dai)
{
	pr_debug("Entered %s\n", __func__);

	s3c24xx_i2s.iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
	s3c24xx_i2s.iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
	s3c24xx_i2s.iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
	s3c24xx_i2s.iispsr = readl(s3c24xx_i2s.regs + S3C2410_IISPSR);

	clk_disable(s3c24xx_i2s.iis_clk);

	return 0;
}

static int s3c24xx_i2s_resume(struct snd_soc_dai *cpu_dai)
{
	pr_debug("Entered %s\n", __func__);
	clk_enable(s3c24xx_i2s.iis_clk);

	writel(s3c24xx_i2s.iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
	writel(s3c24xx_i2s.iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
	writel(s3c24xx_i2s.iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
	writel(s3c24xx_i2s.iispsr, s3c24xx_i2s.regs + S3C2410_IISPSR);

	return 0;
}
#else
#define s3c24xx_i2s_suspend NULL
#define s3c24xx_i2s_resume NULL
#endif


#define S3C24XX_I2S_RATES \
	(SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 | \
	SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
	SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)

static const struct snd_soc_dai_ops s3c24xx_i2s_dai_ops = {
	.trigger	= s3c24xx_i2s_trigger,
	.hw_params	= s3c24xx_i2s_hw_params,
	.set_fmt	= s3c24xx_i2s_set_fmt,
	.set_clkdiv	= s3c24xx_i2s_set_clkdiv,
	.set_sysclk	= s3c24xx_i2s_set_sysclk,
};

static struct snd_soc_dai_driver s3c24xx_i2s_dai = {
	.probe = s3c24xx_i2s_probe,
	.suspend = s3c24xx_i2s_suspend,
	.resume = s3c24xx_i2s_resume,
	.playback = {
		.channels_min = 2,
		.channels_max = 2,
		.rates = S3C24XX_I2S_RATES,
		.formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE,},
	.capture = {
		.channels_min = 2,
		.channels_max = 2,
		.rates = S3C24XX_I2S_RATES,
		.formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE,},
	.ops = &s3c24xx_i2s_dai_ops,
};

static const struct snd_soc_component_driver s3c24xx_i2s_component = {
	.name		= "s3c24xx-i2s",
};

static int s3c24xx_iis_dev_probe(struct platform_device *pdev)
{
	int ret = 0;

	ret = snd_soc_register_component(&pdev->dev, &s3c24xx_i2s_component,
					 &s3c24xx_i2s_dai, 1);
	if (ret) {
		pr_err("failed to register the dai\n");
		return ret;
	}

	ret = samsung_asoc_dma_platform_register(&pdev->dev);
	if (ret) {
		pr_err("failed to register the dma: %d\n", ret);
		goto err;
	}

	return 0;
err:
	snd_soc_unregister_component(&pdev->dev);
	return ret;
}

static int s3c24xx_iis_dev_remove(struct platform_device *pdev)
{
	snd_soc_unregister_component(&pdev->dev);
	return 0;
}

static struct platform_driver s3c24xx_iis_driver = {
	.probe  = s3c24xx_iis_dev_probe,
	.remove = s3c24xx_iis_dev_remove,
	.driver = {
		.name = "s3c24xx-iis",
		.owner = THIS_MODULE,
	},
};

module_platform_driver(s3c24xx_iis_driver);

/* Module information */
MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
MODULE_DESCRIPTION("s3c24xx I2S SoC Interface");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:s3c24xx-iis");
Commit	Line	Data
c1422a66 BD	1	/*
	2	* s3c24xx-i2s.c -- ALSA Soc Audio Layer
	3	*
	4	* (c) 2006 Wolfson Microelectronics PLC.
	5	* Graeme Gregory graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
	6	*
c8efef17	7	* Copyright 2004-2005 Simtec Electronics
c1422a66 BD	8	* http://armlinux.simtec.co.uk/
	9	* Ben Dooks <ben@simtec.co.uk>
	10	*
	11	* This program is free software; you can redistribute it and/or modify it
	12	* under the terms of the GNU General Public License as published by the
	13	* Free Software Foundation; either version 2 of the License, or (at your
	14	* option) any later version.
c1422a66 BD	15	*/
c1422a66 BD	16
c1422a66 BD	17	#include <linux/delay.h>
c1422a66 BD	18	#include <linux/clk.h>
40efc15f	19	#include <linux/io.h>
ec976d6e	20	#include <linux/gpio.h>
da155d5b	21	#include <linux/module.h>
ec976d6e	22
c1422a66	23	#include <sound/soc.h>
0378b6ac	24	#include <sound/pcm_params.h>
c1422a66	25
a09e64fb	26	#include <mach/dma.h>
abffae64 SK	27	#include <mach/gpio-samsung.h>
abffae64 SK	28	#include <plat/gpio-cfg.h>
5d229ce5	29	#include "regs-iis.h"
aa9673cf	30
4b640cf3	31	#include "dma.h"
c1422a66 BD	32	#include "s3c24xx-i2s.h"
c1422a66 BD	33
71e5222c	34	static struct s3c_dma_client s3c24xx_dma_client_out = {
c1422a66 BD	35	.name = "I2S PCM Stereo out"
	36	};
	37
71e5222c	38	static struct s3c_dma_client s3c24xx_dma_client_in = {
c1422a66 BD	39	.name = "I2S PCM Stereo in"
	40	};
	41
faa31776	42	static struct s3c_dma_params s3c24xx_i2s_pcm_stereo_out = {
c1422a66 BD	43	.client = &s3c24xx_dma_client_out,
c1422a66 BD	44	.channel = DMACH_I2S_OUT,
e81208fe GG	45	.dma_addr = S3C2410_PA_IIS + S3C2410_IISFIFO,
e81208fe GG	46	.dma_size = 2,
c1422a66 BD	47	};
c1422a66 BD	48
faa31776	49	static struct s3c_dma_params s3c24xx_i2s_pcm_stereo_in = {
c1422a66 BD	50	.client = &s3c24xx_dma_client_in,
c1422a66 BD	51	.channel = DMACH_I2S_IN,
e81208fe GG	52	.dma_addr = S3C2410_PA_IIS + S3C2410_IISFIFO,
e81208fe GG	53	.dma_size = 2,
c1422a66 BD	54	};
	55
	56	struct s3c24xx_i2s_info {
	57	void __iomem *regs;
	58	struct clk *iis_clk;
5cd919a2 GG	59	u32 iiscon;
	60	u32 iismod;
	61	u32 iisfcon;
	62	u32 iispsr;
c1422a66 BD	63	};
	64	static struct s3c24xx_i2s_info s3c24xx_i2s;
	65
	66	static void s3c24xx_snd_txctrl(int on)
	67	{
	68	u32 iisfcon;
	69	u32 iiscon;
	70	u32 iismod;
	71
ee7d4767	72	pr_debug("Entered %s\n", __func__);
c1422a66 BD	73
	74	iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
	75	iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
	76	iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
	77
5314adc3	78	pr_debug("r: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
c1422a66 BD	79
	80	if (on) {
	81	iisfcon \|= S3C2410_IISFCON_TXDMA \| S3C2410_IISFCON_TXENABLE;
	82	iiscon \|= S3C2410_IISCON_TXDMAEN \| S3C2410_IISCON_IISEN;
	83	iiscon &= ~S3C2410_IISCON_TXIDLE;
	84	iismod \|= S3C2410_IISMOD_TXMODE;
	85
	86	writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
	87	writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
	88	writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
	89	} else {
	90	/* note, we have to disable the FIFOs otherwise bad things
	91	* seem to happen when the DMA stops. According to the
	92	* Samsung supplied kernel, this should allow the DMA
	93	* engine and FIFOs to reset. If this isn't allowed, the
	94	* DMA engine will simply freeze randomly.
	95	*/
	96
	97	iisfcon &= ~S3C2410_IISFCON_TXENABLE;
	98	iisfcon &= ~S3C2410_IISFCON_TXDMA;
	99	iiscon \|= S3C2410_IISCON_TXIDLE;
	100	iiscon &= ~S3C2410_IISCON_TXDMAEN;
	101	iismod &= ~S3C2410_IISMOD_TXMODE;
	102
	103	writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
	104	writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
	105	writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
	106	}
	107
5314adc3	108	pr_debug("w: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
c1422a66 BD	109	}
	110
	111	static void s3c24xx_snd_rxctrl(int on)
	112	{
	113	u32 iisfcon;
	114	u32 iiscon;
	115	u32 iismod;
	116
ee7d4767	117	pr_debug("Entered %s\n", __func__);
c1422a66 BD	118
	119	iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
	120	iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
	121	iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
	122
5314adc3	123	pr_debug("r: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
c1422a66 BD	124
	125	if (on) {
	126	iisfcon \|= S3C2410_IISFCON_RXDMA \| S3C2410_IISFCON_RXENABLE;
	127	iiscon \|= S3C2410_IISCON_RXDMAEN \| S3C2410_IISCON_IISEN;
	128	iiscon &= ~S3C2410_IISCON_RXIDLE;
	129	iismod \|= S3C2410_IISMOD_RXMODE;
	130
	131	writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
	132	writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
	133	writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
	134	} else {
	135	/* note, we have to disable the FIFOs otherwise bad things
	136	* seem to happen when the DMA stops. According to the
	137	* Samsung supplied kernel, this should allow the DMA
	138	* engine and FIFOs to reset. If this isn't allowed, the
	139	* DMA engine will simply freeze randomly.
	140	*/
	141
0015e7d1 MB	142	iisfcon &= ~S3C2410_IISFCON_RXENABLE;
	143	iisfcon &= ~S3C2410_IISFCON_RXDMA;
	144	iiscon \|= S3C2410_IISCON_RXIDLE;
	145	iiscon &= ~S3C2410_IISCON_RXDMAEN;
c1422a66 BD	146	iismod &= ~S3C2410_IISMOD_RXMODE;
	147
	148	writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
	149	writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
	150	writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
	151	}
	152
5314adc3	153	pr_debug("w: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
c1422a66 BD	154	}
	155
	156	/*
	157	* Wait for the LR signal to allow synchronisation to the L/R clock
	158	* from the codec. May only be needed for slave mode.
	159	*/
	160	static int s3c24xx_snd_lrsync(void)
	161	{
	162	u32 iiscon;
33e5b222	163	int timeout = 50; /* 5ms */
c1422a66	164
ee7d4767	165	pr_debug("Entered %s\n", __func__);
c1422a66 BD	166
	167	while (1) {
	168	iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
	169	if (iiscon & S3C2410_IISCON_LRINDEX)
	170	break;
	171
33e5b222	172	if (!timeout--)
c1422a66	173	return -ETIMEDOUT;
33e5b222	174	udelay(100);
c1422a66 BD	175	}
	176
	177	return 0;
	178	}
	179
	180	/*
	181	* Check whether CPU is the master or slave
	182	*/
	183	static inline int s3c24xx_snd_is_clkmaster(void)
	184	{
ee7d4767	185	pr_debug("Entered %s\n", __func__);
c1422a66 BD	186
	187	return (readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & S3C2410_IISMOD_SLAVE) ? 0:1;
	188	}
	189
	190	/*
	191	* Set S3C24xx I2S DAI format
	192	*/
1992a6fb	193	static int s3c24xx_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
c1422a66 BD	194	unsigned int fmt)
	195	{
	196	u32 iismod;
	197
ee7d4767	198	pr_debug("Entered %s\n", __func__);
c1422a66 BD	199
c1422a66 BD	200	iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
5314adc3	201	pr_debug("hw_params r: IISMOD: %x \n", iismod);
c1422a66 BD	202
	203	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	204	case SND_SOC_DAIFMT_CBM_CFM:
	205	iismod \|= S3C2410_IISMOD_SLAVE;
	206	break;
	207	case SND_SOC_DAIFMT_CBS_CFS:
2c36eecf	208	iismod &= ~S3C2410_IISMOD_SLAVE;
c1422a66 BD	209	break;
	210	default:
	211	return -EINVAL;
	212	}
	213
	214	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	215	case SND_SOC_DAIFMT_LEFT_J:
	216	iismod \|= S3C2410_IISMOD_MSB;
	217	break;
	218	case SND_SOC_DAIFMT_I2S:
2c36eecf	219	iismod &= ~S3C2410_IISMOD_MSB;
c1422a66 BD	220	break;
	221	default:
	222	return -EINVAL;
	223	}
	224
	225	writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
5314adc3	226	pr_debug("hw_params w: IISMOD: %x \n", iismod);
c1422a66 BD	227	return 0;
	228	}
	229
	230	static int s3c24xx_i2s_hw_params(struct snd_pcm_substream *substream,
dee89c4d MB	231	struct snd_pcm_hw_params *params,
dee89c4d MB	232	struct snd_soc_dai *dai)
c1422a66 BD	233	{
c1422a66 BD	234	struct snd_soc_pcm_runtime *rtd = substream->private_data;
5f712b2b	235	struct s3c_dma_params *dma_data;
c1422a66 BD	236	u32 iismod;
c1422a66 BD	237
ee7d4767	238	pr_debug("Entered %s\n", __func__);
c1422a66 BD	239
c1422a66 BD	240	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5f712b2b	241	dma_data = &s3c24xx_i2s_pcm_stereo_out;
c1422a66	242	else
5f712b2b DM	243	dma_data = &s3c24xx_i2s_pcm_stereo_in;
5f712b2b DM	244
f0fba2ad	245	snd_soc_dai_set_dma_data(rtd->cpu_dai, substream, dma_data);
c1422a66 BD	246
	247	/* Working copies of register */
	248	iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
5314adc3	249	pr_debug("hw_params r: IISMOD: %x\n", iismod);
c1422a66 BD	250
	251	switch (params_format(params)) {
	252	case SNDRV_PCM_FORMAT_S8:
53599bbc	253	iismod &= ~S3C2410_IISMOD_16BIT;
5f712b2b	254	dma_data->dma_size = 1;
c1422a66 BD	255	break;
	256	case SNDRV_PCM_FORMAT_S16_LE:
	257	iismod \|= S3C2410_IISMOD_16BIT;
5f712b2b	258	dma_data->dma_size = 2;
c1422a66	259	break;
53599bbc CP	260	default:
53599bbc CP	261	return -EINVAL;
c1422a66 BD	262	}
	263
	264	writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
5314adc3	265	pr_debug("hw_params w: IISMOD: %x\n", iismod);
c1422a66 BD	266	return 0;
	267	}
	268
dee89c4d MB	269	static int s3c24xx_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
dee89c4d MB	270	struct snd_soc_dai *dai)
c1422a66 BD	271	{
c1422a66 BD	272	int ret = 0;
5f712b2b	273	struct s3c_dma_params *dma_data =
f0fba2ad	274	snd_soc_dai_get_dma_data(dai, substream);
c1422a66	275
ee7d4767	276	pr_debug("Entered %s\n", __func__);
c1422a66 BD	277
	278	switch (cmd) {
	279	case SNDRV_PCM_TRIGGER_START:
	280	case SNDRV_PCM_TRIGGER_RESUME:
	281	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	282	if (!s3c24xx_snd_is_clkmaster()) {
	283	ret = s3c24xx_snd_lrsync();
	284	if (ret)
	285	goto exit_err;
	286	}
	287
	288	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
	289	s3c24xx_snd_rxctrl(1);
	290	else
	291	s3c24xx_snd_txctrl(1);
faf907c7	292
5f712b2b	293	s3c2410_dma_ctrl(dma_data->channel, S3C2410_DMAOP_STARTED);
c1422a66 BD	294	break;
	295	case SNDRV_PCM_TRIGGER_STOP:
	296	case SNDRV_PCM_TRIGGER_SUSPEND:
	297	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	298	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
	299	s3c24xx_snd_rxctrl(0);
	300	else
	301	s3c24xx_snd_txctrl(0);
	302	break;
	303	default:
	304	ret = -EINVAL;
	305	break;
	306	}
	307
	308	exit_err:
	309	return ret;
	310	}
	311
	312	/*
	313	* Set S3C24xx Clock source
	314	*/
1992a6fb	315	static int s3c24xx_i2s_set_sysclk(struct snd_soc_dai *cpu_dai,
c1422a66 BD	316	int clk_id, unsigned int freq, int dir)
	317	{
	318	u32 iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
	319
ee7d4767	320	pr_debug("Entered %s\n", __func__);
c1422a66 BD	321
	322	iismod &= ~S3C2440_IISMOD_MPLL;
	323
	324	switch (clk_id) {
	325	case S3C24XX_CLKSRC_PCLK:
	326	break;
	327	case S3C24XX_CLKSRC_MPLL:
	328	iismod \|= S3C2440_IISMOD_MPLL;
	329	break;
	330	default:
	331	return -EINVAL;
	332	}
	333
	334	writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
	335	return 0;
	336	}
	337
	338	/*
	339	* Set S3C24xx Clock dividers
	340	*/
1992a6fb	341	static int s3c24xx_i2s_set_clkdiv(struct snd_soc_dai *cpu_dai,
c1422a66 BD	342	int div_id, int div)
	343	{
	344	u32 reg;
	345
ee7d4767	346	pr_debug("Entered %s\n", __func__);
c1422a66 BD	347
c1422a66 BD	348	switch (div_id) {
82fb159a	349	case S3C24XX_DIV_BCLK:
c1422a66 BD	350	reg = readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & ~S3C2410_IISMOD_FS_MASK;
	351	writel(reg \| div, s3c24xx_i2s.regs + S3C2410_IISMOD);
	352	break;
82fb159a	353	case S3C24XX_DIV_MCLK:
c1422a66 BD	354	reg = readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & ~(S3C2410_IISMOD_384FS);
	355	writel(reg \| div, s3c24xx_i2s.regs + S3C2410_IISMOD);
	356	break;
	357	case S3C24XX_DIV_PRESCALER:
	358	writel(div, s3c24xx_i2s.regs + S3C2410_IISPSR);
	359	reg = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
	360	writel(reg \| S3C2410_IISCON_PSCEN, s3c24xx_i2s.regs + S3C2410_IISCON);
	361	break;
	362	default:
	363	return -EINVAL;
	364	}
	365
	366	return 0;
	367	}
	368
	369	/*
	370	* To avoid duplicating clock code, allow machine driver to
	371	* get the clockrate from here.
	372	*/
	373	u32 s3c24xx_i2s_get_clockrate(void)
	374	{
	375	return clk_get_rate(s3c24xx_i2s.iis_clk);
	376	}
	377	EXPORT_SYMBOL_GPL(s3c24xx_i2s_get_clockrate);
	378
f0fba2ad	379	static int s3c24xx_i2s_probe(struct snd_soc_dai *dai)
c1422a66	380	{
ee7d4767	381	pr_debug("Entered %s\n", __func__);
c1422a66 BD	382
	383	s3c24xx_i2s.regs = ioremap(S3C2410_PA_IIS, 0x100);
	384	if (s3c24xx_i2s.regs == NULL)
	385	return -ENXIO;
	386
f0fba2ad	387	s3c24xx_i2s.iis_clk = clk_get(dai->dev, "iis");
7803e329	388	if (IS_ERR(s3c24xx_i2s.iis_clk)) {
b52a5195	389	pr_err("failed to get iis_clock\n");
8642a4ba	390	iounmap(s3c24xx_i2s.regs);
7803e329	391	return PTR_ERR(s3c24xx_i2s.iis_clk);
c1422a66 BD	392	}
	393	clk_enable(s3c24xx_i2s.iis_clk);
	394
0eed8a18 SN	395	/* Configure the I2S pins (GPE0...GPE4) in correct mode */
	396	s3c_gpio_cfgall_range(S3C2410_GPE(0), 5, S3C_GPIO_SFN(2),
	397	S3C_GPIO_PULL_NONE);
c1422a66 BD	398
	399	writel(S3C2410_IISCON_IISEN, s3c24xx_i2s.regs + S3C2410_IISCON);
	400
	401	s3c24xx_snd_txctrl(0);
	402	s3c24xx_snd_rxctrl(0);
	403
	404	return 0;
	405	}
	406
5cd919a2	407	#ifdef CONFIG_PM
dc7d7b83	408	static int s3c24xx_i2s_suspend(struct snd_soc_dai *cpu_dai)
5cd919a2	409	{
ee7d4767	410	pr_debug("Entered %s\n", __func__);
40920307	411
5cd919a2 GG	412	s3c24xx_i2s.iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
	413	s3c24xx_i2s.iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
	414	s3c24xx_i2s.iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
	415	s3c24xx_i2s.iispsr = readl(s3c24xx_i2s.regs + S3C2410_IISPSR);
	416
	417	clk_disable(s3c24xx_i2s.iis_clk);
	418
	419	return 0;
	420	}
	421
dc7d7b83	422	static int s3c24xx_i2s_resume(struct snd_soc_dai *cpu_dai)
5cd919a2	423	{
ee7d4767	424	pr_debug("Entered %s\n", __func__);
5cd919a2 GG	425	clk_enable(s3c24xx_i2s.iis_clk);
	426
	427	writel(s3c24xx_i2s.iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
	428	writel(s3c24xx_i2s.iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
	429	writel(s3c24xx_i2s.iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
	430	writel(s3c24xx_i2s.iispsr, s3c24xx_i2s.regs + S3C2410_IISPSR);
	431
	432	return 0;
	433	}
	434	#else
	435	#define s3c24xx_i2s_suspend NULL
	436	#define s3c24xx_i2s_resume NULL
	437	#endif
	438
	439
c1422a66 BD	440	#define S3C24XX_I2S_RATES \
	441	(SNDRV_PCM_RATE_8000 \| SNDRV_PCM_RATE_11025 \| SNDRV_PCM_RATE_16000 \| \
	442	SNDRV_PCM_RATE_22050 \| SNDRV_PCM_RATE_32000 \| SNDRV_PCM_RATE_44100 \| \
	443	SNDRV_PCM_RATE_48000 \| SNDRV_PCM_RATE_88200 \| SNDRV_PCM_RATE_96000)
	444
85e7652d	445	static const struct snd_soc_dai_ops s3c24xx_i2s_dai_ops = {
6335d055 EM	446	.trigger = s3c24xx_i2s_trigger,
	447	.hw_params = s3c24xx_i2s_hw_params,
	448	.set_fmt = s3c24xx_i2s_set_fmt,
	449	.set_clkdiv = s3c24xx_i2s_set_clkdiv,
	450	.set_sysclk = s3c24xx_i2s_set_sysclk,
	451	};
	452
f0fba2ad	453	static struct snd_soc_dai_driver s3c24xx_i2s_dai = {
c1422a66	454	.probe = s3c24xx_i2s_probe,
5cd919a2 GG	455	.suspend = s3c24xx_i2s_suspend,
5cd919a2 GG	456	.resume = s3c24xx_i2s_resume,
c1422a66 BD	457	.playback = {
	458	.channels_min = 2,
	459	.channels_max = 2,
	460	.rates = S3C24XX_I2S_RATES,
	461	.formats = SNDRV_PCM_FMTBIT_S8 \| SNDRV_PCM_FMTBIT_S16_LE,},
	462	.capture = {
	463	.channels_min = 2,
	464	.channels_max = 2,
	465	.rates = S3C24XX_I2S_RATES,
	466	.formats = SNDRV_PCM_FMTBIT_S8 \| SNDRV_PCM_FMTBIT_S16_LE,},
6335d055	467	.ops = &s3c24xx_i2s_dai_ops,
c1422a66	468	};
f0fba2ad	469
5642ddff KM	470	static const struct snd_soc_component_driver s3c24xx_i2s_component = {
	471	.name = "s3c24xx-i2s",
	472	};
	473
fdca21ad	474	static int s3c24xx_iis_dev_probe(struct platform_device *pdev)
f0fba2ad	475	{
a08485d8 PV	476	int ret = 0;
a08485d8 PV	477
5642ddff KM	478	ret = snd_soc_register_component(&pdev->dev, &s3c24xx_i2s_component,
5642ddff KM	479	&s3c24xx_i2s_dai, 1);
a08485d8 PV	480	if (ret) {
	481	pr_err("failed to register the dai\n");
	482	return ret;
	483	}
	484
06b10ff9	485	ret = samsung_asoc_dma_platform_register(&pdev->dev);
a08485d8 PV	486	if (ret) {
	487	pr_err("failed to register the dma: %d\n", ret);
	488	goto err;
	489	}
	490
	491	return 0;
	492	err:
5642ddff	493	snd_soc_unregister_component(&pdev->dev);
a08485d8	494	return ret;
f0fba2ad LG	495	}
f0fba2ad LG	496
fdca21ad	497	static int s3c24xx_iis_dev_remove(struct platform_device *pdev)
f0fba2ad	498	{
5642ddff	499	snd_soc_unregister_component(&pdev->dev);
f0fba2ad LG	500	return 0;
	501	}
	502
	503	static struct platform_driver s3c24xx_iis_driver = {
	504	.probe = s3c24xx_iis_dev_probe,
fdca21ad	505	.remove = s3c24xx_iis_dev_remove,
f0fba2ad LG	506	.driver = {
	507	.name = "s3c24xx-iis",
	508	.owner = THIS_MODULE,
	509	},
	510	};
c1422a66	511
e00c3f55	512	module_platform_driver(s3c24xx_iis_driver);
3f4b783c	513
c1422a66 BD	514	/* Module information */
	515	MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
	516	MODULE_DESCRIPTION("s3c24xx I2S SoC Interface");
	517	MODULE_LICENSE("GPL");
960d0697	518	MODULE_ALIAS("platform:s3c24xx-iis");