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17467f23 TT |
1 | /* |
2 | * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver | |
3 | * | |
4 | * Author: Timur Tabi <timur@freescale.com> | |
5 | * | |
f0fba2ad LG |
6 | * Copyright 2007-2010 Freescale Semiconductor, Inc. |
7 | * | |
8 | * This file is licensed under the terms of the GNU General Public License | |
9 | * version 2. This program is licensed "as is" without any warranty of any | |
10 | * kind, whether express or implied. | |
de623ece MP |
11 | * |
12 | * | |
13 | * Some notes why imx-pcm-fiq is used instead of DMA on some boards: | |
14 | * | |
15 | * The i.MX SSI core has some nasty limitations in AC97 mode. While most | |
16 | * sane processor vendors have a FIFO per AC97 slot, the i.MX has only | |
17 | * one FIFO which combines all valid receive slots. We cannot even select | |
18 | * which slots we want to receive. The WM9712 with which this driver | |
19 | * was developed with always sends GPIO status data in slot 12 which | |
20 | * we receive in our (PCM-) data stream. The only chance we have is to | |
21 | * manually skip this data in the FIQ handler. With sampling rates different | |
22 | * from 48000Hz not every frame has valid receive data, so the ratio | |
23 | * between pcm data and GPIO status data changes. Our FIQ handler is not | |
24 | * able to handle this, hence this driver only works with 48000Hz sampling | |
25 | * rate. | |
26 | * Reading and writing AC97 registers is another challenge. The core | |
27 | * provides us status bits when the read register is updated with *another* | |
28 | * value. When we read the same register two times (and the register still | |
29 | * contains the same value) these status bits are not set. We work | |
30 | * around this by not polling these bits but only wait a fixed delay. | |
17467f23 TT |
31 | */ |
32 | ||
33 | #include <linux/init.h> | |
dfa1a107 | 34 | #include <linux/io.h> |
17467f23 TT |
35 | #include <linux/module.h> |
36 | #include <linux/interrupt.h> | |
95cd98f9 | 37 | #include <linux/clk.h> |
17467f23 TT |
38 | #include <linux/device.h> |
39 | #include <linux/delay.h> | |
5a0e3ad6 | 40 | #include <linux/slab.h> |
aafa85e7 | 41 | #include <linux/spinlock.h> |
dfa1a107 SG |
42 | #include <linux/of_address.h> |
43 | #include <linux/of_irq.h> | |
f0fba2ad | 44 | #include <linux/of_platform.h> |
17467f23 | 45 | |
17467f23 TT |
46 | #include <sound/core.h> |
47 | #include <sound/pcm.h> | |
48 | #include <sound/pcm_params.h> | |
49 | #include <sound/initval.h> | |
50 | #include <sound/soc.h> | |
a8909c9b | 51 | #include <sound/dmaengine_pcm.h> |
17467f23 | 52 | |
17467f23 | 53 | #include "fsl_ssi.h" |
09ce1111 | 54 | #include "imx-pcm.h" |
17467f23 | 55 | |
dfa1a107 SG |
56 | #ifdef PPC |
57 | #define read_ssi(addr) in_be32(addr) | |
58 | #define write_ssi(val, addr) out_be32(addr, val) | |
59 | #define write_ssi_mask(addr, clear, set) clrsetbits_be32(addr, clear, set) | |
0a9eaa39 | 60 | #else |
dfa1a107 SG |
61 | #define read_ssi(addr) readl(addr) |
62 | #define write_ssi(val, addr) writel(val, addr) | |
63 | /* | |
64 | * FIXME: Proper locking should be added at write_ssi_mask caller level | |
65 | * to ensure this register read/modify/write sequence is race free. | |
66 | */ | |
67 | static inline void write_ssi_mask(u32 __iomem *addr, u32 clear, u32 set) | |
68 | { | |
69 | u32 val = readl(addr); | |
70 | val = (val & ~clear) | set; | |
71 | writel(val, addr); | |
72 | } | |
73 | #endif | |
74 | ||
17467f23 TT |
75 | /** |
76 | * FSLSSI_I2S_RATES: sample rates supported by the I2S | |
77 | * | |
78 | * This driver currently only supports the SSI running in I2S slave mode, | |
79 | * which means the codec determines the sample rate. Therefore, we tell | |
80 | * ALSA that we support all rates and let the codec driver decide what rates | |
81 | * are really supported. | |
82 | */ | |
24710c97 | 83 | #define FSLSSI_I2S_RATES SNDRV_PCM_RATE_CONTINUOUS |
17467f23 TT |
84 | |
85 | /** | |
86 | * FSLSSI_I2S_FORMATS: audio formats supported by the SSI | |
87 | * | |
88 | * This driver currently only supports the SSI running in I2S slave mode. | |
89 | * | |
90 | * The SSI has a limitation in that the samples must be in the same byte | |
91 | * order as the host CPU. This is because when multiple bytes are written | |
92 | * to the STX register, the bytes and bits must be written in the same | |
93 | * order. The STX is a shift register, so all the bits need to be aligned | |
94 | * (bit-endianness must match byte-endianness). Processors typically write | |
95 | * the bits within a byte in the same order that the bytes of a word are | |
96 | * written in. So if the host CPU is big-endian, then only big-endian | |
97 | * samples will be written to STX properly. | |
98 | */ | |
99 | #ifdef __BIG_ENDIAN | |
100 | #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \ | |
101 | SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \ | |
102 | SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE) | |
103 | #else | |
104 | #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \ | |
105 | SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \ | |
106 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE) | |
107 | #endif | |
108 | ||
9368acc4 MP |
109 | #define FSLSSI_SIER_DBG_RX_FLAGS (CCSR_SSI_SIER_RFF0_EN | \ |
110 | CCSR_SSI_SIER_RLS_EN | CCSR_SSI_SIER_RFS_EN | \ | |
111 | CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_RFRC_EN) | |
112 | #define FSLSSI_SIER_DBG_TX_FLAGS (CCSR_SSI_SIER_TFE0_EN | \ | |
113 | CCSR_SSI_SIER_TLS_EN | CCSR_SSI_SIER_TFS_EN | \ | |
114 | CCSR_SSI_SIER_TUE0_EN | CCSR_SSI_SIER_TFRC_EN) | |
c1953bfe MP |
115 | |
116 | enum fsl_ssi_type { | |
117 | FSL_SSI_MCP8610, | |
118 | FSL_SSI_MX21, | |
0888efd1 | 119 | FSL_SSI_MX35, |
c1953bfe MP |
120 | FSL_SSI_MX51, |
121 | }; | |
122 | ||
4e6ec0d9 MP |
123 | struct fsl_ssi_reg_val { |
124 | u32 sier; | |
125 | u32 srcr; | |
126 | u32 stcr; | |
127 | u32 scr; | |
128 | }; | |
129 | ||
130 | struct fsl_ssi_rxtx_reg_val { | |
131 | struct fsl_ssi_reg_val rx; | |
132 | struct fsl_ssi_reg_val tx; | |
133 | }; | |
d5a908b2 | 134 | |
17467f23 TT |
135 | /** |
136 | * fsl_ssi_private: per-SSI private data | |
137 | * | |
17467f23 TT |
138 | * @ssi: pointer to the SSI's registers |
139 | * @ssi_phys: physical address of the SSI registers | |
140 | * @irq: IRQ of this SSI | |
17467f23 TT |
141 | * @playback: the number of playback streams opened |
142 | * @capture: the number of capture streams opened | |
143 | * @cpu_dai: the CPU DAI for this device | |
144 | * @dev_attr: the sysfs device attribute structure | |
145 | * @stats: SSI statistics | |
f0fba2ad | 146 | * @name: name for this device |
17467f23 TT |
147 | */ |
148 | struct fsl_ssi_private { | |
17467f23 TT |
149 | struct ccsr_ssi __iomem *ssi; |
150 | dma_addr_t ssi_phys; | |
151 | unsigned int irq; | |
8e9d8690 | 152 | unsigned int fifo_depth; |
f0fba2ad | 153 | struct snd_soc_dai_driver cpu_dai_drv; |
f0fba2ad | 154 | struct platform_device *pdev; |
17467f23 | 155 | |
0888efd1 | 156 | enum fsl_ssi_type hw_type; |
09ce1111 SG |
157 | bool new_binding; |
158 | bool ssi_on_imx; | |
cd7f0295 | 159 | bool imx_ac97; |
de623ece | 160 | bool use_dma; |
aafa85e7 | 161 | bool baudclk_locked; |
2841be9a | 162 | bool irq_stats; |
bd3ca7d1 | 163 | bool offline_config; |
0da9e55e | 164 | bool use_dual_fifo; |
2924a998 | 165 | u8 i2s_mode; |
aafa85e7 NC |
166 | spinlock_t baudclk_lock; |
167 | struct clk *baudclk; | |
95cd98f9 | 168 | struct clk *clk; |
a8909c9b LPC |
169 | struct snd_dmaengine_dai_dma_data dma_params_tx; |
170 | struct snd_dmaengine_dai_dma_data dma_params_rx; | |
de623ece | 171 | struct imx_pcm_fiq_params fiq_params; |
4e6ec0d9 MP |
172 | /* Register values for rx/tx configuration */ |
173 | struct fsl_ssi_rxtx_reg_val rxtx_reg_val; | |
09ce1111 | 174 | |
f138e621 | 175 | struct fsl_ssi_dbg dbg_stats; |
f0fba2ad LG |
176 | |
177 | char name[1]; | |
17467f23 TT |
178 | }; |
179 | ||
c1953bfe MP |
180 | static const struct of_device_id fsl_ssi_ids[] = { |
181 | { .compatible = "fsl,mpc8610-ssi", .data = (void *) FSL_SSI_MCP8610}, | |
182 | { .compatible = "fsl,imx51-ssi", .data = (void *) FSL_SSI_MX51}, | |
0888efd1 | 183 | { .compatible = "fsl,imx35-ssi", .data = (void *) FSL_SSI_MX35}, |
c1953bfe MP |
184 | { .compatible = "fsl,imx21-ssi", .data = (void *) FSL_SSI_MX21}, |
185 | {} | |
186 | }; | |
187 | MODULE_DEVICE_TABLE(of, fsl_ssi_ids); | |
188 | ||
17467f23 TT |
189 | /** |
190 | * fsl_ssi_isr: SSI interrupt handler | |
191 | * | |
192 | * Although it's possible to use the interrupt handler to send and receive | |
193 | * data to/from the SSI, we use the DMA instead. Programming is more | |
194 | * complicated, but the performance is much better. | |
195 | * | |
196 | * This interrupt handler is used only to gather statistics. | |
197 | * | |
198 | * @irq: IRQ of the SSI device | |
199 | * @dev_id: pointer to the ssi_private structure for this SSI device | |
200 | */ | |
201 | static irqreturn_t fsl_ssi_isr(int irq, void *dev_id) | |
202 | { | |
203 | struct fsl_ssi_private *ssi_private = dev_id; | |
204 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; | |
17467f23 | 205 | __be32 sisr; |
0888efd1 MP |
206 | __be32 sisr2; |
207 | __be32 sisr_write_mask = 0; | |
208 | ||
209 | switch (ssi_private->hw_type) { | |
210 | case FSL_SSI_MX21: | |
211 | sisr_write_mask = 0; | |
212 | break; | |
213 | ||
214 | case FSL_SSI_MCP8610: | |
215 | case FSL_SSI_MX35: | |
216 | sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC | | |
217 | CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 | | |
218 | CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1; | |
219 | break; | |
220 | ||
221 | case FSL_SSI_MX51: | |
222 | sisr_write_mask = CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 | | |
223 | CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1; | |
224 | break; | |
225 | } | |
17467f23 TT |
226 | |
227 | /* We got an interrupt, so read the status register to see what we | |
228 | were interrupted for. We mask it with the Interrupt Enable register | |
229 | so that we only check for events that we're interested in. | |
230 | */ | |
f138e621 | 231 | sisr = read_ssi(&ssi->sisr); |
17467f23 | 232 | |
0888efd1 | 233 | sisr2 = sisr & sisr_write_mask; |
17467f23 TT |
234 | /* Clear the bits that we set */ |
235 | if (sisr2) | |
dfa1a107 | 236 | write_ssi(sisr2, &ssi->sisr); |
17467f23 | 237 | |
f138e621 | 238 | fsl_ssi_dbg_isr(&ssi_private->dbg_stats, sisr); |
9368acc4 | 239 | |
f138e621 | 240 | return IRQ_HANDLED; |
9368acc4 MP |
241 | } |
242 | ||
4e6ec0d9 MP |
243 | /* |
244 | * Enable/Disable all rx/tx config flags at once. | |
245 | */ | |
246 | static void fsl_ssi_rxtx_config(struct fsl_ssi_private *ssi_private, | |
247 | bool enable) | |
248 | { | |
249 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; | |
250 | struct fsl_ssi_rxtx_reg_val *vals = &ssi_private->rxtx_reg_val; | |
251 | ||
252 | if (enable) { | |
253 | write_ssi_mask(&ssi->sier, 0, vals->rx.sier | vals->tx.sier); | |
254 | write_ssi_mask(&ssi->srcr, 0, vals->rx.srcr | vals->tx.srcr); | |
255 | write_ssi_mask(&ssi->stcr, 0, vals->rx.stcr | vals->tx.stcr); | |
256 | } else { | |
257 | write_ssi_mask(&ssi->srcr, vals->rx.srcr | vals->tx.srcr, 0); | |
258 | write_ssi_mask(&ssi->stcr, vals->rx.stcr | vals->tx.stcr, 0); | |
259 | write_ssi_mask(&ssi->sier, vals->rx.sier | vals->tx.sier, 0); | |
260 | } | |
261 | } | |
262 | ||
65c961cc MP |
263 | /* |
264 | * Calculate the bits that have to be disabled for the current stream that is | |
265 | * getting disabled. This keeps the bits enabled that are necessary for the | |
266 | * second stream to work if 'stream_active' is true. | |
267 | * | |
268 | * Detailed calculation: | |
269 | * These are the values that need to be active after disabling. For non-active | |
270 | * second stream, this is 0: | |
271 | * vals_stream * !!stream_active | |
272 | * | |
273 | * The following computes the overall differences between the setup for the | |
274 | * to-disable stream and the active stream, a simple XOR: | |
275 | * vals_disable ^ (vals_stream * !!(stream_active)) | |
276 | * | |
277 | * The full expression adds a mask on all values we care about | |
278 | */ | |
279 | #define fsl_ssi_disable_val(vals_disable, vals_stream, stream_active) \ | |
280 | ((vals_disable) & \ | |
281 | ((vals_disable) ^ ((vals_stream) * (u32)!!(stream_active)))) | |
282 | ||
4e6ec0d9 MP |
283 | /* |
284 | * Enable/Disable a ssi configuration. You have to pass either | |
285 | * ssi_private->rxtx_reg_val.rx or tx as vals parameter. | |
286 | */ | |
287 | static void fsl_ssi_config(struct fsl_ssi_private *ssi_private, bool enable, | |
288 | struct fsl_ssi_reg_val *vals) | |
289 | { | |
290 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; | |
291 | struct fsl_ssi_reg_val *avals; | |
292 | u32 scr_val = read_ssi(&ssi->scr); | |
293 | int nr_active_streams = !!(scr_val & CCSR_SSI_SCR_TE) + | |
294 | !!(scr_val & CCSR_SSI_SCR_RE); | |
65c961cc MP |
295 | int keep_active; |
296 | ||
297 | if (nr_active_streams - 1 > 0) | |
298 | keep_active = 1; | |
299 | else | |
300 | keep_active = 0; | |
4e6ec0d9 MP |
301 | |
302 | /* Find the other direction values rx or tx which we do not want to | |
303 | * modify */ | |
304 | if (&ssi_private->rxtx_reg_val.rx == vals) | |
305 | avals = &ssi_private->rxtx_reg_val.tx; | |
306 | else | |
307 | avals = &ssi_private->rxtx_reg_val.rx; | |
308 | ||
309 | /* If vals should be disabled, start with disabling the unit */ | |
310 | if (!enable) { | |
65c961cc MP |
311 | u32 scr = fsl_ssi_disable_val(vals->scr, avals->scr, |
312 | keep_active); | |
4e6ec0d9 MP |
313 | write_ssi_mask(&ssi->scr, scr, 0); |
314 | } | |
315 | ||
316 | /* | |
317 | * We are running on a SoC which does not support online SSI | |
318 | * reconfiguration, so we have to enable all necessary flags at once | |
319 | * even if we do not use them later (capture and playback configuration) | |
320 | */ | |
321 | if (ssi_private->offline_config) { | |
322 | if ((enable && !nr_active_streams) || | |
65c961cc | 323 | (!enable && !keep_active)) |
4e6ec0d9 MP |
324 | fsl_ssi_rxtx_config(ssi_private, enable); |
325 | ||
326 | goto config_done; | |
327 | } | |
328 | ||
329 | /* | |
330 | * Configure single direction units while the SSI unit is running | |
331 | * (online configuration) | |
332 | */ | |
333 | if (enable) { | |
334 | write_ssi_mask(&ssi->sier, 0, vals->sier); | |
335 | write_ssi_mask(&ssi->srcr, 0, vals->srcr); | |
336 | write_ssi_mask(&ssi->stcr, 0, vals->stcr); | |
337 | } else { | |
338 | u32 sier; | |
339 | u32 srcr; | |
340 | u32 stcr; | |
341 | ||
342 | /* | |
343 | * Disabling the necessary flags for one of rx/tx while the | |
344 | * other stream is active is a little bit more difficult. We | |
345 | * have to disable only those flags that differ between both | |
346 | * streams (rx XOR tx) and that are set in the stream that is | |
347 | * disabled now. Otherwise we could alter flags of the other | |
348 | * stream | |
349 | */ | |
350 | ||
351 | /* These assignments are simply vals without bits set in avals*/ | |
65c961cc MP |
352 | sier = fsl_ssi_disable_val(vals->sier, avals->sier, |
353 | keep_active); | |
354 | srcr = fsl_ssi_disable_val(vals->srcr, avals->srcr, | |
355 | keep_active); | |
356 | stcr = fsl_ssi_disable_val(vals->stcr, avals->stcr, | |
357 | keep_active); | |
4e6ec0d9 MP |
358 | |
359 | write_ssi_mask(&ssi->srcr, srcr, 0); | |
360 | write_ssi_mask(&ssi->stcr, stcr, 0); | |
361 | write_ssi_mask(&ssi->sier, sier, 0); | |
362 | } | |
363 | ||
364 | config_done: | |
365 | /* Enabling of subunits is done after configuration */ | |
366 | if (enable) | |
367 | write_ssi_mask(&ssi->scr, 0, vals->scr); | |
368 | } | |
369 | ||
370 | ||
371 | static void fsl_ssi_rx_config(struct fsl_ssi_private *ssi_private, bool enable) | |
372 | { | |
373 | fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.rx); | |
374 | } | |
375 | ||
376 | static void fsl_ssi_tx_config(struct fsl_ssi_private *ssi_private, bool enable) | |
377 | { | |
378 | fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.tx); | |
379 | } | |
380 | ||
6de83879 MP |
381 | /* |
382 | * Setup rx/tx register values used to enable/disable the streams. These will | |
383 | * be used later in fsl_ssi_config to setup the streams without the need to | |
384 | * check for all different SSI modes. | |
385 | */ | |
386 | static void fsl_ssi_setup_reg_vals(struct fsl_ssi_private *ssi_private) | |
387 | { | |
388 | struct fsl_ssi_rxtx_reg_val *reg = &ssi_private->rxtx_reg_val; | |
389 | ||
390 | reg->rx.sier = CCSR_SSI_SIER_RFF0_EN; | |
391 | reg->rx.srcr = CCSR_SSI_SRCR_RFEN0; | |
392 | reg->rx.scr = 0; | |
393 | reg->tx.sier = CCSR_SSI_SIER_TFE0_EN; | |
394 | reg->tx.stcr = CCSR_SSI_STCR_TFEN0; | |
395 | reg->tx.scr = 0; | |
396 | ||
397 | if (!ssi_private->imx_ac97) { | |
398 | reg->rx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE; | |
399 | reg->rx.sier |= CCSR_SSI_SIER_RFF0_EN; | |
400 | reg->tx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE; | |
401 | reg->tx.sier |= CCSR_SSI_SIER_TFE0_EN; | |
402 | } | |
403 | ||
404 | if (ssi_private->use_dma) { | |
405 | reg->rx.sier |= CCSR_SSI_SIER_RDMAE; | |
406 | reg->tx.sier |= CCSR_SSI_SIER_TDMAE; | |
407 | } else { | |
408 | reg->rx.sier |= CCSR_SSI_SIER_RIE; | |
409 | reg->tx.sier |= CCSR_SSI_SIER_TIE; | |
410 | } | |
411 | ||
412 | reg->rx.sier |= FSLSSI_SIER_DBG_RX_FLAGS; | |
413 | reg->tx.sier |= FSLSSI_SIER_DBG_TX_FLAGS; | |
414 | } | |
415 | ||
d8764646 MP |
416 | static void fsl_ssi_setup_ac97(struct fsl_ssi_private *ssi_private) |
417 | { | |
418 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; | |
419 | ||
420 | /* | |
421 | * Setup the clock control register | |
422 | */ | |
423 | write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13), | |
424 | &ssi->stccr); | |
425 | write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13), | |
426 | &ssi->srccr); | |
427 | ||
428 | /* | |
429 | * Enable AC97 mode and startup the SSI | |
430 | */ | |
431 | write_ssi(CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV, | |
432 | &ssi->sacnt); | |
433 | write_ssi(0xff, &ssi->saccdis); | |
434 | write_ssi(0x300, &ssi->saccen); | |
435 | ||
436 | /* | |
437 | * Enable SSI, Transmit and Receive. AC97 has to communicate with the | |
438 | * codec before a stream is started. | |
439 | */ | |
440 | write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN | | |
441 | CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE); | |
442 | ||
443 | write_ssi(CCSR_SSI_SOR_WAIT(3), &ssi->sor); | |
444 | } | |
445 | ||
17467f23 TT |
446 | /** |
447 | * fsl_ssi_startup: create a new substream | |
448 | * | |
449 | * This is the first function called when a stream is opened. | |
450 | * | |
451 | * If this is the first stream open, then grab the IRQ and program most of | |
452 | * the SSI registers. | |
453 | */ | |
dee89c4d MB |
454 | static int fsl_ssi_startup(struct snd_pcm_substream *substream, |
455 | struct snd_soc_dai *dai) | |
17467f23 TT |
456 | { |
457 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
5e538eca TT |
458 | struct fsl_ssi_private *ssi_private = |
459 | snd_soc_dai_get_drvdata(rtd->cpu_dai); | |
aafa85e7 | 460 | unsigned long flags; |
17467f23 | 461 | |
aafa85e7 | 462 | if (!dai->active && !ssi_private->imx_ac97) { |
aafa85e7 NC |
463 | spin_lock_irqsave(&ssi_private->baudclk_lock, flags); |
464 | ssi_private->baudclk_locked = false; | |
465 | spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags); | |
466 | } | |
be41e941 | 467 | |
0da9e55e NC |
468 | /* When using dual fifo mode, it is safer to ensure an even period |
469 | * size. If appearing to an odd number while DMA always starts its | |
470 | * task from fifo0, fifo1 would be neglected at the end of each | |
471 | * period. But SSI would still access fifo1 with an invalid data. | |
472 | */ | |
473 | if (ssi_private->use_dual_fifo) | |
474 | snd_pcm_hw_constraint_step(substream->runtime, 0, | |
475 | SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2); | |
476 | ||
17467f23 TT |
477 | return 0; |
478 | } | |
479 | ||
480 | /** | |
85ef2375 | 481 | * fsl_ssi_hw_params - program the sample size |
17467f23 TT |
482 | * |
483 | * Most of the SSI registers have been programmed in the startup function, | |
484 | * but the word length must be programmed here. Unfortunately, programming | |
485 | * the SxCCR.WL bits requires the SSI to be temporarily disabled. This can | |
486 | * cause a problem with supporting simultaneous playback and capture. If | |
487 | * the SSI is already playing a stream, then that stream may be temporarily | |
488 | * stopped when you start capture. | |
489 | * | |
490 | * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the | |
491 | * clock master. | |
492 | */ | |
85ef2375 TT |
493 | static int fsl_ssi_hw_params(struct snd_pcm_substream *substream, |
494 | struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai) | |
17467f23 | 495 | { |
f0fba2ad | 496 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); |
5e538eca | 497 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; |
2924a998 | 498 | unsigned int channels = params_channels(hw_params); |
5e538eca TT |
499 | unsigned int sample_size = |
500 | snd_pcm_format_width(params_format(hw_params)); | |
501 | u32 wl = CCSR_SSI_SxCCR_WL(sample_size); | |
dfa1a107 | 502 | int enabled = read_ssi(&ssi->scr) & CCSR_SSI_SCR_SSIEN; |
17467f23 | 503 | |
5e538eca TT |
504 | /* |
505 | * If we're in synchronous mode, and the SSI is already enabled, | |
506 | * then STCCR is already set properly. | |
507 | */ | |
508 | if (enabled && ssi_private->cpu_dai_drv.symmetric_rates) | |
509 | return 0; | |
17467f23 | 510 | |
5e538eca TT |
511 | /* |
512 | * FIXME: The documentation says that SxCCR[WL] should not be | |
513 | * modified while the SSI is enabled. The only time this can | |
514 | * happen is if we're trying to do simultaneous playback and | |
515 | * capture in asynchronous mode. Unfortunately, I have been enable | |
516 | * to get that to work at all on the P1022DS. Therefore, we don't | |
517 | * bother to disable/enable the SSI when setting SxCCR[WL], because | |
518 | * the SSI will stop anyway. Maybe one day, this will get fixed. | |
519 | */ | |
17467f23 | 520 | |
5e538eca TT |
521 | /* In synchronous mode, the SSI uses STCCR for capture */ |
522 | if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) || | |
523 | ssi_private->cpu_dai_drv.symmetric_rates) | |
dfa1a107 | 524 | write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_WL_MASK, wl); |
5e538eca | 525 | else |
dfa1a107 | 526 | write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_WL_MASK, wl); |
17467f23 | 527 | |
2924a998 NC |
528 | if (!ssi_private->imx_ac97) |
529 | write_ssi_mask(&ssi->scr, | |
530 | CCSR_SSI_SCR_NET | CCSR_SSI_SCR_I2S_MODE_MASK, | |
531 | channels == 1 ? 0 : ssi_private->i2s_mode); | |
532 | ||
17467f23 TT |
533 | return 0; |
534 | } | |
535 | ||
aafa85e7 NC |
536 | /** |
537 | * fsl_ssi_set_dai_fmt - configure Digital Audio Interface Format. | |
538 | */ | |
539 | static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) | |
540 | { | |
541 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); | |
542 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; | |
543 | u32 strcr = 0, stcr, srcr, scr, mask; | |
2b0db996 MP |
544 | u8 wm; |
545 | ||
546 | fsl_ssi_setup_reg_vals(ssi_private); | |
aafa85e7 NC |
547 | |
548 | scr = read_ssi(&ssi->scr) & ~(CCSR_SSI_SCR_SYN | CCSR_SSI_SCR_I2S_MODE_MASK); | |
aafa85e7 NC |
549 | |
550 | mask = CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR | | |
551 | CCSR_SSI_STCR_TSCKP | CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TFSL | | |
552 | CCSR_SSI_STCR_TEFS; | |
553 | stcr = read_ssi(&ssi->stcr) & ~mask; | |
554 | srcr = read_ssi(&ssi->srcr) & ~mask; | |
555 | ||
07a28dbe | 556 | ssi_private->i2s_mode = CCSR_SSI_SCR_NET; |
aafa85e7 NC |
557 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
558 | case SND_SOC_DAIFMT_I2S: | |
559 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
560 | case SND_SOC_DAIFMT_CBS_CFS: | |
07a28dbe | 561 | ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_MASTER; |
aafa85e7 NC |
562 | break; |
563 | case SND_SOC_DAIFMT_CBM_CFM: | |
07a28dbe | 564 | ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_SLAVE; |
aafa85e7 NC |
565 | break; |
566 | default: | |
567 | return -EINVAL; | |
568 | } | |
aafa85e7 NC |
569 | |
570 | /* Data on rising edge of bclk, frame low, 1clk before data */ | |
571 | strcr |= CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TSCKP | | |
572 | CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS; | |
573 | break; | |
574 | case SND_SOC_DAIFMT_LEFT_J: | |
575 | /* Data on rising edge of bclk, frame high */ | |
576 | strcr |= CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TSCKP; | |
577 | break; | |
578 | case SND_SOC_DAIFMT_DSP_A: | |
579 | /* Data on rising edge of bclk, frame high, 1clk before data */ | |
580 | strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP | | |
581 | CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS; | |
582 | break; | |
583 | case SND_SOC_DAIFMT_DSP_B: | |
584 | /* Data on rising edge of bclk, frame high */ | |
585 | strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP | | |
586 | CCSR_SSI_STCR_TXBIT0; | |
587 | break; | |
2b0db996 | 588 | case SND_SOC_DAIFMT_AC97: |
07a28dbe | 589 | ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_NORMAL; |
2b0db996 | 590 | break; |
aafa85e7 NC |
591 | default: |
592 | return -EINVAL; | |
593 | } | |
2b0db996 | 594 | scr |= ssi_private->i2s_mode; |
aafa85e7 NC |
595 | |
596 | /* DAI clock inversion */ | |
597 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
598 | case SND_SOC_DAIFMT_NB_NF: | |
599 | /* Nothing to do for both normal cases */ | |
600 | break; | |
601 | case SND_SOC_DAIFMT_IB_NF: | |
602 | /* Invert bit clock */ | |
603 | strcr ^= CCSR_SSI_STCR_TSCKP; | |
604 | break; | |
605 | case SND_SOC_DAIFMT_NB_IF: | |
606 | /* Invert frame clock */ | |
607 | strcr ^= CCSR_SSI_STCR_TFSI; | |
608 | break; | |
609 | case SND_SOC_DAIFMT_IB_IF: | |
610 | /* Invert both clocks */ | |
611 | strcr ^= CCSR_SSI_STCR_TSCKP; | |
612 | strcr ^= CCSR_SSI_STCR_TFSI; | |
613 | break; | |
614 | default: | |
615 | return -EINVAL; | |
616 | } | |
617 | ||
618 | /* DAI clock master masks */ | |
619 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
620 | case SND_SOC_DAIFMT_CBS_CFS: | |
621 | strcr |= CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR; | |
622 | scr |= CCSR_SSI_SCR_SYS_CLK_EN; | |
623 | break; | |
624 | case SND_SOC_DAIFMT_CBM_CFM: | |
625 | scr &= ~CCSR_SSI_SCR_SYS_CLK_EN; | |
626 | break; | |
627 | default: | |
628 | return -EINVAL; | |
629 | } | |
630 | ||
631 | stcr |= strcr; | |
632 | srcr |= strcr; | |
633 | ||
634 | if (ssi_private->cpu_dai_drv.symmetric_rates) { | |
635 | /* Need to clear RXDIR when using SYNC mode */ | |
636 | srcr &= ~CCSR_SSI_SRCR_RXDIR; | |
637 | scr |= CCSR_SSI_SCR_SYN; | |
638 | } | |
639 | ||
640 | write_ssi(stcr, &ssi->stcr); | |
641 | write_ssi(srcr, &ssi->srcr); | |
642 | write_ssi(scr, &ssi->scr); | |
643 | ||
2b0db996 MP |
644 | /* |
645 | * Set the watermark for transmit FIFI 0 and receive FIFO 0. We don't | |
646 | * use FIFO 1. We program the transmit water to signal a DMA transfer | |
647 | * if there are only two (or fewer) elements left in the FIFO. Two | |
648 | * elements equals one frame (left channel, right channel). This value, | |
649 | * however, depends on the depth of the transmit buffer. | |
650 | * | |
651 | * We set the watermark on the same level as the DMA burstsize. For | |
652 | * fiq it is probably better to use the biggest possible watermark | |
653 | * size. | |
654 | */ | |
655 | if (ssi_private->use_dma) | |
656 | wm = ssi_private->fifo_depth - 2; | |
657 | else | |
658 | wm = ssi_private->fifo_depth; | |
659 | ||
660 | write_ssi(CCSR_SSI_SFCSR_TFWM0(wm) | CCSR_SSI_SFCSR_RFWM0(wm) | | |
661 | CCSR_SSI_SFCSR_TFWM1(wm) | CCSR_SSI_SFCSR_RFWM1(wm), | |
662 | &ssi->sfcsr); | |
663 | ||
664 | if (ssi_private->use_dual_fifo) { | |
665 | write_ssi_mask(&ssi->srcr, CCSR_SSI_SRCR_RFEN1, | |
666 | CCSR_SSI_SRCR_RFEN1); | |
667 | write_ssi_mask(&ssi->stcr, CCSR_SSI_STCR_TFEN1, | |
668 | CCSR_SSI_STCR_TFEN1); | |
669 | write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_TCH_EN, | |
670 | CCSR_SSI_SCR_TCH_EN); | |
671 | } | |
672 | ||
673 | if (fmt & SND_SOC_DAIFMT_AC97) | |
674 | fsl_ssi_setup_ac97(ssi_private); | |
675 | ||
aafa85e7 NC |
676 | return 0; |
677 | } | |
678 | ||
679 | /** | |
680 | * fsl_ssi_set_dai_sysclk - configure Digital Audio Interface bit clock | |
681 | * | |
682 | * Note: This function can be only called when using SSI as DAI master | |
683 | * | |
684 | * Quick instruction for parameters: | |
685 | * freq: Output BCLK frequency = samplerate * 32 (fixed) * channels | |
686 | * dir: SND_SOC_CLOCK_OUT -> TxBCLK, SND_SOC_CLOCK_IN -> RxBCLK. | |
687 | */ | |
688 | static int fsl_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai, | |
689 | int clk_id, unsigned int freq, int dir) | |
690 | { | |
691 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); | |
692 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; | |
693 | int synchronous = ssi_private->cpu_dai_drv.symmetric_rates, ret; | |
694 | u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i; | |
695 | unsigned long flags, clkrate, baudrate, tmprate; | |
696 | u64 sub, savesub = 100000; | |
697 | ||
698 | /* Don't apply it to any non-baudclk circumstance */ | |
699 | if (IS_ERR(ssi_private->baudclk)) | |
700 | return -EINVAL; | |
701 | ||
702 | /* It should be already enough to divide clock by setting pm alone */ | |
703 | psr = 0; | |
704 | div2 = 0; | |
705 | ||
706 | factor = (div2 + 1) * (7 * psr + 1) * 2; | |
707 | ||
708 | for (i = 0; i < 255; i++) { | |
709 | /* The bclk rate must be smaller than 1/5 sysclk rate */ | |
710 | if (factor * (i + 1) < 5) | |
711 | continue; | |
712 | ||
713 | tmprate = freq * factor * (i + 2); | |
714 | clkrate = clk_round_rate(ssi_private->baudclk, tmprate); | |
715 | ||
716 | do_div(clkrate, factor); | |
717 | afreq = (u32)clkrate / (i + 1); | |
718 | ||
719 | if (freq == afreq) | |
720 | sub = 0; | |
721 | else if (freq / afreq == 1) | |
722 | sub = freq - afreq; | |
723 | else if (afreq / freq == 1) | |
724 | sub = afreq - freq; | |
725 | else | |
726 | continue; | |
727 | ||
728 | /* Calculate the fraction */ | |
729 | sub *= 100000; | |
730 | do_div(sub, freq); | |
731 | ||
732 | if (sub < savesub) { | |
733 | baudrate = tmprate; | |
734 | savesub = sub; | |
735 | pm = i; | |
736 | } | |
737 | ||
738 | /* We are lucky */ | |
739 | if (savesub == 0) | |
740 | break; | |
741 | } | |
742 | ||
743 | /* No proper pm found if it is still remaining the initial value */ | |
744 | if (pm == 999) { | |
745 | dev_err(cpu_dai->dev, "failed to handle the required sysclk\n"); | |
746 | return -EINVAL; | |
747 | } | |
748 | ||
749 | stccr = CCSR_SSI_SxCCR_PM(pm + 1) | (div2 ? CCSR_SSI_SxCCR_DIV2 : 0) | | |
750 | (psr ? CCSR_SSI_SxCCR_PSR : 0); | |
751 | mask = CCSR_SSI_SxCCR_PM_MASK | CCSR_SSI_SxCCR_DIV2 | CCSR_SSI_SxCCR_PSR; | |
752 | ||
753 | if (dir == SND_SOC_CLOCK_OUT || synchronous) | |
754 | write_ssi_mask(&ssi->stccr, mask, stccr); | |
755 | else | |
756 | write_ssi_mask(&ssi->srccr, mask, stccr); | |
757 | ||
758 | spin_lock_irqsave(&ssi_private->baudclk_lock, flags); | |
759 | if (!ssi_private->baudclk_locked) { | |
760 | ret = clk_set_rate(ssi_private->baudclk, baudrate); | |
761 | if (ret) { | |
762 | spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags); | |
763 | dev_err(cpu_dai->dev, "failed to set baudclk rate\n"); | |
764 | return -EINVAL; | |
765 | } | |
766 | ssi_private->baudclk_locked = true; | |
767 | } | |
768 | spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags); | |
769 | ||
770 | return 0; | |
771 | } | |
772 | ||
773 | /** | |
774 | * fsl_ssi_set_dai_tdm_slot - set TDM slot number | |
775 | * | |
776 | * Note: This function can be only called when using SSI as DAI master | |
777 | */ | |
778 | static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask, | |
779 | u32 rx_mask, int slots, int slot_width) | |
780 | { | |
781 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); | |
782 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; | |
783 | u32 val; | |
784 | ||
785 | /* The slot number should be >= 2 if using Network mode or I2S mode */ | |
786 | val = read_ssi(&ssi->scr) & (CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_NET); | |
787 | if (val && slots < 2) { | |
788 | dev_err(cpu_dai->dev, "slot number should be >= 2 in I2S or NET\n"); | |
789 | return -EINVAL; | |
790 | } | |
791 | ||
792 | write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_DC_MASK, | |
793 | CCSR_SSI_SxCCR_DC(slots)); | |
794 | write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_DC_MASK, | |
795 | CCSR_SSI_SxCCR_DC(slots)); | |
796 | ||
797 | /* The register SxMSKs needs SSI to provide essential clock due to | |
798 | * hardware design. So we here temporarily enable SSI to set them. | |
799 | */ | |
800 | val = read_ssi(&ssi->scr) & CCSR_SSI_SCR_SSIEN; | |
801 | write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN); | |
802 | ||
803 | write_ssi(tx_mask, &ssi->stmsk); | |
804 | write_ssi(rx_mask, &ssi->srmsk); | |
805 | ||
806 | write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, val); | |
807 | ||
808 | return 0; | |
809 | } | |
810 | ||
17467f23 TT |
811 | /** |
812 | * fsl_ssi_trigger: start and stop the DMA transfer. | |
813 | * | |
814 | * This function is called by ALSA to start, stop, pause, and resume the DMA | |
815 | * transfer of data. | |
816 | * | |
817 | * The DMA channel is in external master start and pause mode, which | |
818 | * means the SSI completely controls the flow of data. | |
819 | */ | |
dee89c4d MB |
820 | static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd, |
821 | struct snd_soc_dai *dai) | |
17467f23 TT |
822 | { |
823 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
f0fba2ad | 824 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai); |
17467f23 | 825 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; |
aafa85e7 | 826 | unsigned long flags; |
9b443e3d | 827 | |
17467f23 TT |
828 | switch (cmd) { |
829 | case SNDRV_PCM_TRIGGER_START: | |
17467f23 | 830 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
a4d11fe5 | 831 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
6de83879 | 832 | fsl_ssi_tx_config(ssi_private, true); |
a4d11fe5 | 833 | else |
6de83879 | 834 | fsl_ssi_rx_config(ssi_private, true); |
17467f23 TT |
835 | break; |
836 | ||
837 | case SNDRV_PCM_TRIGGER_STOP: | |
17467f23 TT |
838 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
839 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
6de83879 | 840 | fsl_ssi_tx_config(ssi_private, false); |
17467f23 | 841 | else |
6de83879 | 842 | fsl_ssi_rx_config(ssi_private, false); |
b2c119b0 | 843 | |
cd7f0295 | 844 | if (!ssi_private->imx_ac97 && (read_ssi(&ssi->scr) & |
aafa85e7 | 845 | (CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE)) == 0) { |
aafa85e7 NC |
846 | spin_lock_irqsave(&ssi_private->baudclk_lock, flags); |
847 | ssi_private->baudclk_locked = false; | |
848 | spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags); | |
849 | } | |
17467f23 TT |
850 | break; |
851 | ||
852 | default: | |
853 | return -EINVAL; | |
854 | } | |
855 | ||
a5a7ee7c MP |
856 | if (ssi_private->imx_ac97) { |
857 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
858 | write_ssi(CCSR_SSI_SOR_TX_CLR, &ssi->sor); | |
859 | else | |
860 | write_ssi(CCSR_SSI_SOR_RX_CLR, &ssi->sor); | |
861 | } | |
9b443e3d | 862 | |
17467f23 TT |
863 | return 0; |
864 | } | |
865 | ||
fc8ba7f9 LPC |
866 | static int fsl_ssi_dai_probe(struct snd_soc_dai *dai) |
867 | { | |
868 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(dai); | |
869 | ||
de623ece | 870 | if (ssi_private->ssi_on_imx && ssi_private->use_dma) { |
fc8ba7f9 LPC |
871 | dai->playback_dma_data = &ssi_private->dma_params_tx; |
872 | dai->capture_dma_data = &ssi_private->dma_params_rx; | |
873 | } | |
874 | ||
875 | return 0; | |
876 | } | |
877 | ||
85e7652d | 878 | static const struct snd_soc_dai_ops fsl_ssi_dai_ops = { |
6335d055 EM |
879 | .startup = fsl_ssi_startup, |
880 | .hw_params = fsl_ssi_hw_params, | |
aafa85e7 NC |
881 | .set_fmt = fsl_ssi_set_dai_fmt, |
882 | .set_sysclk = fsl_ssi_set_dai_sysclk, | |
883 | .set_tdm_slot = fsl_ssi_set_dai_tdm_slot, | |
6335d055 | 884 | .trigger = fsl_ssi_trigger, |
6335d055 EM |
885 | }; |
886 | ||
f0fba2ad LG |
887 | /* Template for the CPU dai driver structure */ |
888 | static struct snd_soc_dai_driver fsl_ssi_dai_template = { | |
fc8ba7f9 | 889 | .probe = fsl_ssi_dai_probe, |
17467f23 | 890 | .playback = { |
2924a998 | 891 | .channels_min = 1, |
17467f23 TT |
892 | .channels_max = 2, |
893 | .rates = FSLSSI_I2S_RATES, | |
894 | .formats = FSLSSI_I2S_FORMATS, | |
895 | }, | |
896 | .capture = { | |
2924a998 | 897 | .channels_min = 1, |
17467f23 TT |
898 | .channels_max = 2, |
899 | .rates = FSLSSI_I2S_RATES, | |
900 | .formats = FSLSSI_I2S_FORMATS, | |
901 | }, | |
6335d055 | 902 | .ops = &fsl_ssi_dai_ops, |
17467f23 TT |
903 | }; |
904 | ||
3580aa10 KM |
905 | static const struct snd_soc_component_driver fsl_ssi_component = { |
906 | .name = "fsl-ssi", | |
907 | }; | |
908 | ||
cd7f0295 MP |
909 | static struct snd_soc_dai_driver fsl_ssi_ac97_dai = { |
910 | .ac97_control = 1, | |
911 | .playback = { | |
912 | .stream_name = "AC97 Playback", | |
913 | .channels_min = 2, | |
914 | .channels_max = 2, | |
915 | .rates = SNDRV_PCM_RATE_8000_48000, | |
916 | .formats = SNDRV_PCM_FMTBIT_S16_LE, | |
917 | }, | |
918 | .capture = { | |
919 | .stream_name = "AC97 Capture", | |
920 | .channels_min = 2, | |
921 | .channels_max = 2, | |
922 | .rates = SNDRV_PCM_RATE_48000, | |
923 | .formats = SNDRV_PCM_FMTBIT_S16_LE, | |
924 | }, | |
a5a7ee7c | 925 | .ops = &fsl_ssi_dai_ops, |
cd7f0295 MP |
926 | }; |
927 | ||
928 | ||
929 | static struct fsl_ssi_private *fsl_ac97_data; | |
930 | ||
a851a2bb | 931 | static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg, |
cd7f0295 MP |
932 | unsigned short val) |
933 | { | |
934 | struct ccsr_ssi *ssi = fsl_ac97_data->ssi; | |
935 | unsigned int lreg; | |
936 | unsigned int lval; | |
937 | ||
938 | if (reg > 0x7f) | |
939 | return; | |
940 | ||
941 | ||
942 | lreg = reg << 12; | |
943 | write_ssi(lreg, &ssi->sacadd); | |
944 | ||
945 | lval = val << 4; | |
946 | write_ssi(lval , &ssi->sacdat); | |
947 | ||
948 | write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK, | |
949 | CCSR_SSI_SACNT_WR); | |
950 | udelay(100); | |
951 | } | |
952 | ||
a851a2bb | 953 | static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97, |
cd7f0295 MP |
954 | unsigned short reg) |
955 | { | |
956 | struct ccsr_ssi *ssi = fsl_ac97_data->ssi; | |
957 | ||
958 | unsigned short val = -1; | |
959 | unsigned int lreg; | |
960 | ||
961 | lreg = (reg & 0x7f) << 12; | |
962 | write_ssi(lreg, &ssi->sacadd); | |
963 | write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK, | |
964 | CCSR_SSI_SACNT_RD); | |
965 | ||
966 | udelay(100); | |
967 | ||
968 | val = (read_ssi(&ssi->sacdat) >> 4) & 0xffff; | |
969 | ||
970 | return val; | |
971 | } | |
972 | ||
973 | static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = { | |
974 | .read = fsl_ssi_ac97_read, | |
975 | .write = fsl_ssi_ac97_write, | |
976 | }; | |
977 | ||
17467f23 | 978 | /** |
f0fba2ad | 979 | * Make every character in a string lower-case |
17467f23 | 980 | */ |
f0fba2ad LG |
981 | static void make_lowercase(char *s) |
982 | { | |
983 | char *p = s; | |
984 | char c; | |
985 | ||
986 | while ((c = *p)) { | |
987 | if ((c >= 'A') && (c <= 'Z')) | |
988 | *p = c + ('a' - 'A'); | |
989 | p++; | |
990 | } | |
991 | } | |
992 | ||
49da09e2 MP |
993 | static int fsl_ssi_imx_probe(struct platform_device *pdev, |
994 | struct fsl_ssi_private *ssi_private) | |
995 | { | |
996 | struct device_node *np = pdev->dev.of_node; | |
ed0f1604 | 997 | u32 dmas[4]; |
49da09e2 MP |
998 | int ret; |
999 | ||
1000 | ssi_private->clk = devm_clk_get(&pdev->dev, NULL); | |
1001 | if (IS_ERR(ssi_private->clk)) { | |
1002 | ret = PTR_ERR(ssi_private->clk); | |
1003 | dev_err(&pdev->dev, "could not get clock: %d\n", ret); | |
1004 | return ret; | |
1005 | } | |
1006 | ||
1007 | ret = clk_prepare_enable(ssi_private->clk); | |
1008 | if (ret) { | |
1009 | dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret); | |
1010 | return ret; | |
1011 | } | |
1012 | ||
1013 | /* For those SLAVE implementations, we ingore non-baudclk cases | |
1014 | * and, instead, abandon MASTER mode that needs baud clock. | |
1015 | */ | |
1016 | ssi_private->baudclk = devm_clk_get(&pdev->dev, "baud"); | |
1017 | if (IS_ERR(ssi_private->baudclk)) | |
1018 | dev_dbg(&pdev->dev, "could not get baud clock: %ld\n", | |
1019 | PTR_ERR(ssi_private->baudclk)); | |
1020 | else | |
1021 | clk_prepare_enable(ssi_private->baudclk); | |
1022 | ||
1023 | /* | |
1024 | * We have burstsize be "fifo_depth - 2" to match the SSI | |
1025 | * watermark setting in fsl_ssi_startup(). | |
1026 | */ | |
1027 | ssi_private->dma_params_tx.maxburst = ssi_private->fifo_depth - 2; | |
1028 | ssi_private->dma_params_rx.maxburst = ssi_private->fifo_depth - 2; | |
1029 | ssi_private->dma_params_tx.addr = ssi_private->ssi_phys + | |
1030 | offsetof(struct ccsr_ssi, stx0); | |
1031 | ssi_private->dma_params_rx.addr = ssi_private->ssi_phys + | |
1032 | offsetof(struct ccsr_ssi, srx0); | |
49da09e2 | 1033 | |
ed0f1604 MP |
1034 | ret = !of_property_read_u32_array(np, "dmas", dmas, 4); |
1035 | if (ssi_private->use_dma && !ret && dmas[2] == IMX_DMATYPE_SSI_DUAL) { | |
49da09e2 MP |
1036 | ssi_private->use_dual_fifo = true; |
1037 | /* When using dual fifo mode, we need to keep watermark | |
1038 | * as even numbers due to dma script limitation. | |
1039 | */ | |
1040 | ssi_private->dma_params_tx.maxburst &= ~0x1; | |
1041 | ssi_private->dma_params_rx.maxburst &= ~0x1; | |
1042 | } | |
1043 | ||
49da09e2 | 1044 | return 0; |
49da09e2 MP |
1045 | } |
1046 | ||
1047 | static void fsl_ssi_imx_clean(struct platform_device *pdev, | |
1048 | struct fsl_ssi_private *ssi_private) | |
1049 | { | |
1050 | if (!IS_ERR(ssi_private->baudclk)) | |
1051 | clk_disable_unprepare(ssi_private->baudclk); | |
1052 | clk_disable_unprepare(ssi_private->clk); | |
1053 | } | |
1054 | ||
a0a3d518 | 1055 | static int fsl_ssi_probe(struct platform_device *pdev) |
17467f23 | 1056 | { |
17467f23 TT |
1057 | struct fsl_ssi_private *ssi_private; |
1058 | int ret = 0; | |
87a0632b | 1059 | struct device_attribute *dev_attr = NULL; |
38fec727 | 1060 | struct device_node *np = pdev->dev.of_node; |
c1953bfe MP |
1061 | const struct of_device_id *of_id; |
1062 | enum fsl_ssi_type hw_type; | |
f0fba2ad | 1063 | const char *p, *sprop; |
8e9d8690 | 1064 | const uint32_t *iprop; |
f0fba2ad LG |
1065 | struct resource res; |
1066 | char name[64]; | |
cd7f0295 | 1067 | bool ac97 = false; |
17467f23 | 1068 | |
ff71334a TT |
1069 | /* SSIs that are not connected on the board should have a |
1070 | * status = "disabled" | |
1071 | * property in their device tree nodes. | |
f0fba2ad | 1072 | */ |
ff71334a | 1073 | if (!of_device_is_available(np)) |
f0fba2ad LG |
1074 | return -ENODEV; |
1075 | ||
c1953bfe MP |
1076 | of_id = of_match_device(fsl_ssi_ids, &pdev->dev); |
1077 | if (!of_id) | |
1078 | return -EINVAL; | |
1079 | hw_type = (enum fsl_ssi_type) of_id->data; | |
1080 | ||
f0fba2ad | 1081 | sprop = of_get_property(np, "fsl,mode", NULL); |
cd7f0295 MP |
1082 | if (!sprop) { |
1083 | dev_err(&pdev->dev, "fsl,mode property is necessary\n"); | |
1084 | return -EINVAL; | |
1085 | } | |
ae1f8ce1 | 1086 | if (!strcmp(sprop, "ac97-slave")) |
cd7f0295 | 1087 | ac97 = true; |
f0fba2ad | 1088 | |
2a1d102d MP |
1089 | ssi_private = devm_kzalloc(&pdev->dev, sizeof(*ssi_private), |
1090 | GFP_KERNEL); | |
17467f23 | 1091 | if (!ssi_private) { |
38fec727 | 1092 | dev_err(&pdev->dev, "could not allocate DAI object\n"); |
f0fba2ad | 1093 | return -ENOMEM; |
17467f23 | 1094 | } |
17467f23 | 1095 | |
de623ece MP |
1096 | ssi_private->use_dma = !of_property_read_bool(np, |
1097 | "fsl,fiq-stream-filter"); | |
0888efd1 | 1098 | ssi_private->hw_type = hw_type; |
de623ece | 1099 | |
cd7f0295 MP |
1100 | if (ac97) { |
1101 | memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_ac97_dai, | |
1102 | sizeof(fsl_ssi_ac97_dai)); | |
1103 | ||
1104 | fsl_ac97_data = ssi_private; | |
1105 | ssi_private->imx_ac97 = true; | |
1106 | ||
1107 | snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev); | |
1108 | } else { | |
1109 | /* Initialize this copy of the CPU DAI driver structure */ | |
1110 | memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template, | |
1111 | sizeof(fsl_ssi_dai_template)); | |
1112 | } | |
2a1d102d | 1113 | ssi_private->cpu_dai_drv.name = dev_name(&pdev->dev); |
f0fba2ad LG |
1114 | |
1115 | /* Get the addresses and IRQ */ | |
1116 | ret = of_address_to_resource(np, 0, &res); | |
1117 | if (ret) { | |
38fec727 | 1118 | dev_err(&pdev->dev, "could not determine device resources\n"); |
b0a4747a | 1119 | return ret; |
f0fba2ad | 1120 | } |
147dfe90 TT |
1121 | ssi_private->ssi = of_iomap(np, 0); |
1122 | if (!ssi_private->ssi) { | |
1123 | dev_err(&pdev->dev, "could not map device resources\n"); | |
b0a4747a | 1124 | return -ENOMEM; |
147dfe90 | 1125 | } |
f0fba2ad | 1126 | ssi_private->ssi_phys = res.start; |
1fab6caf | 1127 | |
f0fba2ad | 1128 | ssi_private->irq = irq_of_parse_and_map(np, 0); |
d60336e2 | 1129 | if (!ssi_private->irq) { |
1fab6caf | 1130 | dev_err(&pdev->dev, "no irq for node %s\n", np->full_name); |
b0a4747a | 1131 | return -ENXIO; |
1fab6caf TT |
1132 | } |
1133 | ||
f0fba2ad | 1134 | /* Are the RX and the TX clocks locked? */ |
07a9483a | 1135 | if (!of_find_property(np, "fsl,ssi-asynchronous", NULL)) { |
f0fba2ad | 1136 | ssi_private->cpu_dai_drv.symmetric_rates = 1; |
07a9483a NC |
1137 | ssi_private->cpu_dai_drv.symmetric_channels = 1; |
1138 | ssi_private->cpu_dai_drv.symmetric_samplebits = 1; | |
1139 | } | |
17467f23 | 1140 | |
8e9d8690 TT |
1141 | /* Determine the FIFO depth. */ |
1142 | iprop = of_get_property(np, "fsl,fifo-depth", NULL); | |
1143 | if (iprop) | |
147dfe90 | 1144 | ssi_private->fifo_depth = be32_to_cpup(iprop); |
8e9d8690 TT |
1145 | else |
1146 | /* Older 8610 DTs didn't have the fifo-depth property */ | |
1147 | ssi_private->fifo_depth = 8; | |
1148 | ||
aafa85e7 NC |
1149 | ssi_private->baudclk_locked = false; |
1150 | spin_lock_init(&ssi_private->baudclk_lock); | |
1151 | ||
bd3ca7d1 MP |
1152 | /* |
1153 | * imx51 and later SoCs have a slightly different IP that allows the | |
1154 | * SSI configuration while the SSI unit is running. | |
1155 | * | |
1156 | * More important, it is necessary on those SoCs to configure the | |
1157 | * sperate TX/RX DMA bits just before starting the stream | |
1158 | * (fsl_ssi_trigger). The SDMA unit has to be configured before fsl_ssi | |
1159 | * sends any DMA requests to the SDMA unit, otherwise it is not defined | |
1160 | * how the SDMA unit handles the DMA request. | |
1161 | * | |
1162 | * SDMA units are present on devices starting at imx35 but the imx35 | |
1163 | * reference manual states that the DMA bits should not be changed | |
1164 | * while the SSI unit is running (SSIEN). So we support the necessary | |
1165 | * online configuration of fsl-ssi starting at imx51. | |
1166 | */ | |
1167 | switch (hw_type) { | |
1168 | case FSL_SSI_MCP8610: | |
1169 | case FSL_SSI_MX21: | |
1170 | case FSL_SSI_MX35: | |
1171 | ssi_private->offline_config = true; | |
1172 | break; | |
1173 | case FSL_SSI_MX51: | |
1174 | ssi_private->offline_config = false; | |
1175 | break; | |
1176 | } | |
1177 | ||
c1953bfe MP |
1178 | if (hw_type == FSL_SSI_MX21 || hw_type == FSL_SSI_MX51 || |
1179 | hw_type == FSL_SSI_MX35) { | |
09ce1111 | 1180 | ssi_private->ssi_on_imx = true; |
95cd98f9 | 1181 | |
49da09e2 MP |
1182 | ret = fsl_ssi_imx_probe(pdev, ssi_private); |
1183 | if (ret) | |
b0a4747a | 1184 | goto error_irqmap; |
0888efd1 MP |
1185 | } |
1186 | ||
1187 | /* | |
1188 | * Enable interrupts only for MCP8610 and MX51. The other MXs have | |
1189 | * different writeable interrupt status registers. | |
1190 | */ | |
1191 | if (ssi_private->use_dma) { | |
f0377086 MG |
1192 | ret = devm_request_irq(&pdev->dev, ssi_private->irq, |
1193 | fsl_ssi_isr, 0, ssi_private->name, | |
1194 | ssi_private); | |
2841be9a | 1195 | ssi_private->irq_stats = true; |
f0377086 MG |
1196 | if (ret < 0) { |
1197 | dev_err(&pdev->dev, "could not claim irq %u\n", | |
1198 | ssi_private->irq); | |
49da09e2 | 1199 | goto error_irq; |
f0377086 | 1200 | } |
09ce1111 SG |
1201 | } |
1202 | ||
f0fba2ad | 1203 | /* Register with ASoC */ |
38fec727 | 1204 | dev_set_drvdata(&pdev->dev, ssi_private); |
3f4b783c | 1205 | |
3580aa10 KM |
1206 | ret = snd_soc_register_component(&pdev->dev, &fsl_ssi_component, |
1207 | &ssi_private->cpu_dai_drv, 1); | |
87a0632b | 1208 | if (ret) { |
38fec727 | 1209 | dev_err(&pdev->dev, "failed to register DAI: %d\n", ret); |
1fab6caf | 1210 | goto error_dev; |
f0fba2ad LG |
1211 | } |
1212 | ||
f138e621 | 1213 | ret = fsl_ssi_debugfs_create(&ssi_private->dbg_stats, &pdev->dev); |
9368acc4 MP |
1214 | if (ret) |
1215 | goto error_dbgfs; | |
1216 | ||
09ce1111 | 1217 | if (ssi_private->ssi_on_imx) { |
de623ece MP |
1218 | if (!ssi_private->use_dma) { |
1219 | ||
1220 | /* | |
1221 | * Some boards use an incompatible codec. To get it | |
1222 | * working, we are using imx-fiq-pcm-audio, that | |
1223 | * can handle those codecs. DMA is not possible in this | |
1224 | * situation. | |
1225 | */ | |
1226 | ||
1227 | ssi_private->fiq_params.irq = ssi_private->irq; | |
1228 | ssi_private->fiq_params.base = ssi_private->ssi; | |
1229 | ssi_private->fiq_params.dma_params_rx = | |
1230 | &ssi_private->dma_params_rx; | |
1231 | ssi_private->fiq_params.dma_params_tx = | |
1232 | &ssi_private->dma_params_tx; | |
1233 | ||
1234 | ret = imx_pcm_fiq_init(pdev, &ssi_private->fiq_params); | |
1235 | if (ret) | |
2841be9a | 1236 | goto error_pcm; |
de623ece MP |
1237 | } else { |
1238 | ret = imx_pcm_dma_init(pdev); | |
1239 | if (ret) | |
2841be9a | 1240 | goto error_pcm; |
de623ece | 1241 | } |
09ce1111 SG |
1242 | } |
1243 | ||
1244 | /* | |
1245 | * If codec-handle property is missing from SSI node, we assume | |
1246 | * that the machine driver uses new binding which does not require | |
1247 | * SSI driver to trigger machine driver's probe. | |
1248 | */ | |
1249 | if (!of_get_property(np, "codec-handle", NULL)) { | |
1250 | ssi_private->new_binding = true; | |
1251 | goto done; | |
1252 | } | |
1253 | ||
f0fba2ad | 1254 | /* Trigger the machine driver's probe function. The platform driver |
2b81ec69 | 1255 | * name of the machine driver is taken from /compatible property of the |
f0fba2ad LG |
1256 | * device tree. We also pass the address of the CPU DAI driver |
1257 | * structure. | |
1258 | */ | |
2b81ec69 SG |
1259 | sprop = of_get_property(of_find_node_by_path("/"), "compatible", NULL); |
1260 | /* Sometimes the compatible name has a "fsl," prefix, so we strip it. */ | |
f0fba2ad LG |
1261 | p = strrchr(sprop, ','); |
1262 | if (p) | |
1263 | sprop = p + 1; | |
1264 | snprintf(name, sizeof(name), "snd-soc-%s", sprop); | |
1265 | make_lowercase(name); | |
1266 | ||
1267 | ssi_private->pdev = | |
38fec727 | 1268 | platform_device_register_data(&pdev->dev, name, 0, NULL, 0); |
f0fba2ad LG |
1269 | if (IS_ERR(ssi_private->pdev)) { |
1270 | ret = PTR_ERR(ssi_private->pdev); | |
38fec727 | 1271 | dev_err(&pdev->dev, "failed to register platform: %d\n", ret); |
1fab6caf | 1272 | goto error_dai; |
3f4b783c | 1273 | } |
17467f23 | 1274 | |
09ce1111 | 1275 | done: |
f0fba2ad | 1276 | return 0; |
87a0632b | 1277 | |
1fab6caf | 1278 | error_dai: |
2841be9a MP |
1279 | if (ssi_private->ssi_on_imx && !ssi_private->use_dma) |
1280 | imx_pcm_fiq_exit(pdev); | |
1281 | ||
1282 | error_pcm: | |
f138e621 | 1283 | fsl_ssi_debugfs_remove(&ssi_private->dbg_stats); |
9368acc4 MP |
1284 | |
1285 | error_dbgfs: | |
3580aa10 | 1286 | snd_soc_unregister_component(&pdev->dev); |
1fab6caf TT |
1287 | |
1288 | error_dev: | |
1fab6caf TT |
1289 | device_remove_file(&pdev->dev, dev_attr); |
1290 | ||
49da09e2 | 1291 | error_irq: |
aafa85e7 | 1292 | if (ssi_private->ssi_on_imx) { |
49da09e2 | 1293 | fsl_ssi_imx_clean(pdev, ssi_private); |
aafa85e7 | 1294 | } |
1fab6caf TT |
1295 | |
1296 | error_irqmap: | |
2841be9a MP |
1297 | if (ssi_private->irq_stats) |
1298 | irq_dispose_mapping(ssi_private->irq); | |
1fab6caf | 1299 | |
87a0632b | 1300 | return ret; |
17467f23 | 1301 | } |
17467f23 | 1302 | |
38fec727 | 1303 | static int fsl_ssi_remove(struct platform_device *pdev) |
17467f23 | 1304 | { |
38fec727 | 1305 | struct fsl_ssi_private *ssi_private = dev_get_drvdata(&pdev->dev); |
17467f23 | 1306 | |
f138e621 | 1307 | fsl_ssi_debugfs_remove(&ssi_private->dbg_stats); |
9368acc4 | 1308 | |
09ce1111 SG |
1309 | if (!ssi_private->new_binding) |
1310 | platform_device_unregister(ssi_private->pdev); | |
3580aa10 | 1311 | snd_soc_unregister_component(&pdev->dev); |
49da09e2 MP |
1312 | |
1313 | if (ssi_private->ssi_on_imx) | |
1314 | fsl_ssi_imx_clean(pdev, ssi_private); | |
1315 | ||
2841be9a MP |
1316 | if (ssi_private->irq_stats) |
1317 | irq_dispose_mapping(ssi_private->irq); | |
f0fba2ad LG |
1318 | |
1319 | return 0; | |
17467f23 | 1320 | } |
f0fba2ad | 1321 | |
f07eb223 | 1322 | static struct platform_driver fsl_ssi_driver = { |
f0fba2ad LG |
1323 | .driver = { |
1324 | .name = "fsl-ssi-dai", | |
1325 | .owner = THIS_MODULE, | |
1326 | .of_match_table = fsl_ssi_ids, | |
1327 | }, | |
1328 | .probe = fsl_ssi_probe, | |
1329 | .remove = fsl_ssi_remove, | |
1330 | }; | |
17467f23 | 1331 | |
ba0a7e02 | 1332 | module_platform_driver(fsl_ssi_driver); |
a454dad1 | 1333 | |
f3142807 | 1334 | MODULE_ALIAS("platform:fsl-ssi-dai"); |
17467f23 TT |
1335 | MODULE_AUTHOR("Timur Tabi <timur@freescale.com>"); |
1336 | MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver"); | |
f0fba2ad | 1337 | MODULE_LICENSE("GPL v2"); |