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17467f23 TT |
1 | /* |
2 | * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver | |
3 | * | |
4 | * Author: Timur Tabi <timur@freescale.com> | |
5 | * | |
f0fba2ad LG |
6 | * Copyright 2007-2010 Freescale Semiconductor, Inc. |
7 | * | |
8 | * This file is licensed under the terms of the GNU General Public License | |
9 | * version 2. This program is licensed "as is" without any warranty of any | |
10 | * kind, whether express or implied. | |
de623ece MP |
11 | * |
12 | * | |
13 | * Some notes why imx-pcm-fiq is used instead of DMA on some boards: | |
14 | * | |
15 | * The i.MX SSI core has some nasty limitations in AC97 mode. While most | |
16 | * sane processor vendors have a FIFO per AC97 slot, the i.MX has only | |
17 | * one FIFO which combines all valid receive slots. We cannot even select | |
18 | * which slots we want to receive. The WM9712 with which this driver | |
19 | * was developed with always sends GPIO status data in slot 12 which | |
20 | * we receive in our (PCM-) data stream. The only chance we have is to | |
21 | * manually skip this data in the FIQ handler. With sampling rates different | |
22 | * from 48000Hz not every frame has valid receive data, so the ratio | |
23 | * between pcm data and GPIO status data changes. Our FIQ handler is not | |
24 | * able to handle this, hence this driver only works with 48000Hz sampling | |
25 | * rate. | |
26 | * Reading and writing AC97 registers is another challenge. The core | |
27 | * provides us status bits when the read register is updated with *another* | |
28 | * value. When we read the same register two times (and the register still | |
29 | * contains the same value) these status bits are not set. We work | |
30 | * around this by not polling these bits but only wait a fixed delay. | |
17467f23 TT |
31 | */ |
32 | ||
33 | #include <linux/init.h> | |
dfa1a107 | 34 | #include <linux/io.h> |
17467f23 TT |
35 | #include <linux/module.h> |
36 | #include <linux/interrupt.h> | |
95cd98f9 | 37 | #include <linux/clk.h> |
17467f23 TT |
38 | #include <linux/device.h> |
39 | #include <linux/delay.h> | |
5a0e3ad6 | 40 | #include <linux/slab.h> |
aafa85e7 | 41 | #include <linux/spinlock.h> |
dfa1a107 SG |
42 | #include <linux/of_address.h> |
43 | #include <linux/of_irq.h> | |
f0fba2ad | 44 | #include <linux/of_platform.h> |
17467f23 | 45 | |
17467f23 TT |
46 | #include <sound/core.h> |
47 | #include <sound/pcm.h> | |
48 | #include <sound/pcm_params.h> | |
49 | #include <sound/initval.h> | |
50 | #include <sound/soc.h> | |
a8909c9b | 51 | #include <sound/dmaengine_pcm.h> |
17467f23 | 52 | |
17467f23 | 53 | #include "fsl_ssi.h" |
09ce1111 | 54 | #include "imx-pcm.h" |
17467f23 | 55 | |
dfa1a107 SG |
56 | #ifdef PPC |
57 | #define read_ssi(addr) in_be32(addr) | |
58 | #define write_ssi(val, addr) out_be32(addr, val) | |
59 | #define write_ssi_mask(addr, clear, set) clrsetbits_be32(addr, clear, set) | |
0a9eaa39 | 60 | #else |
dfa1a107 SG |
61 | #define read_ssi(addr) readl(addr) |
62 | #define write_ssi(val, addr) writel(val, addr) | |
63 | /* | |
64 | * FIXME: Proper locking should be added at write_ssi_mask caller level | |
65 | * to ensure this register read/modify/write sequence is race free. | |
66 | */ | |
67 | static inline void write_ssi_mask(u32 __iomem *addr, u32 clear, u32 set) | |
68 | { | |
69 | u32 val = readl(addr); | |
70 | val = (val & ~clear) | set; | |
71 | writel(val, addr); | |
72 | } | |
73 | #endif | |
74 | ||
17467f23 TT |
75 | /** |
76 | * FSLSSI_I2S_RATES: sample rates supported by the I2S | |
77 | * | |
78 | * This driver currently only supports the SSI running in I2S slave mode, | |
79 | * which means the codec determines the sample rate. Therefore, we tell | |
80 | * ALSA that we support all rates and let the codec driver decide what rates | |
81 | * are really supported. | |
82 | */ | |
24710c97 | 83 | #define FSLSSI_I2S_RATES SNDRV_PCM_RATE_CONTINUOUS |
17467f23 TT |
84 | |
85 | /** | |
86 | * FSLSSI_I2S_FORMATS: audio formats supported by the SSI | |
87 | * | |
88 | * This driver currently only supports the SSI running in I2S slave mode. | |
89 | * | |
90 | * The SSI has a limitation in that the samples must be in the same byte | |
91 | * order as the host CPU. This is because when multiple bytes are written | |
92 | * to the STX register, the bytes and bits must be written in the same | |
93 | * order. The STX is a shift register, so all the bits need to be aligned | |
94 | * (bit-endianness must match byte-endianness). Processors typically write | |
95 | * the bits within a byte in the same order that the bytes of a word are | |
96 | * written in. So if the host CPU is big-endian, then only big-endian | |
97 | * samples will be written to STX properly. | |
98 | */ | |
99 | #ifdef __BIG_ENDIAN | |
100 | #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \ | |
101 | SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \ | |
102 | SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE) | |
103 | #else | |
104 | #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \ | |
105 | SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \ | |
106 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE) | |
107 | #endif | |
108 | ||
9368acc4 MP |
109 | #define FSLSSI_SIER_DBG_RX_FLAGS (CCSR_SSI_SIER_RFF0_EN | \ |
110 | CCSR_SSI_SIER_RLS_EN | CCSR_SSI_SIER_RFS_EN | \ | |
111 | CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_RFRC_EN) | |
112 | #define FSLSSI_SIER_DBG_TX_FLAGS (CCSR_SSI_SIER_TFE0_EN | \ | |
113 | CCSR_SSI_SIER_TLS_EN | CCSR_SSI_SIER_TFS_EN | \ | |
114 | CCSR_SSI_SIER_TUE0_EN | CCSR_SSI_SIER_TFRC_EN) | |
c1953bfe MP |
115 | |
116 | enum fsl_ssi_type { | |
117 | FSL_SSI_MCP8610, | |
118 | FSL_SSI_MX21, | |
0888efd1 | 119 | FSL_SSI_MX35, |
c1953bfe MP |
120 | FSL_SSI_MX51, |
121 | }; | |
122 | ||
4e6ec0d9 MP |
123 | struct fsl_ssi_reg_val { |
124 | u32 sier; | |
125 | u32 srcr; | |
126 | u32 stcr; | |
127 | u32 scr; | |
128 | }; | |
129 | ||
130 | struct fsl_ssi_rxtx_reg_val { | |
131 | struct fsl_ssi_reg_val rx; | |
132 | struct fsl_ssi_reg_val tx; | |
133 | }; | |
d5a908b2 | 134 | |
17467f23 TT |
135 | /** |
136 | * fsl_ssi_private: per-SSI private data | |
137 | * | |
17467f23 TT |
138 | * @ssi: pointer to the SSI's registers |
139 | * @ssi_phys: physical address of the SSI registers | |
140 | * @irq: IRQ of this SSI | |
17467f23 TT |
141 | * @playback: the number of playback streams opened |
142 | * @capture: the number of capture streams opened | |
143 | * @cpu_dai: the CPU DAI for this device | |
144 | * @dev_attr: the sysfs device attribute structure | |
145 | * @stats: SSI statistics | |
146 | */ | |
147 | struct fsl_ssi_private { | |
17467f23 TT |
148 | struct ccsr_ssi __iomem *ssi; |
149 | dma_addr_t ssi_phys; | |
150 | unsigned int irq; | |
8e9d8690 | 151 | unsigned int fifo_depth; |
f0fba2ad | 152 | struct snd_soc_dai_driver cpu_dai_drv; |
f0fba2ad | 153 | struct platform_device *pdev; |
171d683d | 154 | unsigned int dai_fmt; |
17467f23 | 155 | |
0888efd1 | 156 | enum fsl_ssi_type hw_type; |
de623ece | 157 | bool use_dma; |
aafa85e7 | 158 | bool baudclk_locked; |
0da9e55e | 159 | bool use_dual_fifo; |
2924a998 | 160 | u8 i2s_mode; |
aafa85e7 NC |
161 | spinlock_t baudclk_lock; |
162 | struct clk *baudclk; | |
95cd98f9 | 163 | struct clk *clk; |
a8909c9b LPC |
164 | struct snd_dmaengine_dai_dma_data dma_params_tx; |
165 | struct snd_dmaengine_dai_dma_data dma_params_rx; | |
de623ece | 166 | struct imx_pcm_fiq_params fiq_params; |
4e6ec0d9 MP |
167 | /* Register values for rx/tx configuration */ |
168 | struct fsl_ssi_rxtx_reg_val rxtx_reg_val; | |
09ce1111 | 169 | |
f138e621 | 170 | struct fsl_ssi_dbg dbg_stats; |
17467f23 TT |
171 | }; |
172 | ||
c1953bfe MP |
173 | static const struct of_device_id fsl_ssi_ids[] = { |
174 | { .compatible = "fsl,mpc8610-ssi", .data = (void *) FSL_SSI_MCP8610}, | |
175 | { .compatible = "fsl,imx51-ssi", .data = (void *) FSL_SSI_MX51}, | |
0888efd1 | 176 | { .compatible = "fsl,imx35-ssi", .data = (void *) FSL_SSI_MX35}, |
c1953bfe MP |
177 | { .compatible = "fsl,imx21-ssi", .data = (void *) FSL_SSI_MX21}, |
178 | {} | |
179 | }; | |
180 | MODULE_DEVICE_TABLE(of, fsl_ssi_ids); | |
181 | ||
171d683d MP |
182 | static bool fsl_ssi_is_ac97(struct fsl_ssi_private *ssi_private) |
183 | { | |
184 | return !!(ssi_private->dai_fmt & SND_SOC_DAIFMT_AC97); | |
185 | } | |
186 | ||
187 | static bool fsl_ssi_on_imx(struct fsl_ssi_private *ssi_private) | |
188 | { | |
189 | switch (ssi_private->hw_type) { | |
190 | case FSL_SSI_MX21: | |
191 | case FSL_SSI_MX35: | |
192 | case FSL_SSI_MX51: | |
193 | return true; | |
194 | case FSL_SSI_MCP8610: | |
195 | return false; | |
196 | } | |
197 | ||
198 | return false; | |
199 | } | |
200 | ||
201 | /* | |
202 | * imx51 and later SoCs have a slightly different IP that allows the | |
203 | * SSI configuration while the SSI unit is running. | |
204 | * | |
205 | * More important, it is necessary on those SoCs to configure the | |
206 | * sperate TX/RX DMA bits just before starting the stream | |
207 | * (fsl_ssi_trigger). The SDMA unit has to be configured before fsl_ssi | |
208 | * sends any DMA requests to the SDMA unit, otherwise it is not defined | |
209 | * how the SDMA unit handles the DMA request. | |
210 | * | |
211 | * SDMA units are present on devices starting at imx35 but the imx35 | |
212 | * reference manual states that the DMA bits should not be changed | |
213 | * while the SSI unit is running (SSIEN). So we support the necessary | |
214 | * online configuration of fsl-ssi starting at imx51. | |
215 | */ | |
216 | static bool fsl_ssi_offline_config(struct fsl_ssi_private *ssi_private) | |
217 | { | |
218 | switch (ssi_private->hw_type) { | |
219 | case FSL_SSI_MCP8610: | |
220 | case FSL_SSI_MX21: | |
221 | case FSL_SSI_MX35: | |
222 | return true; | |
223 | case FSL_SSI_MX51: | |
224 | return false; | |
225 | } | |
226 | ||
227 | return true; | |
228 | } | |
229 | ||
17467f23 TT |
230 | /** |
231 | * fsl_ssi_isr: SSI interrupt handler | |
232 | * | |
233 | * Although it's possible to use the interrupt handler to send and receive | |
234 | * data to/from the SSI, we use the DMA instead. Programming is more | |
235 | * complicated, but the performance is much better. | |
236 | * | |
237 | * This interrupt handler is used only to gather statistics. | |
238 | * | |
239 | * @irq: IRQ of the SSI device | |
240 | * @dev_id: pointer to the ssi_private structure for this SSI device | |
241 | */ | |
242 | static irqreturn_t fsl_ssi_isr(int irq, void *dev_id) | |
243 | { | |
244 | struct fsl_ssi_private *ssi_private = dev_id; | |
245 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; | |
17467f23 | 246 | __be32 sisr; |
0888efd1 MP |
247 | __be32 sisr2; |
248 | __be32 sisr_write_mask = 0; | |
249 | ||
250 | switch (ssi_private->hw_type) { | |
251 | case FSL_SSI_MX21: | |
252 | sisr_write_mask = 0; | |
253 | break; | |
254 | ||
255 | case FSL_SSI_MCP8610: | |
256 | case FSL_SSI_MX35: | |
257 | sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC | | |
258 | CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 | | |
259 | CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1; | |
260 | break; | |
261 | ||
262 | case FSL_SSI_MX51: | |
263 | sisr_write_mask = CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 | | |
264 | CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1; | |
265 | break; | |
266 | } | |
17467f23 TT |
267 | |
268 | /* We got an interrupt, so read the status register to see what we | |
269 | were interrupted for. We mask it with the Interrupt Enable register | |
270 | so that we only check for events that we're interested in. | |
271 | */ | |
f138e621 | 272 | sisr = read_ssi(&ssi->sisr); |
17467f23 | 273 | |
0888efd1 | 274 | sisr2 = sisr & sisr_write_mask; |
17467f23 TT |
275 | /* Clear the bits that we set */ |
276 | if (sisr2) | |
dfa1a107 | 277 | write_ssi(sisr2, &ssi->sisr); |
17467f23 | 278 | |
f138e621 | 279 | fsl_ssi_dbg_isr(&ssi_private->dbg_stats, sisr); |
9368acc4 | 280 | |
f138e621 | 281 | return IRQ_HANDLED; |
9368acc4 MP |
282 | } |
283 | ||
4e6ec0d9 MP |
284 | /* |
285 | * Enable/Disable all rx/tx config flags at once. | |
286 | */ | |
287 | static void fsl_ssi_rxtx_config(struct fsl_ssi_private *ssi_private, | |
288 | bool enable) | |
289 | { | |
290 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; | |
291 | struct fsl_ssi_rxtx_reg_val *vals = &ssi_private->rxtx_reg_val; | |
292 | ||
293 | if (enable) { | |
294 | write_ssi_mask(&ssi->sier, 0, vals->rx.sier | vals->tx.sier); | |
295 | write_ssi_mask(&ssi->srcr, 0, vals->rx.srcr | vals->tx.srcr); | |
296 | write_ssi_mask(&ssi->stcr, 0, vals->rx.stcr | vals->tx.stcr); | |
297 | } else { | |
298 | write_ssi_mask(&ssi->srcr, vals->rx.srcr | vals->tx.srcr, 0); | |
299 | write_ssi_mask(&ssi->stcr, vals->rx.stcr | vals->tx.stcr, 0); | |
300 | write_ssi_mask(&ssi->sier, vals->rx.sier | vals->tx.sier, 0); | |
301 | } | |
302 | } | |
303 | ||
65c961cc MP |
304 | /* |
305 | * Calculate the bits that have to be disabled for the current stream that is | |
306 | * getting disabled. This keeps the bits enabled that are necessary for the | |
307 | * second stream to work if 'stream_active' is true. | |
308 | * | |
309 | * Detailed calculation: | |
310 | * These are the values that need to be active after disabling. For non-active | |
311 | * second stream, this is 0: | |
312 | * vals_stream * !!stream_active | |
313 | * | |
314 | * The following computes the overall differences between the setup for the | |
315 | * to-disable stream and the active stream, a simple XOR: | |
316 | * vals_disable ^ (vals_stream * !!(stream_active)) | |
317 | * | |
318 | * The full expression adds a mask on all values we care about | |
319 | */ | |
320 | #define fsl_ssi_disable_val(vals_disable, vals_stream, stream_active) \ | |
321 | ((vals_disable) & \ | |
322 | ((vals_disable) ^ ((vals_stream) * (u32)!!(stream_active)))) | |
323 | ||
4e6ec0d9 MP |
324 | /* |
325 | * Enable/Disable a ssi configuration. You have to pass either | |
326 | * ssi_private->rxtx_reg_val.rx or tx as vals parameter. | |
327 | */ | |
328 | static void fsl_ssi_config(struct fsl_ssi_private *ssi_private, bool enable, | |
329 | struct fsl_ssi_reg_val *vals) | |
330 | { | |
331 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; | |
332 | struct fsl_ssi_reg_val *avals; | |
333 | u32 scr_val = read_ssi(&ssi->scr); | |
334 | int nr_active_streams = !!(scr_val & CCSR_SSI_SCR_TE) + | |
335 | !!(scr_val & CCSR_SSI_SCR_RE); | |
65c961cc MP |
336 | int keep_active; |
337 | ||
338 | if (nr_active_streams - 1 > 0) | |
339 | keep_active = 1; | |
340 | else | |
341 | keep_active = 0; | |
4e6ec0d9 MP |
342 | |
343 | /* Find the other direction values rx or tx which we do not want to | |
344 | * modify */ | |
345 | if (&ssi_private->rxtx_reg_val.rx == vals) | |
346 | avals = &ssi_private->rxtx_reg_val.tx; | |
347 | else | |
348 | avals = &ssi_private->rxtx_reg_val.rx; | |
349 | ||
350 | /* If vals should be disabled, start with disabling the unit */ | |
351 | if (!enable) { | |
65c961cc MP |
352 | u32 scr = fsl_ssi_disable_val(vals->scr, avals->scr, |
353 | keep_active); | |
4e6ec0d9 MP |
354 | write_ssi_mask(&ssi->scr, scr, 0); |
355 | } | |
356 | ||
357 | /* | |
358 | * We are running on a SoC which does not support online SSI | |
359 | * reconfiguration, so we have to enable all necessary flags at once | |
360 | * even if we do not use them later (capture and playback configuration) | |
361 | */ | |
171d683d | 362 | if (fsl_ssi_offline_config(ssi_private)) { |
4e6ec0d9 | 363 | if ((enable && !nr_active_streams) || |
65c961cc | 364 | (!enable && !keep_active)) |
4e6ec0d9 MP |
365 | fsl_ssi_rxtx_config(ssi_private, enable); |
366 | ||
367 | goto config_done; | |
368 | } | |
369 | ||
370 | /* | |
371 | * Configure single direction units while the SSI unit is running | |
372 | * (online configuration) | |
373 | */ | |
374 | if (enable) { | |
375 | write_ssi_mask(&ssi->sier, 0, vals->sier); | |
376 | write_ssi_mask(&ssi->srcr, 0, vals->srcr); | |
377 | write_ssi_mask(&ssi->stcr, 0, vals->stcr); | |
378 | } else { | |
379 | u32 sier; | |
380 | u32 srcr; | |
381 | u32 stcr; | |
382 | ||
383 | /* | |
384 | * Disabling the necessary flags for one of rx/tx while the | |
385 | * other stream is active is a little bit more difficult. We | |
386 | * have to disable only those flags that differ between both | |
387 | * streams (rx XOR tx) and that are set in the stream that is | |
388 | * disabled now. Otherwise we could alter flags of the other | |
389 | * stream | |
390 | */ | |
391 | ||
392 | /* These assignments are simply vals without bits set in avals*/ | |
65c961cc MP |
393 | sier = fsl_ssi_disable_val(vals->sier, avals->sier, |
394 | keep_active); | |
395 | srcr = fsl_ssi_disable_val(vals->srcr, avals->srcr, | |
396 | keep_active); | |
397 | stcr = fsl_ssi_disable_val(vals->stcr, avals->stcr, | |
398 | keep_active); | |
4e6ec0d9 MP |
399 | |
400 | write_ssi_mask(&ssi->srcr, srcr, 0); | |
401 | write_ssi_mask(&ssi->stcr, stcr, 0); | |
402 | write_ssi_mask(&ssi->sier, sier, 0); | |
403 | } | |
404 | ||
405 | config_done: | |
406 | /* Enabling of subunits is done after configuration */ | |
407 | if (enable) | |
408 | write_ssi_mask(&ssi->scr, 0, vals->scr); | |
409 | } | |
410 | ||
411 | ||
412 | static void fsl_ssi_rx_config(struct fsl_ssi_private *ssi_private, bool enable) | |
413 | { | |
414 | fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.rx); | |
415 | } | |
416 | ||
417 | static void fsl_ssi_tx_config(struct fsl_ssi_private *ssi_private, bool enable) | |
418 | { | |
419 | fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.tx); | |
420 | } | |
421 | ||
6de83879 MP |
422 | /* |
423 | * Setup rx/tx register values used to enable/disable the streams. These will | |
424 | * be used later in fsl_ssi_config to setup the streams without the need to | |
425 | * check for all different SSI modes. | |
426 | */ | |
427 | static void fsl_ssi_setup_reg_vals(struct fsl_ssi_private *ssi_private) | |
428 | { | |
429 | struct fsl_ssi_rxtx_reg_val *reg = &ssi_private->rxtx_reg_val; | |
430 | ||
431 | reg->rx.sier = CCSR_SSI_SIER_RFF0_EN; | |
432 | reg->rx.srcr = CCSR_SSI_SRCR_RFEN0; | |
433 | reg->rx.scr = 0; | |
434 | reg->tx.sier = CCSR_SSI_SIER_TFE0_EN; | |
435 | reg->tx.stcr = CCSR_SSI_STCR_TFEN0; | |
436 | reg->tx.scr = 0; | |
437 | ||
171d683d | 438 | if (!fsl_ssi_is_ac97(ssi_private)) { |
6de83879 MP |
439 | reg->rx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE; |
440 | reg->rx.sier |= CCSR_SSI_SIER_RFF0_EN; | |
441 | reg->tx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE; | |
442 | reg->tx.sier |= CCSR_SSI_SIER_TFE0_EN; | |
443 | } | |
444 | ||
445 | if (ssi_private->use_dma) { | |
446 | reg->rx.sier |= CCSR_SSI_SIER_RDMAE; | |
447 | reg->tx.sier |= CCSR_SSI_SIER_TDMAE; | |
448 | } else { | |
449 | reg->rx.sier |= CCSR_SSI_SIER_RIE; | |
450 | reg->tx.sier |= CCSR_SSI_SIER_TIE; | |
451 | } | |
452 | ||
453 | reg->rx.sier |= FSLSSI_SIER_DBG_RX_FLAGS; | |
454 | reg->tx.sier |= FSLSSI_SIER_DBG_TX_FLAGS; | |
455 | } | |
456 | ||
d8764646 MP |
457 | static void fsl_ssi_setup_ac97(struct fsl_ssi_private *ssi_private) |
458 | { | |
459 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; | |
460 | ||
461 | /* | |
462 | * Setup the clock control register | |
463 | */ | |
464 | write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13), | |
465 | &ssi->stccr); | |
466 | write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13), | |
467 | &ssi->srccr); | |
468 | ||
469 | /* | |
470 | * Enable AC97 mode and startup the SSI | |
471 | */ | |
472 | write_ssi(CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV, | |
473 | &ssi->sacnt); | |
474 | write_ssi(0xff, &ssi->saccdis); | |
475 | write_ssi(0x300, &ssi->saccen); | |
476 | ||
477 | /* | |
478 | * Enable SSI, Transmit and Receive. AC97 has to communicate with the | |
479 | * codec before a stream is started. | |
480 | */ | |
481 | write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN | | |
482 | CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE); | |
483 | ||
484 | write_ssi(CCSR_SSI_SOR_WAIT(3), &ssi->sor); | |
485 | } | |
486 | ||
17467f23 TT |
487 | /** |
488 | * fsl_ssi_startup: create a new substream | |
489 | * | |
490 | * This is the first function called when a stream is opened. | |
491 | * | |
492 | * If this is the first stream open, then grab the IRQ and program most of | |
493 | * the SSI registers. | |
494 | */ | |
dee89c4d MB |
495 | static int fsl_ssi_startup(struct snd_pcm_substream *substream, |
496 | struct snd_soc_dai *dai) | |
17467f23 TT |
497 | { |
498 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
5e538eca TT |
499 | struct fsl_ssi_private *ssi_private = |
500 | snd_soc_dai_get_drvdata(rtd->cpu_dai); | |
aafa85e7 | 501 | unsigned long flags; |
17467f23 | 502 | |
171d683d | 503 | if (!dai->active && !fsl_ssi_is_ac97(ssi_private)) { |
aafa85e7 NC |
504 | spin_lock_irqsave(&ssi_private->baudclk_lock, flags); |
505 | ssi_private->baudclk_locked = false; | |
506 | spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags); | |
507 | } | |
be41e941 | 508 | |
0da9e55e NC |
509 | /* When using dual fifo mode, it is safer to ensure an even period |
510 | * size. If appearing to an odd number while DMA always starts its | |
511 | * task from fifo0, fifo1 would be neglected at the end of each | |
512 | * period. But SSI would still access fifo1 with an invalid data. | |
513 | */ | |
514 | if (ssi_private->use_dual_fifo) | |
515 | snd_pcm_hw_constraint_step(substream->runtime, 0, | |
516 | SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2); | |
517 | ||
17467f23 TT |
518 | return 0; |
519 | } | |
520 | ||
521 | /** | |
85ef2375 | 522 | * fsl_ssi_hw_params - program the sample size |
17467f23 TT |
523 | * |
524 | * Most of the SSI registers have been programmed in the startup function, | |
525 | * but the word length must be programmed here. Unfortunately, programming | |
526 | * the SxCCR.WL bits requires the SSI to be temporarily disabled. This can | |
527 | * cause a problem with supporting simultaneous playback and capture. If | |
528 | * the SSI is already playing a stream, then that stream may be temporarily | |
529 | * stopped when you start capture. | |
530 | * | |
531 | * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the | |
532 | * clock master. | |
533 | */ | |
85ef2375 TT |
534 | static int fsl_ssi_hw_params(struct snd_pcm_substream *substream, |
535 | struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai) | |
17467f23 | 536 | { |
f0fba2ad | 537 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); |
5e538eca | 538 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; |
2924a998 | 539 | unsigned int channels = params_channels(hw_params); |
5e538eca TT |
540 | unsigned int sample_size = |
541 | snd_pcm_format_width(params_format(hw_params)); | |
542 | u32 wl = CCSR_SSI_SxCCR_WL(sample_size); | |
dfa1a107 | 543 | int enabled = read_ssi(&ssi->scr) & CCSR_SSI_SCR_SSIEN; |
17467f23 | 544 | |
5e538eca TT |
545 | /* |
546 | * If we're in synchronous mode, and the SSI is already enabled, | |
547 | * then STCCR is already set properly. | |
548 | */ | |
549 | if (enabled && ssi_private->cpu_dai_drv.symmetric_rates) | |
550 | return 0; | |
17467f23 | 551 | |
5e538eca TT |
552 | /* |
553 | * FIXME: The documentation says that SxCCR[WL] should not be | |
554 | * modified while the SSI is enabled. The only time this can | |
555 | * happen is if we're trying to do simultaneous playback and | |
556 | * capture in asynchronous mode. Unfortunately, I have been enable | |
557 | * to get that to work at all on the P1022DS. Therefore, we don't | |
558 | * bother to disable/enable the SSI when setting SxCCR[WL], because | |
559 | * the SSI will stop anyway. Maybe one day, this will get fixed. | |
560 | */ | |
17467f23 | 561 | |
5e538eca TT |
562 | /* In synchronous mode, the SSI uses STCCR for capture */ |
563 | if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) || | |
564 | ssi_private->cpu_dai_drv.symmetric_rates) | |
dfa1a107 | 565 | write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_WL_MASK, wl); |
5e538eca | 566 | else |
dfa1a107 | 567 | write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_WL_MASK, wl); |
17467f23 | 568 | |
171d683d | 569 | if (!fsl_ssi_is_ac97(ssi_private)) |
2924a998 NC |
570 | write_ssi_mask(&ssi->scr, |
571 | CCSR_SSI_SCR_NET | CCSR_SSI_SCR_I2S_MODE_MASK, | |
572 | channels == 1 ? 0 : ssi_private->i2s_mode); | |
573 | ||
17467f23 TT |
574 | return 0; |
575 | } | |
576 | ||
aafa85e7 NC |
577 | /** |
578 | * fsl_ssi_set_dai_fmt - configure Digital Audio Interface Format. | |
579 | */ | |
580 | static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) | |
581 | { | |
582 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); | |
583 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; | |
584 | u32 strcr = 0, stcr, srcr, scr, mask; | |
2b0db996 MP |
585 | u8 wm; |
586 | ||
171d683d MP |
587 | ssi_private->dai_fmt = fmt; |
588 | ||
2b0db996 | 589 | fsl_ssi_setup_reg_vals(ssi_private); |
aafa85e7 NC |
590 | |
591 | scr = read_ssi(&ssi->scr) & ~(CCSR_SSI_SCR_SYN | CCSR_SSI_SCR_I2S_MODE_MASK); | |
50489479 | 592 | scr |= CCSR_SSI_SCR_SYNC_TX_FS; |
aafa85e7 NC |
593 | |
594 | mask = CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR | | |
595 | CCSR_SSI_STCR_TSCKP | CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TFSL | | |
596 | CCSR_SSI_STCR_TEFS; | |
597 | stcr = read_ssi(&ssi->stcr) & ~mask; | |
598 | srcr = read_ssi(&ssi->srcr) & ~mask; | |
599 | ||
07a28dbe | 600 | ssi_private->i2s_mode = CCSR_SSI_SCR_NET; |
aafa85e7 NC |
601 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
602 | case SND_SOC_DAIFMT_I2S: | |
603 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
604 | case SND_SOC_DAIFMT_CBS_CFS: | |
07a28dbe | 605 | ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_MASTER; |
aafa85e7 NC |
606 | break; |
607 | case SND_SOC_DAIFMT_CBM_CFM: | |
07a28dbe | 608 | ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_SLAVE; |
aafa85e7 NC |
609 | break; |
610 | default: | |
611 | return -EINVAL; | |
612 | } | |
aafa85e7 NC |
613 | |
614 | /* Data on rising edge of bclk, frame low, 1clk before data */ | |
615 | strcr |= CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TSCKP | | |
616 | CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS; | |
617 | break; | |
618 | case SND_SOC_DAIFMT_LEFT_J: | |
619 | /* Data on rising edge of bclk, frame high */ | |
620 | strcr |= CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TSCKP; | |
621 | break; | |
622 | case SND_SOC_DAIFMT_DSP_A: | |
623 | /* Data on rising edge of bclk, frame high, 1clk before data */ | |
624 | strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP | | |
625 | CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS; | |
626 | break; | |
627 | case SND_SOC_DAIFMT_DSP_B: | |
628 | /* Data on rising edge of bclk, frame high */ | |
629 | strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP | | |
630 | CCSR_SSI_STCR_TXBIT0; | |
631 | break; | |
2b0db996 | 632 | case SND_SOC_DAIFMT_AC97: |
07a28dbe | 633 | ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_NORMAL; |
2b0db996 | 634 | break; |
aafa85e7 NC |
635 | default: |
636 | return -EINVAL; | |
637 | } | |
2b0db996 | 638 | scr |= ssi_private->i2s_mode; |
aafa85e7 NC |
639 | |
640 | /* DAI clock inversion */ | |
641 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
642 | case SND_SOC_DAIFMT_NB_NF: | |
643 | /* Nothing to do for both normal cases */ | |
644 | break; | |
645 | case SND_SOC_DAIFMT_IB_NF: | |
646 | /* Invert bit clock */ | |
647 | strcr ^= CCSR_SSI_STCR_TSCKP; | |
648 | break; | |
649 | case SND_SOC_DAIFMT_NB_IF: | |
650 | /* Invert frame clock */ | |
651 | strcr ^= CCSR_SSI_STCR_TFSI; | |
652 | break; | |
653 | case SND_SOC_DAIFMT_IB_IF: | |
654 | /* Invert both clocks */ | |
655 | strcr ^= CCSR_SSI_STCR_TSCKP; | |
656 | strcr ^= CCSR_SSI_STCR_TFSI; | |
657 | break; | |
658 | default: | |
659 | return -EINVAL; | |
660 | } | |
661 | ||
662 | /* DAI clock master masks */ | |
663 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
664 | case SND_SOC_DAIFMT_CBS_CFS: | |
665 | strcr |= CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR; | |
666 | scr |= CCSR_SSI_SCR_SYS_CLK_EN; | |
667 | break; | |
668 | case SND_SOC_DAIFMT_CBM_CFM: | |
669 | scr &= ~CCSR_SSI_SCR_SYS_CLK_EN; | |
670 | break; | |
671 | default: | |
672 | return -EINVAL; | |
673 | } | |
674 | ||
675 | stcr |= strcr; | |
676 | srcr |= strcr; | |
677 | ||
678 | if (ssi_private->cpu_dai_drv.symmetric_rates) { | |
679 | /* Need to clear RXDIR when using SYNC mode */ | |
680 | srcr &= ~CCSR_SSI_SRCR_RXDIR; | |
681 | scr |= CCSR_SSI_SCR_SYN; | |
682 | } | |
683 | ||
684 | write_ssi(stcr, &ssi->stcr); | |
685 | write_ssi(srcr, &ssi->srcr); | |
686 | write_ssi(scr, &ssi->scr); | |
687 | ||
2b0db996 MP |
688 | /* |
689 | * Set the watermark for transmit FIFI 0 and receive FIFO 0. We don't | |
690 | * use FIFO 1. We program the transmit water to signal a DMA transfer | |
691 | * if there are only two (or fewer) elements left in the FIFO. Two | |
692 | * elements equals one frame (left channel, right channel). This value, | |
693 | * however, depends on the depth of the transmit buffer. | |
694 | * | |
695 | * We set the watermark on the same level as the DMA burstsize. For | |
696 | * fiq it is probably better to use the biggest possible watermark | |
697 | * size. | |
698 | */ | |
699 | if (ssi_private->use_dma) | |
700 | wm = ssi_private->fifo_depth - 2; | |
701 | else | |
702 | wm = ssi_private->fifo_depth; | |
703 | ||
704 | write_ssi(CCSR_SSI_SFCSR_TFWM0(wm) | CCSR_SSI_SFCSR_RFWM0(wm) | | |
705 | CCSR_SSI_SFCSR_TFWM1(wm) | CCSR_SSI_SFCSR_RFWM1(wm), | |
706 | &ssi->sfcsr); | |
707 | ||
708 | if (ssi_private->use_dual_fifo) { | |
709 | write_ssi_mask(&ssi->srcr, CCSR_SSI_SRCR_RFEN1, | |
710 | CCSR_SSI_SRCR_RFEN1); | |
711 | write_ssi_mask(&ssi->stcr, CCSR_SSI_STCR_TFEN1, | |
712 | CCSR_SSI_STCR_TFEN1); | |
713 | write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_TCH_EN, | |
714 | CCSR_SSI_SCR_TCH_EN); | |
715 | } | |
716 | ||
717 | if (fmt & SND_SOC_DAIFMT_AC97) | |
718 | fsl_ssi_setup_ac97(ssi_private); | |
719 | ||
aafa85e7 NC |
720 | return 0; |
721 | } | |
722 | ||
723 | /** | |
724 | * fsl_ssi_set_dai_sysclk - configure Digital Audio Interface bit clock | |
725 | * | |
726 | * Note: This function can be only called when using SSI as DAI master | |
727 | * | |
728 | * Quick instruction for parameters: | |
729 | * freq: Output BCLK frequency = samplerate * 32 (fixed) * channels | |
730 | * dir: SND_SOC_CLOCK_OUT -> TxBCLK, SND_SOC_CLOCK_IN -> RxBCLK. | |
731 | */ | |
732 | static int fsl_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai, | |
733 | int clk_id, unsigned int freq, int dir) | |
734 | { | |
735 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); | |
736 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; | |
737 | int synchronous = ssi_private->cpu_dai_drv.symmetric_rates, ret; | |
738 | u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i; | |
739 | unsigned long flags, clkrate, baudrate, tmprate; | |
740 | u64 sub, savesub = 100000; | |
741 | ||
742 | /* Don't apply it to any non-baudclk circumstance */ | |
743 | if (IS_ERR(ssi_private->baudclk)) | |
744 | return -EINVAL; | |
745 | ||
746 | /* It should be already enough to divide clock by setting pm alone */ | |
747 | psr = 0; | |
748 | div2 = 0; | |
749 | ||
750 | factor = (div2 + 1) * (7 * psr + 1) * 2; | |
751 | ||
752 | for (i = 0; i < 255; i++) { | |
753 | /* The bclk rate must be smaller than 1/5 sysclk rate */ | |
754 | if (factor * (i + 1) < 5) | |
755 | continue; | |
756 | ||
757 | tmprate = freq * factor * (i + 2); | |
758 | clkrate = clk_round_rate(ssi_private->baudclk, tmprate); | |
759 | ||
760 | do_div(clkrate, factor); | |
761 | afreq = (u32)clkrate / (i + 1); | |
762 | ||
763 | if (freq == afreq) | |
764 | sub = 0; | |
765 | else if (freq / afreq == 1) | |
766 | sub = freq - afreq; | |
767 | else if (afreq / freq == 1) | |
768 | sub = afreq - freq; | |
769 | else | |
770 | continue; | |
771 | ||
772 | /* Calculate the fraction */ | |
773 | sub *= 100000; | |
774 | do_div(sub, freq); | |
775 | ||
776 | if (sub < savesub) { | |
777 | baudrate = tmprate; | |
778 | savesub = sub; | |
779 | pm = i; | |
780 | } | |
781 | ||
782 | /* We are lucky */ | |
783 | if (savesub == 0) | |
784 | break; | |
785 | } | |
786 | ||
787 | /* No proper pm found if it is still remaining the initial value */ | |
788 | if (pm == 999) { | |
789 | dev_err(cpu_dai->dev, "failed to handle the required sysclk\n"); | |
790 | return -EINVAL; | |
791 | } | |
792 | ||
793 | stccr = CCSR_SSI_SxCCR_PM(pm + 1) | (div2 ? CCSR_SSI_SxCCR_DIV2 : 0) | | |
794 | (psr ? CCSR_SSI_SxCCR_PSR : 0); | |
795 | mask = CCSR_SSI_SxCCR_PM_MASK | CCSR_SSI_SxCCR_DIV2 | CCSR_SSI_SxCCR_PSR; | |
796 | ||
797 | if (dir == SND_SOC_CLOCK_OUT || synchronous) | |
798 | write_ssi_mask(&ssi->stccr, mask, stccr); | |
799 | else | |
800 | write_ssi_mask(&ssi->srccr, mask, stccr); | |
801 | ||
802 | spin_lock_irqsave(&ssi_private->baudclk_lock, flags); | |
803 | if (!ssi_private->baudclk_locked) { | |
804 | ret = clk_set_rate(ssi_private->baudclk, baudrate); | |
805 | if (ret) { | |
806 | spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags); | |
807 | dev_err(cpu_dai->dev, "failed to set baudclk rate\n"); | |
808 | return -EINVAL; | |
809 | } | |
810 | ssi_private->baudclk_locked = true; | |
811 | } | |
812 | spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags); | |
813 | ||
814 | return 0; | |
815 | } | |
816 | ||
817 | /** | |
818 | * fsl_ssi_set_dai_tdm_slot - set TDM slot number | |
819 | * | |
820 | * Note: This function can be only called when using SSI as DAI master | |
821 | */ | |
822 | static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask, | |
823 | u32 rx_mask, int slots, int slot_width) | |
824 | { | |
825 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); | |
826 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; | |
827 | u32 val; | |
828 | ||
829 | /* The slot number should be >= 2 if using Network mode or I2S mode */ | |
830 | val = read_ssi(&ssi->scr) & (CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_NET); | |
831 | if (val && slots < 2) { | |
832 | dev_err(cpu_dai->dev, "slot number should be >= 2 in I2S or NET\n"); | |
833 | return -EINVAL; | |
834 | } | |
835 | ||
836 | write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_DC_MASK, | |
837 | CCSR_SSI_SxCCR_DC(slots)); | |
838 | write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_DC_MASK, | |
839 | CCSR_SSI_SxCCR_DC(slots)); | |
840 | ||
841 | /* The register SxMSKs needs SSI to provide essential clock due to | |
842 | * hardware design. So we here temporarily enable SSI to set them. | |
843 | */ | |
844 | val = read_ssi(&ssi->scr) & CCSR_SSI_SCR_SSIEN; | |
845 | write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN); | |
846 | ||
847 | write_ssi(tx_mask, &ssi->stmsk); | |
848 | write_ssi(rx_mask, &ssi->srmsk); | |
849 | ||
850 | write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, val); | |
851 | ||
852 | return 0; | |
853 | } | |
854 | ||
17467f23 TT |
855 | /** |
856 | * fsl_ssi_trigger: start and stop the DMA transfer. | |
857 | * | |
858 | * This function is called by ALSA to start, stop, pause, and resume the DMA | |
859 | * transfer of data. | |
860 | * | |
861 | * The DMA channel is in external master start and pause mode, which | |
862 | * means the SSI completely controls the flow of data. | |
863 | */ | |
dee89c4d MB |
864 | static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd, |
865 | struct snd_soc_dai *dai) | |
17467f23 TT |
866 | { |
867 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
f0fba2ad | 868 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai); |
17467f23 | 869 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; |
aafa85e7 | 870 | unsigned long flags; |
9b443e3d | 871 | |
17467f23 TT |
872 | switch (cmd) { |
873 | case SNDRV_PCM_TRIGGER_START: | |
17467f23 | 874 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
a4d11fe5 | 875 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
6de83879 | 876 | fsl_ssi_tx_config(ssi_private, true); |
a4d11fe5 | 877 | else |
6de83879 | 878 | fsl_ssi_rx_config(ssi_private, true); |
17467f23 TT |
879 | break; |
880 | ||
881 | case SNDRV_PCM_TRIGGER_STOP: | |
17467f23 TT |
882 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
883 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
6de83879 | 884 | fsl_ssi_tx_config(ssi_private, false); |
17467f23 | 885 | else |
6de83879 | 886 | fsl_ssi_rx_config(ssi_private, false); |
b2c119b0 | 887 | |
171d683d | 888 | if (!fsl_ssi_is_ac97(ssi_private) && (read_ssi(&ssi->scr) & |
aafa85e7 | 889 | (CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE)) == 0) { |
aafa85e7 NC |
890 | spin_lock_irqsave(&ssi_private->baudclk_lock, flags); |
891 | ssi_private->baudclk_locked = false; | |
892 | spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags); | |
893 | } | |
17467f23 TT |
894 | break; |
895 | ||
896 | default: | |
897 | return -EINVAL; | |
898 | } | |
899 | ||
171d683d | 900 | if (fsl_ssi_is_ac97(ssi_private)) { |
a5a7ee7c MP |
901 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
902 | write_ssi(CCSR_SSI_SOR_TX_CLR, &ssi->sor); | |
903 | else | |
904 | write_ssi(CCSR_SSI_SOR_RX_CLR, &ssi->sor); | |
905 | } | |
9b443e3d | 906 | |
17467f23 TT |
907 | return 0; |
908 | } | |
909 | ||
fc8ba7f9 LPC |
910 | static int fsl_ssi_dai_probe(struct snd_soc_dai *dai) |
911 | { | |
912 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(dai); | |
913 | ||
171d683d | 914 | if (fsl_ssi_on_imx(ssi_private) && ssi_private->use_dma) { |
fc8ba7f9 LPC |
915 | dai->playback_dma_data = &ssi_private->dma_params_tx; |
916 | dai->capture_dma_data = &ssi_private->dma_params_rx; | |
917 | } | |
918 | ||
919 | return 0; | |
920 | } | |
921 | ||
85e7652d | 922 | static const struct snd_soc_dai_ops fsl_ssi_dai_ops = { |
6335d055 EM |
923 | .startup = fsl_ssi_startup, |
924 | .hw_params = fsl_ssi_hw_params, | |
aafa85e7 NC |
925 | .set_fmt = fsl_ssi_set_dai_fmt, |
926 | .set_sysclk = fsl_ssi_set_dai_sysclk, | |
927 | .set_tdm_slot = fsl_ssi_set_dai_tdm_slot, | |
6335d055 | 928 | .trigger = fsl_ssi_trigger, |
6335d055 EM |
929 | }; |
930 | ||
f0fba2ad LG |
931 | /* Template for the CPU dai driver structure */ |
932 | static struct snd_soc_dai_driver fsl_ssi_dai_template = { | |
fc8ba7f9 | 933 | .probe = fsl_ssi_dai_probe, |
17467f23 | 934 | .playback = { |
2924a998 | 935 | .channels_min = 1, |
17467f23 TT |
936 | .channels_max = 2, |
937 | .rates = FSLSSI_I2S_RATES, | |
938 | .formats = FSLSSI_I2S_FORMATS, | |
939 | }, | |
940 | .capture = { | |
2924a998 | 941 | .channels_min = 1, |
17467f23 TT |
942 | .channels_max = 2, |
943 | .rates = FSLSSI_I2S_RATES, | |
944 | .formats = FSLSSI_I2S_FORMATS, | |
945 | }, | |
6335d055 | 946 | .ops = &fsl_ssi_dai_ops, |
17467f23 TT |
947 | }; |
948 | ||
3580aa10 KM |
949 | static const struct snd_soc_component_driver fsl_ssi_component = { |
950 | .name = "fsl-ssi", | |
951 | }; | |
952 | ||
cd7f0295 MP |
953 | static struct snd_soc_dai_driver fsl_ssi_ac97_dai = { |
954 | .ac97_control = 1, | |
955 | .playback = { | |
956 | .stream_name = "AC97 Playback", | |
957 | .channels_min = 2, | |
958 | .channels_max = 2, | |
959 | .rates = SNDRV_PCM_RATE_8000_48000, | |
960 | .formats = SNDRV_PCM_FMTBIT_S16_LE, | |
961 | }, | |
962 | .capture = { | |
963 | .stream_name = "AC97 Capture", | |
964 | .channels_min = 2, | |
965 | .channels_max = 2, | |
966 | .rates = SNDRV_PCM_RATE_48000, | |
967 | .formats = SNDRV_PCM_FMTBIT_S16_LE, | |
968 | }, | |
a5a7ee7c | 969 | .ops = &fsl_ssi_dai_ops, |
cd7f0295 MP |
970 | }; |
971 | ||
972 | ||
973 | static struct fsl_ssi_private *fsl_ac97_data; | |
974 | ||
a851a2bb | 975 | static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg, |
cd7f0295 MP |
976 | unsigned short val) |
977 | { | |
978 | struct ccsr_ssi *ssi = fsl_ac97_data->ssi; | |
979 | unsigned int lreg; | |
980 | unsigned int lval; | |
981 | ||
982 | if (reg > 0x7f) | |
983 | return; | |
984 | ||
985 | ||
986 | lreg = reg << 12; | |
987 | write_ssi(lreg, &ssi->sacadd); | |
988 | ||
989 | lval = val << 4; | |
990 | write_ssi(lval , &ssi->sacdat); | |
991 | ||
992 | write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK, | |
993 | CCSR_SSI_SACNT_WR); | |
994 | udelay(100); | |
995 | } | |
996 | ||
a851a2bb | 997 | static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97, |
cd7f0295 MP |
998 | unsigned short reg) |
999 | { | |
1000 | struct ccsr_ssi *ssi = fsl_ac97_data->ssi; | |
1001 | ||
1002 | unsigned short val = -1; | |
1003 | unsigned int lreg; | |
1004 | ||
1005 | lreg = (reg & 0x7f) << 12; | |
1006 | write_ssi(lreg, &ssi->sacadd); | |
1007 | write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK, | |
1008 | CCSR_SSI_SACNT_RD); | |
1009 | ||
1010 | udelay(100); | |
1011 | ||
1012 | val = (read_ssi(&ssi->sacdat) >> 4) & 0xffff; | |
1013 | ||
1014 | return val; | |
1015 | } | |
1016 | ||
1017 | static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = { | |
1018 | .read = fsl_ssi_ac97_read, | |
1019 | .write = fsl_ssi_ac97_write, | |
1020 | }; | |
1021 | ||
17467f23 | 1022 | /** |
f0fba2ad | 1023 | * Make every character in a string lower-case |
17467f23 | 1024 | */ |
f0fba2ad LG |
1025 | static void make_lowercase(char *s) |
1026 | { | |
1027 | char *p = s; | |
1028 | char c; | |
1029 | ||
1030 | while ((c = *p)) { | |
1031 | if ((c >= 'A') && (c <= 'Z')) | |
1032 | *p = c + ('a' - 'A'); | |
1033 | p++; | |
1034 | } | |
1035 | } | |
1036 | ||
49da09e2 | 1037 | static int fsl_ssi_imx_probe(struct platform_device *pdev, |
4d9b7926 | 1038 | struct fsl_ssi_private *ssi_private, void __iomem *iomem) |
49da09e2 MP |
1039 | { |
1040 | struct device_node *np = pdev->dev.of_node; | |
ed0f1604 | 1041 | u32 dmas[4]; |
49da09e2 MP |
1042 | int ret; |
1043 | ||
1044 | ssi_private->clk = devm_clk_get(&pdev->dev, NULL); | |
1045 | if (IS_ERR(ssi_private->clk)) { | |
1046 | ret = PTR_ERR(ssi_private->clk); | |
1047 | dev_err(&pdev->dev, "could not get clock: %d\n", ret); | |
1048 | return ret; | |
1049 | } | |
1050 | ||
1051 | ret = clk_prepare_enable(ssi_private->clk); | |
1052 | if (ret) { | |
1053 | dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret); | |
1054 | return ret; | |
1055 | } | |
1056 | ||
1057 | /* For those SLAVE implementations, we ingore non-baudclk cases | |
1058 | * and, instead, abandon MASTER mode that needs baud clock. | |
1059 | */ | |
1060 | ssi_private->baudclk = devm_clk_get(&pdev->dev, "baud"); | |
1061 | if (IS_ERR(ssi_private->baudclk)) | |
1062 | dev_dbg(&pdev->dev, "could not get baud clock: %ld\n", | |
1063 | PTR_ERR(ssi_private->baudclk)); | |
1064 | else | |
1065 | clk_prepare_enable(ssi_private->baudclk); | |
1066 | ||
1067 | /* | |
1068 | * We have burstsize be "fifo_depth - 2" to match the SSI | |
1069 | * watermark setting in fsl_ssi_startup(). | |
1070 | */ | |
1071 | ssi_private->dma_params_tx.maxburst = ssi_private->fifo_depth - 2; | |
1072 | ssi_private->dma_params_rx.maxburst = ssi_private->fifo_depth - 2; | |
1073 | ssi_private->dma_params_tx.addr = ssi_private->ssi_phys + | |
1074 | offsetof(struct ccsr_ssi, stx0); | |
1075 | ssi_private->dma_params_rx.addr = ssi_private->ssi_phys + | |
1076 | offsetof(struct ccsr_ssi, srx0); | |
49da09e2 | 1077 | |
ed0f1604 MP |
1078 | ret = !of_property_read_u32_array(np, "dmas", dmas, 4); |
1079 | if (ssi_private->use_dma && !ret && dmas[2] == IMX_DMATYPE_SSI_DUAL) { | |
49da09e2 MP |
1080 | ssi_private->use_dual_fifo = true; |
1081 | /* When using dual fifo mode, we need to keep watermark | |
1082 | * as even numbers due to dma script limitation. | |
1083 | */ | |
1084 | ssi_private->dma_params_tx.maxburst &= ~0x1; | |
1085 | ssi_private->dma_params_rx.maxburst &= ~0x1; | |
1086 | } | |
1087 | ||
4d9b7926 MP |
1088 | if (!ssi_private->use_dma) { |
1089 | ||
1090 | /* | |
1091 | * Some boards use an incompatible codec. To get it | |
1092 | * working, we are using imx-fiq-pcm-audio, that | |
1093 | * can handle those codecs. DMA is not possible in this | |
1094 | * situation. | |
1095 | */ | |
1096 | ||
1097 | ssi_private->fiq_params.irq = ssi_private->irq; | |
1098 | ssi_private->fiq_params.base = iomem; | |
1099 | ssi_private->fiq_params.dma_params_rx = | |
1100 | &ssi_private->dma_params_rx; | |
1101 | ssi_private->fiq_params.dma_params_tx = | |
1102 | &ssi_private->dma_params_tx; | |
1103 | ||
1104 | ret = imx_pcm_fiq_init(pdev, &ssi_private->fiq_params); | |
1105 | if (ret) | |
1106 | goto error_pcm; | |
1107 | } else { | |
1108 | ret = imx_pcm_dma_init(pdev); | |
1109 | if (ret) | |
1110 | goto error_pcm; | |
1111 | } | |
1112 | ||
49da09e2 | 1113 | return 0; |
4d9b7926 MP |
1114 | |
1115 | error_pcm: | |
1116 | if (!IS_ERR(ssi_private->baudclk)) | |
1117 | clk_disable_unprepare(ssi_private->baudclk); | |
1118 | ||
1119 | clk_disable_unprepare(ssi_private->clk); | |
1120 | ||
1121 | return ret; | |
49da09e2 MP |
1122 | } |
1123 | ||
1124 | static void fsl_ssi_imx_clean(struct platform_device *pdev, | |
1125 | struct fsl_ssi_private *ssi_private) | |
1126 | { | |
4d9b7926 MP |
1127 | if (!ssi_private->use_dma) |
1128 | imx_pcm_fiq_exit(pdev); | |
49da09e2 MP |
1129 | if (!IS_ERR(ssi_private->baudclk)) |
1130 | clk_disable_unprepare(ssi_private->baudclk); | |
1131 | clk_disable_unprepare(ssi_private->clk); | |
1132 | } | |
1133 | ||
a0a3d518 | 1134 | static int fsl_ssi_probe(struct platform_device *pdev) |
17467f23 | 1135 | { |
17467f23 TT |
1136 | struct fsl_ssi_private *ssi_private; |
1137 | int ret = 0; | |
38fec727 | 1138 | struct device_node *np = pdev->dev.of_node; |
c1953bfe MP |
1139 | const struct of_device_id *of_id; |
1140 | enum fsl_ssi_type hw_type; | |
f0fba2ad | 1141 | const char *p, *sprop; |
8e9d8690 | 1142 | const uint32_t *iprop; |
f0fba2ad LG |
1143 | struct resource res; |
1144 | char name[64]; | |
cd7f0295 | 1145 | bool ac97 = false; |
17467f23 | 1146 | |
ff71334a TT |
1147 | /* SSIs that are not connected on the board should have a |
1148 | * status = "disabled" | |
1149 | * property in their device tree nodes. | |
f0fba2ad | 1150 | */ |
ff71334a | 1151 | if (!of_device_is_available(np)) |
f0fba2ad LG |
1152 | return -ENODEV; |
1153 | ||
c1953bfe MP |
1154 | of_id = of_match_device(fsl_ssi_ids, &pdev->dev); |
1155 | if (!of_id) | |
1156 | return -EINVAL; | |
1157 | hw_type = (enum fsl_ssi_type) of_id->data; | |
1158 | ||
f0fba2ad | 1159 | sprop = of_get_property(np, "fsl,mode", NULL); |
cd7f0295 MP |
1160 | if (!sprop) { |
1161 | dev_err(&pdev->dev, "fsl,mode property is necessary\n"); | |
1162 | return -EINVAL; | |
1163 | } | |
ae1f8ce1 | 1164 | if (!strcmp(sprop, "ac97-slave")) |
cd7f0295 | 1165 | ac97 = true; |
f0fba2ad | 1166 | |
2a1d102d MP |
1167 | ssi_private = devm_kzalloc(&pdev->dev, sizeof(*ssi_private), |
1168 | GFP_KERNEL); | |
17467f23 | 1169 | if (!ssi_private) { |
38fec727 | 1170 | dev_err(&pdev->dev, "could not allocate DAI object\n"); |
f0fba2ad | 1171 | return -ENOMEM; |
17467f23 | 1172 | } |
17467f23 | 1173 | |
de623ece MP |
1174 | ssi_private->use_dma = !of_property_read_bool(np, |
1175 | "fsl,fiq-stream-filter"); | |
0888efd1 | 1176 | ssi_private->hw_type = hw_type; |
de623ece | 1177 | |
cd7f0295 MP |
1178 | if (ac97) { |
1179 | memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_ac97_dai, | |
1180 | sizeof(fsl_ssi_ac97_dai)); | |
1181 | ||
1182 | fsl_ac97_data = ssi_private; | |
cd7f0295 MP |
1183 | |
1184 | snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev); | |
1185 | } else { | |
1186 | /* Initialize this copy of the CPU DAI driver structure */ | |
1187 | memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template, | |
1188 | sizeof(fsl_ssi_dai_template)); | |
1189 | } | |
2a1d102d | 1190 | ssi_private->cpu_dai_drv.name = dev_name(&pdev->dev); |
f0fba2ad LG |
1191 | |
1192 | /* Get the addresses and IRQ */ | |
1193 | ret = of_address_to_resource(np, 0, &res); | |
1194 | if (ret) { | |
38fec727 | 1195 | dev_err(&pdev->dev, "could not determine device resources\n"); |
b0a4747a | 1196 | return ret; |
f0fba2ad | 1197 | } |
147dfe90 TT |
1198 | ssi_private->ssi = of_iomap(np, 0); |
1199 | if (!ssi_private->ssi) { | |
1200 | dev_err(&pdev->dev, "could not map device resources\n"); | |
b0a4747a | 1201 | return -ENOMEM; |
147dfe90 | 1202 | } |
f0fba2ad | 1203 | ssi_private->ssi_phys = res.start; |
1fab6caf | 1204 | |
f0fba2ad | 1205 | ssi_private->irq = irq_of_parse_and_map(np, 0); |
d60336e2 | 1206 | if (!ssi_private->irq) { |
1fab6caf | 1207 | dev_err(&pdev->dev, "no irq for node %s\n", np->full_name); |
b0a4747a | 1208 | return -ENXIO; |
1fab6caf TT |
1209 | } |
1210 | ||
f0fba2ad | 1211 | /* Are the RX and the TX clocks locked? */ |
07a9483a | 1212 | if (!of_find_property(np, "fsl,ssi-asynchronous", NULL)) { |
f0fba2ad | 1213 | ssi_private->cpu_dai_drv.symmetric_rates = 1; |
07a9483a NC |
1214 | ssi_private->cpu_dai_drv.symmetric_channels = 1; |
1215 | ssi_private->cpu_dai_drv.symmetric_samplebits = 1; | |
1216 | } | |
17467f23 | 1217 | |
8e9d8690 TT |
1218 | /* Determine the FIFO depth. */ |
1219 | iprop = of_get_property(np, "fsl,fifo-depth", NULL); | |
1220 | if (iprop) | |
147dfe90 | 1221 | ssi_private->fifo_depth = be32_to_cpup(iprop); |
8e9d8690 TT |
1222 | else |
1223 | /* Older 8610 DTs didn't have the fifo-depth property */ | |
1224 | ssi_private->fifo_depth = 8; | |
1225 | ||
aafa85e7 NC |
1226 | ssi_private->baudclk_locked = false; |
1227 | spin_lock_init(&ssi_private->baudclk_lock); | |
1228 | ||
4d9b7926 MP |
1229 | dev_set_drvdata(&pdev->dev, ssi_private); |
1230 | ||
171d683d | 1231 | if (fsl_ssi_on_imx(ssi_private)) { |
4d9b7926 | 1232 | ret = fsl_ssi_imx_probe(pdev, ssi_private, ssi_private->ssi); |
49da09e2 | 1233 | if (ret) |
b0a4747a | 1234 | goto error_irqmap; |
0888efd1 MP |
1235 | } |
1236 | ||
4d9b7926 MP |
1237 | ret = snd_soc_register_component(&pdev->dev, &fsl_ssi_component, |
1238 | &ssi_private->cpu_dai_drv, 1); | |
1239 | if (ret) { | |
1240 | dev_err(&pdev->dev, "failed to register DAI: %d\n", ret); | |
1241 | goto error_asoc_register; | |
1242 | } | |
1243 | ||
0888efd1 | 1244 | if (ssi_private->use_dma) { |
f0377086 | 1245 | ret = devm_request_irq(&pdev->dev, ssi_private->irq, |
171d683d | 1246 | fsl_ssi_isr, 0, dev_name(&pdev->dev), |
f0377086 MG |
1247 | ssi_private); |
1248 | if (ret < 0) { | |
1249 | dev_err(&pdev->dev, "could not claim irq %u\n", | |
1250 | ssi_private->irq); | |
49da09e2 | 1251 | goto error_irq; |
f0377086 | 1252 | } |
09ce1111 SG |
1253 | } |
1254 | ||
f138e621 | 1255 | ret = fsl_ssi_debugfs_create(&ssi_private->dbg_stats, &pdev->dev); |
9368acc4 | 1256 | if (ret) |
4d9b7926 | 1257 | goto error_asoc_register; |
09ce1111 SG |
1258 | |
1259 | /* | |
1260 | * If codec-handle property is missing from SSI node, we assume | |
1261 | * that the machine driver uses new binding which does not require | |
1262 | * SSI driver to trigger machine driver's probe. | |
1263 | */ | |
171d683d | 1264 | if (!of_get_property(np, "codec-handle", NULL)) |
09ce1111 | 1265 | goto done; |
09ce1111 | 1266 | |
f0fba2ad | 1267 | /* Trigger the machine driver's probe function. The platform driver |
2b81ec69 | 1268 | * name of the machine driver is taken from /compatible property of the |
f0fba2ad LG |
1269 | * device tree. We also pass the address of the CPU DAI driver |
1270 | * structure. | |
1271 | */ | |
2b81ec69 SG |
1272 | sprop = of_get_property(of_find_node_by_path("/"), "compatible", NULL); |
1273 | /* Sometimes the compatible name has a "fsl," prefix, so we strip it. */ | |
f0fba2ad LG |
1274 | p = strrchr(sprop, ','); |
1275 | if (p) | |
1276 | sprop = p + 1; | |
1277 | snprintf(name, sizeof(name), "snd-soc-%s", sprop); | |
1278 | make_lowercase(name); | |
1279 | ||
1280 | ssi_private->pdev = | |
38fec727 | 1281 | platform_device_register_data(&pdev->dev, name, 0, NULL, 0); |
f0fba2ad LG |
1282 | if (IS_ERR(ssi_private->pdev)) { |
1283 | ret = PTR_ERR(ssi_private->pdev); | |
38fec727 | 1284 | dev_err(&pdev->dev, "failed to register platform: %d\n", ret); |
4d9b7926 | 1285 | goto error_sound_card; |
3f4b783c | 1286 | } |
17467f23 | 1287 | |
09ce1111 | 1288 | done: |
f0fba2ad | 1289 | return 0; |
87a0632b | 1290 | |
4d9b7926 | 1291 | error_sound_card: |
f138e621 | 1292 | fsl_ssi_debugfs_remove(&ssi_private->dbg_stats); |
9368acc4 | 1293 | |
4d9b7926 | 1294 | error_irq: |
3580aa10 | 1295 | snd_soc_unregister_component(&pdev->dev); |
1fab6caf | 1296 | |
4d9b7926 | 1297 | error_asoc_register: |
171d683d | 1298 | if (fsl_ssi_on_imx(ssi_private)) |
49da09e2 | 1299 | fsl_ssi_imx_clean(pdev, ssi_private); |
1fab6caf TT |
1300 | |
1301 | error_irqmap: | |
4d9b7926 | 1302 | if (ssi_private->use_dma) |
2841be9a | 1303 | irq_dispose_mapping(ssi_private->irq); |
1fab6caf | 1304 | |
87a0632b | 1305 | return ret; |
17467f23 | 1306 | } |
17467f23 | 1307 | |
38fec727 | 1308 | static int fsl_ssi_remove(struct platform_device *pdev) |
17467f23 | 1309 | { |
38fec727 | 1310 | struct fsl_ssi_private *ssi_private = dev_get_drvdata(&pdev->dev); |
17467f23 | 1311 | |
f138e621 | 1312 | fsl_ssi_debugfs_remove(&ssi_private->dbg_stats); |
9368acc4 | 1313 | |
171d683d | 1314 | if (ssi_private->pdev) |
09ce1111 | 1315 | platform_device_unregister(ssi_private->pdev); |
3580aa10 | 1316 | snd_soc_unregister_component(&pdev->dev); |
49da09e2 | 1317 | |
171d683d | 1318 | if (fsl_ssi_on_imx(ssi_private)) |
49da09e2 MP |
1319 | fsl_ssi_imx_clean(pdev, ssi_private); |
1320 | ||
4d9b7926 | 1321 | if (ssi_private->use_dma) |
2841be9a | 1322 | irq_dispose_mapping(ssi_private->irq); |
f0fba2ad LG |
1323 | |
1324 | return 0; | |
17467f23 | 1325 | } |
f0fba2ad | 1326 | |
f07eb223 | 1327 | static struct platform_driver fsl_ssi_driver = { |
f0fba2ad LG |
1328 | .driver = { |
1329 | .name = "fsl-ssi-dai", | |
1330 | .owner = THIS_MODULE, | |
1331 | .of_match_table = fsl_ssi_ids, | |
1332 | }, | |
1333 | .probe = fsl_ssi_probe, | |
1334 | .remove = fsl_ssi_remove, | |
1335 | }; | |
17467f23 | 1336 | |
ba0a7e02 | 1337 | module_platform_driver(fsl_ssi_driver); |
a454dad1 | 1338 | |
f3142807 | 1339 | MODULE_ALIAS("platform:fsl-ssi-dai"); |
17467f23 TT |
1340 | MODULE_AUTHOR("Timur Tabi <timur@freescale.com>"); |
1341 | MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver"); | |
f0fba2ad | 1342 | MODULE_LICENSE("GPL v2"); |