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17467f23 TT |
1 | /* |
2 | * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver | |
3 | * | |
4 | * Author: Timur Tabi <timur@freescale.com> | |
5 | * | |
f0fba2ad LG |
6 | * Copyright 2007-2010 Freescale Semiconductor, Inc. |
7 | * | |
8 | * This file is licensed under the terms of the GNU General Public License | |
9 | * version 2. This program is licensed "as is" without any warranty of any | |
10 | * kind, whether express or implied. | |
de623ece MP |
11 | * |
12 | * | |
13 | * Some notes why imx-pcm-fiq is used instead of DMA on some boards: | |
14 | * | |
15 | * The i.MX SSI core has some nasty limitations in AC97 mode. While most | |
16 | * sane processor vendors have a FIFO per AC97 slot, the i.MX has only | |
17 | * one FIFO which combines all valid receive slots. We cannot even select | |
18 | * which slots we want to receive. The WM9712 with which this driver | |
19 | * was developed with always sends GPIO status data in slot 12 which | |
20 | * we receive in our (PCM-) data stream. The only chance we have is to | |
21 | * manually skip this data in the FIQ handler. With sampling rates different | |
22 | * from 48000Hz not every frame has valid receive data, so the ratio | |
23 | * between pcm data and GPIO status data changes. Our FIQ handler is not | |
24 | * able to handle this, hence this driver only works with 48000Hz sampling | |
25 | * rate. | |
26 | * Reading and writing AC97 registers is another challenge. The core | |
27 | * provides us status bits when the read register is updated with *another* | |
28 | * value. When we read the same register two times (and the register still | |
29 | * contains the same value) these status bits are not set. We work | |
30 | * around this by not polling these bits but only wait a fixed delay. | |
17467f23 TT |
31 | */ |
32 | ||
33 | #include <linux/init.h> | |
dfa1a107 | 34 | #include <linux/io.h> |
17467f23 TT |
35 | #include <linux/module.h> |
36 | #include <linux/interrupt.h> | |
95cd98f9 | 37 | #include <linux/clk.h> |
17467f23 TT |
38 | #include <linux/device.h> |
39 | #include <linux/delay.h> | |
5a0e3ad6 | 40 | #include <linux/slab.h> |
aafa85e7 | 41 | #include <linux/spinlock.h> |
dfa1a107 SG |
42 | #include <linux/of_address.h> |
43 | #include <linux/of_irq.h> | |
f0fba2ad | 44 | #include <linux/of_platform.h> |
17467f23 | 45 | |
17467f23 TT |
46 | #include <sound/core.h> |
47 | #include <sound/pcm.h> | |
48 | #include <sound/pcm_params.h> | |
49 | #include <sound/initval.h> | |
50 | #include <sound/soc.h> | |
a8909c9b | 51 | #include <sound/dmaengine_pcm.h> |
17467f23 | 52 | |
17467f23 | 53 | #include "fsl_ssi.h" |
09ce1111 | 54 | #include "imx-pcm.h" |
17467f23 | 55 | |
dfa1a107 SG |
56 | #ifdef PPC |
57 | #define read_ssi(addr) in_be32(addr) | |
58 | #define write_ssi(val, addr) out_be32(addr, val) | |
59 | #define write_ssi_mask(addr, clear, set) clrsetbits_be32(addr, clear, set) | |
0a9eaa39 | 60 | #else |
dfa1a107 SG |
61 | #define read_ssi(addr) readl(addr) |
62 | #define write_ssi(val, addr) writel(val, addr) | |
63 | /* | |
64 | * FIXME: Proper locking should be added at write_ssi_mask caller level | |
65 | * to ensure this register read/modify/write sequence is race free. | |
66 | */ | |
67 | static inline void write_ssi_mask(u32 __iomem *addr, u32 clear, u32 set) | |
68 | { | |
69 | u32 val = readl(addr); | |
70 | val = (val & ~clear) | set; | |
71 | writel(val, addr); | |
72 | } | |
73 | #endif | |
74 | ||
17467f23 TT |
75 | /** |
76 | * FSLSSI_I2S_RATES: sample rates supported by the I2S | |
77 | * | |
78 | * This driver currently only supports the SSI running in I2S slave mode, | |
79 | * which means the codec determines the sample rate. Therefore, we tell | |
80 | * ALSA that we support all rates and let the codec driver decide what rates | |
81 | * are really supported. | |
82 | */ | |
24710c97 | 83 | #define FSLSSI_I2S_RATES SNDRV_PCM_RATE_CONTINUOUS |
17467f23 TT |
84 | |
85 | /** | |
86 | * FSLSSI_I2S_FORMATS: audio formats supported by the SSI | |
87 | * | |
88 | * This driver currently only supports the SSI running in I2S slave mode. | |
89 | * | |
90 | * The SSI has a limitation in that the samples must be in the same byte | |
91 | * order as the host CPU. This is because when multiple bytes are written | |
92 | * to the STX register, the bytes and bits must be written in the same | |
93 | * order. The STX is a shift register, so all the bits need to be aligned | |
94 | * (bit-endianness must match byte-endianness). Processors typically write | |
95 | * the bits within a byte in the same order that the bytes of a word are | |
96 | * written in. So if the host CPU is big-endian, then only big-endian | |
97 | * samples will be written to STX properly. | |
98 | */ | |
99 | #ifdef __BIG_ENDIAN | |
100 | #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \ | |
101 | SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \ | |
102 | SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE) | |
103 | #else | |
104 | #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \ | |
105 | SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \ | |
106 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE) | |
107 | #endif | |
108 | ||
9368acc4 MP |
109 | #define FSLSSI_SIER_DBG_RX_FLAGS (CCSR_SSI_SIER_RFF0_EN | \ |
110 | CCSR_SSI_SIER_RLS_EN | CCSR_SSI_SIER_RFS_EN | \ | |
111 | CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_RFRC_EN) | |
112 | #define FSLSSI_SIER_DBG_TX_FLAGS (CCSR_SSI_SIER_TFE0_EN | \ | |
113 | CCSR_SSI_SIER_TLS_EN | CCSR_SSI_SIER_TFS_EN | \ | |
114 | CCSR_SSI_SIER_TUE0_EN | CCSR_SSI_SIER_TFRC_EN) | |
c1953bfe MP |
115 | |
116 | enum fsl_ssi_type { | |
117 | FSL_SSI_MCP8610, | |
118 | FSL_SSI_MX21, | |
0888efd1 | 119 | FSL_SSI_MX35, |
c1953bfe MP |
120 | FSL_SSI_MX51, |
121 | }; | |
122 | ||
4e6ec0d9 MP |
123 | struct fsl_ssi_reg_val { |
124 | u32 sier; | |
125 | u32 srcr; | |
126 | u32 stcr; | |
127 | u32 scr; | |
128 | }; | |
129 | ||
130 | struct fsl_ssi_rxtx_reg_val { | |
131 | struct fsl_ssi_reg_val rx; | |
132 | struct fsl_ssi_reg_val tx; | |
133 | }; | |
d5a908b2 | 134 | |
17467f23 TT |
135 | /** |
136 | * fsl_ssi_private: per-SSI private data | |
137 | * | |
17467f23 TT |
138 | * @ssi: pointer to the SSI's registers |
139 | * @ssi_phys: physical address of the SSI registers | |
140 | * @irq: IRQ of this SSI | |
17467f23 TT |
141 | * @playback: the number of playback streams opened |
142 | * @capture: the number of capture streams opened | |
143 | * @cpu_dai: the CPU DAI for this device | |
144 | * @dev_attr: the sysfs device attribute structure | |
145 | * @stats: SSI statistics | |
f0fba2ad | 146 | * @name: name for this device |
17467f23 TT |
147 | */ |
148 | struct fsl_ssi_private { | |
17467f23 TT |
149 | struct ccsr_ssi __iomem *ssi; |
150 | dma_addr_t ssi_phys; | |
151 | unsigned int irq; | |
8e9d8690 | 152 | unsigned int fifo_depth; |
f0fba2ad | 153 | struct snd_soc_dai_driver cpu_dai_drv; |
f0fba2ad | 154 | struct platform_device *pdev; |
17467f23 | 155 | |
0888efd1 | 156 | enum fsl_ssi_type hw_type; |
09ce1111 SG |
157 | bool new_binding; |
158 | bool ssi_on_imx; | |
cd7f0295 | 159 | bool imx_ac97; |
de623ece | 160 | bool use_dma; |
aafa85e7 | 161 | bool baudclk_locked; |
2841be9a | 162 | bool irq_stats; |
bd3ca7d1 | 163 | bool offline_config; |
0da9e55e | 164 | bool use_dual_fifo; |
2924a998 | 165 | u8 i2s_mode; |
aafa85e7 NC |
166 | spinlock_t baudclk_lock; |
167 | struct clk *baudclk; | |
95cd98f9 | 168 | struct clk *clk; |
a8909c9b LPC |
169 | struct snd_dmaengine_dai_dma_data dma_params_tx; |
170 | struct snd_dmaengine_dai_dma_data dma_params_rx; | |
171 | struct imx_dma_data filter_data_tx; | |
172 | struct imx_dma_data filter_data_rx; | |
de623ece | 173 | struct imx_pcm_fiq_params fiq_params; |
4e6ec0d9 MP |
174 | /* Register values for rx/tx configuration */ |
175 | struct fsl_ssi_rxtx_reg_val rxtx_reg_val; | |
09ce1111 | 176 | |
f138e621 | 177 | struct fsl_ssi_dbg dbg_stats; |
f0fba2ad LG |
178 | |
179 | char name[1]; | |
17467f23 TT |
180 | }; |
181 | ||
c1953bfe MP |
182 | static const struct of_device_id fsl_ssi_ids[] = { |
183 | { .compatible = "fsl,mpc8610-ssi", .data = (void *) FSL_SSI_MCP8610}, | |
184 | { .compatible = "fsl,imx51-ssi", .data = (void *) FSL_SSI_MX51}, | |
0888efd1 | 185 | { .compatible = "fsl,imx35-ssi", .data = (void *) FSL_SSI_MX35}, |
c1953bfe MP |
186 | { .compatible = "fsl,imx21-ssi", .data = (void *) FSL_SSI_MX21}, |
187 | {} | |
188 | }; | |
189 | MODULE_DEVICE_TABLE(of, fsl_ssi_ids); | |
190 | ||
17467f23 TT |
191 | /** |
192 | * fsl_ssi_isr: SSI interrupt handler | |
193 | * | |
194 | * Although it's possible to use the interrupt handler to send and receive | |
195 | * data to/from the SSI, we use the DMA instead. Programming is more | |
196 | * complicated, but the performance is much better. | |
197 | * | |
198 | * This interrupt handler is used only to gather statistics. | |
199 | * | |
200 | * @irq: IRQ of the SSI device | |
201 | * @dev_id: pointer to the ssi_private structure for this SSI device | |
202 | */ | |
203 | static irqreturn_t fsl_ssi_isr(int irq, void *dev_id) | |
204 | { | |
205 | struct fsl_ssi_private *ssi_private = dev_id; | |
206 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; | |
17467f23 | 207 | __be32 sisr; |
0888efd1 MP |
208 | __be32 sisr2; |
209 | __be32 sisr_write_mask = 0; | |
210 | ||
211 | switch (ssi_private->hw_type) { | |
212 | case FSL_SSI_MX21: | |
213 | sisr_write_mask = 0; | |
214 | break; | |
215 | ||
216 | case FSL_SSI_MCP8610: | |
217 | case FSL_SSI_MX35: | |
218 | sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC | | |
219 | CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 | | |
220 | CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1; | |
221 | break; | |
222 | ||
223 | case FSL_SSI_MX51: | |
224 | sisr_write_mask = CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 | | |
225 | CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1; | |
226 | break; | |
227 | } | |
17467f23 TT |
228 | |
229 | /* We got an interrupt, so read the status register to see what we | |
230 | were interrupted for. We mask it with the Interrupt Enable register | |
231 | so that we only check for events that we're interested in. | |
232 | */ | |
f138e621 | 233 | sisr = read_ssi(&ssi->sisr); |
17467f23 | 234 | |
0888efd1 | 235 | sisr2 = sisr & sisr_write_mask; |
17467f23 TT |
236 | /* Clear the bits that we set */ |
237 | if (sisr2) | |
dfa1a107 | 238 | write_ssi(sisr2, &ssi->sisr); |
17467f23 | 239 | |
f138e621 | 240 | fsl_ssi_dbg_isr(&ssi_private->dbg_stats, sisr); |
9368acc4 | 241 | |
f138e621 | 242 | return IRQ_HANDLED; |
9368acc4 MP |
243 | } |
244 | ||
4e6ec0d9 MP |
245 | /* |
246 | * Enable/Disable all rx/tx config flags at once. | |
247 | */ | |
248 | static void fsl_ssi_rxtx_config(struct fsl_ssi_private *ssi_private, | |
249 | bool enable) | |
250 | { | |
251 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; | |
252 | struct fsl_ssi_rxtx_reg_val *vals = &ssi_private->rxtx_reg_val; | |
253 | ||
254 | if (enable) { | |
255 | write_ssi_mask(&ssi->sier, 0, vals->rx.sier | vals->tx.sier); | |
256 | write_ssi_mask(&ssi->srcr, 0, vals->rx.srcr | vals->tx.srcr); | |
257 | write_ssi_mask(&ssi->stcr, 0, vals->rx.stcr | vals->tx.stcr); | |
258 | } else { | |
259 | write_ssi_mask(&ssi->srcr, vals->rx.srcr | vals->tx.srcr, 0); | |
260 | write_ssi_mask(&ssi->stcr, vals->rx.stcr | vals->tx.stcr, 0); | |
261 | write_ssi_mask(&ssi->sier, vals->rx.sier | vals->tx.sier, 0); | |
262 | } | |
263 | } | |
264 | ||
65c961cc MP |
265 | /* |
266 | * Calculate the bits that have to be disabled for the current stream that is | |
267 | * getting disabled. This keeps the bits enabled that are necessary for the | |
268 | * second stream to work if 'stream_active' is true. | |
269 | * | |
270 | * Detailed calculation: | |
271 | * These are the values that need to be active after disabling. For non-active | |
272 | * second stream, this is 0: | |
273 | * vals_stream * !!stream_active | |
274 | * | |
275 | * The following computes the overall differences between the setup for the | |
276 | * to-disable stream and the active stream, a simple XOR: | |
277 | * vals_disable ^ (vals_stream * !!(stream_active)) | |
278 | * | |
279 | * The full expression adds a mask on all values we care about | |
280 | */ | |
281 | #define fsl_ssi_disable_val(vals_disable, vals_stream, stream_active) \ | |
282 | ((vals_disable) & \ | |
283 | ((vals_disable) ^ ((vals_stream) * (u32)!!(stream_active)))) | |
284 | ||
4e6ec0d9 MP |
285 | /* |
286 | * Enable/Disable a ssi configuration. You have to pass either | |
287 | * ssi_private->rxtx_reg_val.rx or tx as vals parameter. | |
288 | */ | |
289 | static void fsl_ssi_config(struct fsl_ssi_private *ssi_private, bool enable, | |
290 | struct fsl_ssi_reg_val *vals) | |
291 | { | |
292 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; | |
293 | struct fsl_ssi_reg_val *avals; | |
294 | u32 scr_val = read_ssi(&ssi->scr); | |
295 | int nr_active_streams = !!(scr_val & CCSR_SSI_SCR_TE) + | |
296 | !!(scr_val & CCSR_SSI_SCR_RE); | |
65c961cc MP |
297 | int keep_active; |
298 | ||
299 | if (nr_active_streams - 1 > 0) | |
300 | keep_active = 1; | |
301 | else | |
302 | keep_active = 0; | |
4e6ec0d9 MP |
303 | |
304 | /* Find the other direction values rx or tx which we do not want to | |
305 | * modify */ | |
306 | if (&ssi_private->rxtx_reg_val.rx == vals) | |
307 | avals = &ssi_private->rxtx_reg_val.tx; | |
308 | else | |
309 | avals = &ssi_private->rxtx_reg_val.rx; | |
310 | ||
311 | /* If vals should be disabled, start with disabling the unit */ | |
312 | if (!enable) { | |
65c961cc MP |
313 | u32 scr = fsl_ssi_disable_val(vals->scr, avals->scr, |
314 | keep_active); | |
4e6ec0d9 MP |
315 | write_ssi_mask(&ssi->scr, scr, 0); |
316 | } | |
317 | ||
318 | /* | |
319 | * We are running on a SoC which does not support online SSI | |
320 | * reconfiguration, so we have to enable all necessary flags at once | |
321 | * even if we do not use them later (capture and playback configuration) | |
322 | */ | |
323 | if (ssi_private->offline_config) { | |
324 | if ((enable && !nr_active_streams) || | |
65c961cc | 325 | (!enable && !keep_active)) |
4e6ec0d9 MP |
326 | fsl_ssi_rxtx_config(ssi_private, enable); |
327 | ||
328 | goto config_done; | |
329 | } | |
330 | ||
331 | /* | |
332 | * Configure single direction units while the SSI unit is running | |
333 | * (online configuration) | |
334 | */ | |
335 | if (enable) { | |
336 | write_ssi_mask(&ssi->sier, 0, vals->sier); | |
337 | write_ssi_mask(&ssi->srcr, 0, vals->srcr); | |
338 | write_ssi_mask(&ssi->stcr, 0, vals->stcr); | |
339 | } else { | |
340 | u32 sier; | |
341 | u32 srcr; | |
342 | u32 stcr; | |
343 | ||
344 | /* | |
345 | * Disabling the necessary flags for one of rx/tx while the | |
346 | * other stream is active is a little bit more difficult. We | |
347 | * have to disable only those flags that differ between both | |
348 | * streams (rx XOR tx) and that are set in the stream that is | |
349 | * disabled now. Otherwise we could alter flags of the other | |
350 | * stream | |
351 | */ | |
352 | ||
353 | /* These assignments are simply vals without bits set in avals*/ | |
65c961cc MP |
354 | sier = fsl_ssi_disable_val(vals->sier, avals->sier, |
355 | keep_active); | |
356 | srcr = fsl_ssi_disable_val(vals->srcr, avals->srcr, | |
357 | keep_active); | |
358 | stcr = fsl_ssi_disable_val(vals->stcr, avals->stcr, | |
359 | keep_active); | |
4e6ec0d9 MP |
360 | |
361 | write_ssi_mask(&ssi->srcr, srcr, 0); | |
362 | write_ssi_mask(&ssi->stcr, stcr, 0); | |
363 | write_ssi_mask(&ssi->sier, sier, 0); | |
364 | } | |
365 | ||
366 | config_done: | |
367 | /* Enabling of subunits is done after configuration */ | |
368 | if (enable) | |
369 | write_ssi_mask(&ssi->scr, 0, vals->scr); | |
370 | } | |
371 | ||
372 | ||
373 | static void fsl_ssi_rx_config(struct fsl_ssi_private *ssi_private, bool enable) | |
374 | { | |
375 | fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.rx); | |
376 | } | |
377 | ||
378 | static void fsl_ssi_tx_config(struct fsl_ssi_private *ssi_private, bool enable) | |
379 | { | |
380 | fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.tx); | |
381 | } | |
382 | ||
6de83879 MP |
383 | /* |
384 | * Setup rx/tx register values used to enable/disable the streams. These will | |
385 | * be used later in fsl_ssi_config to setup the streams without the need to | |
386 | * check for all different SSI modes. | |
387 | */ | |
388 | static void fsl_ssi_setup_reg_vals(struct fsl_ssi_private *ssi_private) | |
389 | { | |
390 | struct fsl_ssi_rxtx_reg_val *reg = &ssi_private->rxtx_reg_val; | |
391 | ||
392 | reg->rx.sier = CCSR_SSI_SIER_RFF0_EN; | |
393 | reg->rx.srcr = CCSR_SSI_SRCR_RFEN0; | |
394 | reg->rx.scr = 0; | |
395 | reg->tx.sier = CCSR_SSI_SIER_TFE0_EN; | |
396 | reg->tx.stcr = CCSR_SSI_STCR_TFEN0; | |
397 | reg->tx.scr = 0; | |
398 | ||
399 | if (!ssi_private->imx_ac97) { | |
400 | reg->rx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE; | |
401 | reg->rx.sier |= CCSR_SSI_SIER_RFF0_EN; | |
402 | reg->tx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE; | |
403 | reg->tx.sier |= CCSR_SSI_SIER_TFE0_EN; | |
404 | } | |
405 | ||
406 | if (ssi_private->use_dma) { | |
407 | reg->rx.sier |= CCSR_SSI_SIER_RDMAE; | |
408 | reg->tx.sier |= CCSR_SSI_SIER_TDMAE; | |
409 | } else { | |
410 | reg->rx.sier |= CCSR_SSI_SIER_RIE; | |
411 | reg->tx.sier |= CCSR_SSI_SIER_TIE; | |
412 | } | |
413 | ||
414 | reg->rx.sier |= FSLSSI_SIER_DBG_RX_FLAGS; | |
415 | reg->tx.sier |= FSLSSI_SIER_DBG_TX_FLAGS; | |
416 | } | |
417 | ||
d8764646 MP |
418 | static void fsl_ssi_setup_ac97(struct fsl_ssi_private *ssi_private) |
419 | { | |
420 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; | |
421 | ||
422 | /* | |
423 | * Setup the clock control register | |
424 | */ | |
425 | write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13), | |
426 | &ssi->stccr); | |
427 | write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13), | |
428 | &ssi->srccr); | |
429 | ||
430 | /* | |
431 | * Enable AC97 mode and startup the SSI | |
432 | */ | |
433 | write_ssi(CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV, | |
434 | &ssi->sacnt); | |
435 | write_ssi(0xff, &ssi->saccdis); | |
436 | write_ssi(0x300, &ssi->saccen); | |
437 | ||
438 | /* | |
439 | * Enable SSI, Transmit and Receive. AC97 has to communicate with the | |
440 | * codec before a stream is started. | |
441 | */ | |
442 | write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN | | |
443 | CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE); | |
444 | ||
445 | write_ssi(CCSR_SSI_SOR_WAIT(3), &ssi->sor); | |
446 | } | |
447 | ||
17467f23 TT |
448 | /** |
449 | * fsl_ssi_startup: create a new substream | |
450 | * | |
451 | * This is the first function called when a stream is opened. | |
452 | * | |
453 | * If this is the first stream open, then grab the IRQ and program most of | |
454 | * the SSI registers. | |
455 | */ | |
dee89c4d MB |
456 | static int fsl_ssi_startup(struct snd_pcm_substream *substream, |
457 | struct snd_soc_dai *dai) | |
17467f23 TT |
458 | { |
459 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
5e538eca TT |
460 | struct fsl_ssi_private *ssi_private = |
461 | snd_soc_dai_get_drvdata(rtd->cpu_dai); | |
aafa85e7 | 462 | unsigned long flags; |
17467f23 | 463 | |
aafa85e7 | 464 | if (!dai->active && !ssi_private->imx_ac97) { |
aafa85e7 NC |
465 | spin_lock_irqsave(&ssi_private->baudclk_lock, flags); |
466 | ssi_private->baudclk_locked = false; | |
467 | spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags); | |
468 | } | |
be41e941 | 469 | |
0da9e55e NC |
470 | /* When using dual fifo mode, it is safer to ensure an even period |
471 | * size. If appearing to an odd number while DMA always starts its | |
472 | * task from fifo0, fifo1 would be neglected at the end of each | |
473 | * period. But SSI would still access fifo1 with an invalid data. | |
474 | */ | |
475 | if (ssi_private->use_dual_fifo) | |
476 | snd_pcm_hw_constraint_step(substream->runtime, 0, | |
477 | SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2); | |
478 | ||
17467f23 TT |
479 | return 0; |
480 | } | |
481 | ||
482 | /** | |
85ef2375 | 483 | * fsl_ssi_hw_params - program the sample size |
17467f23 TT |
484 | * |
485 | * Most of the SSI registers have been programmed in the startup function, | |
486 | * but the word length must be programmed here. Unfortunately, programming | |
487 | * the SxCCR.WL bits requires the SSI to be temporarily disabled. This can | |
488 | * cause a problem with supporting simultaneous playback and capture. If | |
489 | * the SSI is already playing a stream, then that stream may be temporarily | |
490 | * stopped when you start capture. | |
491 | * | |
492 | * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the | |
493 | * clock master. | |
494 | */ | |
85ef2375 TT |
495 | static int fsl_ssi_hw_params(struct snd_pcm_substream *substream, |
496 | struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai) | |
17467f23 | 497 | { |
f0fba2ad | 498 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); |
5e538eca | 499 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; |
2924a998 | 500 | unsigned int channels = params_channels(hw_params); |
5e538eca TT |
501 | unsigned int sample_size = |
502 | snd_pcm_format_width(params_format(hw_params)); | |
503 | u32 wl = CCSR_SSI_SxCCR_WL(sample_size); | |
dfa1a107 | 504 | int enabled = read_ssi(&ssi->scr) & CCSR_SSI_SCR_SSIEN; |
17467f23 | 505 | |
5e538eca TT |
506 | /* |
507 | * If we're in synchronous mode, and the SSI is already enabled, | |
508 | * then STCCR is already set properly. | |
509 | */ | |
510 | if (enabled && ssi_private->cpu_dai_drv.symmetric_rates) | |
511 | return 0; | |
17467f23 | 512 | |
5e538eca TT |
513 | /* |
514 | * FIXME: The documentation says that SxCCR[WL] should not be | |
515 | * modified while the SSI is enabled. The only time this can | |
516 | * happen is if we're trying to do simultaneous playback and | |
517 | * capture in asynchronous mode. Unfortunately, I have been enable | |
518 | * to get that to work at all on the P1022DS. Therefore, we don't | |
519 | * bother to disable/enable the SSI when setting SxCCR[WL], because | |
520 | * the SSI will stop anyway. Maybe one day, this will get fixed. | |
521 | */ | |
17467f23 | 522 | |
5e538eca TT |
523 | /* In synchronous mode, the SSI uses STCCR for capture */ |
524 | if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) || | |
525 | ssi_private->cpu_dai_drv.symmetric_rates) | |
dfa1a107 | 526 | write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_WL_MASK, wl); |
5e538eca | 527 | else |
dfa1a107 | 528 | write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_WL_MASK, wl); |
17467f23 | 529 | |
2924a998 NC |
530 | if (!ssi_private->imx_ac97) |
531 | write_ssi_mask(&ssi->scr, | |
532 | CCSR_SSI_SCR_NET | CCSR_SSI_SCR_I2S_MODE_MASK, | |
533 | channels == 1 ? 0 : ssi_private->i2s_mode); | |
534 | ||
17467f23 TT |
535 | return 0; |
536 | } | |
537 | ||
aafa85e7 NC |
538 | /** |
539 | * fsl_ssi_set_dai_fmt - configure Digital Audio Interface Format. | |
540 | */ | |
541 | static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) | |
542 | { | |
543 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); | |
544 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; | |
545 | u32 strcr = 0, stcr, srcr, scr, mask; | |
2b0db996 MP |
546 | u8 wm; |
547 | ||
548 | fsl_ssi_setup_reg_vals(ssi_private); | |
aafa85e7 NC |
549 | |
550 | scr = read_ssi(&ssi->scr) & ~(CCSR_SSI_SCR_SYN | CCSR_SSI_SCR_I2S_MODE_MASK); | |
aafa85e7 NC |
551 | |
552 | mask = CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR | | |
553 | CCSR_SSI_STCR_TSCKP | CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TFSL | | |
554 | CCSR_SSI_STCR_TEFS; | |
555 | stcr = read_ssi(&ssi->stcr) & ~mask; | |
556 | srcr = read_ssi(&ssi->srcr) & ~mask; | |
557 | ||
07a28dbe | 558 | ssi_private->i2s_mode = CCSR_SSI_SCR_NET; |
aafa85e7 NC |
559 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
560 | case SND_SOC_DAIFMT_I2S: | |
561 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
562 | case SND_SOC_DAIFMT_CBS_CFS: | |
07a28dbe | 563 | ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_MASTER; |
aafa85e7 NC |
564 | break; |
565 | case SND_SOC_DAIFMT_CBM_CFM: | |
07a28dbe | 566 | ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_SLAVE; |
aafa85e7 NC |
567 | break; |
568 | default: | |
569 | return -EINVAL; | |
570 | } | |
aafa85e7 NC |
571 | |
572 | /* Data on rising edge of bclk, frame low, 1clk before data */ | |
573 | strcr |= CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TSCKP | | |
574 | CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS; | |
575 | break; | |
576 | case SND_SOC_DAIFMT_LEFT_J: | |
577 | /* Data on rising edge of bclk, frame high */ | |
578 | strcr |= CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TSCKP; | |
579 | break; | |
580 | case SND_SOC_DAIFMT_DSP_A: | |
581 | /* Data on rising edge of bclk, frame high, 1clk before data */ | |
582 | strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP | | |
583 | CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS; | |
584 | break; | |
585 | case SND_SOC_DAIFMT_DSP_B: | |
586 | /* Data on rising edge of bclk, frame high */ | |
587 | strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP | | |
588 | CCSR_SSI_STCR_TXBIT0; | |
589 | break; | |
2b0db996 | 590 | case SND_SOC_DAIFMT_AC97: |
07a28dbe | 591 | ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_NORMAL; |
2b0db996 | 592 | break; |
aafa85e7 NC |
593 | default: |
594 | return -EINVAL; | |
595 | } | |
2b0db996 | 596 | scr |= ssi_private->i2s_mode; |
aafa85e7 NC |
597 | |
598 | /* DAI clock inversion */ | |
599 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
600 | case SND_SOC_DAIFMT_NB_NF: | |
601 | /* Nothing to do for both normal cases */ | |
602 | break; | |
603 | case SND_SOC_DAIFMT_IB_NF: | |
604 | /* Invert bit clock */ | |
605 | strcr ^= CCSR_SSI_STCR_TSCKP; | |
606 | break; | |
607 | case SND_SOC_DAIFMT_NB_IF: | |
608 | /* Invert frame clock */ | |
609 | strcr ^= CCSR_SSI_STCR_TFSI; | |
610 | break; | |
611 | case SND_SOC_DAIFMT_IB_IF: | |
612 | /* Invert both clocks */ | |
613 | strcr ^= CCSR_SSI_STCR_TSCKP; | |
614 | strcr ^= CCSR_SSI_STCR_TFSI; | |
615 | break; | |
616 | default: | |
617 | return -EINVAL; | |
618 | } | |
619 | ||
620 | /* DAI clock master masks */ | |
621 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
622 | case SND_SOC_DAIFMT_CBS_CFS: | |
623 | strcr |= CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR; | |
624 | scr |= CCSR_SSI_SCR_SYS_CLK_EN; | |
625 | break; | |
626 | case SND_SOC_DAIFMT_CBM_CFM: | |
627 | scr &= ~CCSR_SSI_SCR_SYS_CLK_EN; | |
628 | break; | |
629 | default: | |
630 | return -EINVAL; | |
631 | } | |
632 | ||
633 | stcr |= strcr; | |
634 | srcr |= strcr; | |
635 | ||
636 | if (ssi_private->cpu_dai_drv.symmetric_rates) { | |
637 | /* Need to clear RXDIR when using SYNC mode */ | |
638 | srcr &= ~CCSR_SSI_SRCR_RXDIR; | |
639 | scr |= CCSR_SSI_SCR_SYN; | |
640 | } | |
641 | ||
642 | write_ssi(stcr, &ssi->stcr); | |
643 | write_ssi(srcr, &ssi->srcr); | |
644 | write_ssi(scr, &ssi->scr); | |
645 | ||
2b0db996 MP |
646 | /* |
647 | * Set the watermark for transmit FIFI 0 and receive FIFO 0. We don't | |
648 | * use FIFO 1. We program the transmit water to signal a DMA transfer | |
649 | * if there are only two (or fewer) elements left in the FIFO. Two | |
650 | * elements equals one frame (left channel, right channel). This value, | |
651 | * however, depends on the depth of the transmit buffer. | |
652 | * | |
653 | * We set the watermark on the same level as the DMA burstsize. For | |
654 | * fiq it is probably better to use the biggest possible watermark | |
655 | * size. | |
656 | */ | |
657 | if (ssi_private->use_dma) | |
658 | wm = ssi_private->fifo_depth - 2; | |
659 | else | |
660 | wm = ssi_private->fifo_depth; | |
661 | ||
662 | write_ssi(CCSR_SSI_SFCSR_TFWM0(wm) | CCSR_SSI_SFCSR_RFWM0(wm) | | |
663 | CCSR_SSI_SFCSR_TFWM1(wm) | CCSR_SSI_SFCSR_RFWM1(wm), | |
664 | &ssi->sfcsr); | |
665 | ||
666 | if (ssi_private->use_dual_fifo) { | |
667 | write_ssi_mask(&ssi->srcr, CCSR_SSI_SRCR_RFEN1, | |
668 | CCSR_SSI_SRCR_RFEN1); | |
669 | write_ssi_mask(&ssi->stcr, CCSR_SSI_STCR_TFEN1, | |
670 | CCSR_SSI_STCR_TFEN1); | |
671 | write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_TCH_EN, | |
672 | CCSR_SSI_SCR_TCH_EN); | |
673 | } | |
674 | ||
675 | if (fmt & SND_SOC_DAIFMT_AC97) | |
676 | fsl_ssi_setup_ac97(ssi_private); | |
677 | ||
aafa85e7 NC |
678 | return 0; |
679 | } | |
680 | ||
681 | /** | |
682 | * fsl_ssi_set_dai_sysclk - configure Digital Audio Interface bit clock | |
683 | * | |
684 | * Note: This function can be only called when using SSI as DAI master | |
685 | * | |
686 | * Quick instruction for parameters: | |
687 | * freq: Output BCLK frequency = samplerate * 32 (fixed) * channels | |
688 | * dir: SND_SOC_CLOCK_OUT -> TxBCLK, SND_SOC_CLOCK_IN -> RxBCLK. | |
689 | */ | |
690 | static int fsl_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai, | |
691 | int clk_id, unsigned int freq, int dir) | |
692 | { | |
693 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); | |
694 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; | |
695 | int synchronous = ssi_private->cpu_dai_drv.symmetric_rates, ret; | |
696 | u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i; | |
697 | unsigned long flags, clkrate, baudrate, tmprate; | |
698 | u64 sub, savesub = 100000; | |
699 | ||
700 | /* Don't apply it to any non-baudclk circumstance */ | |
701 | if (IS_ERR(ssi_private->baudclk)) | |
702 | return -EINVAL; | |
703 | ||
704 | /* It should be already enough to divide clock by setting pm alone */ | |
705 | psr = 0; | |
706 | div2 = 0; | |
707 | ||
708 | factor = (div2 + 1) * (7 * psr + 1) * 2; | |
709 | ||
710 | for (i = 0; i < 255; i++) { | |
711 | /* The bclk rate must be smaller than 1/5 sysclk rate */ | |
712 | if (factor * (i + 1) < 5) | |
713 | continue; | |
714 | ||
715 | tmprate = freq * factor * (i + 2); | |
716 | clkrate = clk_round_rate(ssi_private->baudclk, tmprate); | |
717 | ||
718 | do_div(clkrate, factor); | |
719 | afreq = (u32)clkrate / (i + 1); | |
720 | ||
721 | if (freq == afreq) | |
722 | sub = 0; | |
723 | else if (freq / afreq == 1) | |
724 | sub = freq - afreq; | |
725 | else if (afreq / freq == 1) | |
726 | sub = afreq - freq; | |
727 | else | |
728 | continue; | |
729 | ||
730 | /* Calculate the fraction */ | |
731 | sub *= 100000; | |
732 | do_div(sub, freq); | |
733 | ||
734 | if (sub < savesub) { | |
735 | baudrate = tmprate; | |
736 | savesub = sub; | |
737 | pm = i; | |
738 | } | |
739 | ||
740 | /* We are lucky */ | |
741 | if (savesub == 0) | |
742 | break; | |
743 | } | |
744 | ||
745 | /* No proper pm found if it is still remaining the initial value */ | |
746 | if (pm == 999) { | |
747 | dev_err(cpu_dai->dev, "failed to handle the required sysclk\n"); | |
748 | return -EINVAL; | |
749 | } | |
750 | ||
751 | stccr = CCSR_SSI_SxCCR_PM(pm + 1) | (div2 ? CCSR_SSI_SxCCR_DIV2 : 0) | | |
752 | (psr ? CCSR_SSI_SxCCR_PSR : 0); | |
753 | mask = CCSR_SSI_SxCCR_PM_MASK | CCSR_SSI_SxCCR_DIV2 | CCSR_SSI_SxCCR_PSR; | |
754 | ||
755 | if (dir == SND_SOC_CLOCK_OUT || synchronous) | |
756 | write_ssi_mask(&ssi->stccr, mask, stccr); | |
757 | else | |
758 | write_ssi_mask(&ssi->srccr, mask, stccr); | |
759 | ||
760 | spin_lock_irqsave(&ssi_private->baudclk_lock, flags); | |
761 | if (!ssi_private->baudclk_locked) { | |
762 | ret = clk_set_rate(ssi_private->baudclk, baudrate); | |
763 | if (ret) { | |
764 | spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags); | |
765 | dev_err(cpu_dai->dev, "failed to set baudclk rate\n"); | |
766 | return -EINVAL; | |
767 | } | |
768 | ssi_private->baudclk_locked = true; | |
769 | } | |
770 | spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags); | |
771 | ||
772 | return 0; | |
773 | } | |
774 | ||
775 | /** | |
776 | * fsl_ssi_set_dai_tdm_slot - set TDM slot number | |
777 | * | |
778 | * Note: This function can be only called when using SSI as DAI master | |
779 | */ | |
780 | static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask, | |
781 | u32 rx_mask, int slots, int slot_width) | |
782 | { | |
783 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); | |
784 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; | |
785 | u32 val; | |
786 | ||
787 | /* The slot number should be >= 2 if using Network mode or I2S mode */ | |
788 | val = read_ssi(&ssi->scr) & (CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_NET); | |
789 | if (val && slots < 2) { | |
790 | dev_err(cpu_dai->dev, "slot number should be >= 2 in I2S or NET\n"); | |
791 | return -EINVAL; | |
792 | } | |
793 | ||
794 | write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_DC_MASK, | |
795 | CCSR_SSI_SxCCR_DC(slots)); | |
796 | write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_DC_MASK, | |
797 | CCSR_SSI_SxCCR_DC(slots)); | |
798 | ||
799 | /* The register SxMSKs needs SSI to provide essential clock due to | |
800 | * hardware design. So we here temporarily enable SSI to set them. | |
801 | */ | |
802 | val = read_ssi(&ssi->scr) & CCSR_SSI_SCR_SSIEN; | |
803 | write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN); | |
804 | ||
805 | write_ssi(tx_mask, &ssi->stmsk); | |
806 | write_ssi(rx_mask, &ssi->srmsk); | |
807 | ||
808 | write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, val); | |
809 | ||
810 | return 0; | |
811 | } | |
812 | ||
17467f23 TT |
813 | /** |
814 | * fsl_ssi_trigger: start and stop the DMA transfer. | |
815 | * | |
816 | * This function is called by ALSA to start, stop, pause, and resume the DMA | |
817 | * transfer of data. | |
818 | * | |
819 | * The DMA channel is in external master start and pause mode, which | |
820 | * means the SSI completely controls the flow of data. | |
821 | */ | |
dee89c4d MB |
822 | static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd, |
823 | struct snd_soc_dai *dai) | |
17467f23 TT |
824 | { |
825 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
f0fba2ad | 826 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai); |
17467f23 | 827 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; |
aafa85e7 | 828 | unsigned long flags; |
9b443e3d | 829 | |
17467f23 TT |
830 | switch (cmd) { |
831 | case SNDRV_PCM_TRIGGER_START: | |
17467f23 | 832 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
a4d11fe5 | 833 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
6de83879 | 834 | fsl_ssi_tx_config(ssi_private, true); |
a4d11fe5 | 835 | else |
6de83879 | 836 | fsl_ssi_rx_config(ssi_private, true); |
17467f23 TT |
837 | break; |
838 | ||
839 | case SNDRV_PCM_TRIGGER_STOP: | |
17467f23 TT |
840 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
841 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
6de83879 | 842 | fsl_ssi_tx_config(ssi_private, false); |
17467f23 | 843 | else |
6de83879 | 844 | fsl_ssi_rx_config(ssi_private, false); |
b2c119b0 | 845 | |
cd7f0295 | 846 | if (!ssi_private->imx_ac97 && (read_ssi(&ssi->scr) & |
aafa85e7 | 847 | (CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE)) == 0) { |
aafa85e7 NC |
848 | spin_lock_irqsave(&ssi_private->baudclk_lock, flags); |
849 | ssi_private->baudclk_locked = false; | |
850 | spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags); | |
851 | } | |
17467f23 TT |
852 | break; |
853 | ||
854 | default: | |
855 | return -EINVAL; | |
856 | } | |
857 | ||
a5a7ee7c MP |
858 | if (ssi_private->imx_ac97) { |
859 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
860 | write_ssi(CCSR_SSI_SOR_TX_CLR, &ssi->sor); | |
861 | else | |
862 | write_ssi(CCSR_SSI_SOR_RX_CLR, &ssi->sor); | |
863 | } | |
9b443e3d | 864 | |
17467f23 TT |
865 | return 0; |
866 | } | |
867 | ||
fc8ba7f9 LPC |
868 | static int fsl_ssi_dai_probe(struct snd_soc_dai *dai) |
869 | { | |
870 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(dai); | |
871 | ||
de623ece | 872 | if (ssi_private->ssi_on_imx && ssi_private->use_dma) { |
fc8ba7f9 LPC |
873 | dai->playback_dma_data = &ssi_private->dma_params_tx; |
874 | dai->capture_dma_data = &ssi_private->dma_params_rx; | |
875 | } | |
876 | ||
877 | return 0; | |
878 | } | |
879 | ||
85e7652d | 880 | static const struct snd_soc_dai_ops fsl_ssi_dai_ops = { |
6335d055 EM |
881 | .startup = fsl_ssi_startup, |
882 | .hw_params = fsl_ssi_hw_params, | |
aafa85e7 NC |
883 | .set_fmt = fsl_ssi_set_dai_fmt, |
884 | .set_sysclk = fsl_ssi_set_dai_sysclk, | |
885 | .set_tdm_slot = fsl_ssi_set_dai_tdm_slot, | |
6335d055 | 886 | .trigger = fsl_ssi_trigger, |
6335d055 EM |
887 | }; |
888 | ||
f0fba2ad LG |
889 | /* Template for the CPU dai driver structure */ |
890 | static struct snd_soc_dai_driver fsl_ssi_dai_template = { | |
fc8ba7f9 | 891 | .probe = fsl_ssi_dai_probe, |
17467f23 | 892 | .playback = { |
2924a998 | 893 | .channels_min = 1, |
17467f23 TT |
894 | .channels_max = 2, |
895 | .rates = FSLSSI_I2S_RATES, | |
896 | .formats = FSLSSI_I2S_FORMATS, | |
897 | }, | |
898 | .capture = { | |
2924a998 | 899 | .channels_min = 1, |
17467f23 TT |
900 | .channels_max = 2, |
901 | .rates = FSLSSI_I2S_RATES, | |
902 | .formats = FSLSSI_I2S_FORMATS, | |
903 | }, | |
6335d055 | 904 | .ops = &fsl_ssi_dai_ops, |
17467f23 TT |
905 | }; |
906 | ||
3580aa10 KM |
907 | static const struct snd_soc_component_driver fsl_ssi_component = { |
908 | .name = "fsl-ssi", | |
909 | }; | |
910 | ||
cd7f0295 MP |
911 | static struct snd_soc_dai_driver fsl_ssi_ac97_dai = { |
912 | .ac97_control = 1, | |
913 | .playback = { | |
914 | .stream_name = "AC97 Playback", | |
915 | .channels_min = 2, | |
916 | .channels_max = 2, | |
917 | .rates = SNDRV_PCM_RATE_8000_48000, | |
918 | .formats = SNDRV_PCM_FMTBIT_S16_LE, | |
919 | }, | |
920 | .capture = { | |
921 | .stream_name = "AC97 Capture", | |
922 | .channels_min = 2, | |
923 | .channels_max = 2, | |
924 | .rates = SNDRV_PCM_RATE_48000, | |
925 | .formats = SNDRV_PCM_FMTBIT_S16_LE, | |
926 | }, | |
a5a7ee7c | 927 | .ops = &fsl_ssi_dai_ops, |
cd7f0295 MP |
928 | }; |
929 | ||
930 | ||
931 | static struct fsl_ssi_private *fsl_ac97_data; | |
932 | ||
a851a2bb | 933 | static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg, |
cd7f0295 MP |
934 | unsigned short val) |
935 | { | |
936 | struct ccsr_ssi *ssi = fsl_ac97_data->ssi; | |
937 | unsigned int lreg; | |
938 | unsigned int lval; | |
939 | ||
940 | if (reg > 0x7f) | |
941 | return; | |
942 | ||
943 | ||
944 | lreg = reg << 12; | |
945 | write_ssi(lreg, &ssi->sacadd); | |
946 | ||
947 | lval = val << 4; | |
948 | write_ssi(lval , &ssi->sacdat); | |
949 | ||
950 | write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK, | |
951 | CCSR_SSI_SACNT_WR); | |
952 | udelay(100); | |
953 | } | |
954 | ||
a851a2bb | 955 | static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97, |
cd7f0295 MP |
956 | unsigned short reg) |
957 | { | |
958 | struct ccsr_ssi *ssi = fsl_ac97_data->ssi; | |
959 | ||
960 | unsigned short val = -1; | |
961 | unsigned int lreg; | |
962 | ||
963 | lreg = (reg & 0x7f) << 12; | |
964 | write_ssi(lreg, &ssi->sacadd); | |
965 | write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK, | |
966 | CCSR_SSI_SACNT_RD); | |
967 | ||
968 | udelay(100); | |
969 | ||
970 | val = (read_ssi(&ssi->sacdat) >> 4) & 0xffff; | |
971 | ||
972 | return val; | |
973 | } | |
974 | ||
975 | static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = { | |
976 | .read = fsl_ssi_ac97_read, | |
977 | .write = fsl_ssi_ac97_write, | |
978 | }; | |
979 | ||
17467f23 | 980 | /** |
f0fba2ad | 981 | * Make every character in a string lower-case |
17467f23 | 982 | */ |
f0fba2ad LG |
983 | static void make_lowercase(char *s) |
984 | { | |
985 | char *p = s; | |
986 | char c; | |
987 | ||
988 | while ((c = *p)) { | |
989 | if ((c >= 'A') && (c <= 'Z')) | |
990 | *p = c + ('a' - 'A'); | |
991 | p++; | |
992 | } | |
993 | } | |
994 | ||
a0a3d518 | 995 | static int fsl_ssi_probe(struct platform_device *pdev) |
17467f23 | 996 | { |
17467f23 TT |
997 | struct fsl_ssi_private *ssi_private; |
998 | int ret = 0; | |
87a0632b | 999 | struct device_attribute *dev_attr = NULL; |
38fec727 | 1000 | struct device_node *np = pdev->dev.of_node; |
c1953bfe MP |
1001 | const struct of_device_id *of_id; |
1002 | enum fsl_ssi_type hw_type; | |
f0fba2ad | 1003 | const char *p, *sprop; |
8e9d8690 | 1004 | const uint32_t *iprop; |
f0fba2ad LG |
1005 | struct resource res; |
1006 | char name[64]; | |
312bb4f6 | 1007 | bool shared; |
cd7f0295 | 1008 | bool ac97 = false; |
17467f23 | 1009 | |
ff71334a TT |
1010 | /* SSIs that are not connected on the board should have a |
1011 | * status = "disabled" | |
1012 | * property in their device tree nodes. | |
f0fba2ad | 1013 | */ |
ff71334a | 1014 | if (!of_device_is_available(np)) |
f0fba2ad LG |
1015 | return -ENODEV; |
1016 | ||
c1953bfe MP |
1017 | of_id = of_match_device(fsl_ssi_ids, &pdev->dev); |
1018 | if (!of_id) | |
1019 | return -EINVAL; | |
1020 | hw_type = (enum fsl_ssi_type) of_id->data; | |
1021 | ||
f0fba2ad | 1022 | sprop = of_get_property(np, "fsl,mode", NULL); |
cd7f0295 MP |
1023 | if (!sprop) { |
1024 | dev_err(&pdev->dev, "fsl,mode property is necessary\n"); | |
1025 | return -EINVAL; | |
1026 | } | |
ae1f8ce1 | 1027 | if (!strcmp(sprop, "ac97-slave")) |
cd7f0295 | 1028 | ac97 = true; |
f0fba2ad | 1029 | |
2a1d102d MP |
1030 | ssi_private = devm_kzalloc(&pdev->dev, sizeof(*ssi_private), |
1031 | GFP_KERNEL); | |
17467f23 | 1032 | if (!ssi_private) { |
38fec727 | 1033 | dev_err(&pdev->dev, "could not allocate DAI object\n"); |
f0fba2ad | 1034 | return -ENOMEM; |
17467f23 | 1035 | } |
17467f23 | 1036 | |
de623ece MP |
1037 | ssi_private->use_dma = !of_property_read_bool(np, |
1038 | "fsl,fiq-stream-filter"); | |
0888efd1 | 1039 | ssi_private->hw_type = hw_type; |
de623ece | 1040 | |
cd7f0295 MP |
1041 | if (ac97) { |
1042 | memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_ac97_dai, | |
1043 | sizeof(fsl_ssi_ac97_dai)); | |
1044 | ||
1045 | fsl_ac97_data = ssi_private; | |
1046 | ssi_private->imx_ac97 = true; | |
1047 | ||
1048 | snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev); | |
1049 | } else { | |
1050 | /* Initialize this copy of the CPU DAI driver structure */ | |
1051 | memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template, | |
1052 | sizeof(fsl_ssi_dai_template)); | |
1053 | } | |
2a1d102d | 1054 | ssi_private->cpu_dai_drv.name = dev_name(&pdev->dev); |
f0fba2ad LG |
1055 | |
1056 | /* Get the addresses and IRQ */ | |
1057 | ret = of_address_to_resource(np, 0, &res); | |
1058 | if (ret) { | |
38fec727 | 1059 | dev_err(&pdev->dev, "could not determine device resources\n"); |
b0a4747a | 1060 | return ret; |
f0fba2ad | 1061 | } |
147dfe90 TT |
1062 | ssi_private->ssi = of_iomap(np, 0); |
1063 | if (!ssi_private->ssi) { | |
1064 | dev_err(&pdev->dev, "could not map device resources\n"); | |
b0a4747a | 1065 | return -ENOMEM; |
147dfe90 | 1066 | } |
f0fba2ad | 1067 | ssi_private->ssi_phys = res.start; |
1fab6caf | 1068 | |
f0fba2ad | 1069 | ssi_private->irq = irq_of_parse_and_map(np, 0); |
d60336e2 | 1070 | if (!ssi_private->irq) { |
1fab6caf | 1071 | dev_err(&pdev->dev, "no irq for node %s\n", np->full_name); |
b0a4747a | 1072 | return -ENXIO; |
1fab6caf TT |
1073 | } |
1074 | ||
f0fba2ad | 1075 | /* Are the RX and the TX clocks locked? */ |
07a9483a | 1076 | if (!of_find_property(np, "fsl,ssi-asynchronous", NULL)) { |
f0fba2ad | 1077 | ssi_private->cpu_dai_drv.symmetric_rates = 1; |
07a9483a NC |
1078 | ssi_private->cpu_dai_drv.symmetric_channels = 1; |
1079 | ssi_private->cpu_dai_drv.symmetric_samplebits = 1; | |
1080 | } | |
17467f23 | 1081 | |
8e9d8690 TT |
1082 | /* Determine the FIFO depth. */ |
1083 | iprop = of_get_property(np, "fsl,fifo-depth", NULL); | |
1084 | if (iprop) | |
147dfe90 | 1085 | ssi_private->fifo_depth = be32_to_cpup(iprop); |
8e9d8690 TT |
1086 | else |
1087 | /* Older 8610 DTs didn't have the fifo-depth property */ | |
1088 | ssi_private->fifo_depth = 8; | |
1089 | ||
aafa85e7 NC |
1090 | ssi_private->baudclk_locked = false; |
1091 | spin_lock_init(&ssi_private->baudclk_lock); | |
1092 | ||
bd3ca7d1 MP |
1093 | /* |
1094 | * imx51 and later SoCs have a slightly different IP that allows the | |
1095 | * SSI configuration while the SSI unit is running. | |
1096 | * | |
1097 | * More important, it is necessary on those SoCs to configure the | |
1098 | * sperate TX/RX DMA bits just before starting the stream | |
1099 | * (fsl_ssi_trigger). The SDMA unit has to be configured before fsl_ssi | |
1100 | * sends any DMA requests to the SDMA unit, otherwise it is not defined | |
1101 | * how the SDMA unit handles the DMA request. | |
1102 | * | |
1103 | * SDMA units are present on devices starting at imx35 but the imx35 | |
1104 | * reference manual states that the DMA bits should not be changed | |
1105 | * while the SSI unit is running (SSIEN). So we support the necessary | |
1106 | * online configuration of fsl-ssi starting at imx51. | |
1107 | */ | |
1108 | switch (hw_type) { | |
1109 | case FSL_SSI_MCP8610: | |
1110 | case FSL_SSI_MX21: | |
1111 | case FSL_SSI_MX35: | |
1112 | ssi_private->offline_config = true; | |
1113 | break; | |
1114 | case FSL_SSI_MX51: | |
1115 | ssi_private->offline_config = false; | |
1116 | break; | |
1117 | } | |
1118 | ||
c1953bfe MP |
1119 | if (hw_type == FSL_SSI_MX21 || hw_type == FSL_SSI_MX51 || |
1120 | hw_type == FSL_SSI_MX35) { | |
0da9e55e | 1121 | u32 dma_events[2], dmas[4]; |
09ce1111 | 1122 | ssi_private->ssi_on_imx = true; |
95cd98f9 | 1123 | |
b0a4747a | 1124 | ssi_private->clk = devm_clk_get(&pdev->dev, NULL); |
95cd98f9 SG |
1125 | if (IS_ERR(ssi_private->clk)) { |
1126 | ret = PTR_ERR(ssi_private->clk); | |
1127 | dev_err(&pdev->dev, "could not get clock: %d\n", ret); | |
b0a4747a | 1128 | goto error_irqmap; |
95cd98f9 | 1129 | } |
ede32d3a FE |
1130 | ret = clk_prepare_enable(ssi_private->clk); |
1131 | if (ret) { | |
1132 | dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", | |
1133 | ret); | |
1134 | goto error_irqmap; | |
1135 | } | |
95cd98f9 | 1136 | |
aafa85e7 NC |
1137 | /* For those SLAVE implementations, we ingore non-baudclk cases |
1138 | * and, instead, abandon MASTER mode that needs baud clock. | |
1139 | */ | |
1140 | ssi_private->baudclk = devm_clk_get(&pdev->dev, "baud"); | |
1141 | if (IS_ERR(ssi_private->baudclk)) | |
efe2ab9b | 1142 | dev_dbg(&pdev->dev, "could not get baud clock: %ld\n", |
6873ee46 | 1143 | PTR_ERR(ssi_private->baudclk)); |
aafa85e7 NC |
1144 | else |
1145 | clk_prepare_enable(ssi_private->baudclk); | |
1146 | ||
09ce1111 SG |
1147 | /* |
1148 | * We have burstsize be "fifo_depth - 2" to match the SSI | |
1149 | * watermark setting in fsl_ssi_startup(). | |
1150 | */ | |
a8909c9b | 1151 | ssi_private->dma_params_tx.maxburst = |
09ce1111 | 1152 | ssi_private->fifo_depth - 2; |
a8909c9b | 1153 | ssi_private->dma_params_rx.maxburst = |
09ce1111 | 1154 | ssi_private->fifo_depth - 2; |
a8909c9b | 1155 | ssi_private->dma_params_tx.addr = |
09ce1111 | 1156 | ssi_private->ssi_phys + offsetof(struct ccsr_ssi, stx0); |
a8909c9b | 1157 | ssi_private->dma_params_rx.addr = |
09ce1111 | 1158 | ssi_private->ssi_phys + offsetof(struct ccsr_ssi, srx0); |
a8909c9b LPC |
1159 | ssi_private->dma_params_tx.filter_data = |
1160 | &ssi_private->filter_data_tx; | |
1161 | ssi_private->dma_params_rx.filter_data = | |
1162 | &ssi_private->filter_data_rx; | |
3a5e517b MP |
1163 | if (!of_property_read_bool(pdev->dev.of_node, "dmas") && |
1164 | ssi_private->use_dma) { | |
1165 | /* | |
1166 | * FIXME: This is a temporary solution until all | |
1167 | * necessary dma drivers support the generic dma | |
1168 | * bindings. | |
1169 | */ | |
1170 | ret = of_property_read_u32_array(pdev->dev.of_node, | |
09ce1111 | 1171 | "fsl,ssi-dma-events", dma_events, 2); |
3a5e517b MP |
1172 | if (ret && ssi_private->use_dma) { |
1173 | dev_err(&pdev->dev, "could not get dma events but fsl-ssi is configured to use DMA\n"); | |
1174 | goto error_clk; | |
1175 | } | |
09ce1111 | 1176 | } |
ca2a650f | 1177 | /* Should this be merge with the above? */ |
0da9e55e NC |
1178 | if (!of_property_read_u32_array(pdev->dev.of_node, "dmas", dmas, 4) |
1179 | && dmas[2] == IMX_DMATYPE_SSI_DUAL) { | |
1180 | ssi_private->use_dual_fifo = true; | |
1181 | /* When using dual fifo mode, we need to keep watermark | |
1182 | * as even numbers due to dma script limitation. | |
1183 | */ | |
1184 | ssi_private->dma_params_tx.maxburst &= ~0x1; | |
1185 | ssi_private->dma_params_rx.maxburst &= ~0x1; | |
1186 | } | |
312bb4f6 LPC |
1187 | |
1188 | shared = of_device_is_compatible(of_get_parent(np), | |
1189 | "fsl,spba-bus"); | |
1190 | ||
a8909c9b | 1191 | imx_pcm_dma_params_init_data(&ssi_private->filter_data_tx, |
32bd8cd2 | 1192 | dma_events[0], shared ? IMX_DMATYPE_SSI_SP : IMX_DMATYPE_SSI); |
a8909c9b | 1193 | imx_pcm_dma_params_init_data(&ssi_private->filter_data_rx, |
32bd8cd2 | 1194 | dma_events[1], shared ? IMX_DMATYPE_SSI_SP : IMX_DMATYPE_SSI); |
0888efd1 MP |
1195 | } |
1196 | ||
1197 | /* | |
1198 | * Enable interrupts only for MCP8610 and MX51. The other MXs have | |
1199 | * different writeable interrupt status registers. | |
1200 | */ | |
1201 | if (ssi_private->use_dma) { | |
f0377086 MG |
1202 | ret = devm_request_irq(&pdev->dev, ssi_private->irq, |
1203 | fsl_ssi_isr, 0, ssi_private->name, | |
1204 | ssi_private); | |
2841be9a | 1205 | ssi_private->irq_stats = true; |
f0377086 MG |
1206 | if (ret < 0) { |
1207 | dev_err(&pdev->dev, "could not claim irq %u\n", | |
1208 | ssi_private->irq); | |
e1cffe8c | 1209 | goto error_clk; |
f0377086 | 1210 | } |
09ce1111 SG |
1211 | } |
1212 | ||
f0fba2ad | 1213 | /* Register with ASoC */ |
38fec727 | 1214 | dev_set_drvdata(&pdev->dev, ssi_private); |
3f4b783c | 1215 | |
3580aa10 KM |
1216 | ret = snd_soc_register_component(&pdev->dev, &fsl_ssi_component, |
1217 | &ssi_private->cpu_dai_drv, 1); | |
87a0632b | 1218 | if (ret) { |
38fec727 | 1219 | dev_err(&pdev->dev, "failed to register DAI: %d\n", ret); |
1fab6caf | 1220 | goto error_dev; |
f0fba2ad LG |
1221 | } |
1222 | ||
f138e621 | 1223 | ret = fsl_ssi_debugfs_create(&ssi_private->dbg_stats, &pdev->dev); |
9368acc4 MP |
1224 | if (ret) |
1225 | goto error_dbgfs; | |
1226 | ||
09ce1111 | 1227 | if (ssi_private->ssi_on_imx) { |
de623ece MP |
1228 | if (!ssi_private->use_dma) { |
1229 | ||
1230 | /* | |
1231 | * Some boards use an incompatible codec. To get it | |
1232 | * working, we are using imx-fiq-pcm-audio, that | |
1233 | * can handle those codecs. DMA is not possible in this | |
1234 | * situation. | |
1235 | */ | |
1236 | ||
1237 | ssi_private->fiq_params.irq = ssi_private->irq; | |
1238 | ssi_private->fiq_params.base = ssi_private->ssi; | |
1239 | ssi_private->fiq_params.dma_params_rx = | |
1240 | &ssi_private->dma_params_rx; | |
1241 | ssi_private->fiq_params.dma_params_tx = | |
1242 | &ssi_private->dma_params_tx; | |
1243 | ||
1244 | ret = imx_pcm_fiq_init(pdev, &ssi_private->fiq_params); | |
1245 | if (ret) | |
2841be9a | 1246 | goto error_pcm; |
de623ece MP |
1247 | } else { |
1248 | ret = imx_pcm_dma_init(pdev); | |
1249 | if (ret) | |
2841be9a | 1250 | goto error_pcm; |
de623ece | 1251 | } |
09ce1111 SG |
1252 | } |
1253 | ||
1254 | /* | |
1255 | * If codec-handle property is missing from SSI node, we assume | |
1256 | * that the machine driver uses new binding which does not require | |
1257 | * SSI driver to trigger machine driver's probe. | |
1258 | */ | |
1259 | if (!of_get_property(np, "codec-handle", NULL)) { | |
1260 | ssi_private->new_binding = true; | |
1261 | goto done; | |
1262 | } | |
1263 | ||
f0fba2ad | 1264 | /* Trigger the machine driver's probe function. The platform driver |
2b81ec69 | 1265 | * name of the machine driver is taken from /compatible property of the |
f0fba2ad LG |
1266 | * device tree. We also pass the address of the CPU DAI driver |
1267 | * structure. | |
1268 | */ | |
2b81ec69 SG |
1269 | sprop = of_get_property(of_find_node_by_path("/"), "compatible", NULL); |
1270 | /* Sometimes the compatible name has a "fsl," prefix, so we strip it. */ | |
f0fba2ad LG |
1271 | p = strrchr(sprop, ','); |
1272 | if (p) | |
1273 | sprop = p + 1; | |
1274 | snprintf(name, sizeof(name), "snd-soc-%s", sprop); | |
1275 | make_lowercase(name); | |
1276 | ||
1277 | ssi_private->pdev = | |
38fec727 | 1278 | platform_device_register_data(&pdev->dev, name, 0, NULL, 0); |
f0fba2ad LG |
1279 | if (IS_ERR(ssi_private->pdev)) { |
1280 | ret = PTR_ERR(ssi_private->pdev); | |
38fec727 | 1281 | dev_err(&pdev->dev, "failed to register platform: %d\n", ret); |
1fab6caf | 1282 | goto error_dai; |
3f4b783c | 1283 | } |
17467f23 | 1284 | |
09ce1111 | 1285 | done: |
f0fba2ad | 1286 | return 0; |
87a0632b | 1287 | |
1fab6caf | 1288 | error_dai: |
2841be9a MP |
1289 | if (ssi_private->ssi_on_imx && !ssi_private->use_dma) |
1290 | imx_pcm_fiq_exit(pdev); | |
1291 | ||
1292 | error_pcm: | |
f138e621 | 1293 | fsl_ssi_debugfs_remove(&ssi_private->dbg_stats); |
9368acc4 MP |
1294 | |
1295 | error_dbgfs: | |
3580aa10 | 1296 | snd_soc_unregister_component(&pdev->dev); |
1fab6caf TT |
1297 | |
1298 | error_dev: | |
1fab6caf TT |
1299 | device_remove_file(&pdev->dev, dev_attr); |
1300 | ||
95cd98f9 | 1301 | error_clk: |
aafa85e7 NC |
1302 | if (ssi_private->ssi_on_imx) { |
1303 | if (!IS_ERR(ssi_private->baudclk)) | |
1304 | clk_disable_unprepare(ssi_private->baudclk); | |
95cd98f9 | 1305 | clk_disable_unprepare(ssi_private->clk); |
aafa85e7 | 1306 | } |
1fab6caf TT |
1307 | |
1308 | error_irqmap: | |
2841be9a MP |
1309 | if (ssi_private->irq_stats) |
1310 | irq_dispose_mapping(ssi_private->irq); | |
1fab6caf | 1311 | |
87a0632b | 1312 | return ret; |
17467f23 | 1313 | } |
17467f23 | 1314 | |
38fec727 | 1315 | static int fsl_ssi_remove(struct platform_device *pdev) |
17467f23 | 1316 | { |
38fec727 | 1317 | struct fsl_ssi_private *ssi_private = dev_get_drvdata(&pdev->dev); |
17467f23 | 1318 | |
f138e621 | 1319 | fsl_ssi_debugfs_remove(&ssi_private->dbg_stats); |
9368acc4 | 1320 | |
09ce1111 SG |
1321 | if (!ssi_private->new_binding) |
1322 | platform_device_unregister(ssi_private->pdev); | |
3580aa10 | 1323 | snd_soc_unregister_component(&pdev->dev); |
aafa85e7 NC |
1324 | if (ssi_private->ssi_on_imx) { |
1325 | if (!IS_ERR(ssi_private->baudclk)) | |
1326 | clk_disable_unprepare(ssi_private->baudclk); | |
0783e648 | 1327 | clk_disable_unprepare(ssi_private->clk); |
aafa85e7 | 1328 | } |
2841be9a MP |
1329 | if (ssi_private->irq_stats) |
1330 | irq_dispose_mapping(ssi_private->irq); | |
f0fba2ad LG |
1331 | |
1332 | return 0; | |
17467f23 | 1333 | } |
f0fba2ad | 1334 | |
f07eb223 | 1335 | static struct platform_driver fsl_ssi_driver = { |
f0fba2ad LG |
1336 | .driver = { |
1337 | .name = "fsl-ssi-dai", | |
1338 | .owner = THIS_MODULE, | |
1339 | .of_match_table = fsl_ssi_ids, | |
1340 | }, | |
1341 | .probe = fsl_ssi_probe, | |
1342 | .remove = fsl_ssi_remove, | |
1343 | }; | |
17467f23 | 1344 | |
ba0a7e02 | 1345 | module_platform_driver(fsl_ssi_driver); |
a454dad1 | 1346 | |
f3142807 | 1347 | MODULE_ALIAS("platform:fsl-ssi-dai"); |
17467f23 TT |
1348 | MODULE_AUTHOR("Timur Tabi <timur@freescale.com>"); |
1349 | MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver"); | |
f0fba2ad | 1350 | MODULE_LICENSE("GPL v2"); |