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ASoC: twl4030: Replace TLV_DB_RANGE_HEAD with DECLARE_TLV_DB_RANGE
[linux-2.6-block.git] / sound / soc / codecs / twl4030.c
CommitLineData
cc17557e
SS		 1/*
2 * ALSA SoC TWL4030 codec driver
3 *
4 * Author: Steve Sakoman, <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/pm.h>
27#include <linux/i2c.h>
28#include <linux/platform_device.h>
2d6d649a
PU		 29#include <linux/of.h>
30#include <linux/of_gpio.h>
b07682b6 31#include <linux/i2c/twl.h>
5a0e3ad6 32#include <linux/slab.h>
281ecd16 33#include <linux/gpio.h>
cc17557e
SS		 34#include <sound/core.h>
35#include <sound/pcm.h>
36#include <sound/pcm_params.h>
37#include <sound/soc.h>
cc17557e 38#include <sound/initval.h>
c10b82cf 39#include <sound/tlv.h>
cc17557e 40
f0fba2ad 41/* Register descriptions are here */
57fe7251 42#include <linux/mfd/twl4030-audio.h>
f0fba2ad 43
5712ded9
PU		 44/* TWL4030 PMBR1 Register */
45#define TWL4030_PMBR1_REG 0x0D
46/* TWL4030 PMBR1 Register GPIO6 mux bits */
47#define TWL4030_GPIO6_PWM0_MUTE(value) ((value & 0x03) << 2)
48
052901f4 49#define TWL4030_CACHEREGNUM (TWL4030_REG_MISC_SET_2 + 1)
cc17557e 50
7393958f
PU		 51/* codec private data */
52struct twl4030_priv {
7393958f 53 unsigned int codec_powered;
7b4c734e
PU		 54
55 /* reference counts of AIF/APLL users */
2845fa13 56 unsigned int apll_enabled;
7220b9f4
PU		 57
58 struct snd_pcm_substream *master_substream;
59 struct snd_pcm_substream *slave_substream;
6b87a91f
PU		 60
61 unsigned int configured;
62 unsigned int rate;
63 unsigned int sample_bits;
64 unsigned int channels;
6943c92e
PU		 65
66 unsigned int sysclk;
67
c96907f2
PU		 68 /* Output (with associated amp) states */
69 u8 hsl_enabled, hsr_enabled;
70 u8 earpiece_enabled;
71 u8 predrivel_enabled, predriver_enabled;
72 u8 carkitl_enabled, carkitr_enabled;
8b3bca29 73 u8 ctl_cache[TWL4030_REG_PRECKR_CTL - TWL4030_REG_EAR_CTL + 1];
01ea6ba2 74
182f73f6 75 struct twl4030_codec_data *pdata;
7393958f
PU		 76};
77
8b3bca29
PU		 78static void tw4030_init_ctl_cache(struct twl4030_priv *twl4030)
79{
80 int i;
81 u8 byte;
82
83 for (i = TWL4030_REG_EAR_CTL; i <= TWL4030_REG_PRECKR_CTL; i++) {
84 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte, i);
85 twl4030->ctl_cache[i - TWL4030_REG_EAR_CTL] = byte;
86 }
87}
88
efc8acff 89static unsigned int twl4030_read(struct snd_soc_codec *codec, unsigned int reg)
cc17557e 90{
efc8acff
PU		 91 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
92 u8 value = 0;
cc17557e
SS		 93
94 if (reg >= TWL4030_CACHEREGNUM)
efc8acff
PU		 95 return -EIO;
96
97 switch (reg) {
98 case TWL4030_REG_EAR_CTL:
99 case TWL4030_REG_PREDL_CTL:
100 case TWL4030_REG_PREDR_CTL:
101 case TWL4030_REG_PRECKL_CTL:
102 case TWL4030_REG_PRECKR_CTL:
103 case TWL4030_REG_HS_GAIN_SET:
104 value = twl4030->ctl_cache[reg - TWL4030_REG_EAR_CTL];
105 break;
106 default:
107 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &value, reg);
108 break;
109 }
110
111 return value;
cc17557e
SS		 112}
113
b703b504 114static bool twl4030_can_write_to_chip(struct twl4030_priv *twl4030,
a8fc415c 115 unsigned int reg)
cc17557e 116{
a8fc415c 117 bool write_to_reg = false;
c96907f2 118
052901f4
LPC		 119 /* Decide if the given register can be written */
120 switch (reg) {
121 case TWL4030_REG_EAR_CTL:
122 if (twl4030->earpiece_enabled)
a8fc415c 123 write_to_reg = true;
052901f4
LPC		 124 break;
125 case TWL4030_REG_PREDL_CTL:
126 if (twl4030->predrivel_enabled)
a8fc415c 127 write_to_reg = true;
052901f4
LPC		 128 break;
129 case TWL4030_REG_PREDR_CTL:
130 if (twl4030->predriver_enabled)
a8fc415c 131 write_to_reg = true;
052901f4
LPC		 132 break;
133 case TWL4030_REG_PRECKL_CTL:
134 if (twl4030->carkitl_enabled)
a8fc415c 135 write_to_reg = true;
052901f4
LPC		 136 break;
137 case TWL4030_REG_PRECKR_CTL:
138 if (twl4030->carkitr_enabled)
a8fc415c 139 write_to_reg = true;
052901f4
LPC		 140 break;
141 case TWL4030_REG_HS_GAIN_SET:
142 if (twl4030->hsl_enabled || twl4030->hsr_enabled)
a8fc415c 143 write_to_reg = true;
052901f4
LPC		 144 break;
145 default:
146 /* All other register can be written */
a8fc415c 147 write_to_reg = true;
052901f4 148 break;
c96907f2 149 }
a8fc415c
PU		 150
151 return write_to_reg;
152}
153
7ded5fe0
PU		 154static int twl4030_write(struct snd_soc_codec *codec, unsigned int reg,
155 unsigned int value)
a8fc415c 156{
a450aa6f
PU		 157 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
158
159 /* Update the ctl cache */
160 switch (reg) {
161 case TWL4030_REG_EAR_CTL:
162 case TWL4030_REG_PREDL_CTL:
163 case TWL4030_REG_PREDR_CTL:
164 case TWL4030_REG_PRECKL_CTL:
165 case TWL4030_REG_PRECKR_CTL:
166 case TWL4030_REG_HS_GAIN_SET:
167 twl4030->ctl_cache[reg - TWL4030_REG_EAR_CTL] = value;
168 break;
169 default:
170 break;
171 }
172
b703b504 173 if (twl4030_can_write_to_chip(twl4030, reg))
a8fc415c 174 return twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg);
052901f4 175
c96907f2 176 return 0;
cc17557e
SS		 177}
178
7e6120c5
PU		 179static inline void twl4030_wait_ms(int time)
180{
181 if (time < 60) {
182 time *= 1000;
183 usleep_range(time, time + 500);
184 } else {
185 msleep(time);
186 }
187}
188
db04e2c5 189static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
cc17557e 190{
b2c812e2 191 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7a1fecf5 192 int mode;
cc17557e 193
7393958f
PU		 194 if (enable == twl4030->codec_powered)
195 return;
196
db04e2c5 197 if (enable)
57fe7251 198 mode = twl4030_audio_enable_resource(TWL4030_AUDIO_RES_POWER);
db04e2c5 199 else
57fe7251 200 mode = twl4030_audio_disable_resource(TWL4030_AUDIO_RES_POWER);
cc17557e 201
efc8acff 202 if (mode >= 0)
7a1fecf5 203 twl4030->codec_powered = enable;
cc17557e
SS		 204
205 /* REVISIT: this delay is present in TI sample drivers */
206 /* but there seems to be no TRM requirement for it */
207 udelay(10);
208}
209
2d6d649a
PU		 210static void twl4030_setup_pdata_of(struct twl4030_codec_data *pdata,
211 struct device_node *node)
212{
213 int value;
214
215 of_property_read_u32(node, "ti,digimic_delay",
216 &pdata->digimic_delay);
217 of_property_read_u32(node, "ti,ramp_delay_value",
218 &pdata->ramp_delay_value);
219 of_property_read_u32(node, "ti,offset_cncl_path",
220 &pdata->offset_cncl_path);
221 if (!of_property_read_u32(node, "ti,hs_extmute", &value))
222 pdata->hs_extmute = value;
223
224 pdata->hs_extmute_gpio = of_get_named_gpio(node,
225 "ti,hs_extmute_gpio", 0);
226 if (gpio_is_valid(pdata->hs_extmute_gpio))
227 pdata->hs_extmute = 1;
228}
229
230static struct twl4030_codec_data *twl4030_get_pdata(struct snd_soc_codec *codec)
7393958f 231{
4ae6df5e 232 struct twl4030_codec_data *pdata = dev_get_platdata(codec->dev);
2d6d649a
PU		 233 struct device_node *twl4030_codec_node = NULL;
234
235 twl4030_codec_node = of_find_node_by_name(codec->dev->parent->of_node,
236 "codec");
237
238 if (!pdata && twl4030_codec_node) {
239 pdata = devm_kzalloc(codec->dev,
240 sizeof(struct twl4030_codec_data),
241 GFP_KERNEL);
242 if (!pdata) {
243 dev_err(codec->dev, "Can not allocate memory\n");
244 return NULL;
245 }
246 twl4030_setup_pdata_of(pdata, twl4030_codec_node);
247 }
248
249 return pdata;
250}
251
252static void twl4030_init_chip(struct snd_soc_codec *codec)
253{
254 struct twl4030_codec_data *pdata;
b2c812e2 255 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
ee4ccac7
PU		 256 u8 reg, byte;
257 int i = 0;
7393958f 258
2d6d649a
PU		 259 pdata = twl4030_get_pdata(codec);
260
5712ded9
PU		 261 if (pdata && pdata->hs_extmute) {
262 if (gpio_is_valid(pdata->hs_extmute_gpio)) {
263 int ret;
264
265 if (!pdata->hs_extmute_gpio)
266 dev_warn(codec->dev,
267 "Extmute GPIO is 0 is this correct?\n");
268
269 ret = gpio_request_one(pdata->hs_extmute_gpio,
270 GPIOF_OUT_INIT_LOW,
271 "hs_extmute");
272 if (ret) {
273 dev_err(codec->dev,
274 "Failed to get hs_extmute GPIO\n");
275 pdata->hs_extmute_gpio = -1;
276 }
277 } else {
278 u8 pin_mux;
279
280 /* Set TWL4030 GPIO6 as EXTMUTE signal */
281 twl_i2c_read_u8(TWL4030_MODULE_INTBR, &pin_mux,
282 TWL4030_PMBR1_REG);
283 pin_mux &= ~TWL4030_GPIO6_PWM0_MUTE(0x03);
284 pin_mux |= TWL4030_GPIO6_PWM0_MUTE(0x02);
285 twl_i2c_write_u8(TWL4030_MODULE_INTBR, pin_mux,
286 TWL4030_PMBR1_REG);
281ecd16
PU		 287 }
288 }
289
8b3bca29
PU		 290 /* Initialize the local ctl register cache */
291 tw4030_init_ctl_cache(twl4030);
292
ee4ccac7 293 /* anti-pop when changing analog gain */
efc8acff 294 reg = twl4030_read(codec, TWL4030_REG_MISC_SET_1);
ee4ccac7 295 twl4030_write(codec, TWL4030_REG_MISC_SET_1,
7ded5fe0 296 reg | TWL4030_SMOOTH_ANAVOL_EN);
7393958f 297
ee4ccac7 298 twl4030_write(codec, TWL4030_REG_OPTION,
7ded5fe0
PU		 299 TWL4030_ATXL1_EN | TWL4030_ATXR1_EN |
300 TWL4030_ARXL2_EN | TWL4030_ARXR2_EN);
006f367e 301
3c36cc68
PU		 302 /* REG_ARXR2_APGA_CTL reset according to the TRM: 0dB, DA_EN */
303 twl4030_write(codec, TWL4030_REG_ARXR2_APGA_CTL, 0x32);
304
ee4ccac7 305 /* Machine dependent setup */
f0fba2ad 306 if (!pdata)
7393958f
PU		 307 return;
308
182f73f6 309 twl4030->pdata = pdata;
ee4ccac7 310
efc8acff 311 reg = twl4030_read(codec, TWL4030_REG_HS_POPN_SET);
ee4ccac7 312 reg &= ~TWL4030_RAMP_DELAY;
f0fba2ad 313 reg |= (pdata->ramp_delay_value << 2);
efc8acff 314 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, reg);
006f367e
PU		 315
316 /* initiate offset cancellation */
ee4ccac7
PU		 317 twl4030_codec_enable(codec, 1);
318
efc8acff 319 reg = twl4030_read(codec, TWL4030_REG_ANAMICL);
ee4ccac7 320 reg &= ~TWL4030_OFFSET_CNCL_SEL;
f0fba2ad 321 reg |= pdata->offset_cncl_path;
006f367e 322 twl4030_write(codec, TWL4030_REG_ANAMICL,
7ded5fe0 323 reg | TWL4030_CNCL_OFFSET_START);
006f367e 324
7e6120c5
PU		 325 /*
326 * Wait for offset cancellation to complete.
327 * Since this takes a while, do not slam the i2c.
328 * Start polling the status after ~20ms.
329 */
330 msleep(20);
006f367e 331 do {
7e6120c5 332 usleep_range(1000, 2000);
efc8acff 333 twl_set_regcache_bypass(TWL4030_MODULE_AUDIO_VOICE, true);
fc7b92fc 334 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
7ded5fe0 335 TWL4030_REG_ANAMICL);
efc8acff 336 twl_set_regcache_bypass(TWL4030_MODULE_AUDIO_VOICE, false);
006f367e
PU		 337 } while ((i++ < 100) &&
338 ((byte & TWL4030_CNCL_OFFSET_START) ==
339 TWL4030_CNCL_OFFSET_START));
340
006f367e 341 twl4030_codec_enable(codec, 0);
006f367e
PU		 342}
343
ee4ccac7 344static void twl4030_apll_enable(struct snd_soc_codec *codec, int enable)
006f367e 345{
ee4ccac7 346 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
ee4ccac7
PU		 347
348 if (enable) {
349 twl4030->apll_enabled++;
350 if (twl4030->apll_enabled == 1)
bb17bc78 351 twl4030_audio_enable_resource(
57fe7251 352 TWL4030_AUDIO_RES_APLL);
ee4ccac7
PU		 353 } else {
354 twl4030->apll_enabled--;
355 if (!twl4030->apll_enabled)
bb17bc78 356 twl4030_audio_disable_resource(
57fe7251 357 TWL4030_AUDIO_RES_APLL);
ee4ccac7 358 }
006f367e
PU		 359}
360
5e98a464 361/* Earpiece */
1a787e7a
JS		 362static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
363 SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
364 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
365 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
366 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
367};
5e98a464 368
2a6f5c58 369/* PreDrive Left */
1a787e7a
JS		 370static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
371 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
372 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
373 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
374 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
375};
2a6f5c58
PU		 376
377/* PreDrive Right */
1a787e7a
JS		 378static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
379 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
380 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
381 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
382 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
383};
2a6f5c58 384
dfad21a2 385/* Headset Left */
1a787e7a
JS		 386static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
387 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
388 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
389 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
390};
dfad21a2
PU		 391
392/* Headset Right */
1a787e7a
JS		 393static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
394 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
395 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
396 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
397};
dfad21a2 398
5152d8c2 399/* Carkit Left */
1a787e7a
JS		 400static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
401 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
402 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
403 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
404};
5152d8c2
PU		 405
406/* Carkit Right */
1a787e7a
JS		 407static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
408 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
409 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
410 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
411};
5152d8c2 412
df339804
PU		 413/* Handsfree Left */
414static const char *twl4030_handsfreel_texts[] =
1a787e7a 415 {"Voice", "AudioL1", "AudioL2", "AudioR2"};
df339804 416
9f04fba7
TI		 417static SOC_ENUM_SINGLE_DECL(twl4030_handsfreel_enum,
418 TWL4030_REG_HFL_CTL, 0,
419 twl4030_handsfreel_texts);
df339804
PU		 420
421static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
422SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
423
0f89bdca
PU		 424/* Handsfree Left virtual mute */
425static const struct snd_kcontrol_new twl4030_dapm_handsfreelmute_control =
052901f4 426 SOC_DAPM_SINGLE_VIRT("Switch", 1);
0f89bdca 427
df339804
PU		 428/* Handsfree Right */
429static const char *twl4030_handsfreer_texts[] =
1a787e7a 430 {"Voice", "AudioR1", "AudioR2", "AudioL2"};
df339804 431
9f04fba7
TI		 432static SOC_ENUM_SINGLE_DECL(twl4030_handsfreer_enum,
433 TWL4030_REG_HFR_CTL, 0,
434 twl4030_handsfreer_texts);
df339804
PU		 435
436static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
437SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
438
0f89bdca
PU		 439/* Handsfree Right virtual mute */
440static const struct snd_kcontrol_new twl4030_dapm_handsfreermute_control =
052901f4 441 SOC_DAPM_SINGLE_VIRT("Switch", 1);
0f89bdca 442
376f7839
PU		 443/* Vibra */
444/* Vibra audio path selection */
445static const char *twl4030_vibra_texts[] =
446 {"AudioL1", "AudioR1", "AudioL2", "AudioR2"};
447
9f04fba7
TI		 448static SOC_ENUM_SINGLE_DECL(twl4030_vibra_enum,
449 TWL4030_REG_VIBRA_CTL, 2,
450 twl4030_vibra_texts);
376f7839
PU		 451
452static const struct snd_kcontrol_new twl4030_dapm_vibra_control =
453SOC_DAPM_ENUM("Route", twl4030_vibra_enum);
454
455/* Vibra path selection: local vibrator (PWM) or audio driven */
456static const char *twl4030_vibrapath_texts[] =
457 {"Local vibrator", "Audio"};
458
9f04fba7
TI		 459static SOC_ENUM_SINGLE_DECL(twl4030_vibrapath_enum,
460 TWL4030_REG_VIBRA_CTL, 4,
461 twl4030_vibrapath_texts);
376f7839
PU		 462
463static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =
464SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);
465
276c6222 466/* Left analog microphone selection */
97b8096d 467static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = {
9028935d
PU		 468 SOC_DAPM_SINGLE("Main Mic Capture Switch",
469 TWL4030_REG_ANAMICL, 0, 1, 0),
470 SOC_DAPM_SINGLE("Headset Mic Capture Switch",
471 TWL4030_REG_ANAMICL, 1, 1, 0),
472 SOC_DAPM_SINGLE("AUXL Capture Switch",
473 TWL4030_REG_ANAMICL, 2, 1, 0),
474 SOC_DAPM_SINGLE("Carkit Mic Capture Switch",
475 TWL4030_REG_ANAMICL, 3, 1, 0),
97b8096d 476};
276c6222
PU		 477
478/* Right analog microphone selection */
97b8096d 479static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = {
9028935d
PU		 480 SOC_DAPM_SINGLE("Sub Mic Capture Switch", TWL4030_REG_ANAMICR, 0, 1, 0),
481 SOC_DAPM_SINGLE("AUXR Capture Switch", TWL4030_REG_ANAMICR, 2, 1, 0),
97b8096d 482};
276c6222
PU		 483
484/* TX1 L/R Analog/Digital microphone selection */
485static const char *twl4030_micpathtx1_texts[] =
486 {"Analog", "Digimic0"};
487
9f04fba7
TI		 488static SOC_ENUM_SINGLE_DECL(twl4030_micpathtx1_enum,
489 TWL4030_REG_ADCMICSEL, 0,
490 twl4030_micpathtx1_texts);
276c6222
PU		 491
492static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
493SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
494
495/* TX2 L/R Analog/Digital microphone selection */
496static const char *twl4030_micpathtx2_texts[] =
497 {"Analog", "Digimic1"};
498
9f04fba7
TI		 499static SOC_ENUM_SINGLE_DECL(twl4030_micpathtx2_enum,
500 TWL4030_REG_ADCMICSEL, 2,
501 twl4030_micpathtx2_texts);
276c6222
PU		 502
503static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
504SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
505
7393958f
PU		 506/* Analog bypass for AudioR1 */
507static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
508 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
509
510/* Analog bypass for AudioL1 */
511static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
512 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
513
514/* Analog bypass for AudioR2 */
515static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
516 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
517
518/* Analog bypass for AudioL2 */
519static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
520 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
521
fcd274a3
LCM		 522/* Analog bypass for Voice */
523static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =
524 SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);
525
8b0d3153 526/* Digital bypass gain, mute instead of -30dB */
2524911e 527static const DECLARE_TLV_DB_RANGE(twl4030_dapm_dbypass_tlv,
8b0d3153
PU		 528 0, 1, TLV_DB_SCALE_ITEM(-3000, 600, 1),
529 2, 3, TLV_DB_SCALE_ITEM(-2400, 0, 0),
2524911e
LPC		 530 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0)
531);
6bab83fd
PU		 532
533/* Digital bypass left (TX1L -> RX2L) */
534static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
535 SOC_DAPM_SINGLE_TLV("Volume",
536 TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
537 twl4030_dapm_dbypass_tlv);
538
539/* Digital bypass right (TX1R -> RX2R) */
540static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
541 SOC_DAPM_SINGLE_TLV("Volume",
542 TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
543 twl4030_dapm_dbypass_tlv);
544
ee8f6894
LCM		 545/*
546 * Voice Sidetone GAIN volume control:
547 * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)
548 */
549static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);
550
551/* Digital bypass voice: sidetone (VUL -> VDL)*/
552static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =
553 SOC_DAPM_SINGLE_TLV("Volume",
554 TWL4030_REG_VSTPGA, 0, 0x29, 0,
555 twl4030_dapm_dbypassv_tlv);
556
9008adf9
PU		 557/*
558 * Output PGA builder:
559 * Handle the muting and unmuting of the given output (turning off the
560 * amplifier associated with the output pin)
c96907f2
PU		 561 * On mute bypass the reg_cache and write 0 to the register
562 * On unmute: restore the register content from the reg_cache
9008adf9
PU		 563 * Outputs handled in this way: Earpiece, PreDrivL/R, CarkitL/R
564 */
565#define TWL4030_OUTPUT_PGA(pin_name, reg, mask) \
566static int pin_name##pga_event(struct snd_soc_dapm_widget *w, \
7ded5fe0 567 struct snd_kcontrol *kcontrol, int event) \
9008adf9 568{ \
a36ac9b3
LPC		 569 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); \
570 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); \
9008adf9
PU		 571 \
572 switch (event) { \
573 case SND_SOC_DAPM_POST_PMU: \
c96907f2 574 twl4030->pin_name##_enabled = 1; \
a36ac9b3 575 twl4030_write(codec, reg, twl4030_read(codec, reg)); \
9008adf9
PU		 576 break; \
577 case SND_SOC_DAPM_POST_PMD: \
c96907f2 578 twl4030->pin_name##_enabled = 0; \
7ded5fe0 579 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, 0, reg); \
9008adf9
PU		 580 break; \
581 } \
582 return 0; \
583}
584
585TWL4030_OUTPUT_PGA(earpiece, TWL4030_REG_EAR_CTL, TWL4030_EAR_GAIN);
586TWL4030_OUTPUT_PGA(predrivel, TWL4030_REG_PREDL_CTL, TWL4030_PREDL_GAIN);
587TWL4030_OUTPUT_PGA(predriver, TWL4030_REG_PREDR_CTL, TWL4030_PREDR_GAIN);
588TWL4030_OUTPUT_PGA(carkitl, TWL4030_REG_PRECKL_CTL, TWL4030_PRECKL_GAIN);
589TWL4030_OUTPUT_PGA(carkitr, TWL4030_REG_PRECKR_CTL, TWL4030_PRECKR_GAIN);
590
5a2e9a48 591static void handsfree_ramp(struct snd_soc_codec *codec, int reg, int ramp)
49d92c7d 592{
49d92c7d
SM		 593 unsigned char hs_ctl;
594
efc8acff 595 hs_ctl = twl4030_read(codec, reg);
49d92c7d 596
5a2e9a48
PU		 597 if (ramp) {
598 /* HF ramp-up */
599 hs_ctl |= TWL4030_HF_CTL_REF_EN;
600 twl4030_write(codec, reg, hs_ctl);
601 udelay(10);
49d92c7d 602 hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
5a2e9a48
PU		 603 twl4030_write(codec, reg, hs_ctl);
604 udelay(40);
49d92c7d 605 hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
49d92c7d 606 hs_ctl |= TWL4030_HF_CTL_HB_EN;
5a2e9a48 607 twl4030_write(codec, reg, hs_ctl);
49d92c7d 608 } else {
5a2e9a48
PU		 609 /* HF ramp-down */
610 hs_ctl &= ~TWL4030_HF_CTL_LOOP_EN;
611 hs_ctl &= ~TWL4030_HF_CTL_HB_EN;
612 twl4030_write(codec, reg, hs_ctl);
613 hs_ctl &= ~TWL4030_HF_CTL_RAMP_EN;
614 twl4030_write(codec, reg, hs_ctl);
615 udelay(40);
616 hs_ctl &= ~TWL4030_HF_CTL_REF_EN;
617 twl4030_write(codec, reg, hs_ctl);
49d92c7d 618 }
5a2e9a48 619}
49d92c7d 620
5a2e9a48 621static int handsfreelpga_event(struct snd_soc_dapm_widget *w,
7ded5fe0 622 struct snd_kcontrol *kcontrol, int event)
5a2e9a48 623{
a36ac9b3
LPC		 624 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
625
5a2e9a48
PU		 626 switch (event) {
627 case SND_SOC_DAPM_POST_PMU:
a36ac9b3 628 handsfree_ramp(codec, TWL4030_REG_HFL_CTL, 1);
5a2e9a48
PU		 629 break;
630 case SND_SOC_DAPM_POST_PMD:
a36ac9b3 631 handsfree_ramp(codec, TWL4030_REG_HFL_CTL, 0);
5a2e9a48
PU		 632 break;
633 }
634 return 0;
635}
636
637static int handsfreerpga_event(struct snd_soc_dapm_widget *w,
7ded5fe0 638 struct snd_kcontrol *kcontrol, int event)
5a2e9a48 639{
a36ac9b3
LPC		 640 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
641
5a2e9a48
PU		 642 switch (event) {
643 case SND_SOC_DAPM_POST_PMU:
a36ac9b3 644 handsfree_ramp(codec, TWL4030_REG_HFR_CTL, 1);
5a2e9a48
PU		 645 break;
646 case SND_SOC_DAPM_POST_PMD:
a36ac9b3 647 handsfree_ramp(codec, TWL4030_REG_HFR_CTL, 0);
5a2e9a48
PU		 648 break;
649 }
49d92c7d
SM		 650 return 0;
651}
652
86139a13 653static int vibramux_event(struct snd_soc_dapm_widget *w,
7ded5fe0 654 struct snd_kcontrol *kcontrol, int event)
86139a13 655{
a36ac9b3
LPC		 656 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
657
658 twl4030_write(codec, TWL4030_REG_VIBRA_SET, 0xff);
86139a13
JV		 659 return 0;
660}
661
7729cf74 662static int apll_event(struct snd_soc_dapm_widget *w,
7ded5fe0 663 struct snd_kcontrol *kcontrol, int event)
7729cf74 664{
a36ac9b3
LPC		 665 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
666
7729cf74
PU		 667 switch (event) {
668 case SND_SOC_DAPM_PRE_PMU:
a36ac9b3 669 twl4030_apll_enable(codec, 1);
7729cf74
PU		 670 break;
671 case SND_SOC_DAPM_POST_PMD:
a36ac9b3 672 twl4030_apll_enable(codec, 0);
7729cf74
PU		 673 break;
674 }
675 return 0;
676}
677
7b4c734e 678static int aif_event(struct snd_soc_dapm_widget *w,
7ded5fe0 679 struct snd_kcontrol *kcontrol, int event)
7b4c734e 680{
a36ac9b3 681 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
7b4c734e
PU		 682 u8 audio_if;
683
a36ac9b3 684 audio_if = twl4030_read(codec, TWL4030_REG_AUDIO_IF);
7b4c734e
PU		 685 switch (event) {
686 case SND_SOC_DAPM_PRE_PMU:
687 /* Enable AIF */
688 /* enable the PLL before we use it to clock the DAI */
a36ac9b3 689 twl4030_apll_enable(codec, 1);
7b4c734e 690
a36ac9b3 691 twl4030_write(codec, TWL4030_REG_AUDIO_IF,
7ded5fe0 692 audio_if | TWL4030_AIF_EN);
7b4c734e
PU		 693 break;
694 case SND_SOC_DAPM_POST_PMD:
695 /* disable the DAI before we stop it's source PLL */
a36ac9b3 696 twl4030_write(codec, TWL4030_REG_AUDIO_IF,
7ded5fe0 697 audio_if & ~TWL4030_AIF_EN);
a36ac9b3 698 twl4030_apll_enable(codec, 0);
7b4c734e
PU		 699 break;
700 }
701 return 0;
702}
703
6943c92e 704static void headset_ramp(struct snd_soc_codec *codec, int ramp)
aad749e5
PU		 705{
706 unsigned char hs_gain, hs_pop;
b2c812e2 707 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
182f73f6 708 struct twl4030_codec_data *pdata = twl4030->pdata;
6943c92e
PU		 709 /* Base values for ramp delay calculation: 2^19 - 2^26 */
710 unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304,
711 8388608, 16777216, 33554432, 67108864};
7e6120c5 712 unsigned int delay;
aad749e5 713
efc8acff
PU		 714 hs_gain = twl4030_read(codec, TWL4030_REG_HS_GAIN_SET);
715 hs_pop = twl4030_read(codec, TWL4030_REG_HS_POPN_SET);
7e6120c5
PU		 716 delay = (ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
717 twl4030->sysclk) + 1;
aad749e5 718
4e49ffd1
CVJ		 719 /* Enable external mute control, this dramatically reduces
720 * the pop-noise */
f0fba2ad 721 if (pdata && pdata->hs_extmute) {
281ecd16
PU		 722 if (gpio_is_valid(pdata->hs_extmute_gpio)) {
723 gpio_set_value(pdata->hs_extmute_gpio, 1);
4e49ffd1
CVJ		 724 } else {
725 hs_pop |= TWL4030_EXTMUTE;
726 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
727 }
728 }
729
6943c92e
PU		 730 if (ramp) {
731 /* Headset ramp-up according to the TRM */
aad749e5 732 hs_pop |= TWL4030_VMID_EN;
6943c92e 733 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
c96907f2 734 /* Actually write to the register */
7ded5fe0
PU		 735 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, hs_gain,
736 TWL4030_REG_HS_GAIN_SET);
aad749e5 737 hs_pop |= TWL4030_RAMP_EN;
6943c92e 738 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
4e49ffd1 739 /* Wait ramp delay time + 1, so the VMID can settle */
7e6120c5 740 twl4030_wait_ms(delay);
6943c92e
PU		 741 } else {
742 /* Headset ramp-down _not_ according to
743 * the TRM, but in a way that it is working */
aad749e5 744 hs_pop &= ~TWL4030_RAMP_EN;
6943c92e
PU		 745 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
746 /* Wait ramp delay time + 1, so the VMID can settle */
7e6120c5 747 twl4030_wait_ms(delay);
aad749e5 748 /* Bypass the reg_cache to mute the headset */
7ded5fe0
PU		 749 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, hs_gain & (~0x0f),
750 TWL4030_REG_HS_GAIN_SET);
6943c92e 751
aad749e5 752 hs_pop &= ~TWL4030_VMID_EN;
6943c92e
PU		 753 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
754 }
4e49ffd1
CVJ		 755
756 /* Disable external mute */
f0fba2ad 757 if (pdata && pdata->hs_extmute) {
281ecd16
PU		 758 if (gpio_is_valid(pdata->hs_extmute_gpio)) {
759 gpio_set_value(pdata->hs_extmute_gpio, 0);
4e49ffd1
CVJ		 760 } else {
761 hs_pop &= ~TWL4030_EXTMUTE;
762 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
763 }
764 }
6943c92e
PU		 765}
766
767static int headsetlpga_event(struct snd_soc_dapm_widget *w,
7ded5fe0 768 struct snd_kcontrol *kcontrol, int event)
6943c92e 769{
a36ac9b3
LPC		 770 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
771 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
6943c92e
PU		 772
773 switch (event) {
774 case SND_SOC_DAPM_POST_PMU:
775 /* Do the ramp-up only once */
776 if (!twl4030->hsr_enabled)
a36ac9b3 777 headset_ramp(codec, 1);
6943c92e
PU		 778
779 twl4030->hsl_enabled = 1;
780 break;
781 case SND_SOC_DAPM_POST_PMD:
782 /* Do the ramp-down only if both headsetL/R is disabled */
783 if (!twl4030->hsr_enabled)
a36ac9b3 784 headset_ramp(codec, 0);
6943c92e
PU		 785
786 twl4030->hsl_enabled = 0;
787 break;
788 }
789 return 0;
790}
791
792static int headsetrpga_event(struct snd_soc_dapm_widget *w,
7ded5fe0 793 struct snd_kcontrol *kcontrol, int event)
6943c92e 794{
a36ac9b3
LPC		 795 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
796 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
6943c92e
PU		 797
798 switch (event) {
799 case SND_SOC_DAPM_POST_PMU:
800 /* Do the ramp-up only once */
801 if (!twl4030->hsl_enabled)
a36ac9b3 802 headset_ramp(codec, 1);
6943c92e
PU		 803
804 twl4030->hsr_enabled = 1;
805 break;
806 case SND_SOC_DAPM_POST_PMD:
807 /* Do the ramp-down only if both headsetL/R is disabled */
808 if (!twl4030->hsl_enabled)
a36ac9b3 809 headset_ramp(codec, 0);
6943c92e
PU		 810
811 twl4030->hsr_enabled = 0;
aad749e5
PU		 812 break;
813 }
814 return 0;
815}
816
01ea6ba2 817static int digimic_event(struct snd_soc_dapm_widget *w,
7ded5fe0 818 struct snd_kcontrol *kcontrol, int event)
01ea6ba2 819{
a36ac9b3
LPC		 820 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
821 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
182f73f6 822 struct twl4030_codec_data *pdata = twl4030->pdata;
01ea6ba2 823
182f73f6
PU		 824 if (pdata && pdata->digimic_delay)
825 twl4030_wait_ms(pdata->digimic_delay);
01ea6ba2
PU		 826 return 0;
827}
828
b0bd53a7
PU		 829/*
830 * Some of the gain controls in TWL (mostly those which are associated with
831 * the outputs) are implemented in an interesting way:
832 * 0x0 : Power down (mute)
833 * 0x1 : 6dB
834 * 0x2 : 0 dB
835 * 0x3 : -6 dB
836 * Inverting not going to help with these.
837 * Custom volsw and volsw_2r get/put functions to handle these gain bits.
838 */
b0bd53a7 839static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
7ded5fe0 840 struct snd_ctl_elem_value *ucontrol)
b0bd53a7
PU		 841{
842 struct soc_mixer_control *mc =
843 (struct soc_mixer_control *)kcontrol->private_value;
ea53bf77 844 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
b0bd53a7
PU		 845 unsigned int reg = mc->reg;
846 unsigned int shift = mc->shift;
847 unsigned int rshift = mc->rshift;
848 int max = mc->max;
849 int mask = (1 << fls(max)) - 1;
850
851 ucontrol->value.integer.value[0] =
852 (snd_soc_read(codec, reg) >> shift) & mask;
853 if (ucontrol->value.integer.value[0])
854 ucontrol->value.integer.value[0] =
855 max + 1 - ucontrol->value.integer.value[0];
856
857 if (shift != rshift) {
858 ucontrol->value.integer.value[1] =
859 (snd_soc_read(codec, reg) >> rshift) & mask;
860 if (ucontrol->value.integer.value[1])
861 ucontrol->value.integer.value[1] =
862 max + 1 - ucontrol->value.integer.value[1];
863 }
864
865 return 0;
866}
867
868static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
7ded5fe0 869 struct snd_ctl_elem_value *ucontrol)
b0bd53a7
PU		 870{
871 struct soc_mixer_control *mc =
872 (struct soc_mixer_control *)kcontrol->private_value;
ea53bf77 873 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
b0bd53a7
PU		 874 unsigned int reg = mc->reg;
875 unsigned int shift = mc->shift;
876 unsigned int rshift = mc->rshift;
877 int max = mc->max;
878 int mask = (1 << fls(max)) - 1;
879 unsigned short val, val2, val_mask;
880
881 val = (ucontrol->value.integer.value[0] & mask);
882
883 val_mask = mask << shift;
884 if (val)
885 val = max + 1 - val;
886 val = val << shift;
887 if (shift != rshift) {
888 val2 = (ucontrol->value.integer.value[1] & mask);
889 val_mask |= mask << rshift;
890 if (val2)
891 val2 = max + 1 - val2;
892 val |= val2 << rshift;
893 }
894 return snd_soc_update_bits(codec, reg, val_mask, val);
895}
896
897static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
7ded5fe0 898 struct snd_ctl_elem_value *ucontrol)
b0bd53a7
PU		 899{
900 struct soc_mixer_control *mc =
901 (struct soc_mixer_control *)kcontrol->private_value;
ea53bf77 902 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
b0bd53a7
PU		 903 unsigned int reg = mc->reg;
904 unsigned int reg2 = mc->rreg;
905 unsigned int shift = mc->shift;
906 int max = mc->max;
907 int mask = (1<<fls(max))-1;
908
909 ucontrol->value.integer.value[0] =
910 (snd_soc_read(codec, reg) >> shift) & mask;
911 ucontrol->value.integer.value[1] =
912 (snd_soc_read(codec, reg2) >> shift) & mask;
913
914 if (ucontrol->value.integer.value[0])
915 ucontrol->value.integer.value[0] =
916 max + 1 - ucontrol->value.integer.value[0];
917 if (ucontrol->value.integer.value[1])
918 ucontrol->value.integer.value[1] =
919 max + 1 - ucontrol->value.integer.value[1];
920
921 return 0;
922}
923
924static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
7ded5fe0 925 struct snd_ctl_elem_value *ucontrol)
b0bd53a7
PU		 926{
927 struct soc_mixer_control *mc =
928 (struct soc_mixer_control *)kcontrol->private_value;
ea53bf77 929 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
b0bd53a7
PU		 930 unsigned int reg = mc->reg;
931 unsigned int reg2 = mc->rreg;
932 unsigned int shift = mc->shift;
933 int max = mc->max;
934 int mask = (1 << fls(max)) - 1;
935 int err;
936 unsigned short val, val2, val_mask;
937
938 val_mask = mask << shift;
939 val = (ucontrol->value.integer.value[0] & mask);
940 val2 = (ucontrol->value.integer.value[1] & mask);
941
942 if (val)
943 val = max + 1 - val;
944 if (val2)
945 val2 = max + 1 - val2;
946
947 val = val << shift;
948 val2 = val2 << shift;
949
950 err = snd_soc_update_bits(codec, reg, val_mask, val);
951 if (err < 0)
952 return err;
953
954 err = snd_soc_update_bits(codec, reg2, val_mask, val2);
955 return err;
956}
957
b74bd40f
LCM		 958/* Codec operation modes */
959static const char *twl4030_op_modes_texts[] = {
960 "Option 2 (voice/audio)", "Option 1 (audio)"
961};
962
9f04fba7
TI		 963static SOC_ENUM_SINGLE_DECL(twl4030_op_modes_enum,
964 TWL4030_REG_CODEC_MODE, 0,
965 twl4030_op_modes_texts);
b74bd40f 966
423c238d 967static int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol,
b74bd40f
LCM		 968 struct snd_ctl_elem_value *ucontrol)
969{
ea53bf77 970 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
b2c812e2 971 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
b74bd40f
LCM		 972
973 if (twl4030->configured) {
3b8a0795
PU		 974 dev_err(codec->dev,
975 "operation mode cannot be changed on-the-fly\n");
b74bd40f
LCM		 976 return -EBUSY;
977 }
978
6b207c0f 979 return snd_soc_put_enum_double(kcontrol, ucontrol);
b74bd40f
LCM		 980}
981
c10b82cf
PU		 982/*
983 * FGAIN volume control:
984 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
985 */
d889a72c 986static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
c10b82cf 987
0d33ea0b
PU		 988/*
989 * CGAIN volume control:
990 * 0 dB to 12 dB in 6 dB steps
991 * value 2 and 3 means 12 dB
992 */
d889a72c
PU		 993static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
994
1a787e7a
JS		 995/*
996 * Voice Downlink GAIN volume control:
997 * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
998 */
999static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
1000
d889a72c
PU		 1001/*
1002 * Analog playback gain
1003 * -24 dB to 12 dB in 2 dB steps
1004 */
1005static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
0d33ea0b 1006
4290239c
PU		 1007/*
1008 * Gain controls tied to outputs
1009 * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
1010 */
1011static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
1012
18cc8d8d
JS		 1013/*
1014 * Gain control for earpiece amplifier
1015 * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
1016 */
1017static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
1018
381a22b5
PU		 1019/*
1020 * Capture gain after the ADCs
1021 * from 0 dB to 31 dB in 1 dB steps
1022 */
1023static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
1024
5920b453
GI		 1025/*
1026 * Gain control for input amplifiers
1027 * 0 dB to 30 dB in 6 dB steps
1028 */
1029static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
1030
328d0a13
LCM		 1031/* AVADC clock priority */
1032static const char *twl4030_avadc_clk_priority_texts[] = {
1033 "Voice high priority", "HiFi high priority"
1034};
1035
9f04fba7
TI		 1036static SOC_ENUM_SINGLE_DECL(twl4030_avadc_clk_priority_enum,
1037 TWL4030_REG_AVADC_CTL, 2,
1038 twl4030_avadc_clk_priority_texts);
328d0a13 1039
89492be8
PU		 1040static const char *twl4030_rampdelay_texts[] = {
1041 "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
1042 "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
1043 "3495/2581/1748 ms"
1044};
1045
9f04fba7
TI		 1046static SOC_ENUM_SINGLE_DECL(twl4030_rampdelay_enum,
1047 TWL4030_REG_HS_POPN_SET, 2,
1048 twl4030_rampdelay_texts);
89492be8 1049
376f7839
PU		 1050/* Vibra H-bridge direction mode */
1051static const char *twl4030_vibradirmode_texts[] = {
1052 "Vibra H-bridge direction", "Audio data MSB",
1053};
1054
9f04fba7
TI		 1055static SOC_ENUM_SINGLE_DECL(twl4030_vibradirmode_enum,
1056 TWL4030_REG_VIBRA_CTL, 5,
1057 twl4030_vibradirmode_texts);
376f7839
PU		 1058
1059/* Vibra H-bridge direction */
1060static const char *twl4030_vibradir_texts[] = {
1061 "Positive polarity", "Negative polarity",
1062};
1063
9f04fba7
TI		 1064static SOC_ENUM_SINGLE_DECL(twl4030_vibradir_enum,
1065 TWL4030_REG_VIBRA_CTL, 1,
1066 twl4030_vibradir_texts);
376f7839 1067
36aeff61
PU		 1068/* Digimic Left and right swapping */
1069static const char *twl4030_digimicswap_texts[] = {
1070 "Not swapped", "Swapped",
1071};
1072
9f04fba7
TI		 1073static SOC_ENUM_SINGLE_DECL(twl4030_digimicswap_enum,
1074 TWL4030_REG_MISC_SET_1, 0,
1075 twl4030_digimicswap_texts);
36aeff61 1076
cc17557e 1077static const struct snd_kcontrol_new twl4030_snd_controls[] = {
b74bd40f
LCM		 1078 /* Codec operation mode control */
1079 SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum,
1080 snd_soc_get_enum_double,
1081 snd_soc_put_twl4030_opmode_enum_double),
1082
d889a72c
PU		 1083 /* Common playback gain controls */
1084 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
1085 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1086 0, 0x3f, 0, digital_fine_tlv),
1087 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
1088 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1089 0, 0x3f, 0, digital_fine_tlv),
1090
1091 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
1092 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1093 6, 0x2, 0, digital_coarse_tlv),
1094 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
1095 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1096 6, 0x2, 0, digital_coarse_tlv),
1097
1098 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
1099 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1100 3, 0x12, 1, analog_tlv),
1101 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
1102 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1103 3, 0x12, 1, analog_tlv),
44c55870
PU		 1104 SOC_DOUBLE_R("DAC1 Analog Playback Switch",
1105 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1106 1, 1, 0),
1107 SOC_DOUBLE_R("DAC2 Analog Playback Switch",
1108 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1109 1, 1, 0),
381a22b5 1110
1a787e7a
JS		 1111 /* Common voice downlink gain controls */
1112 SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
1113 TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
1114
1115 SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
1116 TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
1117
1118 SOC_SINGLE("DAC Voice Analog Downlink Switch",
1119 TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
1120
4290239c 1121 /* Separate output gain controls */
0f9887d1 1122 SOC_DOUBLE_R_EXT_TLV("PreDriv Playback Volume",
4290239c 1123 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
0f9887d1
PU		 1124 4, 3, 0, snd_soc_get_volsw_r2_twl4030,
1125 snd_soc_put_volsw_r2_twl4030, output_tvl),
4290239c 1126
0f9887d1
PU		 1127 SOC_DOUBLE_EXT_TLV("Headset Playback Volume",
1128 TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, snd_soc_get_volsw_twl4030,
1129 snd_soc_put_volsw_twl4030, output_tvl),
4290239c 1130
0f9887d1 1131 SOC_DOUBLE_R_EXT_TLV("Carkit Playback Volume",
4290239c 1132 TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
0f9887d1
PU		 1133 4, 3, 0, snd_soc_get_volsw_r2_twl4030,
1134 snd_soc_put_volsw_r2_twl4030, output_tvl),
4290239c 1135
0f9887d1
PU		 1136 SOC_SINGLE_EXT_TLV("Earpiece Playback Volume",
1137 TWL4030_REG_EAR_CTL, 4, 3, 0, snd_soc_get_volsw_twl4030,
1138 snd_soc_put_volsw_twl4030, output_ear_tvl),
4290239c 1139
381a22b5 1140 /* Common capture gain controls */
276c6222 1141 SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
381a22b5
PU		 1142 TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
1143 0, 0x1f, 0, digital_capture_tlv),
276c6222
PU		 1144 SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
1145 TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
1146 0, 0x1f, 0, digital_capture_tlv),
5920b453 1147
276c6222 1148 SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
5920b453 1149 0, 3, 5, 0, input_gain_tlv),
89492be8 1150
328d0a13
LCM		 1151 SOC_ENUM("AVADC Clock Priority", twl4030_avadc_clk_priority_enum),
1152
89492be8 1153 SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
376f7839
PU		 1154
1155 SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),
1156 SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),
36aeff61
PU		 1157
1158 SOC_ENUM("Digimic LR Swap", twl4030_digimicswap_enum),
cc17557e
SS		 1159};
1160
cc17557e 1161static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
276c6222
PU		 1162 /* Left channel inputs */
1163 SND_SOC_DAPM_INPUT("MAINMIC"),
1164 SND_SOC_DAPM_INPUT("HSMIC"),
1165 SND_SOC_DAPM_INPUT("AUXL"),
1166 SND_SOC_DAPM_INPUT("CARKITMIC"),
1167 /* Right channel inputs */
1168 SND_SOC_DAPM_INPUT("SUBMIC"),
1169 SND_SOC_DAPM_INPUT("AUXR"),
1170 /* Digital microphones (Stereo) */
1171 SND_SOC_DAPM_INPUT("DIGIMIC0"),
1172 SND_SOC_DAPM_INPUT("DIGIMIC1"),
1173
1174 /* Outputs */
5e98a464 1175 SND_SOC_DAPM_OUTPUT("EARPIECE"),
2a6f5c58
PU		 1176 SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
1177 SND_SOC_DAPM_OUTPUT("PREDRIVER"),
dfad21a2
PU		 1178 SND_SOC_DAPM_OUTPUT("HSOL"),
1179 SND_SOC_DAPM_OUTPUT("HSOR"),
6a1bee4a
PU		 1180 SND_SOC_DAPM_OUTPUT("CARKITL"),
1181 SND_SOC_DAPM_OUTPUT("CARKITR"),
df339804
PU		 1182 SND_SOC_DAPM_OUTPUT("HFL"),
1183 SND_SOC_DAPM_OUTPUT("HFR"),
376f7839 1184 SND_SOC_DAPM_OUTPUT("VIBRA"),
cc17557e 1185
7b4c734e
PU		 1186 /* AIF and APLL clocks for running DAIs (including loopback) */
1187 SND_SOC_DAPM_OUTPUT("Virtual HiFi OUT"),
1188 SND_SOC_DAPM_INPUT("Virtual HiFi IN"),
1189 SND_SOC_DAPM_OUTPUT("Virtual Voice OUT"),
1190
53b5047d 1191 /* DACs */
7f51e7d3
PU		 1192 SND_SOC_DAPM_DAC("DAC Right1", NULL, SND_SOC_NOPM, 0, 0),
1193 SND_SOC_DAPM_DAC("DAC Left1", NULL, SND_SOC_NOPM, 0, 0),
1194 SND_SOC_DAPM_DAC("DAC Right2", NULL, SND_SOC_NOPM, 0, 0),
1195 SND_SOC_DAPM_DAC("DAC Left2", NULL, SND_SOC_NOPM, 0, 0),
1196 SND_SOC_DAPM_DAC("DAC Voice", NULL, SND_SOC_NOPM, 0, 0),
cc17557e 1197
927a7747
PU		 1198 SND_SOC_DAPM_AIF_IN("VAIFIN", "Voice Playback", 0,
1199 TWL4030_REG_VOICE_IF, 6, 0),
1200
7393958f 1201 /* Analog bypasses */
78e08e2f
PU		 1202 SND_SOC_DAPM_SWITCH("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1203 &twl4030_dapm_abypassr1_control),
1204 SND_SOC_DAPM_SWITCH("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1205 &twl4030_dapm_abypassl1_control),
1206 SND_SOC_DAPM_SWITCH("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1207 &twl4030_dapm_abypassr2_control),
1208 SND_SOC_DAPM_SWITCH("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1209 &twl4030_dapm_abypassl2_control),
1210 SND_SOC_DAPM_SWITCH("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,
1211 &twl4030_dapm_abypassv_control),
1212
1213 /* Master analog loopback switch */
1214 SND_SOC_DAPM_SUPPLY("FM Loop Enable", TWL4030_REG_MISC_SET_1, 5, 0,
1215 NULL, 0),
7393958f 1216
6bab83fd 1217 /* Digital bypasses */
78e08e2f
PU		 1218 SND_SOC_DAPM_SWITCH("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
1219 &twl4030_dapm_dbypassl_control),
1220 SND_SOC_DAPM_SWITCH("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
1221 &twl4030_dapm_dbypassr_control),
1222 SND_SOC_DAPM_SWITCH("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,
1223 &twl4030_dapm_dbypassv_control),
6bab83fd 1224
4005d39a
PU		 1225 /* Digital mixers, power control for the physical DACs */
1226 SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer",
1227 TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0),
1228 SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer",
1229 TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0),
1230 SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer",
1231 TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0),
1232 SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer",
1233 TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0),
1234 SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer",
1235 TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0),
1236
1237 /* Analog mixers, power control for the physical PGAs */
1238 SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer",
1239 TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0),
1240 SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer",
1241 TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0),
1242 SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer",
1243 TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0),
1244 SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer",
1245 TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0),
1246 SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer",
1247 TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0),
7393958f 1248
7729cf74
PU		 1249 SND_SOC_DAPM_SUPPLY("APLL Enable", SND_SOC_NOPM, 0, 0, apll_event,
1250 SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
1251
7b4c734e
PU		 1252 SND_SOC_DAPM_SUPPLY("AIF Enable", SND_SOC_NOPM, 0, 0, aif_event,
1253 SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
c42a59ea 1254
1a787e7a 1255 /* Output MIXER controls */
5e98a464 1256 /* Earpiece */
1a787e7a
JS		 1257 SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
1258 &twl4030_dapm_earpiece_controls[0],
1259 ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
9008adf9
PU		 1260 SND_SOC_DAPM_PGA_E("Earpiece PGA", SND_SOC_NOPM,
1261 0, 0, NULL, 0, earpiecepga_event,
1262 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
2a6f5c58 1263 /* PreDrivL/R */
1a787e7a
JS		 1264 SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
1265 &twl4030_dapm_predrivel_controls[0],
1266 ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
9008adf9
PU		 1267 SND_SOC_DAPM_PGA_E("PredriveL PGA", SND_SOC_NOPM,
1268 0, 0, NULL, 0, predrivelpga_event,
1269 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1a787e7a
JS		 1270 SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
1271 &twl4030_dapm_predriver_controls[0],
1272 ARRAY_SIZE(twl4030_dapm_predriver_controls)),
9008adf9
PU		 1273 SND_SOC_DAPM_PGA_E("PredriveR PGA", SND_SOC_NOPM,
1274 0, 0, NULL, 0, predriverpga_event,
1275 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
dfad21a2 1276 /* HeadsetL/R */
6943c92e 1277 SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
1a787e7a 1278 &twl4030_dapm_hsol_controls[0],
6943c92e
PU		 1279 ARRAY_SIZE(twl4030_dapm_hsol_controls)),
1280 SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM,
1281 0, 0, NULL, 0, headsetlpga_event,
1a787e7a
JS		 1282 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1283 SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
1284 &twl4030_dapm_hsor_controls[0],
1285 ARRAY_SIZE(twl4030_dapm_hsor_controls)),
6943c92e
PU		 1286 SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM,
1287 0, 0, NULL, 0, headsetrpga_event,
1288 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
5152d8c2 1289 /* CarkitL/R */
1a787e7a
JS		 1290 SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
1291 &twl4030_dapm_carkitl_controls[0],
1292 ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
9008adf9
PU		 1293 SND_SOC_DAPM_PGA_E("CarkitL PGA", SND_SOC_NOPM,
1294 0, 0, NULL, 0, carkitlpga_event,
1295 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1a787e7a
JS		 1296 SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
1297 &twl4030_dapm_carkitr_controls[0],
1298 ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
9008adf9
PU		 1299 SND_SOC_DAPM_PGA_E("CarkitR PGA", SND_SOC_NOPM,
1300 0, 0, NULL, 0, carkitrpga_event,
1301 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1a787e7a
JS		 1302
1303 /* Output MUX controls */
df339804 1304 /* HandsfreeL/R */
5a2e9a48
PU		 1305 SND_SOC_DAPM_MUX("HandsfreeL Mux", SND_SOC_NOPM, 0, 0,
1306 &twl4030_dapm_handsfreel_control),
e3c7dbb0 1307 SND_SOC_DAPM_SWITCH("HandsfreeL", SND_SOC_NOPM, 0, 0,
0f89bdca 1308 &twl4030_dapm_handsfreelmute_control),
5a2e9a48
PU		 1309 SND_SOC_DAPM_PGA_E("HandsfreeL PGA", SND_SOC_NOPM,
1310 0, 0, NULL, 0, handsfreelpga_event,
1311 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1312 SND_SOC_DAPM_MUX("HandsfreeR Mux", SND_SOC_NOPM, 5, 0,
1313 &twl4030_dapm_handsfreer_control),
e3c7dbb0 1314 SND_SOC_DAPM_SWITCH("HandsfreeR", SND_SOC_NOPM, 0, 0,
0f89bdca 1315 &twl4030_dapm_handsfreermute_control),
5a2e9a48
PU		 1316 SND_SOC_DAPM_PGA_E("HandsfreeR PGA", SND_SOC_NOPM,
1317 0, 0, NULL, 0, handsfreerpga_event,
1318 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
376f7839 1319 /* Vibra */
86139a13
JV		 1320 SND_SOC_DAPM_MUX_E("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,
1321 &twl4030_dapm_vibra_control, vibramux_event,
1322 SND_SOC_DAPM_PRE_PMU),
376f7839
PU		 1323 SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,
1324 &twl4030_dapm_vibrapath_control),
5e98a464 1325
276c6222
PU		 1326 /* Introducing four virtual ADC, since TWL4030 have four channel for
1327 capture */
7f51e7d3
PU		 1328 SND_SOC_DAPM_ADC("ADC Virtual Left1", NULL, SND_SOC_NOPM, 0, 0),
1329 SND_SOC_DAPM_ADC("ADC Virtual Right1", NULL, SND_SOC_NOPM, 0, 0),
1330 SND_SOC_DAPM_ADC("ADC Virtual Left2", NULL, SND_SOC_NOPM, 0, 0),
1331 SND_SOC_DAPM_ADC("ADC Virtual Right2", NULL, SND_SOC_NOPM, 0, 0),
276c6222 1332
927a7747
PU		 1333 SND_SOC_DAPM_AIF_OUT("VAIFOUT", "Voice Capture", 0,
1334 TWL4030_REG_VOICE_IF, 5, 0),
1335
276c6222
PU		 1336 /* Analog/Digital mic path selection.
1337 TX1 Left/Right: either analog Left/Right or Digimic0
1338 TX2 Left/Right: either analog Left/Right or Digimic1 */
bda7d2a8
PU		 1339 SND_SOC_DAPM_MUX("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
1340 &twl4030_dapm_micpathtx1_control),
1341 SND_SOC_DAPM_MUX("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
1342 &twl4030_dapm_micpathtx2_control),
276c6222 1343
97b8096d 1344 /* Analog input mixers for the capture amplifiers */
9028935d 1345 SND_SOC_DAPM_MIXER("Analog Left",
97b8096d
JS		 1346 TWL4030_REG_ANAMICL, 4, 0,
1347 &twl4030_dapm_analoglmic_controls[0],
1348 ARRAY_SIZE(twl4030_dapm_analoglmic_controls)),
9028935d 1349 SND_SOC_DAPM_MIXER("Analog Right",
97b8096d
JS		 1350 TWL4030_REG_ANAMICR, 4, 0,
1351 &twl4030_dapm_analogrmic_controls[0],
1352 ARRAY_SIZE(twl4030_dapm_analogrmic_controls)),
276c6222 1353
fb2a2f84
PU		 1354 SND_SOC_DAPM_PGA("ADC Physical Left",
1355 TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
1356 SND_SOC_DAPM_PGA("ADC Physical Right",
1357 TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
276c6222 1358
01ea6ba2
PU		 1359 SND_SOC_DAPM_PGA_E("Digimic0 Enable",
1360 TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0,
1361 digimic_event, SND_SOC_DAPM_POST_PMU),
1362 SND_SOC_DAPM_PGA_E("Digimic1 Enable",
1363 TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0,
1364 digimic_event, SND_SOC_DAPM_POST_PMU),
276c6222 1365
bda7d2a8
PU		 1366 SND_SOC_DAPM_SUPPLY("micbias1 select", TWL4030_REG_MICBIAS_CTL, 5, 0,
1367 NULL, 0),
1368 SND_SOC_DAPM_SUPPLY("micbias2 select", TWL4030_REG_MICBIAS_CTL, 6, 0,
1369 NULL, 0),
1370
e04d6e55
PU		 1371 /* Microphone bias */
1372 SND_SOC_DAPM_SUPPLY("Mic Bias 1",
1373 TWL4030_REG_MICBIAS_CTL, 0, 0, NULL, 0),
1374 SND_SOC_DAPM_SUPPLY("Mic Bias 2",
1375 TWL4030_REG_MICBIAS_CTL, 1, 0, NULL, 0),
1376 SND_SOC_DAPM_SUPPLY("Headset Mic Bias",
1377 TWL4030_REG_MICBIAS_CTL, 2, 0, NULL, 0),
7393958f 1378
927a7747 1379 SND_SOC_DAPM_SUPPLY("VIF Enable", TWL4030_REG_VOICE_IF, 0, 0, NULL, 0),
cc17557e
SS		 1380};
1381
1382static const struct snd_soc_dapm_route intercon[] = {
7f51e7d3
PU		 1383 /* Stream -> DAC mapping */
1384 {"DAC Right1", NULL, "HiFi Playback"},
1385 {"DAC Left1", NULL, "HiFi Playback"},
1386 {"DAC Right2", NULL, "HiFi Playback"},
1387 {"DAC Left2", NULL, "HiFi Playback"},
927a7747 1388 {"DAC Voice", NULL, "VAIFIN"},
7f51e7d3
PU		 1389
1390 /* ADC -> Stream mapping */
1391 {"HiFi Capture", NULL, "ADC Virtual Left1"},
1392 {"HiFi Capture", NULL, "ADC Virtual Right1"},
1393 {"HiFi Capture", NULL, "ADC Virtual Left2"},
1394 {"HiFi Capture", NULL, "ADC Virtual Right2"},
927a7747
PU		 1395 {"VAIFOUT", NULL, "ADC Virtual Left2"},
1396 {"VAIFOUT", NULL, "ADC Virtual Right2"},
1397 {"VAIFOUT", NULL, "VIF Enable"},
7f51e7d3 1398
4005d39a
PU		 1399 {"Digital L1 Playback Mixer", NULL, "DAC Left1"},
1400 {"Digital R1 Playback Mixer", NULL, "DAC Right1"},
1401 {"Digital L2 Playback Mixer", NULL, "DAC Left2"},
1402 {"Digital R2 Playback Mixer", NULL, "DAC Right2"},
1403 {"Digital Voice Playback Mixer", NULL, "DAC Voice"},
1404
7729cf74 1405 /* Supply for the digital part (APLL) */
7729cf74
PU		 1406 {"Digital Voice Playback Mixer", NULL, "APLL Enable"},
1407
27eeb1fe
PU		 1408 {"DAC Left1", NULL, "AIF Enable"},
1409 {"DAC Right1", NULL, "AIF Enable"},
1410 {"DAC Left2", NULL, "AIF Enable"},
1411 {"DAC Right1", NULL, "AIF Enable"},
927a7747 1412 {"DAC Voice", NULL, "VIF Enable"},
27eeb1fe 1413
c42a59ea
PU		 1414 {"Digital R2 Playback Mixer", NULL, "AIF Enable"},
1415 {"Digital L2 Playback Mixer", NULL, "AIF Enable"},
1416
4005d39a
PU		 1417 {"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"},
1418 {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"},
1419 {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"},
1420 {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"},
1421 {"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"},
1a787e7a 1422
5e98a464
PU		 1423 /* Internal playback routings */
1424 /* Earpiece */
4005d39a
PU		 1425 {"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"},
1426 {"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1427 {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1428 {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"},
9008adf9 1429 {"Earpiece PGA", NULL, "Earpiece Mixer"},
2a6f5c58 1430 /* PreDrivL */
4005d39a
PU		 1431 {"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"},
1432 {"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1433 {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1434 {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"},
9008adf9 1435 {"PredriveL PGA", NULL, "PredriveL Mixer"},
2a6f5c58 1436 /* PreDrivR */
4005d39a
PU		 1437 {"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"},
1438 {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1439 {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1440 {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"},
9008adf9 1441 {"PredriveR PGA", NULL, "PredriveR Mixer"},
dfad21a2 1442 /* HeadsetL */
4005d39a
PU		 1443 {"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"},
1444 {"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1445 {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
6943c92e 1446 {"HeadsetL PGA", NULL, "HeadsetL Mixer"},
dfad21a2 1447 /* HeadsetR */
4005d39a
PU		 1448 {"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"},
1449 {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1450 {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
6943c92e 1451 {"HeadsetR PGA", NULL, "HeadsetR Mixer"},
5152d8c2 1452 /* CarkitL */
4005d39a
PU		 1453 {"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"},
1454 {"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1455 {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
9008adf9 1456 {"CarkitL PGA", NULL, "CarkitL Mixer"},
5152d8c2 1457 /* CarkitR */
4005d39a
PU		 1458 {"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"},
1459 {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1460 {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
9008adf9 1461 {"CarkitR PGA", NULL, "CarkitR Mixer"},
df339804 1462 /* HandsfreeL */
4005d39a
PU		 1463 {"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"},
1464 {"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"},
1465 {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"},
1466 {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"},
e3c7dbb0
LCM		 1467 {"HandsfreeL", "Switch", "HandsfreeL Mux"},
1468 {"HandsfreeL PGA", NULL, "HandsfreeL"},
df339804 1469 /* HandsfreeR */
4005d39a
PU		 1470 {"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"},
1471 {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"},
1472 {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"},
1473 {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"},
e3c7dbb0
LCM		 1474 {"HandsfreeR", "Switch", "HandsfreeR Mux"},
1475 {"HandsfreeR PGA", NULL, "HandsfreeR"},
376f7839
PU		 1476 /* Vibra */
1477 {"Vibra Mux", "AudioL1", "DAC Left1"},
1478 {"Vibra Mux", "AudioR1", "DAC Right1"},
1479 {"Vibra Mux", "AudioL2", "DAC Left2"},
1480 {"Vibra Mux", "AudioR2", "DAC Right2"},
5e98a464 1481
cc17557e 1482 /* outputs */
7b4c734e 1483 /* Must be always connected (for AIF and APLL) */
27eeb1fe
PU		 1484 {"Virtual HiFi OUT", NULL, "DAC Left1"},
1485 {"Virtual HiFi OUT", NULL, "DAC Right1"},
1486 {"Virtual HiFi OUT", NULL, "DAC Left2"},
1487 {"Virtual HiFi OUT", NULL, "DAC Right2"},
7b4c734e
PU		 1488 /* Must be always connected (for APLL) */
1489 {"Virtual Voice OUT", NULL, "Digital Voice Playback Mixer"},
1490 /* Physical outputs */
9008adf9
PU		 1491 {"EARPIECE", NULL, "Earpiece PGA"},
1492 {"PREDRIVEL", NULL, "PredriveL PGA"},
1493 {"PREDRIVER", NULL, "PredriveR PGA"},
6943c92e
PU		 1494 {"HSOL", NULL, "HeadsetL PGA"},
1495 {"HSOR", NULL, "HeadsetR PGA"},
9008adf9
PU		 1496 {"CARKITL", NULL, "CarkitL PGA"},
1497 {"CARKITR", NULL, "CarkitR PGA"},
5a2e9a48
PU		 1498 {"HFL", NULL, "HandsfreeL PGA"},
1499 {"HFR", NULL, "HandsfreeR PGA"},
376f7839
PU		 1500 {"Vibra Route", "Audio", "Vibra Mux"},
1501 {"VIBRA", NULL, "Vibra Route"},
cc17557e 1502
276c6222 1503 /* Capture path */
7b4c734e
PU		 1504 /* Must be always connected (for AIF and APLL) */
1505 {"ADC Virtual Left1", NULL, "Virtual HiFi IN"},
1506 {"ADC Virtual Right1", NULL, "Virtual HiFi IN"},
1507 {"ADC Virtual Left2", NULL, "Virtual HiFi IN"},
1508 {"ADC Virtual Right2", NULL, "Virtual HiFi IN"},
1509 /* Physical inputs */
9028935d
PU		 1510 {"Analog Left", "Main Mic Capture Switch", "MAINMIC"},
1511 {"Analog Left", "Headset Mic Capture Switch", "HSMIC"},
1512 {"Analog Left", "AUXL Capture Switch", "AUXL"},
1513 {"Analog Left", "Carkit Mic Capture Switch", "CARKITMIC"},
276c6222 1514
9028935d
PU		 1515 {"Analog Right", "Sub Mic Capture Switch", "SUBMIC"},
1516 {"Analog Right", "AUXR Capture Switch", "AUXR"},
276c6222 1517
9028935d
PU		 1518 {"ADC Physical Left", NULL, "Analog Left"},
1519 {"ADC Physical Right", NULL, "Analog Right"},
276c6222
PU		 1520
1521 {"Digimic0 Enable", NULL, "DIGIMIC0"},
1522 {"Digimic1 Enable", NULL, "DIGIMIC1"},
1523
bda7d2a8
PU		 1524 {"DIGIMIC0", NULL, "micbias1 select"},
1525 {"DIGIMIC1", NULL, "micbias2 select"},
1526
276c6222 1527 /* TX1 Left capture path */
fb2a2f84 1528 {"TX1 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1529 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1530 /* TX1 Right capture path */
fb2a2f84 1531 {"TX1 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1532 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1533 /* TX2 Left capture path */
fb2a2f84 1534 {"TX2 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1535 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1536 /* TX2 Right capture path */
fb2a2f84 1537 {"TX2 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1538 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1539
1540 {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
1541 {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
1542 {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
1543 {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
1544
c42a59ea
PU		 1545 {"ADC Virtual Left1", NULL, "AIF Enable"},
1546 {"ADC Virtual Right1", NULL, "AIF Enable"},
1547 {"ADC Virtual Left2", NULL, "AIF Enable"},
1548 {"ADC Virtual Right2", NULL, "AIF Enable"},
1549
7393958f 1550 /* Analog bypass routes */
9028935d
PU		 1551 {"Right1 Analog Loopback", "Switch", "Analog Right"},
1552 {"Left1 Analog Loopback", "Switch", "Analog Left"},
1553 {"Right2 Analog Loopback", "Switch", "Analog Right"},
1554 {"Left2 Analog Loopback", "Switch", "Analog Left"},
1555 {"Voice Analog Loopback", "Switch", "Analog Left"},
7393958f 1556
78e08e2f
PU		 1557 /* Supply for the Analog loopbacks */
1558 {"Right1 Analog Loopback", NULL, "FM Loop Enable"},
1559 {"Left1 Analog Loopback", NULL, "FM Loop Enable"},
1560 {"Right2 Analog Loopback", NULL, "FM Loop Enable"},
1561 {"Left2 Analog Loopback", NULL, "FM Loop Enable"},
1562 {"Voice Analog Loopback", NULL, "FM Loop Enable"},
1563
7393958f
PU		 1564 {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
1565 {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
1566 {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
1567 {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
fcd274a3 1568 {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},
7393958f 1569
6bab83fd
PU		 1570 /* Digital bypass routes */
1571 {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
1572 {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
ee8f6894 1573 {"Voice Digital Loopback", "Volume", "TX2 Capture Route"},
6bab83fd 1574
4005d39a
PU		 1575 {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"},
1576 {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"},
1577 {"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"},
6bab83fd 1578
cc17557e
SS		 1579};
1580
cc17557e
SS		 1581static int twl4030_set_bias_level(struct snd_soc_codec *codec,
1582 enum snd_soc_bias_level level)
1583{
1584 switch (level) {
1585 case SND_SOC_BIAS_ON:
cc17557e
SS		 1586 break;
1587 case SND_SOC_BIAS_PREPARE:
cc17557e
SS		 1588 break;
1589 case SND_SOC_BIAS_STANDBY:
1682c8e5 1590 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF)
ee4ccac7 1591 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1592 break;
1593 case SND_SOC_BIAS_OFF:
cbd2db12 1594 twl4030_codec_enable(codec, 0);
cc17557e
SS		 1595 break;
1596 }
cc17557e
SS		 1597
1598 return 0;
1599}
1600
6b87a91f
PU		 1601static void twl4030_constraints(struct twl4030_priv *twl4030,
1602 struct snd_pcm_substream *mst_substream)
1603{
1604 struct snd_pcm_substream *slv_substream;
1605
1606 /* Pick the stream, which need to be constrained */
1607 if (mst_substream == twl4030->master_substream)
1608 slv_substream = twl4030->slave_substream;
1609 else if (mst_substream == twl4030->slave_substream)
1610 slv_substream = twl4030->master_substream;
1611 else /* This should not happen.. */
1612 return;
1613
1614 /* Set the constraints according to the already configured stream */
1615 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1616 SNDRV_PCM_HW_PARAM_RATE,
1617 twl4030->rate,
1618 twl4030->rate);
1619
1620 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1621 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1622 twl4030->sample_bits,
1623 twl4030->sample_bits);
1624
1625 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1626 SNDRV_PCM_HW_PARAM_CHANNELS,
1627 twl4030->channels,
1628 twl4030->channels);
1629}
1630
8a1f936a
PU		 1631/* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
1632 * capture has to be enabled/disabled. */
1633static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
7ded5fe0 1634 int enable)
8a1f936a
PU		 1635{
1636 u8 reg, mask;
1637
efc8acff 1638 reg = twl4030_read(codec, TWL4030_REG_OPTION);
8a1f936a
PU		 1639
1640 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1641 mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
1642 else
1643 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1644
1645 if (enable)
1646 reg |= mask;
1647 else
1648 reg &= ~mask;
1649
1650 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1651}
1652
d6648da1
PU		 1653static int twl4030_startup(struct snd_pcm_substream *substream,
1654 struct snd_soc_dai *dai)
7220b9f4 1655{
e6968a17 1656 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1657 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7220b9f4 1658
7220b9f4 1659 if (twl4030->master_substream) {
7220b9f4 1660 twl4030->slave_substream = substream;
6b87a91f
PU		 1661 /* The DAI has one configuration for playback and capture, so
1662 * if the DAI has been already configured then constrain this
1663 * substream to match it. */
1664 if (twl4030->configured)
1665 twl4030_constraints(twl4030, twl4030->master_substream);
1666 } else {
efc8acff 1667 if (!(twl4030_read(codec, TWL4030_REG_CODEC_MODE) &
8a1f936a
PU		 1668 TWL4030_OPTION_1)) {
1669 /* In option2 4 channel is not supported, set the
1670 * constraint for the first stream for channels, the
1671 * second stream will 'inherit' this cosntraint */
1672 snd_pcm_hw_constraint_minmax(substream->runtime,
7ded5fe0
PU		 1673 SNDRV_PCM_HW_PARAM_CHANNELS,
1674 2, 2);
8a1f936a 1675 }
7220b9f4 1676 twl4030->master_substream = substream;
6b87a91f 1677 }
7220b9f4
PU		 1678
1679 return 0;
1680}
1681
d6648da1
PU		 1682static void twl4030_shutdown(struct snd_pcm_substream *substream,
1683 struct snd_soc_dai *dai)
7220b9f4 1684{
e6968a17 1685 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1686 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7220b9f4
PU		 1687
1688 if (twl4030->master_substream == substream)
1689 twl4030->master_substream = twl4030->slave_substream;
1690
1691 twl4030->slave_substream = NULL;
6b87a91f
PU		 1692
1693 /* If all streams are closed, or the remaining stream has not yet
1694 * been configured than set the DAI as not configured. */
1695 if (!twl4030->master_substream)
1696 twl4030->configured = 0;
1697 else if (!twl4030->master_substream->runtime->channels)
1698 twl4030->configured = 0;
8a1f936a
PU		 1699
1700 /* If the closing substream had 4 channel, do the necessary cleanup */
1701 if (substream->runtime->channels == 4)
1702 twl4030_tdm_enable(codec, substream->stream, 0);
7220b9f4
PU		 1703}
1704
cc17557e 1705static int twl4030_hw_params(struct snd_pcm_substream *substream,
7ded5fe0
PU		 1706 struct snd_pcm_hw_params *params,
1707 struct snd_soc_dai *dai)
cc17557e 1708{
e6968a17 1709 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1710 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
cc17557e
SS		 1711 u8 mode, old_mode, format, old_format;
1712
8a1f936a
PU		 1713 /* If the substream has 4 channel, do the necessary setup */
1714 if (params_channels(params) == 4) {
efc8acff
PU		 1715 format = twl4030_read(codec, TWL4030_REG_AUDIO_IF);
1716 mode = twl4030_read(codec, TWL4030_REG_CODEC_MODE);
eaf1ac8b
PU		 1717
1718 /* Safety check: are we in the correct operating mode and
1719 * the interface is in TDM mode? */
1720 if ((mode & TWL4030_OPTION_1) &&
1721 ((format & TWL4030_AIF_FORMAT) == TWL4030_AIF_FORMAT_TDM))
8a1f936a
PU		 1722 twl4030_tdm_enable(codec, substream->stream, 1);
1723 else
1724 return -EINVAL;
1725 }
1726
6b87a91f
PU		 1727 if (twl4030->configured)
1728 /* Ignoring hw_params for already configured DAI */
7220b9f4
PU		 1729 return 0;
1730
cc17557e 1731 /* bit rate */
efc8acff
PU		 1732 old_mode = twl4030_read(codec,
1733 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
cc17557e
SS		 1734 mode = old_mode & ~TWL4030_APLL_RATE;
1735
1736 switch (params_rate(params)) {
1737 case 8000:
1738 mode |= TWL4030_APLL_RATE_8000;
1739 break;
1740 case 11025:
1741 mode |= TWL4030_APLL_RATE_11025;
1742 break;
1743 case 12000:
1744 mode |= TWL4030_APLL_RATE_12000;
1745 break;
1746 case 16000:
1747 mode |= TWL4030_APLL_RATE_16000;
1748 break;
1749 case 22050:
1750 mode |= TWL4030_APLL_RATE_22050;
1751 break;
1752 case 24000:
1753 mode |= TWL4030_APLL_RATE_24000;
1754 break;
1755 case 32000:
1756 mode |= TWL4030_APLL_RATE_32000;
1757 break;
1758 case 44100:
1759 mode |= TWL4030_APLL_RATE_44100;
1760 break;
1761 case 48000:
1762 mode |= TWL4030_APLL_RATE_48000;
1763 break;
103f211d
PU		 1764 case 96000:
1765 mode |= TWL4030_APLL_RATE_96000;
1766 break;
cc17557e 1767 default:
3b8a0795 1768 dev_err(codec->dev, "%s: unknown rate %d\n", __func__,
cc17557e
SS		 1769 params_rate(params));
1770 return -EINVAL;
1771 }
1772
cc17557e 1773 /* sample size */
efc8acff 1774 old_format = twl4030_read(codec, TWL4030_REG_AUDIO_IF);
cc17557e
SS		 1775 format = old_format;
1776 format &= ~TWL4030_DATA_WIDTH;
04f630d8
MB		 1777 switch (params_width(params)) {
1778 case 16:
cc17557e
SS		 1779 format |= TWL4030_DATA_WIDTH_16S_16W;
1780 break;
04f630d8 1781 case 32:
cc17557e
SS		 1782 format |= TWL4030_DATA_WIDTH_32S_24W;
1783 break;
1784 default:
04f630d8
MB		 1785 dev_err(codec->dev, "%s: unsupported bits/sample %d\n",
1786 __func__, params_width(params));
cc17557e
SS		 1787 return -EINVAL;
1788 }
1789
2046f175
PU		 1790 if (format != old_format || mode != old_mode) {
1791 if (twl4030->codec_powered) {
1792 /*
1793 * If the codec is powered, than we need to toggle the
1794 * codec power.
1795 */
1796 twl4030_codec_enable(codec, 0);
1797 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1798 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1799 twl4030_codec_enable(codec, 1);
1800 } else {
1801 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1802 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1803 }
cc17557e 1804 }
6b87a91f
PU		 1805
1806 /* Store the important parameters for the DAI configuration and set
1807 * the DAI as configured */
1808 twl4030->configured = 1;
1809 twl4030->rate = params_rate(params);
1810 twl4030->sample_bits = hw_param_interval(params,
1811 SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
1812 twl4030->channels = params_channels(params);
1813
1814 /* If both playback and capture streams are open, and one of them
1815 * is setting the hw parameters right now (since we are here), set
1816 * constraints to the other stream to match the current one. */
1817 if (twl4030->slave_substream)
1818 twl4030_constraints(twl4030, substream);
1819
cc17557e
SS		 1820 return 0;
1821}
1822
7ded5fe0
PU		 1823static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai, int clk_id,
1824 unsigned int freq, int dir)
cc17557e
SS		 1825{
1826 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1827 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
cc17557e
SS		 1828
1829 switch (freq) {
1830 case 19200000:
cc17557e 1831 case 26000000:
cc17557e 1832 case 38400000:
cc17557e
SS		 1833 break;
1834 default:
3b8a0795 1835 dev_err(codec->dev, "Unsupported HFCLKIN: %u\n", freq);
cc17557e
SS		 1836 return -EINVAL;
1837 }
1838
68d01955
PU		 1839 if ((freq / 1000) != twl4030->sysclk) {
1840 dev_err(codec->dev,
3b8a0795 1841 "Mismatch in HFCLKIN: %u (configured: %u)\n",
68d01955
PU		 1842 freq, twl4030->sysclk * 1000);
1843 return -EINVAL;
1844 }
cc17557e
SS		 1845
1846 return 0;
1847}
1848
7ded5fe0 1849static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
cc17557e
SS		 1850{
1851 struct snd_soc_codec *codec = codec_dai->codec;
2046f175 1852 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
cc17557e
SS		 1853 u8 old_format, format;
1854
1855 /* get format */
efc8acff 1856 old_format = twl4030_read(codec, TWL4030_REG_AUDIO_IF);
cc17557e
SS		 1857 format = old_format;
1858
1859 /* set master/slave audio interface */
1860 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1861 case SND_SOC_DAIFMT_CBM_CFM:
1862 format &= ~(TWL4030_AIF_SLAVE_EN);
e18c94d2 1863 format &= ~(TWL4030_CLK256FS_EN);
cc17557e
SS		 1864 break;
1865 case SND_SOC_DAIFMT_CBS_CFS:
cc17557e 1866 format |= TWL4030_AIF_SLAVE_EN;
e18c94d2 1867 format |= TWL4030_CLK256FS_EN;
cc17557e
SS		 1868 break;
1869 default:
1870 return -EINVAL;
1871 }
1872
1873 /* interface format */
1874 format &= ~TWL4030_AIF_FORMAT;
1875 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1876 case SND_SOC_DAIFMT_I2S:
1877 format |= TWL4030_AIF_FORMAT_CODEC;
1878 break;
8a1f936a
PU		 1879 case SND_SOC_DAIFMT_DSP_A:
1880 format |= TWL4030_AIF_FORMAT_TDM;
1881 break;
cc17557e
SS		 1882 default:
1883 return -EINVAL;
1884 }
1885
1886 if (format != old_format) {
2046f175
PU		 1887 if (twl4030->codec_powered) {
1888 /*
1889 * If the codec is powered, than we need to toggle the
1890 * codec power.
1891 */
1892 twl4030_codec_enable(codec, 0);
1893 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1894 twl4030_codec_enable(codec, 1);
1895 } else {
1896 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1897 }
cc17557e
SS		 1898 }
1899
1900 return 0;
1901}
1902
68140443
LCM		 1903static int twl4030_set_tristate(struct snd_soc_dai *dai, int tristate)
1904{
1905 struct snd_soc_codec *codec = dai->codec;
efc8acff 1906 u8 reg = twl4030_read(codec, TWL4030_REG_AUDIO_IF);
68140443
LCM		 1907
1908 if (tristate)
1909 reg |= TWL4030_AIF_TRI_EN;
1910 else
1911 reg &= ~TWL4030_AIF_TRI_EN;
1912
1913 return twl4030_write(codec, TWL4030_REG_AUDIO_IF, reg);
1914}
1915
b7a755a8
MLC		 1916/* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R
1917 * (VTXL, VTXR) for uplink has to be enabled/disabled. */
1918static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction,
7ded5fe0 1919 int enable)
b7a755a8
MLC		 1920{
1921 u8 reg, mask;
1922
efc8acff 1923 reg = twl4030_read(codec, TWL4030_REG_OPTION);
b7a755a8
MLC		 1924
1925 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1926 mask = TWL4030_ARXL1_VRX_EN;
1927 else
1928 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1929
1930 if (enable)
1931 reg |= mask;
1932 else
1933 reg &= ~mask;
1934
1935 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1936}
1937
7154b3e8 1938static int twl4030_voice_startup(struct snd_pcm_substream *substream,
7ded5fe0 1939 struct snd_soc_dai *dai)
7154b3e8 1940{
e6968a17 1941 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1942 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7154b3e8
JS		 1943 u8 mode;
1944
1945 /* If the system master clock is not 26MHz, the voice PCM interface is
25985edc 1946 * not available.
7154b3e8 1947 */
68d01955 1948 if (twl4030->sysclk != 26000) {
3b8a0795
PU		 1949 dev_err(codec->dev,
1950 "%s: HFCLKIN is %u KHz, voice interface needs 26MHz\n",
1951 __func__, twl4030->sysclk);
7154b3e8
JS		 1952 return -EINVAL;
1953 }
1954
1955 /* If the codec mode is not option2, the voice PCM interface is not
25985edc 1956 * available.
7154b3e8 1957 */
efc8acff 1958 mode = twl4030_read(codec, TWL4030_REG_CODEC_MODE)
7154b3e8
JS		 1959 & TWL4030_OPT_MODE;
1960
1961 if (mode != TWL4030_OPTION_2) {
3b8a0795
PU		 1962 dev_err(codec->dev, "%s: the codec mode is not option2\n",
1963 __func__);
7154b3e8
JS		 1964 return -EINVAL;
1965 }
1966
1967 return 0;
1968}
1969
b7a755a8 1970static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
7ded5fe0 1971 struct snd_soc_dai *dai)
b7a755a8 1972{
e6968a17 1973 struct snd_soc_codec *codec = dai->codec;
b7a755a8
MLC		 1974
1975 /* Enable voice digital filters */
1976 twl4030_voice_enable(codec, substream->stream, 0);
1977}
1978
7154b3e8 1979static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
7ded5fe0
PU		 1980 struct snd_pcm_hw_params *params,
1981 struct snd_soc_dai *dai)
7154b3e8 1982{
e6968a17 1983 struct snd_soc_codec *codec = dai->codec;
2046f175 1984 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7154b3e8
JS		 1985 u8 old_mode, mode;
1986
b7a755a8
MLC		 1987 /* Enable voice digital filters */
1988 twl4030_voice_enable(codec, substream->stream, 1);
1989
7154b3e8 1990 /* bit rate */
7ded5fe0
PU		 1991 old_mode = twl4030_read(codec,
1992 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
7154b3e8
JS		 1993 mode = old_mode;
1994
1995 switch (params_rate(params)) {
1996 case 8000:
1997 mode &= ~(TWL4030_SEL_16K);
1998 break;
1999 case 16000:
2000 mode |= TWL4030_SEL_16K;
2001 break;
2002 default:
3b8a0795 2003 dev_err(codec->dev, "%s: unknown rate %d\n", __func__,
7154b3e8
JS		 2004 params_rate(params));
2005 return -EINVAL;
2006 }
2007
2008 if (mode != old_mode) {
2046f175
PU		 2009 if (twl4030->codec_powered) {
2010 /*
2011 * If the codec is powered, than we need to toggle the
2012 * codec power.
2013 */
2014 twl4030_codec_enable(codec, 0);
2015 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
2016 twl4030_codec_enable(codec, 1);
2017 } else {
2018 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
2019 }
7154b3e8
JS		 2020 }
2021
2022 return 0;
2023}
2024
2025static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
7ded5fe0 2026 int clk_id, unsigned int freq, int dir)
7154b3e8
JS		 2027{
2028 struct snd_soc_codec *codec = codec_dai->codec;
d4a8ca24 2029 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7154b3e8 2030
68d01955 2031 if (freq != 26000000) {
3b8a0795
PU		 2032 dev_err(codec->dev,
2033 "%s: HFCLKIN is %u KHz, voice interface needs 26MHz\n",
2034 __func__, freq / 1000);
68d01955
PU		 2035 return -EINVAL;
2036 }
2037 if ((freq / 1000) != twl4030->sysclk) {
2038 dev_err(codec->dev,
3b8a0795 2039 "Mismatch in HFCLKIN: %u (configured: %u)\n",
68d01955 2040 freq, twl4030->sysclk * 1000);
7154b3e8
JS		 2041 return -EINVAL;
2042 }
7154b3e8
JS		 2043 return 0;
2044}
2045
2046static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
7ded5fe0 2047 unsigned int fmt)
7154b3e8
JS		 2048{
2049 struct snd_soc_codec *codec = codec_dai->codec;
2046f175 2050 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7154b3e8
JS		 2051 u8 old_format, format;
2052
2053 /* get format */
efc8acff 2054 old_format = twl4030_read(codec, TWL4030_REG_VOICE_IF);
7154b3e8
JS		 2055 format = old_format;
2056
2057 /* set master/slave audio interface */
2058 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
c264301c 2059 case SND_SOC_DAIFMT_CBM_CFM:
7154b3e8
JS		 2060 format &= ~(TWL4030_VIF_SLAVE_EN);
2061 break;
2062 case SND_SOC_DAIFMT_CBS_CFS:
2063 format |= TWL4030_VIF_SLAVE_EN;
2064 break;
2065 default:
2066 return -EINVAL;
2067 }
2068
2069 /* clock inversion */
2070 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2071 case SND_SOC_DAIFMT_IB_NF:
2072 format &= ~(TWL4030_VIF_FORMAT);
2073 break;
2074 case SND_SOC_DAIFMT_NB_IF:
2075 format |= TWL4030_VIF_FORMAT;
2076 break;
2077 default:
2078 return -EINVAL;
2079 }
2080
2081 if (format != old_format) {
2046f175
PU		 2082 if (twl4030->codec_powered) {
2083 /*
2084 * If the codec is powered, than we need to toggle the
2085 * codec power.
2086 */
2087 twl4030_codec_enable(codec, 0);
2088 twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
2089 twl4030_codec_enable(codec, 1);
2090 } else {
2091 twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
2092 }
7154b3e8
JS		 2093 }
2094
2095 return 0;
2096}
2097
68140443
LCM		 2098static int twl4030_voice_set_tristate(struct snd_soc_dai *dai, int tristate)
2099{
2100 struct snd_soc_codec *codec = dai->codec;
efc8acff 2101 u8 reg = twl4030_read(codec, TWL4030_REG_VOICE_IF);
68140443
LCM		 2102
2103 if (tristate)
2104 reg |= TWL4030_VIF_TRI_EN;
2105 else
2106 reg &= ~TWL4030_VIF_TRI_EN;
2107
2108 return twl4030_write(codec, TWL4030_REG_VOICE_IF, reg);
2109}
2110
bbba9444 2111#define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
dcdeda4a 2112#define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
cc17557e 2113
85e7652d 2114static const struct snd_soc_dai_ops twl4030_dai_hifi_ops = {
7220b9f4
PU		 2115 .startup = twl4030_startup,
2116 .shutdown = twl4030_shutdown,
10d9e3d9
JS		 2117 .hw_params = twl4030_hw_params,
2118 .set_sysclk = twl4030_set_dai_sysclk,
2119 .set_fmt = twl4030_set_dai_fmt,
68140443 2120 .set_tristate = twl4030_set_tristate,
10d9e3d9
JS		 2121};
2122
85e7652d 2123static const struct snd_soc_dai_ops twl4030_dai_voice_ops = {
7154b3e8 2124 .startup = twl4030_voice_startup,
b7a755a8 2125 .shutdown = twl4030_voice_shutdown,
7154b3e8
JS		 2126 .hw_params = twl4030_voice_hw_params,
2127 .set_sysclk = twl4030_voice_set_dai_sysclk,
2128 .set_fmt = twl4030_voice_set_dai_fmt,
68140443 2129 .set_tristate = twl4030_voice_set_tristate,
7154b3e8
JS		 2130};
2131
f0fba2ad 2132static struct snd_soc_dai_driver twl4030_dai[] = {
7154b3e8 2133{
f0fba2ad 2134 .name = "twl4030-hifi",
cc17557e 2135 .playback = {
b4852b79 2136 .stream_name = "HiFi Playback",
cc17557e 2137 .channels_min = 2,
8a1f936a 2138 .channels_max = 4,
31ad0f31 2139 .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
8819f65c
PU		 2140 .formats = TWL4030_FORMATS,
2141 .sig_bits = 24,},
cc17557e 2142 .capture = {
7f51e7d3 2143 .stream_name = "HiFi Capture",
cc17557e 2144 .channels_min = 2,
8a1f936a 2145 .channels_max = 4,
cc17557e 2146 .rates = TWL4030_RATES,
8819f65c
PU		 2147 .formats = TWL4030_FORMATS,
2148 .sig_bits = 24,},
f0fba2ad 2149 .ops = &twl4030_dai_hifi_ops,
7154b3e8
JS		 2150},
2151{
f0fba2ad 2152 .name = "twl4030-voice",
7154b3e8 2153 .playback = {
b4852b79 2154 .stream_name = "Voice Playback",
7154b3e8
JS		 2155 .channels_min = 1,
2156 .channels_max = 1,
2157 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2158 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2159 .capture = {
7f51e7d3 2160 .stream_name = "Voice Capture",
7154b3e8
JS		 2161 .channels_min = 1,
2162 .channels_max = 2,
2163 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2164 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2165 .ops = &twl4030_dai_voice_ops,
2166},
cc17557e 2167};
cc17557e 2168
f0fba2ad 2169static int twl4030_soc_probe(struct snd_soc_codec *codec)
cc17557e 2170{
f0fba2ad 2171 struct twl4030_priv *twl4030;
9da28c7b 2172
f2b1ce49
PU		 2173 twl4030 = devm_kzalloc(codec->dev, sizeof(struct twl4030_priv),
2174 GFP_KERNEL);
04cc41a8 2175 if (!twl4030)
f0fba2ad 2176 return -ENOMEM;
f0fba2ad
LG		 2177 snd_soc_codec_set_drvdata(codec, twl4030);
2178 /* Set the defaults, and power up the codec */
57fe7251 2179 twl4030->sysclk = twl4030_audio_get_mclk() / 1000;
f0fba2ad
LG		 2180
2181 twl4030_init_chip(codec);
cc17557e 2182
7a1fecf5 2183 return 0;
cc17557e
SS		 2184}
2185
f0fba2ad 2186static int twl4030_soc_remove(struct snd_soc_codec *codec)
cc17557e 2187{
5b3b0fa8 2188 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
182f73f6 2189 struct twl4030_codec_data *pdata = twl4030->pdata;
5b3b0fa8 2190
281ecd16
PU		 2191 if (pdata && pdata->hs_extmute && gpio_is_valid(pdata->hs_extmute_gpio))
2192 gpio_free(pdata->hs_extmute_gpio);
2193
7a1fecf5
PU		 2194 return 0;
2195}
2196
f0fba2ad
LG		 2197static struct snd_soc_codec_driver soc_codec_dev_twl4030 = {
2198 .probe = twl4030_soc_probe,
2199 .remove = twl4030_soc_remove,
efc8acff 2200 .read = twl4030_read,
f0fba2ad
LG		 2201 .write = twl4030_write,
2202 .set_bias_level = twl4030_set_bias_level,
eb3032f8 2203 .idle_bias_off = true,
f7c93f01
PU		 2204
2205 .controls = twl4030_snd_controls,
2206 .num_controls = ARRAY_SIZE(twl4030_snd_controls),
2207 .dapm_widgets = twl4030_dapm_widgets,
2208 .num_dapm_widgets = ARRAY_SIZE(twl4030_dapm_widgets),
2209 .dapm_routes = intercon,
2210 .num_dapm_routes = ARRAY_SIZE(intercon),
f0fba2ad
LG		 2211};
2212
05c4c6f7 2213static int twl4030_codec_probe(struct platform_device *pdev)
7a1fecf5 2214{
f0fba2ad 2215 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_twl4030,
7ded5fe0 2216 twl4030_dai, ARRAY_SIZE(twl4030_dai));
cc17557e
SS		 2217}
2218
05c4c6f7 2219static int twl4030_codec_remove(struct platform_device *pdev)
cc17557e 2220{
f0fba2ad 2221 snd_soc_unregister_codec(&pdev->dev);
cc17557e
SS		 2222 return 0;
2223}
2224
f0fba2ad 2225MODULE_ALIAS("platform:twl4030-codec");
7a1fecf5
PU		 2226
2227static struct platform_driver twl4030_codec_driver = {
2228 .probe = twl4030_codec_probe,
05c4c6f7 2229 .remove = twl4030_codec_remove,
7a1fecf5 2230 .driver = {
f0fba2ad 2231 .name = "twl4030-codec",
7a1fecf5 2232 },
cc17557e 2233};
cc17557e 2234
5bbcc3c0 2235module_platform_driver(twl4030_codec_driver);
64089b84 2236
cc17557e
SS		 2237MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
2238MODULE_AUTHOR("Steve Sakoman");
2239MODULE_LICENSE("GPL");
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